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Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer application by customer’s
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January 2014
©2013 Fairchild Semiconductor Corporation
FDMC86340 Rev. C2 www.fairchildsemi.com
1
FDMC86340 N-Channel Shielded Gate Power Trench® MOSFET
FDMC86340
N-Channel Shielded Gate Power Trench® MOSFET
80 V, 48 A, 6.5 mΩ
Features
Shielded Gate MOSFET Technology
Max rDS(on) = 6.5 mΩ at VGS = 10 V, ID = 14 A
Max rDS(on) = 8.5 mΩ at VGS = 8 V, ID = 12 A
High performance technology for extremely low rDS(on)
Termination is Lead-free
RoHS Compliant
General Description
This N-Channel MOSFET is produced using Fairchild
Semiconductor’s advanced PowerTrench® process that
incorporates Shielded Gate technology. This process has been
optimized for the on-state resistance and yet maintain superior
switching performance.
Application
DC-DC Conversion
BottomTop
Pin 1
Pin 1
G
D
S
S
S
D
DD
S
S
S
G
D
D
D
D
Power 33
MOSFET Maximum Ratings TA = 25 °C unless otherwise noted
Thermal Characteristics
Package Marking and Ordering Information
Symbol Parameter Ratings Units
VDS Drain to Source Voltage 80 V
VGS Gate to Source Voltage ±20 V
ID
Drain Current -Continuous TC = 25 °C 48 A -Continuous TA = 25 °C (Note 1a) 14
-Pulsed (Note 4) 200
EAS Single Pulse Avalanche Energy (Note 3) 216 mJ
PDPower Dissipation TC = 25 °C 54 W
Power Dissipation TA = 25 °C (Note 1a) 2.3
TJ, TSTG Operating and Storage Junction Temperature Range -55 to +150 °C
RθJC Thermal Resistance, Junction to Case (Note 1) 2.3 °C/W
RθJA Thermal Resistance, Junction to Ambient (Note 1a) 53
Device Marking Device Package Reel Size Tape Width Quantity
FDMC86340 FDMC86340 Power33 13 ’’ 12 mm 3000 units
FDMC86340 N-Channel Shielded Gate Power Trench® MOSFET
www.fairchildsemi.com
2
©2013 Fairchild Semiconductor Cor poration
FDMC86340 Rev. C2
Electrical Characteristics TJ = 25 °C unless otherwise noted
Off Characteristics
On Characteristics
Dynamic Characteristics
Switching Characteristics
Drain-Source Diode Characteristics
Symbol Parameter Test Conditions Min Typ Max Units
BVDSS Drain to Source Breakdown Voltage ID = 250 μA, VGS = 0 V 80 V
ΔBVDSS
ΔTJ
Breakdown Voltage Temperature
Coefficient ID = 250 μA, referenced to 25 °C 46 mV/°C
IDSS Zero Gate Voltage Drain Current VDS = 64 V, VGS = 0 V 1 μA
IGSS Gate to Source Leakage Current VGS = ±20 V, VDS = 0 V ±100 nA
VGS(th) Gate to Source Threshold Voltage VGS = VDS, ID = 250 μA 2.0 3.4 4.0 V
ΔVGS(th)
ΔTJ
Gate to Source Threshold Voltage
Temperature Coefficient ID = 250 μA, referenced to 25 °C -10 mV/°C
rDS(on) Static Drain to Source On Resistance VGS = 10 V, ID = 14 A 5.0 6.5 mΩVGS = 8 V, ID = 12 A 6.0 8.5
VGS = 10 V, ID = 14 A, TJ = 125 °C 8.5 11
gFS Forward Transconductance VDD = 10 V, ID = 14 A 36 S
Ciss Input Capacitance VDS = 40 V, VGS = 0 V,
f = 1 MHz
2775 3885 pF
Coss Output Capacitance 468 655 pF
Crss Reverse Transfer Capacitance 15 25 pF
RgGate Resistance 0.1 0.7 2.1 Ω
td(on) Turn-On Delay Time VDD = 40 V, ID = 14 A,
VGS = 10 V, RGEN = 6 Ω
20 32 ns
trRise Time 7.9 16 ns
td(off) Turn-Off Delay Time 23 37 ns
tfFall Time 5.1 10 ns
Qg(TOT) Total Gate Charge VGS = 0 V to 10 V VDD = 40 V,
ID = 14 A
38 53 nC
Qg(TOT) Total Gate Charge VGS = 0 V to 8 V 31 44 nC
Qgs Gate to Source Charge 14 nC
Qgd Gate to Drain “Miller” Charge 8.0 nC
Qoss Output Charge VDD = 40 V, VGS = 0 V 42 nC
VSD Source to Drain Diode Forward Voltage VGS = 0 V, IS = 14 A (Note 2) 0.8 1.3 V
VGS = 0 V, IS = 1.9 A (Note 2) 0.7 1.2 V
trr Reverse Recovery Time IF = 14 A, di/dt = 100 A/μs 41 66 ns
Qrr Reverse Recovery Charge 25 40 nC
Notes:
1. RθJA is deter mined with th e de vice m ount ed on a 1 in2 pad 2 oz co ppe r pad on a 1 .5 x 1 .5 i n. bo ard of FR-4 mat erial . RθJC is guaranteed by design while RθCA is determined by
the user's board design.
2. Pulse Test: Pulse Width < 300 μs, Duty cycle < 2.0%.
3. EAS of 216 mJ is based on starting TJ = 25 °C, L = 3 mH, IAS = 12 A, VDD = 80 V, VGS = 10 V. 100% test at L = 0.1 mH, IAS = 37 A.
4. Pulsed Id limited by junction temperature, td<=100 μS, please refer to SOA curve for more details.
53 °C/W when mounted
on a 1 in2 pad of 2 oz
copper
125 °C/W when mounted
on a minimum pad o f 2 oz
copper
G
DF
DS
SF
SS
G
DF
DS
SF
SS
a. b.
FDMC86340 N-Channel Shielded Gate Power Trench® MOSFET
www.fairchildsemi.com
3
©2013 Fairchild Semiconductor Corporation
FDMC86340 Rev. C2
Typical Characteristics TJ = 25 °C unless otherwise noted
Figure 1.
01234
0
40
80
120
160
200
VGS = 6 V
VGS = 6.5 V
VGS = 7 V
VGS = 8 V
PULSE DURA T ION = 80 μs
DUTY CYCLE = 0.5% MAX
VGS = 10 V
ID, DRAIN CURRENT (A)
VDS, DRAIN TO SOURCE VOLTAGE (V)
On-Region Characteristics Figure 2.
0 40 80 120 160 200
0
1
2
3
4
5
VGS = 8 V
PULSE DURATION = 80 μs
DUTY CYCLE = 0.5% MAX
NORMALIZED
DRAIN TO SOURCE ON-RESISTANCE
ID, DRA IN CURRENT (A)
VGS = 7 V
VGS = 6.5 V
VGS = 10 V
VGS = 6 V
Normali zed On-Resistance
vs Drain Current and Gate Voltage
Figure 3. Normalized On- Resistance
-75 -50 -25 0 25 50 75 100 125 150
0.6
0.8
1.0
1.2
1.4
1.6
1.8
2.0
ID = 14 A
VGS = 10 V
NORMALIZED
DRAIN TO SOURCE ON-RESIST ANCE
TJ, JUNCTION TEMPERATURE (oC)
vs Junction Te mperature Figure 4.
5678910
0
10
20
30
40
50
TJ = 125 oC
ID = 14 A
TJ = 25 oC
VGS, G ATE TO SOURCE VOLTAG E (V)
rDS(on), DRAIN TO
SOURCE ON-RESIS TANCE (mΩ)
PULSE DURA TIO N = 80 μs
DUTY CYCLE = 0.5% MAX
On-Resistance vs Gate to
Source Voltage
Figure 5. Transfer Characteristics
345678910
0
40
80
120
160
200
TJ = 150 oC
VDS = 5 V
PULSE DURA TION = 80 μs
DUTY CYCLE = 0.5% MAX
TJ = -55 oC
TJ = 25 oC
ID, DRAIN CURRENT (A)
VGS, GATE TO SOURCE VOLTAGE (V)
Figure 6.
0.0 0.3 0.6 0.9 1.2
0.001
0.01
0.1
1
10
100
200
TJ = -55 oC
TJ = 25 o C
TJ = 150 oC
VGS = 0 V
IS, REVERSE DRAIN CURRENT (A)
VSD, BODY DIODE FORWA RD VOLTAGE (V)
Source to Drain Diode
Forward Voltage vs Source Current
FDMC86340 N-Channel Shielded Gate Power Trench® MOSFET
www.fairchildsemi.com
4
©2013 Fairchild Semiconductor Corporation
FDMC86340 Rev. C2
Figure 7.
0 8 16 24 32 40
0
2
4
6
8
10 ID = 14 A
VDD = 50 V
VDD = 40 V
VGS, GATE TO SOURCE VOLTAGE (V)
Qg, GATE CHARGE (nC)
VDD = 30 V
Gate Charge Characteristics Figure 8.
0.1 1 10 80
1
10
100
1000
10000
f = 1 MHz
VGS = 0 V
CAPACITANCE (pF)
VDS, DRAIN TO SOURCE VOLTA GE (V)
Crss
Coss
Ciss
Capacitance vs Drain
to Source Voltage
Figure 9.
0.001 0.01 0.1 1 10 100
1
10
60
TJ = 100 oC
TJ = 25 oC
TJ = 125 oC
tAV, TIME IN A VALANC HE (ms)
IAS, AVALANCHE CURRENT (A)
Uncl a mped I nduc t ive
Switching Capability Figure 10.
25 50 75 100 125 150
0
20
40
60
80
VGS = 8 V
Limited by Package
RθJC = 2.3 oC/W
VGS = 10 V
ID, DRAIN CURRENT (A)
TC, CA SE TEMPERA T URE (oC)
Maximum Continuous Drain
Current vs Case Temperature
Figure 11.
0.01 0.1 1 10 100 400
0.001
0.01
0.1
1
10
100
300
10 s
CURVE BENT TO
MEASURED DATA
100 µs
10 ms
DC
1 s
100 ms
1 ms
ID, DRAIN CURRENT (A)
VDS, DRAIN to SOURCE VOLTAGE (V)
THIS AREA IS
LIMITED BY rDS(on)
SINGLE PULSE
TJ = MAX RATED
RθJA = 125 oC/W
TA = 25 oC
Forward Bias Safe
Operating Area Figure 12. Single Pulse Maximum
Power Dissipation
10-4 10-3 10-2 10-1 110
100 1000
0.1
1
10
100
1000
2000
SINGLE PULSE
RθJA = 125 oC/W
TA = 25 oC
P(PK), PEAK TRANSIENT POWER (W)
t, PULSE W IDTH (sec)
Typical Characteristics TJ = 25 °C unless otherwise noted
FDMC86340 N-Channel Shielded Gate Power Trench® MOSFET
www.fairchildsemi.com
5
©2013 Fairchild Semiconductor Corporation
FDMC86340 Rev. C2
Figure 13. Junction-to-Ambient Transient Thermal Respon se Curve
10-4 10-3 10-2 10-1 110
100 1000
0.0001
0.001
0.01
0.1
1
2
SINGLE PULSE
DUTY CYCLE-DESCENDING ORDER
r(t), NORMALIZED EFFE CT IV E TRANSIENT
THERMAL RESISTANCE
t, RECTANGULAR PULSE DURA T ION (sec)
D = 0.5
0. 2
0. 1
0. 0 5
0. 0 2
0. 0 1
PDM
t1t2
NOTES:
Duty Cycle, D = t1 / t2
ZθJA(t) = r(t) x RθJA
Peak TJ = PDM x ZθJA(t) + TA
RθJA = 125 °C/W
Typical Characteristics TJ = 25 °C unless otherwise noted
NOTES: UNLESS OTHERWISE SPECIFIED
A) PACKAGE STANDARD REFERENCE:
JEDEC MO-240, ISSUE A, VAR. BA,
DATED OCTOBER 2002.
B) ALL DIMENSIONS ARE IN MILLIMETERS.
C) DIMENS I O NS DO NOT INCL UD E BURRS
OR MOLD FLASH. MOLD FLASH OR
BURRS DOES NOT EXCEED 0.10MM.
D) DIMENSIONING AND TOLERANCING PER
ASME Y14.5M-1994.
E) DRAWING FILE NAME: PQFN08HREV1
8
1
5
4
41
85
LAND PATTERN
RECOMMENDATION
14
85
PKG
C
L
PKG
L
C
PKG L
C
L
C
SYM
PKG
C
L
A
B
SCALE: 2X
SEE
DETAIL A
3.40
3.20
3.40
3.20
1.95
0.65
0.37
0.27 (8X)
0.50
0.30
2.05
1.85
0.10 C A B
(0.34)
(2.27)(0.52 TYP)
0.25
0.15
0.80
0.70
0.10 C
0.08 C0.05
0.00 C
SEATING
PLANE
2.37 MIN
(0.45)
(0.40)
(0.65)
2.15 MIN
0.70 MIN
0.42 MIN
(8X)
1.95
0.65
PIN 1
INDICATOR
(0.33) TYP
www.onsemi.com
1
ON Semiconductor and are trademarks of Semiconductor Components Industries, LLC dba ON Semiconductor or its subsidiaries in the United States and/or other countries.
ON Semiconductor owns the rights to a number of patents, trademarks, copyrights, trade secrets, and other intellectual property. A listing of ON Semiconductor’s product/patent
coverage may be accessed at www.onsemi.com/site/pdf/Patent−Marking.pdf. ON Semiconductor reserves the right to make changes without further notice to any products herein.
ON Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does ON Semiconductor assume any liability
arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation special, consequential or incidental damages.
Buyer is responsible for its products and applications using ON Semiconductor products, including compliance with all laws, regulations and safety requirements or standards,
regardless of any support or applications information provided by ON Semiconductor. “Typical” parameters which may be provided in ON Semiconductor data sheets and/or
specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including “Typicals” must be validated for each customer
application by customer’s technical experts. ON Semiconductor does not convey any license under its patent rights nor the rights of others. ON Semiconductor products are not
designed, intended, or authorized for use as a critical component in life support systems or any FDA Class 3 medical devices or medical devices with a same or similar classification
in a foreign jurisdiction or any devices intended for implantation in the human body. Should Buyer purchase or use ON Semiconductor products for any such unintended or unauthorized
application, Buyer shall indemnify and hold ON Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and
expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such
claim alleges that ON Semiconductor was negligent regarding the design or manufacture of the part. ON Semiconductor is an Equal Opportunity/Affirmative Action Employer. This
literature is subject to all applicable copyright laws and is not for resale in any manner.
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