5962-8974601CA - Texas Instruments High-Performance Analog

Data sheet acquired from Harris Semiconductor

SCHS121D

Features

• Buffered Inputs

• Typical Propagation Delay: 10ns at VCC = 5V,

CL = 15pF, TA = 25oC

• Fanout (Over Temperature Range)

- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads

- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads

• Wide Operating T emperature Range . . . -55oC to 125oC

• Balanced Propagation Delay and Transition Times

• Signiﬁcant Power Reduction Compared to LSTTL

Logic ICs

• HC Types

- 2V to 6V Operation

- High Noise Immunity: NIL = 30%, NIH = 30% of VCC

at VCC = 5V

• HCT Types

- 4.5V to 5.5V Operation

- Direct LSTTL Input Logic Compatibility,

VIL= 0.8V (Max), VIH = 2V (Min)

- CMOS Input Compatibility, Il≤1µA at VOL, VOH

Pinout

CD54HC30, CD54HCT30 (CERDIP)

CD74HC30 (PDIP, SOIC, SOP, TSSOP)

CD74HCT30 (PDIP, SOIC)

TOP VIEW

Description

The ’HC30 and ’HCT30 each contain an 8-input NAND gate

in one package. They provide the system designer with the

direct implementation of the positive logic 8-input NAND

function. Logic gates utilize silicon gate CMOS technology to

achieve operating speeds similar to LSTTL gates with the

low power consumption of standard CMOS integrated cir-

cuits. All devices have the ability to drive 10 LSTTL loads.

The HCT logic family is functionally pin compatible with the

standard LS logic family.

GND

Ordering Information

PART NUMBER TEMP. RANGE

(oC) PACKAGE

CD54HC30F3A -55 to 125 14 Ld CERDIP

CD54HCT30F3A -55 to 125 14 Ld CERDIP

CD74HC30E -55 to 125 14 Ld PDIP

CD74HC30M -55 to 125 14 Ld SOIC

CD74HC30MT -55 to 125 14 Ld SOIC

CD74HC30M96 -55 to 125 14 Ld SOIC

CD74HC30NSR -55 to 125 14 Ld SOP

CD74HC30PW -55 to 125 14 Ld TSSOP

CD74HC30PWR -55 to 125 14 Ld TSSOP

CD74HC30PWT -55 to 125 14 Ld TSSOP

CD74HCT30E -55 to 125 14 Ld PDIP

CD74HCT30M -55 to 125 14 Ld SOIC

CD74HCT30MT -55 to 125 14 Ld SOIC

CD74HCT30M96 -55 to 125 14 Ld SOIC

NOTE: When ordering, use the entire part number. The sufﬁxes 96

and R denote tape and reel. The sufﬁx T denotes a small-quantity

reel of 250.

CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.

CD54/74HC30,

CD54/74HCT30

High Speed CMOS Logic

8-Input NAND Gate

[

/Title

(

CD54H

30,

D74H

30,

D74H

T30)

Subject

(

High

peed

MOS

ogic 8-

August 1997 - Revised September 2003

Functional Diagram

Logic Symbol

TRUTH TABLE

INPUTS

OUTPUTABCDEFGH

LXXXXXXX H

XLXXXXXX H

XXLXXXXX H

XXXLXXXX H

XXXXLXXX H

XXXXXLXX H

XXXXXXLX H

XXXXXXXL H

HHHHHHHH L

NOTE: H = HIGH Voltage Level, L = LOW Voltage Level, X = Irrelevant

Y = ABCDEFGH

CD54/74HC30, CD54/74HCT30

Absolute Maximum Ratings Thermal Information

DC Supply Voltage, VCC . . . . . . . . . . . . . . . . . . . . . . . . -0.5V to 7V

DC Input Diode Current, IIK

For VI < -0.5V or VI > VCC + 0.5V. . . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Diode Current, IOK

For VO < -0.5V or VO > VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±20mA

DC Output Source or Sink Current per Output Pin, IO

For VO > -0.5V or VO < VCC + 0.5V . . . . . . . . . . . . . . . . . . . .±25mA

DC VCC or Ground Current, ICC or IGND . . . . . . . . . . . . . . . . . .±50mA

Operating Conditions

Temperature Range (TA) . . . . . . . . . . . . . . . . . . . . . -55oC to 125oC

Supply Voltage Range, VCC

HC Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .2V to 6V

HCT Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .4.5V to 5.5V

DC Input or Output Voltage, VI, VO . . . . . . . . . . . . . . . . . 0V to VCC

Input Rise and Fall Time

2V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1000ns (Max)

4.5V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 500ns (Max)

6V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 400ns (Max)

Package Thermal Impedance, θJA (see Note 1)

E (PDIP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .80oC/W

M (SOIC) Package. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86oC/W

NS (SOP) Package . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76oC/W

PW (TSSOP) Package. . . . . . . . . . . . . . . . . . . . . . . . . .113oC/W

Maximum Junction Temperature (Hermetic Pac kage or Die) . . . 175oC

Maximum Junction Temperature (Plastic Package) . . . . . . . . 150oC

Maximum Storage Temperature Range . . . . . . . . . .-65oC to 150oC

Maximum Lead Temperature (Soldering 10s). . . . . . . . . . . . . 300oC

(SOIC - Lead Tips Only)

CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation

of the device at these or any other conditions above those indicated in the operational sections of this speciﬁcation is not implied.

NOTE:

1. The package thermal impedance is calculated in accordance with JESD 51-7.

DC Electrical Speciﬁcations

PARAMETER SYMBOL

TEST

CONDITIONS

VCC (V)

25oC -40oC TO +85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HC TYPES

High Level Input

Voltage VIH - - 2 1.5 - - 1.5 - 1.5 - V

4.5 3.15 - - 3.15 - 3.15 - V

6 4.2 - - 4.2 - 4.2 - V

Low Level Input

Voltage VIL - - 2 - - 0.5 - 0.5 - 0.5 V

4.5 - - 1.35 - 1.35 - 1.35 V

6 - - 1.8 - 1.8 - 1.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or

VIL -0.02 2 1.9 - - 1.9 - 1.9 - V

-0.02 4.5 4.4 - - 4.4 - 4.4 - V

-0.02 6 5.9 - - 5.9 - 5.9 - V

High Level Output

Voltage

TTL Loads

---------V

-4 4.5 3.98 - - 3.84 - 3.7 - V

-5.2 6 5.48 - - 5.34 - 5.2 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or

VIL 0.02 2 - - 0.1 - 0.1 - 0.1 V

0.02 4.5 - - 0.1 - 0.1 - 0.1 V

0.02 6 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

---------V

4 4.5 - - 0.26 - 0.33 - 0.4 V

5.2 6 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC or

GND -6--±0.1 - ±1-±1µA

CD54/74HC30, CD54/74HCT30

Quiescent Device

Current ICC VCC or

GND 0 6 - - 2 - 20 - 40 µA

HCT TYPES

High Level Input

Voltage VIH - - 4.5 to

5.5 2-- 2 - 2 - V

Low Level Input

Voltage VIL - - 4.5 to

5.5 - - 0.8 - 0.8 - 0.8 V

High Level Output

Voltage

CMOS Loads

VOH VIH or

VIL -0.02 4.5 4.4 - - 4.4 - 4.4 - V

High Level Output

Voltage

TTL Loads

-4 4.5 3.98 - - 3.84 - 3.7 - V

Low Level Output

Voltage

CMOS Loads

VOL VIH or

VIL -0.02 4.5 - - 0.1 - 0.1 - 0.1 V

Low Level Output

Voltage

TTL Loads

4 4.5 - - 0.26 - 0.33 - 0.4 V

Input Leakage

Current IIVCC

and

GND

- 5.5 - ±0.1 - ±1-±1µA

Quiescent Device

Current ICC VCC or

GND 0 5.5 - - 2 - 20 - 40 µA

Additional Quiescent

Device Current Per

Input Pin: 1 Unit Load

(Note 2)

∆ICC VCC

-2.1 - 4.5 to

5.5 - 100 360 - 450 - 490 µA

NOTE:

2. For dual-supply systems theoretical worst case (VI = 2.4V, VCC = 5.5V) specification is 1.8mA.

DC Electrical Speciﬁcations (Continued)

PARAMETER SYMBOL

TEST

CONDITIONS

VCC (V)

25oC -40oC TO +85oC -55oC TO 125oC

UNITSVI(V) IO(mA) MIN TYP MAX MIN MAX MIN MAX

HCT Input Loading Table

INPUT UNIT LOADS

All 0.6

NOTE: Unit Load is ∆ICC limit speciﬁed in DC Electrical

Speciﬁcations table, e.g. 360µA max at 25oC.

Switching Speciﬁcations Input tr, tf = 6ns

PARAMETER SYMBOL TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

HC TYPES

Propagation Delay, Input to

Output (Figure 1) tPLH, tPHL CL= 50pF 2 - - 130 - 165 - 195 ns

4.5 - - 26 - 33 - 39 ns

6 - - 22 - 28 - 33 ns

PropagationDelay,DataInputto

Output Y tPLH, tPHL CL= 15pF 5 - 10 - ----ns

CD54/74HC30, CD54/74HCT30

Transition Times (Figure 1) tTLH, tTHL CL= 50pF 2 - - 75 - 95 - 110 ns

4.5 - - 15 - 19 - 22 ns

6 - - 13 - 16 - 19 ns

Input Capacitance CI- - - - 10 - 10 - 10 pF

Power Dissipation Capacitance

(Notes 3, 4) CPD - 5-25-----pF

HCT TYPES

Propagation Delay, Input to

Output (Figure 2) tRHL, tPHL CL= 50pF 4.5 - - 28 - 35 - 42 ns

PropagationDelay,DataInputto

Output Y tPLH, tPHL CL= 15pF 5 - 11 - ----ns

Transition Times (Figure 2) tTLH, tTHL CL= 50pF 4.5 - - 15 - 19 - 22 ns

Input Capacitance CI- - - - 10 - 10 - 10 pF

Power Dissipation Capacitance

(Notes 3, 4) CPD - 5-26-----pF

NOTES:

3. CPD is used to determine the dynamic power consumption, per gate.

4. PD = VCC2 fi (CPD + CL) where fi = Input Frequency, CL = Output Load Capacitance, VCC = Supply Voltage.

Switching Speciﬁcations Input tr, tf = 6ns (Continued)

PARAMETER SYMBOL TEST

CONDITIONS VCC

(V)

25oC -40oC TO 85oC -55oC TO 125oC

UNITSMIN TYP MAX MIN MAX MIN MAX

Test Circuits and Waveforms

FIGURE 1. HC AND HCU TRANSITION TIMES AND PROPAGA-

TION DELAY TIMES, COMBINATION LOGIC FIGURE 2. HCT TRANSITION TIMES AND PROPAGATION

DELAY TIMES, COMBINATION LOGIC

tPHL tPLH

tTHL tTLH

90%

50%

10%

50%

10%

INVERTING

OUTPUT

INPUT

GND

VCC

tr = 6ns tf = 6ns

90%

tPHL tPLH

tTHL tTLH

2.7V

1.3V

0.3V

1.3V

10%

INVERTING

OUTPUT

INPUT

GND

tr = 6ns tf = 6ns

90%

CD54/74HC30, CD54/74HCT30

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2013

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

5962-8974601CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8974601CA

CD54HCT30F3A

8404001CA ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8404001CA

CD54HC30F3A

CD54HC30F ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 CD54HC30F

CD54HC30F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 8404001CA

CD54HC30F3A

CD54HCT30F3A ACTIVE CDIP J 14 1 TBD A42 N / A for Pkg Type -55 to 125 5962-8974601CA

CD54HCT30F3A

CD74HC30E ACTIVE PDIP N 14 25 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC30E

CD74HC30EE4 ACTIVE PDIP N 14 25 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HC30E

CD74HC30M ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M

CD74HC30M96 ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M

CD74HC30M96E4 ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M

CD74HC30M96G4 ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M

CD74HC30ME4 ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M

CD74HC30MG4 ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M

CD74HC30MT ACTIVE SOIC D 14 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M

CD74HC30MTE4 ACTIVE SOIC D 14 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M

CD74HC30MTG4 ACTIVE SOIC D 14 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M

CD74HC30NSR ACTIVE SO NS 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2013

Addendum-Page 2

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

CD74HC30NSRE4 ACTIVE SO NS 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M

CD74HC30NSRG4 ACTIVE SO NS 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HC30M

CD74HC30PW ACTIVE TSSOP PW 14 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ30

CD74HC30PWE4 ACTIVE TSSOP PW 14 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ30

CD74HC30PWG4 ACTIVE TSSOP PW 14 90 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ30

CD74HC30PWR ACTIVE TSSOP PW 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ30

CD74HC30PWRE4 ACTIVE TSSOP PW 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ30

CD74HC30PWRG4 ACTIVE TSSOP PW 14 2000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ30

CD74HC30PWT ACTIVE TSSOP PW 14 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ30

CD74HC30PWTE4 ACTIVE TSSOP PW 14 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ30

CD74HC30PWTG4 ACTIVE TSSOP PW 14 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HJ30

CD74HCT30E ACTIVE PDIP N 14 25 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT30E

CD74HCT30EE4 ACTIVE PDIP N 14 25 Pb-Free

(RoHS) CU NIPDAU N / A for Pkg Type -55 to 125 CD74HCT30E

CD74HCT30M ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT30M

CD74HCT30M96 ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT30M

CD74HCT30M96E4 ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT30M

CD74HCT30M96G4 ACTIVE SOIC D 14 2500 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT30M

CD74HCT30ME4 ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT30M

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2013

Addendum-Page 3

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

CD74HCT30MG4 ACTIVE SOIC D 14 50 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT30M

CD74HCT30MT ACTIVE SOIC D 14 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT30M

CD74HCT30MTE4 ACTIVE SOIC D 14 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT30M

CD74HCT30MTG4 ACTIVE SOIC D 14 250 Green (RoHS

& no Sb/Br) CU NIPDAU Level-1-260C-UNLIM -55 to 125 HCT30M

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 25-Sep-2013

Addendum-Page 4

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

OTHER QUALIFIED VERSIONS OF CD54HC30, CD54HCT30, CD74HC30, CD74HCT30 :

•Catalog: CD74HC30, CD74HCT30

•Military: CD54HC30, CD54HCT30

NOTE: Qualified Version Definitions:

•Catalog - TI's standard catalog product

•Military - QML certified for Military and Defense Applications

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

CD74HC30M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

CD74HC30MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

CD74HC30NSR SO NS 14 2000 330.0 16.4 8.2 10.5 2.5 12.0 16.0 Q1

CD74HC30PWR TSSOP PW 14 2000 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

CD74HC30PWT TSSOP PW 14 250 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1

CD74HCT30M96 SOIC D 14 2500 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

CD74HCT30MT SOIC D 14 250 330.0 16.4 6.5 9.0 2.1 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

CD74HC30M96 SOIC D 14 2500 367.0 367.0 38.0

CD74HC30MT SOIC D 14 250 367.0 367.0 38.0

CD74HC30NSR SO NS 14 2000 367.0 367.0 38.0

CD74HC30PWR TSSOP PW 14 2000 367.0 367.0 35.0

CD74HC30PWT TSSOP PW 14 250 367.0 367.0 35.0

CD74HCT30M96 SOIC D 14 2500 367.0 367.0 38.0

CD74HCT30MT SOIC D 14 250 367.0 367.0 38.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

IMPORTANT NOTICE

Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, enhancements, improvements and other

changes to its semiconductor products and services per JESD46, latest issue, and to discontinue any product or service per JESD48, latest

issue. Buyers should obtain the latest relevant information before placing orders and should verify that such information is current and

complete. All semiconductor products (also referred to herein as “components”) are sold subject to TI’s terms and conditions of sale

supplied at the time of order acknowledgment.

TI warrants performance of its components to the specifications applicable at the time of sale, in accordance with the warranty in TI’s terms

and conditions of sale of semiconductor products. Testing and other quality control techniques are used to the extent TI deems necessary

to support this warranty. Except where mandated by applicable law, testing of all parameters of each component is not necessarily

performed.

TI assumes no liability for applications assistance or the design of Buyers’ products. Buyers are responsible for their products and

applications using TI components. To minimize the risks associated with Buyers’ products and applications, Buyers should provide

adequate design and operating safeguards.

TI does not warrant or represent that any license, either express or implied, is granted under any patent right, copyright, mask work right, or

other intellectual property right relating to any combination, machine, or process in which TI components or services are used. Information

published by TI regarding third-party products or services does not constitute a license to use such products or services or a warranty or

endorsement thereof. Use of such information may require a license from a third party under the patents or other intellectual property of the

third party, or a license from TI under the patents or other intellectual property of TI.

Reproduction of significant portions of TI information in TI data books or data sheets is permissible only if reproduction is without alteration

and is accompanied by all associated warranties, conditions, limitations, and notices. TI is not responsible or liable for such altered

documentation. Information of third parties may be subject to additional restrictions.

Resale of TI components or services with statements different from or beyond the parameters stated by TI for that component or service

voids all express and any implied warranties for the associated TI component or service and is an unfair and deceptive business practice.

TI is not responsible or liable for any such statements.

Buyer acknowledges and agrees that it is solely responsible for compliance with all legal, regulatory and safety-related requirements

concerning its products, and any use of TI components in its applications, notwithstanding any applications-related information or support

that may be provided by TI. Buyer represents and agrees that it has all the necessary expertise to create and implement safeguards which

anticipate dangerous consequences of failures, monitor failures and their consequences, lessen the likelihood of failures that might cause

harm and take appropriate remedial actions. Buyer will fully indemnify TI and its representatives against any damages arising out of the use

of any TI components in safety-critical applications.

In some cases, TI components may be promoted specifically to facilitate safety-related applications. With such components, TI’s goal is to

help enable customers to design and create their own end-product solutions that meet applicable functional safety standards and

requirements. Nonetheless, such components are subject to these terms.

No TI components are authorized for use in FDA Class III (or similar life-critical medical equipment) unless authorized officers of the parties

have executed a special agreement specifically governing such use.

Only those TI components which TI has specifically designated as military grade or “enhanced plastic” are designed and intended for use in

military/aerospace applications or environments. Buyer acknowledges and agrees that any military or aerospace use of TI components

which have not been so designated is solely at the Buyer's risk, and that Buyer is solely responsible for compliance with all legal and

regulatory requirements in connection with such use.

TI has specifically designated certain components as meeting ISO/TS16949 requirements, mainly for automotive use. In any case of use of

non-designated products, TI will not be responsible for any failure to meet ISO/TS16949.

Products Applications

Audio www.ti.com/audio Automotive and Transportation www.ti.com/automotive

Amplifiers amplifier.ti.com Communications and Telecom www.ti.com/communications

Data Converters dataconverter.ti.com Computers and Peripherals www.ti.com/computers

DLP® Products www.dlp.com Consumer Electronics www.ti.com/consumer-apps

DSP dsp.ti.com Energy and Lighting www.ti.com/energy

Clocks and Timers www.ti.com/clocks Industrial www.ti.com/industrial

Interface interface.ti.com Medical www.ti.com/medical

Logic logic.ti.com Security www.ti.com/security

Power Mgmt power.ti.com Space, Avionics and Defense www.ti.com/space-avionics-defense

Microcontrollers microcontroller.ti.com Video and Imaging www.ti.com/video

RFID www.ti-rfid.com

OMAP Applications Processors www.ti.com/omap TI E2E Community e2e.ti.com

Wireless Connectivity www.ti.com/wirelessconnectivity

Mailing Address: Texas Instruments, Post Office Box 655303, Dallas, Texas 75265