DS1340C-3+ - Maxim Integrated Products, Inc.

General Description

The DS1340 is a real-time clock (RTC)/calendar that is

pin compatible and functionally equivalent to the ST

M41T00, including the software clock calibration. The

device additionally provides trickle-charge capability

on the VBACKUP pin, a lower timekeeping voltage, and

an oscillator STOP flag. Block access of the register

map is identical to the ST device. Two additional regis-

ters, which are accessed individually, are required for

the trickle charger and flag. The clock/calendar pro-

vides seconds, minutes, hours, day, date, month, and

year information. A built-in power-sense circuit detects

power failures and automatically switches to the back-

up supply. The device is programmed serially through

an I2CTM bidirectional bus.

Applications

Portable Instruments

Point-of-Sale Equipment

Medical Equipment

Telecommunications

Features

♦Enhanced Second Source for the ST M41T00

♦Available in a Surface-Mount Package with an

Integrated Crystal (DS1340C)

♦Fast (400kHz) I2C Interface

♦Software Clock Calibration

♦RTC Counts Seconds, Minutes, Hours, Day, Date,

Month, and Year

♦Automatic Power-Fail Detect and Switch Circuitry

♦Trickle-Charge Capability

♦Low Timekeeping Voltage Down to 1.3V

♦Three Operating Voltage Ranges (1.8V, 3V, and 3.3V)

♦Oscillator Stop Flag

♦Available in 8-Pin µSOP or SO Packages

♦Underwriters Laboratory (UL) Recognized

DS1340

I2C RTC with Trickle Charger

______________________________________________ Maxim Integrated Products 1

Ordering Information

CPU

VCC

SDA

SCL

GND

X2X1

VCC

RPU RPU

CRYSTAL

FT/OUT

VBACKUP

RPU = tR / CB

DS1340

Typical Operating Circuit

Rev 2; 12/04

For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at

1-888-629-4642, or visit Maxim’s website at www.maxim-ic.com.

PART TEMP RANGE PIN-PACKAGE TOP

MARK

DS1340Z-18 -40°C to +85°C 8 SO (0.150in) D1340-18

DS1340Z-3 -40°C to +85°C 8 SO (0.150in) DS1340-3

DS1340Z-33 -40°C to +85°C 8 SO (0.150in) D1340-33

DS1340U-18 -40°C to +85°C 8 µSOP 1340

A1-18

DS1340U-3 -40°C to +85°C 8 µSOP 1340

A1-3

DS1340U-33 -40°C to +85°C 8 µSOP 1340

A1-33

DS1340C-18 -40°C to +85°C 16 SO 1340C-18

DS1340C-3 -40°C to +85°C 16 SO 1340C-3

DS1340C-33 -40°C to +85°C 16 SO 1340C-33

DS1340Z-18+ -40°C to +85°C 8 SO (0.150in) D1340-18

DS1340Z-3+ -40°C to +85°C 8 SO (0.150in) DS1340-3

DS1340Z-33+ -40°C to +85°C 8 SO (0.150in) D1340-33

DS1340U-18+ -40°C to +85°C 8 µSOP 1340

A1-18

DS1340U-3+ -40°C to +85°C 8 µSOP 1340

A1-3

DS1340U-33+ -40°C to +85°C 8 µSOP 1340

A1-33

DS1340C-18+ -40°C to +85°C 16 SO 1340C-18

DS1340C-3+ -40°C to +85°C 16 SO 1340C-3

DS1340C-33+ -40°C to +85°C 16 SO 1340C-33

I2C is a trademark of Philips Corp. Purchase of I2C compo-

nents from Maxim Integrated Products, Inc., or one of its subli-

censed Associated Companies, conveys a license under the

Philips I2C Patent Rights to use these components in an I2C

system, provided that the system conforms to the I2C Standard

Specification as defined by Philips.

Note: A "+" in the part number and a "+" anywhere on the top

mark indicates a lead-free device.

Pin Configurations appear at end of data sheet.

DS1340

I2C RTC with Trickle Charger

2_____________________________________________________________________

ABSOLUTE MAXIMUM RATINGS

Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional

operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to

absolute maximum rating conditions for extended periods may affect device reliability.

Voltage Range on VCC Pin Relative to Ground .....-0.3V to +6.0V

Voltage Range on SDA, SCL, and FT/OUT

Relative to Ground..................................-0.3V to (VCC + 0.3V)

Operating Temperature Range ...........................-40°C to +85°C

Storage Temperature Range .............................-55°C to +125°C

Soldering Temperature Range............................See IPC/JEDEC

J-STD-020 Specification

AC ELECTRICAL CHARACTERISTICS

(VCC = VCC MIN to VCC MAX, TA= -40°C to +85°C, unless otherwise noted.) (Note 1, Figure 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

UNITS

Standard mode 0

100

SCL Clock Frequency fSCL Fast mode

100 400

kHz

Standard mode 4.7

Bus Free Time Between STOP

and START Conditions tBUF Fast mode 1.3 µs

Standard mode 4.0

Hold Time (Repeated) START

Condition (Note 2)

tHD:STA

Fast mode 0.6 µs

Standard mode 4.7

Low Period of SCL Clock tLOW Fast mode 1.3 µs

Standard mode 4.0

High Period of SCL Clock tHIGH Fast mode 0.6 µs

Standard mode 0 0.9

Data Hold Time (Notes 3, 4)

tHD:DAT

Fast mode 0 0.9 µs

Standard mode

250

Data Setup Time (Note 5)

tSU:DAT

Fast mode

100

Standard mode 4.7

START Setup Time tSU:STA Fast mode 0.6 µs

Standard mode

20 + 0.1CB1000

Rise Time of SDA and SCL

Signals (Note 6) tRFast mode

20 + 0.1CB300

Standard mode

20 + 0.1CB300

Fall Time of SDA and SCL Signals

(Note 6) tFFast mode

20 + 0.1CB300

Standard mode 4.7

Setup Time for STOP Condition

tSU:STO

Fast mode 0.6 µs

Capacitive Load for Each Bus

Line CB(Note 6)

400

I/O Capacitance (SCL, SDA) CI/O 10 pF

Pulse Width of Spikes that Must

be Suppressed by the Input Filter

tSP Fast mode 30 ns

Oscillator Stop Flag (OSF) Delay

tOSF (Note 7) 100 ms

DS1340

I2C RTC with Trickle Charger

_____________________________________________________________________ 3

RECOMMENDED DC OPERATING CONDITIONS

(VCC = VCC MIN to VCC MAX, TA= -40°C to +85°C, unless otherwise noted. Typical values are at VCC = 3.3V, TA= +25°C, unless

otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

UNITS

DS1340-18

1.71

1.8

1.89

DS1340-3 2.7 3.0 3.3

Supply Voltage (Note 8) VCC

DS1340-33

2.97

3.3 5.5

Input Logic 1 (SDA, SCL) VIH (Note 8)

0.7 x VCC VCC + 0.3

Input Logic 0 (SDA, SCL) VIL (Note 8)

-0.3 +0.3 x VCC

Supply Voltage, Pullup

(FT/OUT, SDA, SCL), VCC = 0V VPU (Note 8) 5.5 V

DS1340-18 1.3 3.7

DS1340-3 1.3 3.7

Backup Supply Voltage (Note 8)

VBACKUP

DS1340-33 1.3 5.5

R1 (Notes 9, 10)

250

R2 (Note 11)

2000

Trickle-Charge Current-Limiting

Resistors

R3 (Note 12)

4000

Ω

DS1340-18

1.51

1.6

1.71

DS1340-3

2.45

2.6 2.7

Power-Fail Voltage (Note 8) VPF

DS1340-33

2.70 2.88 2.97

Input Leakage (SCL, CLK) ILI -1 +1 µA

I/O Leakage (SDA, FT/OUT) ILO -1 +1 µA

VCC > 2V; VOL = 0.4V 3.0

SDA Logic 0 Output IOLSDA 1.7V < VCC < 2V; VOL = 0.2 x VCC 3.0 mA

VCC > 2V; VOL = 0.4V 3.0

1.7V < VCC < 2V; VOL = 0.2 x VCC 3.0 mA

FT/OUT Logic 0 Output IOLSQW

1.3V < VCC < 1.7V; VOL = 0.2x VCC 250 µA

DS1340-18 72 150

DS1340-3

108

200Active Supply Current (Note 13) ICCA

DS1340-33

192

300

µA

DS1340-18 60 100

DS1340-3 81 125

Standby Current (Note 14) ICCS

DS1340-33

100

150

µA

VBACKUP Leakage Current

IBACKUPLKG

VBACKUP = 3.7V 100 nA

DC ELECTRICAL CHARACTERISTICS

(VCC = 0V, VBACKUP = 3.7V, TA= -40°C to +85°C, unless otherwise noted.) (Note 1)

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

IBACKUP1

OSC ON, FT = 0 (Note 15)

800 1150

IBACKUP2

OSC ON, FT = 1 (Note 15)

850 1250

VBACKUP Current

IBACKUP3

OSC ON, FT = 0, VBACKUP = 3.0V,

TA = +25°C (Notes 15, 16)

800 1000

VBACKUP Data-Retention Current

IBACKUPDR

OSC OFF

25.0

100 nA

DS1340

I2C RTC with Trickle Charger

4_____________________________________________________________________

POWER-UP/POWER-DOWN CHARACTERISTICS

(TA= -40°C to +85°C) (Figure 2)

PARAMETER

SYMBOL

CONDITIONS

MIN TYP MAX

UNITS

Recovery at Power-Up tREC (Note 17) 2 ms

VCC Fall Time; VPF(MAX) to

VPF(MIN) tVCCF

300

µs

VCC Rise Time; VPF(MIN) to

VPF(MAX) tVCCR 0µs

WARNING: Under no circumstances are negative undershoots, of any amplitude, allowed when device is in battery-backup mode.

Note 1: Limits at -40°C are guaranteed by design and not production tested.

Note 2: After this period, the first clock pulse is generated.

Note 3: A device must internally provide a hold time of at least 300ns for the SDA signal (referred to as the VIH(MIN) of the SCL

signal) to bridge the undefined region of the falling edge of SCL.

Note 4: The maximum tHD:DAT only has to be met if the device does not stretch the low period (tLOW) of the SCL signal.

Note 5: A fast-mode device can be used in a standard-mode system, but the requirement tSU:DAT ≥to 250ns must be met. This

is automatically the case if the device does not stretch the low period of the SCL signal. If such a device does stretch the

low period of the SCL signal, it must output the next data bit to the SDA line tR MAX + tSU:DAT = 1000 + 250 = 1250ns

before the SCL line is released.

Note 6: CB—total capacitance of one bus line in pF.

Note 7: The parameter tOSF is the period of time the oscillator must be stopped for the OSF flag to be set over the 0V ≤VCC ≤

VCCMAX and 1.3V ≤VBAT ≤ 3.7V range.

Note 8: All voltages are referenced to ground.

Note 9: Measured at VCC = typ, VBACKUP = 0V, register 08h = A5h.

Note 10: The use of the 250Ωtrickle-charge resistor is not allowed at VCC > 3.63V and should not be enabled.

Note 11: Measured at VCC = typ, VBACKUP = 0V, register 08h = A6h.

Note 12: Measured at VCC = typ, VBACKUP = 0V, register 08h = A7h.

Note 13: ICCA—SCL clocking at max frequency = 400kHz.

Note 14: Specified with I2C bus inactive.

Note 15: Measured with a 32.768kHz crystal attached to the X1 and X2 pins.

Note 16: Limits at +25°C are guaranteed by design and not production tested.

Note 17: This delay applies only if the oscillator is enabled and running. If the oscillator is disabled or stopped, no power-up delay

occurs.

SDA

SCL

tHD:STA

tLOW

tHIGH

tRtF

tBUF

tHD:DAT

tSU:DAT REPEATED

START

tSU:STA

tHD:STA

tSU:STO

tSP

STOP START

Figure 1. Data Transfer on I2C Serial Bus

DS1340

I2C RTC with Trickle Charger

_____________________________________________________________________ 5

OUTPUTS

VCC

VPF(MAX)

INPUTS

HIGH-Z

RST

DON'T CARE

VALID

RECOGNIZED RECOGNIZED

VALID

VPF(MIN)

tRST

tRPU

VPF VPF

Figure 2. Power-Up/Power-Down Timing

ICCSA vs. VCC FT = 0

DS1340 toc01

VCC (V)

SUPPLY CURRENT (µA)

5.04.54.03.53.02.52.01.5

100

150

200

250

1.0 5.5

100

125

150

ICCS vs. VCC FT = 0

DS1340 toc02

VCC (V)

SUPPLY CURRENT (µA)

5.04.54.03.53.02.52.01.51.0 5.5

-1.8V

-3.0V

-3.3V

IBACKUP1 (FT = 0) vs. VBACKUP

DS1340 toc03

450

500

550

600

650

700

750

800

850

400

VBACKUP (V)

SUPPLY CURRENT (nA)

5.04.54.03.53.02.52.01.51.0 5.5

Typical Operating Characteristics

(VCC = +3.3V, TA= +25°C, unless otherwise noted.)

IBACKUP2 (FT = 1) vs. VBACKUP

DS1340 toc04

450

500

550

600

650

700

750

800

850

400

VBACKUP (V)

SUPPLY CURRENT (nA)

5.04.54.03.53.02.52.01.51.0 5.5

FT vs. VBACKUP

DS1340 toc06

VBACKUP (V)

FREQUENCY (Hz)

5.04.51.5 2.0 2.5 3.53.0 4.0

511.9965

511.9970

511.9975

511.9980

511.9985

511.9990

511.9995

512.0000

511.9960

1.0 5.5

IBACKUP3 vs. TEMPERATURE

DS1340 toc05

TEMPERATURE (°C)

SUPPLY CURRENT (nA)

6040-20 0 20

500

550

600

650

700

750

800

850

-40 80

VBACKUP = 3.0V

DS1340

Detailed Description

The DS1340 is a low-power clock/calendar with a trickle

charger. Address and data are transferred serially

through a I2C bidirectional bus. The clock/calendar pro-

vides seconds, minutes, hours, day, date, month, and

year information. The date at the end of the month is

automatically adjusted for months with fewer than 31

days, including corrections for leap year. The DS1340

has a built-in power-sense circuit that detects power fail-

ures and automatically switches to the backup supply.

Oscillator Circuit

The DS1340 uses an external 32.768kHz crystal. The

oscillator circuit does not require any external resistors

or capacitors to operate. Table 1 specifies several crys-

tal parameters for the external crystal. Figure 3 shows a

functional schematic of the oscillator circuit. If using a

crystal with the specified characteristics, the startup

time is usually less than one second.

Clock Accuracy

The initial clock accuracy depends on the accuracy of

the crystal and the accuracy of the match between the

capacitive load of the oscillator circuit and the capaci-

tive load for which the crystal was trimmed. Additional

I2C RTC with Trickle Charger

6_____________________________________________________________________

Pin Description

NAME FUNCTION

—

Connections for a Standard 32.768kHz Quartz Crystal. The internal oscillator circuitry is designed for

operation with a crystal having a specified load capacitance (CL) of 12.5pF. X1 is the input to the

oscillator and can optionally be connected to an external 32.768kHz oscillator. The output of the internal

oscillator, X2, is floated if an external oscillator is connected to X1.

14 VBACKUP

Connection for a Secondary Power Supply. For the 1.8V and 3V devices, VBACKUP must be held

between 1.3V and 3.7V for proper operation. VBACKUP can be as high as 5.5V on the 3.3V device.

This pin can be connected to a primary cell such as a lithium coin cell. Additionally, this pin can be

connected to a rechargeable cell or a super cap when used with the trickle-charge feature. UL

recognized to ensure against reverse charging when used with a lithium battery.

GND Ground

SDA Serial Data Input/Output. SDA is the data input/output for the I2C serial interface. The SDA pin is open

drain and requires an external pullup resistor.

SCL Serial Clock Input. SCL is the clock input for the I2C interface and is used to synchronize data movement

on the serial interface.

2FT/OUT

Frequency Test/Output. This pin is used to output either a 512Hz signal or the value of the OUT bit. When

the FT bit is logic 1, the FT/OUT pin toggles at a 512Hz rate. When the FT bit is logic 0, the FT/OUT pin

reflects the value of the OUT bit. This open-drain pin requires an external pullup resistor, and operates

with either VCC or VBACKUP applied.

VCC DC Power for Primary Power Supply

—

4–13

N.C. No Connection. Must be connected to ground.

PARAMETER SYMBOL MIN TYP MAX UNITS

Nominal

Frequency fO32.768 kHz

Series Resistance ESR 45,60** kΩ

Load Capacitance CL12.5 pF

Table 1. Crystal Specifications*

*The crystal, traces, and crystal input pins should be isolated

from RF generating signals. Refer to Application Note 58:

Crystal Considerations for Dallas Real-Time Clocks for addi-

tional specifications.

**A crystal with up to 60kΩESR can be used if the minimum

operating voltages on both VCC and VBACKUP are at least 2.0V.

COUNTDOWN

CHAIN

RTC

X1 X2

CL1CL2

CRYSTAL

RTC

REGISTERS

Figure 3. Oscillator Circuit Showing Internal Bias Network

error is added by crystal frequency drift caused by

temperature shifts. External circuit noise coupled into

the oscillator circuit can result in the clock running fast.

Figure 4 shows a typical PC board layout for isolating

the crystal and oscillator from noise. Refer to

Application Note 58: Crystal Considerations with Dallas

Real-Time Clocks (www.maxim-ic.com/RTCapps) for

detailed information.

DS1340C Only

The DS1340C integrates a standard 32,768Hz crystal

into the package. Typical accuracy with nominal VCC

and +25°C is approximately +15ppm. Refer to

Application Note 58 for information about crystal accu-

racy vs. temperature.

Operation

The DS1340 operates as a slave device on the serial

bus. Access is obtained by implementing a START

condition and providing a device identification code fol-

lowed by data. Subsequent registers can be accessed

sequentially until a STOP condition is executed. The

device is fully accessible and data can be written and

read when VCC is greater than VPF. However, when

VCC falls below VPF, the internal clock registers are

blocked from any access. If VPF is less than VBACKUP,

the device power is switched from VCC to VBACKUP

when VCC drops below VPF. If VPF is greater than

VBACKUP, the device power is switched from VCC to

VBACKUP when VCC drops below VBACKUP. The regis-

ters are maintained from the VBACKUP source until VCC

is returned to nominal levels. The functional diagram

(Figure 5) shows the main elements of the serial RTC.

Address Map

Table 2 shows the DS1340 address map. The RTC reg-

isters are located in address locations 00h to 06h, and

the control register is located at 07h. The trickle-charge

DS1340

I2C RTC with Trickle Charger

_____________________________________________________________________ 7

CRYSTAL

GND

LOCAL GROUND PLANE (LAYER 2)

Figure 4. Layout Example

SERIAL BUS

INTERFACE

AND ADDRESS

OSCILLATOR

CONTROL

LOGIC

"C" VERSION ONLY

SCL

SDA

512Hz

MUX/BUFFER

FT/OUT

USER BUFFER

(7 BYTES)

CLOCK AND

CALENDAR

REGISTERS

32,768Hz

1Hz

POWER

CONTROL

VCC

VBACKUP

DIVIDER AND

CALIBRATION

CIRCUIT

DS1340

Figure 5. Functional Diagram

ADDRESS

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2 BIT 1

BIT 0

FUNCTION RANGE

00H

EOSC

10 Seconds Seconds Seconds 00–59

01H X 10 Minutes Minutes Minutes 00–59

02H CEB CB 10 Hours Hours

Century/Hours

0–1; 00–23

03H X X X X X Day Day 01–07

04H X X 10 Date Date Date 01–31

05H X X X

10 Month

Month Month 01–12

06H 10 Year Year Year 00–99

07H OUT FT S CAL4

CAL3

CAL2 CAL1

CAL0

Control —

08H

TCS3 TCS2 TCS1

TCS0

DS1

DS0

ROUT1 ROUT0 Trickle Charger

—

09H OSF 0 0 0 0 0 0 0 Flag —

Table 2. Address Map

X = Read/Write bit

Note: Unless otherwise specified, the state of the registers is not defined when power is first applied.

DS1340

and flag registers are located in address locations 08h

to 09h. During a multibyte access of the timekeeping

registers, when the address pointer reaches 07h—the

end of the clock and control register space—it wraps

around to location 00h. Writing the address pointer to

the corresponding location accesses address locations

08h and 09h. After accessing location 09h, the address

pointer wraps around to location 00h. On a I2CSTART,

STOP, or address pointer incrementing to location 00h,

the current time is transferred to a second set of regis-

ters. The time information is read from these secondary

registers, while the clock may continue to run. This

eliminates the need to reread the registers in case the

main registers update during a read.

Clock and Calendar

The time and calendar information is obtained by read-

ing the appropriate register bytes. Table 2 shows the

RTC registers. The time and calendar data are set or

initialized by writing the appropriate register bytes. The

contents of the time and calendar registers are in the

binary-coded decimal (BCD) format. The day-of-week

to the day of week are user-defined but must be

sequential (i.e., if 1 equals Sunday, then 2 equals

Monday, and so on). Illogical time and date entries

result in undefined operation. Bit 7 of register 0 is the

enable oscillator (EOSC) bit. When this bit is set to 1, the

oscillator is disabled. When cleared to 0, the oscillator is

enabled. The initial power-up value of EOSC is 0.

Location 02h is the century/hours register. Bit 7 and bit

6 of the century/hours register are the century-enable

bit (CEB) and the century bit (CB). Setting CEB to logic

1 causes the CB bit to toggle, either from a logic 0 to a

logic 1, or from a logic 1 to a logic 0, when the years

CB does not toggle.

When reading or writing the time and date registers,

secondary (user) buffers are used to prevent errors

when the internal registers update. When reading the

time and date registers, the user buffers are synchro-

nized to the internal registers on any START or STOP

and when the register pointer rolls over to zero. The

time information is read from these secondary registers

while the clock continues to run. This eliminates the

need to reread the registers in case the internal regis-

ters update during a read.

The divider chain is reset whenever the seconds regis-

ter is written. Write transfers occur on the acknowledge

from the DS1340. Once the divider chain is reset, to

avoid rollover issues, the remaining time and date reg-

isters must be written within one second.

Special-Purpose Registers

The DS1340 has three additional registers (control,

trickle charger, and flag) that control the RTC, trickle

charger, and oscillator flag output.

Control Register (07h)

Bit 7: Output Control (OUT). This bit controls the out-

put level of the FT/OUT pin when the FT bit is set to 0. If

FT = 0, the logic level on the FT/OUT pin is 1 if OUT = 1

and 0 if OUT = 0. The initial power-up OUT value is 1.

I2C RTC with Trickle Charger

8_____________________________________________________________________

BIT 7

TCS3

1 OF 16 SELECT

NOTE: ONLY 1010b

ENABLES CHARGER

1 OF 2

SELECT

VCC VBACKUP

250Ω

TCS0-3 = TRICKLE-CHARGER SELECT

DS0-1 = DIODE SELECT

TOUT0-1 = RESISTOR SELECT

2kΩ

4kΩ

1 OF 3

SELECT

BIT 6

TCS2

BIT 5

TCS1

BIT 4

TCS0

BIT 3

DS1

BIT 2

DS0

BIT 1

ROUT1

BIT 0

ROUT0

Figure 6. Trickle Charger Functional Diagram

Bit 6: Frequency Test (FT). When this bit is 1, the

FT/OUT pin toggles at a 512Hz rate. When FT is written

to 0, the OUT bit controls the state of the FT/OUT pin.

The initial power-up value of FT is 0.

Bit 5: Calibration Sign Bit (S). A logic 1 in this bit indi-

cates positive calibration for the RTC. A 0 indicates

negative calibration for the clock. See the Clock

Calibration section for a detailed description of the bit

operation. The initial power-up value of S is 0.

Bits 4 to 0: Calibration Bits (CAL4 to CAL0). These

bits can be set to any value between 0 and 31 in binary

form. See the Clock Calibration section for a detailed

description of the bit operation. The initial power-up

value of CAL0–CAL4 is 0.

Trickle-Charger Register (08h)

The simplified schematic in Figure 6 shows the basic

components of the trickle charger. The trickle-charge

select (TCS) bits (bits 4–7) control the selection of the

trickle charger. To prevent accidental enabling, only a

pattern on 1010 enables the trickle charger. All other

patterns disable the trickle charger. The trickle charger

is disabled when power is first applied. The diode-

select (DS) bits (bits 2, 3) select whether or not a diode

is connected between VCC and VBACKUP. If DS is 01,

no diode is selected; if DS is 10, a diode is selected.

The ROUT bits (bits 0, 1) select the value of the resistor

connected between VCC and VBACKUP. Table 3 shows

the resistor selected by the resistor select (ROUT) bits

and the diode selected by the diode select (DS) bits.

Warning: The ROUT value of 250Ωmust not be select-

ed whenever VCC is greater than 3.63V.

The user determines diode and resistor selection

according to the maximum current desired for battery

or super cap charging (Table 3). The maximum charg-

ing current can be calculated as illustrated in the fol-

lowing example.

Assume that a 3.3V system power supply is applied to

VCC and a super cap is connected to VBACKUP. Also

assume that the trickle charger has been enabled with

a diode and resistor R2 between VCC and VBACKUP.

The maximum current IMAX would therefore be calculat-

ed as follows:

IMAX = (3.3V - diode drop) / R2 ≈(3.3V - 0.7V) /

2kΩ≈1.3mA

As the super cap charges, the voltage drop between

VCC and VBACKUP decreases and therefore the charge

current decreases.

Flag Register (09h)

Bit 7: Oscillator Stop Flag (OSF). A logic 1 in this bit

indicates that the oscillator has stopped or was

stopped for some time period and may be used to

judge the validity of the clock and calendar data. This

bit is edge triggered and is set to logic 1 when the

internal circuitry senses that the oscillator has transi-

tioned from a normal run state to a STOP condition. The

following are examples of conditions that can cause the

OSF bit to be set:

1) The first time power is applied.

2) The voltages present on VCC and VBACKUP

are insufficient to support oscillation.

3) The EOSC bit is set to 1, disabling the

oscillator.

4) External influences on the crystal (e.g., noise,

leakage).

The OSF bit remains at logic 1 until written to logic 0. It

can only be written to logic 0. Attempting to write OSF

to logic 1 leaves the value unchanged.

DS1340

I2C RTC with Trickle Charger

_____________________________________________________________________ 9

TCS3 TCS2 TCS1 TCS0 DS1 DS0

ROUT1 ROUT0

FUNCTION

XXXX00XXDisabled

XXXX11XXDisabled

XXXXXX00Disabled

10100101No diode, 250Ω resistor

10101001One diode, 250Ω resistor

10100110No diode, 2kΩ resistor

10101010One diode, 2kΩ resistor

10100111No diode, 4kΩ resistor

10101011One diode, 4kΩ resistor

00000000Power-on reset value

Table 3. Trickle-Charge Register

DS1340

Bits 6 to 0: All other bits in the flag register read as 0

and cannot be written.

Clock Calibration

The DS1340 provides a digital clock calibration feature

to allow compensation for crystal and temperature vari-

ations. The calibration circuit adds or subtracts counts

from the oscillator divider chain at the divide-by-256

stage. The number of pulses blanked (subtracted for

negative calibration) or inserted (added for positive cal-

ibration) depends upon the value loaded into the five

calibration bits (CAL4–CAL0) located in the control reg-

ister. Adding counts speeds the clock up and subtract-

ing counts slows the clock down.

The calibration bits can be set to any value between 0

and 31 in binary form. Bit 5 of the control register, S, is

the sign bit. A value of 1 for the S bit indicates positive

calibration, while a value of 0 represents negative cali-

bration. Calibration occurs within a 64-minute cycle.

The first 62 minutes in the cycle can, once per minute,

have a one-second interval where the calibration is per-

formed. Negative calibration blanks 128 cycles of the

32,768Hz oscillator, slowing the clock down. Positive

calibration inserts 256 cycles of the 32,768Hz oscillator,

speeding the clock up. If a binary 1 is loaded into the

calibration bits, only the first two minutes in the 64-

minute cycle are modified. If a binary 6 is loaded, the

first 12 minutes are affected, and so on. Therefore,

each calibration step either adds 512 or subtracts 256

oscillator cycles for every 125,829,120 actual 32,678Hz

oscillator cycles (64 minutes). This equates to

+4.068ppm or -2.034ppm of adjustment per calibration

step. If the oscillator runs at exactly 32,768Hz, each of

the 31 increments of the calibration bits would repre-

sent +10.7 or -5.35 seconds per month, corresponding

to +5.5 or -2.75 minutes per month.

For example, if using the FT function, a reading of

512.01024Hz would indicate a +20ppm oscillator fre-

quency error, requiring a -10(00 1010) value to be

loaded in the S bit and the five calibration bits.

Note: Setting the calibration bits does not affect the fre-

quency test output frequency. Also note that writing to

the control register resets the divider chain.

I2C Serial Data Bus

The DS1340 supports a bidirectional I2Cbus and data

transmission protocol. A device that sends data onto

the bus is defined as a transmitter and a device receiv-

ing data as a receiver. The device that controls the

message is called a master. The devices that are con-

trolled by the master are slaves. A master device that

generates the serial clock (SCL), controls the bus

access, and generates the START and STOP condi-

tions must control the bus. The DS1340 operates as a

slave on the I2Cbus. Connections to the bus are made

through the open-drain I/O lines SDA and SCL. Within

the bus specifications a standard mode (100kHz max

clock rate) and a fast mode (400kHz max clock rate)

are defined. The DS1340 works in both modes.

The following bus protocol has been defined (Figure 7):

•Data transfer can be initiated only when the bus is

not busy.

•During data transfer, the data line must remain

stable whenever the clock line is high. Changes in

the data line while the clock line is high are inter-

preted as control signals.

I2C RTC with Trickle Charger

10 ____________________________________________________________________

STOP

CONDITION

OR REPEATED

START

CONDITION

REPEATED IF MORE BYTES

ARE TRANSFERED

ACK

START

CONDITION

ACK

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

ACKNOWLEDGEMENT

SIGNAL FROM RECEIVER

SLAVE ADDRESS

MSB

SCL

SDA

R/W

DIRECTION

BIT

12 678 9 12 893–7

Figure 7. I2C Data Transfer Overview

Accordingly, the following bus conditions have been

defined:

Bus not busy: Both data and clock lines remain

high.

START data transfer: A change in the data line’s

state from high to low, while the clock line is high,

defines a START condition.

STOP data transfer: A change in the data line’s

state from low to high, while the clock line is high,

defines a STOP condition.

Data valid: The data line’s state represents valid

data when, after a START condition, the data line is

stable for the duration of the high period of the

clock signal. The data on the line must be changed

during the low period of the clock signal. There is

one clock pulse per bit of data.

Each data transfer is initiated with a START condi-

tion and terminated with a STOP condition. The

number of data bytes transferred between the

START and STOP conditions is not limited, and is

determined by the master device. The information

is transferred byte-wise and each receiver

acknowledges with a ninth bit.

Acknowledge: Each receiving device, when

addressed, is obliged to generate an acknowl-

edge after the reception of each byte. The master

device must generate an extra clock pulse that is

associated with this acknowledge bit.

A device that acknowledges must pull down the

SDA line during the acknowledge clock pulse in

such a way that the SDA line is stable low during

the high period of the acknowledge-related clock

pulse. Setup and hold times must be taken into

account. A master must signal an end of data to

the slave by not generating an acknowledge bit on

the last byte that has been clocked out of the

slave. In this case, the slave must leave the data

line high to enable the master to generate the

STOP condition.

Figures 8 and 9 detail how data transfer is accom-

plished on the I2Cbus. Depending upon the state of

the R/Wbit, two types of data transfer are possible:

Data transfer from a master transmitter to a

slave receiver. The first byte transmitted by the

master is the slave address. Next follows a num-

ber of data bytes. The slave returns an acknowl-

edge bit after each received byte.

Data transfer from a slave transmitter to a mas-

ter receiver. The master transmits the first byte (the

slave address). The slave then returns an acknowl-

edge bit. Next follows a number of data bytes trans-

mitted by the slave to the master. The master

returns an acknowledge bit after all received bytes

other than the last byte. At the end of the last

received byte, a not acknowledge is returned.

The master device generates all the serial clock

pulses and the START and STOP conditions. A

transfer is ended with a STOP condition or with a

repeated START condition. Since a repeated

START condition is also the beginning of the next

serial transfer, the bus is not released.

The DS1340 can operate in the following two modes:

Slave Receiver Mode (Write Mode): Serial data

and clock are received through SDA and SCL.

After each byte is received, an acknowledge bit is

transmitted. Start and STOP conditions are recog-

nized as the beginning and end of a serial trans-

fer. Hardware performs address recognition after

reception of the slave address and direction bit.

The slave address byte is the first byte received

after the master generates the START condition.

The slave address byte contains the 7-bit DS1340

address, which is 1101000, followed by the direc-

tion bit (R/W), which is 0 for a write. After receiving

and decoding the slave address byte, the DS1340

outputs an acknowledge on SDA. After the

DS1340 acknowledges the slave address + write

bit, the master transmits a word address to the

DS1340. This sets the register pointer on the

DS1340, with the DS1340 acknowledging the

transfer. The master can then transmit zero or

DS1340

I2C RTC with Trickle Charger

____________________________________________________________________ 11

AXXXXXXXXA1101000S 0 XXXXXXXX A XXXXXXXX A XXXXXXXX A P

<SLAVE

ADDRESS>

S — START

A — ACKNOWLEDGE

P — STOP

R/W — READ/WRITE OR DIRECTION BIT ADDRESS = D0H

<RW>

DATA TRANSFERRED

(X + 1 BYTES + ACKNOWLEDGE)

<WORD

ADDRESS (n)>

Figure 8. Slave Receiver Mode (Write Mode)

AXXXXXXXXA1101000S 1 XXXXXXXX A XXXXXXXX A XXXXXXXX A P

<SLAVE

ADDRESS>

S — START

A — ACKNOWLEDGE

P — STOP

A — NOT ACKNOWLEDGE

R/W — READ/WRITE OR DIRECTION BIT ADDRESS = D0H

<RW>

DATA TRANSFERRED

(X + 1 BYTES + ACKNOWLEDGE)

NOTE: LAST DATA BYTE IS FOLLOWED BY

A NOT ACKNOWLEDGE (A) SIGNAL

Figure 9. Slave Transmitter Mode (Read Mode

DS1340

I2C RTC with Trickle Charger

12 ____________________________________________________________________

more bytes of data, with the DS1340 acknowledg-

ing each byte received. The register pointer incre-

ments after each data byte is transferred. The

master generates a STOP condition to terminate

the data write.

Slave Transmitter Mode (Read Mode): The first

byte is received and handled as in the slave

receiver mode. However, in this mode, the direc-

tion bit indicates that the transfer direction is

reversed. The DS1340 transmits serial data on

SDA while the serial clock is input on SCL. Start

and STOP conditions are recognized as the begin-

ning and end of a serial transfer. Hardware per-

forms address recognition after reception of the

slave address and direction bit. The slave address

byte is the first byte received after the master gen-

erates the START condition. The slave address

byte contains the 7-bit DS1340 address, which is

1101000, followed by the direction bit (R/W),

which is 1 for a read. After receiving and decoding

the slave address byte, the DS1340 outputs an

acknowledge on SDA. The DS1340 then begins to

transmit data starting with the register address

pointed to by the register pointer. If the register

pointer is not written to before the initiation of a

read mode, the first address that is read is the last

one stored in the register pointer. The DS1340

must receive a not acknowledge to end a read.

Handling, PC Board

Layout, and Assembly

The DS1340C package contains a quartz tuning-fork

crystal. Pick-and-place equipment may be used, but

precautions should be taken to ensure that excessive

shocks are avoided. Ultrasonic cleaning should be

avoided to prevent damage to the crystal.

Avoid running signal traces under the package, unless

a ground plane is placed between the package and the

signal line. All N.C. (no connect) pins must be connect-

ed to ground.

The SO package may be reflowed as long as the peak

temperature does not exceed 240°C. Peak reflow tem-

perature (≥230°C) duration should not exceed 10 sec-

onds, and the total time above 200°C should not

exceed 40 seconds (30 seconds nominal). Exposure to

reflow is limited to 2 times maximum.

Moisture-sensitive packages are shipped from the facto-

ry dry-packed.Handling instructions listed on the pack-

age label must be followed to prevent damage during

reflow. Refer to the IPC/JEDEC J-STD-020 standard for

moisture-sensitive device (MSD) classifications.

VCC

FT/OUT

SCL

SDA

VBACKUP

GND

TOP VIEW

DS1340

SO, µSOP

DS1340C

SCL SDA

GND

VBACKUP

N.C.

SO (300 mils)

FT/OUT

VCC

N.C.

Pin Configurations

DS1340

I2C RTC with Trickle Charger

Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are

implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.

Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13

is a registered trademark of Dallas Semiconductor Corporation.

Package Information

For the latest package outline information, go to

www.maxim-ic.com/DallasPackInfo.

Chip Information

TRANSISTOR COUNT: 10,930

PROCESS: CMOS

SUBSTRATE CONNECTED TO GROUND

Thermal Information

Theta-JA: +170°C/W (0.150in SO)

Theta-JC: +40°C/W (0.150in SO)

Theta-JA: +221°C/W (µSOP)

Theta-JC: +39°C/W (µSOP)

Theta-JA: +89.6°C/W (0.300in SO)

Theta-JC: +24.8°C/W (0.300in SO)