PIC24FJ256GB106-I/PT - Microchip Technology

 2011 Microchip Technology Inc. DS39907B-page 1

PIC24FJXXXGA1/GB1

1.0 DEVICE OVERVIEW

This document defines the programming specification

for the PIC24FJXXXGA1/GB1 families of 16-bit

microcontroller devices. This programm ing s pecification

is required only for those developing programming

support for the PIC24FJXXXGA1/GB1 families.

Custo me rs using only o ne of these devic es s hould us e

development tools that already provide support for

device programming.

This spe ci fic ation incl udes pr ogra mming spec ific ations

for the following devices:

2.0 PROGRAMMING OVERVIEW

OF THE PIC24FJXXXGA1/GB1

FAMILIES

There are two methods of programming the

PIC24FJXXXGA1/GB1 families of devices discussed

in this programming specification. They are:

• In-Circuit Serial Programming™ (ICSP™)

• Enhanced In-Circuit Serial Programming

(Enhanced ICSP)

The ICSP programming method is the most direct

method to program the device; however, it is also the

slowe r o f the two me tho ds . It provides nati ve , l ow -l evel

programming capability to erase, program and verify

the chip.

The Enhanced In-Circuit Serial Programming

(Enhanced ICSP) protocol uses a faster method that

takes advantage of the programming executive, as

illustrated in Figure 2-1. The programming executive

provides all the necessary functionality to erase, pro-

gram and verify the chip throug h a small co mmand se t.

The command set allows the programmer to program

the PIC24FJXXXGA1/GB1 devices without having to

deal with the low-level programming protocols of the

chip.

FIGURE 2-1: PROGRAMMING SYSTEM

OVERVIEW FOR

ENHANCED ICSP™

This specification is divided into major sections that

describe the programming methods independently.

Section 4.0 “Device Programming – Enhanced

ICSP” describes the Run-Time Self-Programming

(RTSP) method. Section 3.0 “Device Programming –

ICSP” describes the In-Circuit Serial Programming

method.

• PIC24FJ256GA106 • PIC24FJ256GB106

• PIC24FJ256GA108 • PIC24FJ256GB108

• PIC24FJ256GA110 • PIC24FJ256GB110

• PIC24FJ192GA106 • PIC24FJ192GB106

• PIC24FJ192GA108 • PIC24FJ192GB108

• PIC24FJ192GA110 • PIC24FJ192GB110

• PIC24FJ128GA106 • PIC24FJ128GB106

• PIC24FJ128GA108 • PIC24FJ128GB108

• PIC24FJ128GA110 • PIC24FJ128GB110

• PIC24FJ64GA106 • PIC24FJ64GB106

• PIC24FJ64GA108 • PIC24FJ64GB108

• PIC24FJ64GA110 • PIC24FJ64GB110

PIC24FJXXXGA1/GB1

Programmer Programming

Executive

On-Chip Memory

PIC24FJXXXGA1/GB1 Families Flash

Programming Specification

PIC24FJXXXGA1/GB1

DS39907B-page 2  2011 Microchip Technology Inc.

2.1 Power Requirements

All devices in the PIC24FJXXXGA1/GB1 families are

dual voltage supply designs: one supply for the core

and perip herals , and ano ther for th e I/O pin s. A regula-

tor is provided on-chip to alleviate the need for two

external voltage supplies.

All PIC24FJXXXGA1/GB1 devices power their core

digital logic at a nominal 2.5V. To simplify system

design, all devices in the PIC24FJXXXGA1/GB1 fami-

lies incorporate an on-chip regulator that allows the

device to run its core logic from VDD.

The regulator provides power to the core from the other

VDD pins. A l ow-E S R capac it or ( s uch a s tan talu m) mu st

be connected to the VDDCORE pin (Table 2-1 and

Figure 2-2). This helps to maintain the stability of the

regulator. The specifications for core voltage and capac-

it ance are li sted in Secti on 7.0 “AC/DC Characteristics

and Ti ming Req uireme nt s”.

2.2 Program Memory Write/Erase

Requirements

The Flas h prog ram memory on PIC24 FJXXXGA1/GB1

devices has a specific write/erase requirement that

must be adhered to for proper device operation. The

rule is that an y give n wor d in memo ry must no t be writ-

ten more than twice before eras in g the page in wh ic h it

is loc ated. Thus, the e asiest way to confo rm to this rule

is to write all the data in a programming block within

one write cycle. The programming methods specified in

this specification comply with this requirement.

2.3 Pin Diagrams

The pin diagrams for the PIC24FJXXXGA1/GB1 fami-

lies are sh own in the following figures. The pins that are

required for programming are listed in Table 2-1 and

are shown in bold letters in the figures. Refer to the

appropriate device data sheet for complete pin

descriptions.

2.3.1 PGCx AND PGDx PIN PAIRS

All of the devices in the PIC24FJXXXGA1/GB1 fami lies

have three separate pairs of programming pins,

labelled as PGEC1/PGED1, PGEC2/PGED2, and

PGEC3/PGED3. Any one of these pin pairs may be

used for device programming by either ICSP or

Enhanced ICSP. Unlike voltage supply and ground

pins, it i s not nec essary to con nect all th ree pin p airs to

program the device. However, the programming

method must use both pins of the same pair.

FIGURE 2-2: CONNECTIONS FOR THE

ON-C HI P REGU LA TOR

Note: Writing to a location multiple times without

erasing i s not recommended.

VDD

ENVREG

VDDCORE/VCAP

VSS

PIC24FJXXXGA1/GB1

CEFC

3.3V

Regulator Enabled (ENVREG tied to VDD):

(10 F typ)

Note 1: These are ty pical op erating voltages. Refer

Section 7.0 “AC/DC Characteristics and

Timing Requ irement s”

for the full operating

ranges of VDD and VDDCORE.

VDD

ENVREG

VDDCORE/VCAP

VSS

PIC24FJXXXGA1/GB1

3.3V(1)

2.5V(1)

Regulator Disabled (ENVREG tied to ground):

VDD

ENVREG

VDDCORE/VCAP

VSS

PIC24FJXXXGA1/GB1

2.5V(1)

Regulator Disabled (VDD tied to VDDCORE):

 2011 Microchip Technology Inc. DS39907B-page 3

PIC24FJXXXGA1/GB1

TABLE 2-1: PIN DESCRIPTIONS (DURING PROGRAMMING)

FIGURE 2-3: PIN DIAGRAMS

Pin Name During Programming

Pin Name Pin Type Pin Description

MCLR MCLR P Programmi ng Enable

ENVREG ENVREG I Enable for On-Chip Voltage Regulator

VDD and AVDD(1) VDD P Power Supply

VSS and AVSS(1) VSS PGround

VDDCORE VDDCORE P Regulated Power Supply for Core

PGECx PGCx I Programming Pin Pairs 1, 2 and 3: Serial Clock

PGEDx PGDXI/O Programming Pin Pairs 1, 2 and 3: Serial Data

Legend: I = Input, O = Output, P = Power

Note 1: All power supply and ground pins must be connected, including analog supplies (AVDD) and ground

(AVSS).

PIC24FJXXXGA106

RD6

RD5

RD4

RD3

RD2

RD1

RE4

RE3

RE2

RE1

RF0

VCAP/VDDCORE

RC13

RD0

RD9

RD8

RC15

RC12

VDD

RG2

RF6

RF2

RF3

RG3

AVDD

RB8

RB9

RB10

RB11

VDD

PGEC2/AN6/RP6/CN24/RB6

PGED2/AN7/RP7/CN25/RB7

RF5

RF4

RE5

RE6

RE7

RG6

VDD

PGEC3/AN5/RP18/C1INA/CN7/RB5

PGED3/AN4/RP28/C1INB/CN6/RB4

RB3

RB2

RG7

RG8

PGEC1/AN1/RP1/VREF-/CN3/RB1

PGED1/AN0/RP0/PMA6/VREF+/

RG9

MCLR

RB12

RB13

RB14

RB15

RE0

RF1

RD7

VSS

ENVREG

AVSS

RC14

CN2/RB0

RD10

RD11

64-Pin TQFP

PIC24FJXXXGA1/GB1

DS39907B-page 4  2011 Microchip Technology Inc.

FIGURE 2-4: PIN DIAGRAMS (CONTINUED

PIC24FJXXXGA108

RD5

RD4

RD13

RD12

RD3

RD2

RD1

RE2

RE1

RE0

RG0

RE4

RE3

RF0

VCAP/VDDCORE

RC13

RD0

RD9

RD8

RA15

RA14

RC15

RC12

VDD

RG2

RF6

RF7

RF8

RG3

RF2

RF3

RA10

RA9

AVDD

RB8

RB9

RB10

RB11

VDD

RD14

RD15

PGEC2/AN6/RP6/CN24/RB6

PGED2/AN7/RP7/CN25/RB7

RF5

RF4

RE5

RE6

RE7

RC1

RC3

RG6

VDD

CN66/RE8

CN67/RE9

PGEC3/AN5/RP18/

PGED3/AN4/RP28/ RB3

RB2

RG7

RG8

PGEC1/AN1/RP1/CN3/RB1

PGED1/AN0/RP0/CN2/RB0

RG9

MCLR

RB12

RB13

RB14

RB15

RG1

RF1

RD7

RD6

VSS

ENVREG

AVSS

C1INA/CN7/RB5

C1INB/CN6/RB4

RC14

RD10

RD11

80-Pin TQFP

 2011 Microchip Technology Inc. DS39907B-page 5

PIC24FJXXXGA1/GB1

FIGURE 2-5: PIN DIAGRAMS (CONTINUED)

100-Pin TQFP

PIC24FJXXXGA110

100

RD5

RD4

RD13

RD12

RD3

RD2

RD1

RA7

RA6

RE2

RG13

RG12

RG14

RE1

RE0

RG0

RE4

RE3

RF0

VCAP/VDDCORE

RC13

RD0

RD9

RD8

RA15

RA14

RC15

RC12

VDD

RG2

RF6

RF7

RF8

RG3

RF2

RF3

VSS

RA10

RA9

AVDD

AVSS

RB8

RB9

RB10

RB11

VDD

RF12

RF13

VSS

VDD

RD15

RD14

PGEC2/AN6/RP6/CN24/RB6

PGED2/AN7/RP7/RCV/CN25/RB7

RF5

RF4

RE5

RE6

RE7

RC1

RC2

RC3

RC4

RG6

VDD

RA0

RE8

RE9

RB3

RB2

RG7

RG8

PGEC1/AN1/RP1/CN3/RB1

PGED1/AN0/RP0/CN2/RB0

RG15

VDD

RG9

MCLR

RB12

RB13

RB14

RB15

RG1

RF1

RD7

RD6

RA5

RA3

RA2

VSS

ENVREG

RA4

RA1

RC14

RD10

RD11

PGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5

PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4

PIC24FJXXXGA1/GB1

DS39907B-page 6  2011 Microchip Technology Inc.

FIGURE 2-6: PIN DIAGRAMS (CONTINUED)

PIC24FJXXXGB106

RD6

RD5

RD4

RD3

RD2

RD1

RE4

RE3

RE2

RE1

RF0

VCAP/VDDCORE

RC13

RD0

RD9

RD8

RC15

RC12

VDD

D+/RG2

VUSB

VBUS

RF3

D-/RG3

AVDD

RB8

RB9

RB10

RB11

VDD

PGEC2/AN6/RP6/CN24/RB6

PGED2/AN7/RP7/RCV/CN25/RB7

RF5

RF4

RE5

RE6

RE7

RG6

VDD

PGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5

PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4

RB3

RB2

RG7

RG8

PGEC1/AN1/RP1/VREF-/CN3/RB1

PGED1/AN0/RP0/PMA6/VREF+/

RG9

MCLR

RB12

RB13

RB14

RB15

RE0

RF1

RD7

VSS

ENVREG

AVSS

RC14

CN2/RB0

RD10

RD11

64-Pin TQFP

 2011 Microchip Technology Inc. DS39907B-page 7

PIC24FJXXXGA1/GB1

FIGURE 2-7: PIN DIAGRAMS (CONTINUED)

PIC24FJXXXGB108

RD5

RD4

RD13

RD12

RD3

RD2

RD1

RE2

RE1

RE0

RG0

RE4

RE3

RF0

VCAP/VDDCORE

RC13

RD0

RD9

RD8

RA15

RA14

RC15

RC12

VDD

D+/RG2

VUSB

VBUS

RF8

D-/RG3

RF2

RF3

RA10

RA9

AVDD

RB8

RB9

RB10

RB11

VDD

RD14

RD15

PGEC2/AN6/RP6/CN24/RB6

PGED2/AN7/RP7/RCV/CN25/RB7

RF5

RF4

RE5

RE6

RE7

RC1

RC3

RG6

VDD

CN66/RE8

CN67/RE9

PGEC3/AN5/RP18/VBUSON/

PGED3/AN4/RP28/USBOEN/ RB3

RB2

RG7

RG8

PGEC1/AN1/RP1/CN3/RB1

PGED1/AN0/RP0/CN2/RB0

RG9

MCLR

RB12

RB13

RB14

RB15

RG1

RF1

RD7

RD6

VSS

ENVREG

AVSS

C1INA/CN7/RB5

C1INB/CN6/RB4

RC14

RD10

RD11

80-Pin TQFP

PIC24FJXXXGA1/GB1

DS39907B-page 8  2011 Microchip Technology Inc.

FIGURE 2-8: PIN DIAGRAMS (CONTINUED)

PIC24FJXXXGB110

100

RD5

RD4

RD13

RD12

RD3

RD2

RD1

RA7

RA6

RE2

RG13

RG12

RG14

RE1

RE0

RG0

RE4

RE3

RF0

VCAP/VDDCORE

RC13

RD0

RD9

RD8

RA15

RA14

RC15

RC12

VDD

D+/RG2

VUSB

VBUS

RF8

D-/RG3

RF2

RF3

VSS

RA10

RA9

AVDD

AVSS

RB8

RB9

RB10

RB11

VDD

RF12

RF13

VSS

VDD

RD15

RD14

PGEC2/AN6/RP6/CN24/RB6

PGED2/AN7/RP7/RCV/CN25/RB7

RF5

RF4

RE5

RE6

RE7

RC1

RC2

RC3

RC4

RG6

VDD

RA0

RE8

RE9

RB3

RB2

RG7

RG8

PGEC1/AN1/RP1/CN3/RB1

PGED1/AN0/RP0/CN2/RB0

RG15

VDD

RG9

MCLR

RB12

RB13

RB14

RB15

RG1

RF1

RD7

RD6

RA5

RA3

RA2

VSS

ENVREG

RA4

RA1

RC14

RD10

RD11

PGEC3/AN5/RP18/VBUSON/C1INA/CN7/RB5

PGED3/AN4/RP28/USBOEN/C1INB/CN6/RB4

100-Pin TQFP

 2011 Microchip Technology Inc. DS39907B-page 9

PIC24FJXXXGA1/GB1

2.4 Memory Map

The program memory map extends from 000000h to

FFFFFEh. Code storage is located at the base of the

memory ma p an d suppo rts up to 87K i nstructio n word s

(about 256 Kbytes). Table 2-2 shows the program

memory size, and number of erase and program blocks

present in each device variant. Each erase block, or

page, contains 512 instructions, and each program

block, or row, contains 64 instructions.

Locations, 800000h through 8007FEh, are reserved for

executive code memory. This region stores the

programming executive and the debugging executive.

The programming executive is used for device pro-

gramming and the debugging executive is used for

in-circ uit d eb ugg ing. This region of me mo ry c an not b e

use d to store us er code.

The last thre e impleme nted program mem ory location s

are reserved for the Flash Configuration Words. In

PIC24FJXXXGB1 family devices, the last three loca-

tions are used for the Configuration Words; for

PIC24FJXXXGA1 devices, the last two locations are

used. Th e re served addresse s are s ho w n in Table 2-2.

Locatio ns, FF0000h and FF00 02h, are reserv ed for th e

Device ID registers. These bits can be used by the

programmer to identify what device type is being

programmed. They are described in Section 6.1

“Device ID”. The Device ID registers read out

normally, even after code protection is applied.

Figure 2-9 shows the memory map for the

PIC24FJXXXGA1/GB1 family variant s .

TABLE 2-2: CODE MEMORY SIZE AND FLASH CONFIGURATION WORD LOCATIONS FOR

PIC24FJXXXGA1/GB1 DEVICES

Device User Mem or y

Address Limit

(Instruction W ords )

Write

Blocks Erase

Blocks

Configuration Word Addresses

123

PIC24FJ64GA1XX 00ABFEh (22K) 344 43 00ABFEh 00ABFCh 00ABFAh

PIC24FJ64GB1XX

PIC24FJ128GA1XX 0157FEh (44K) 688 86 0157FEh 0157FCh 0157FAh

PIC24FJ128GB1XX

PIC24FJ192GA1XX 020BFEh (67K) 1048 131 020BFEh 020BFCh 020BFA

PIC24FJ192GB1XX

PIC24FJ256GA1XX 02ABFEh (87K) 1368 171 02ABFEh 02ABFCh 02ABFA

PIC24FJ256GB1XX

PIC24FJXXXGA1/GB1

DS39907B-page 10  2011 Microchip Technology Inc.

FIGURE 2-9: PROGRAM MEMORY MAP

User Memory

Space

000000h

Flash Configuration Words

Code Memory(1)

0XXX00h(1)

0XXXFEh(1)

Configuration Memory

Space

800000h

Device ID FEFFFEh

FF0000h

FFFFFEh

Reserved

8007FAh

800800h

Executive Code Memory

7FFFFEh

FF0002h

FF0004h

Reserved

(2 x 16-bit)

Note 1: The size and address boundaries for user Flash code memory are device dependent. See Table 2-2 for details.

User Flash

(1024 x 24-bit)

8007F0h

Diagnostic and Calibration

Words

(8 x 24-bit)

0XXXFAh(1)

0XXXF9h(1)

 2011 Microchip Technology Inc. DS39907B-page 11

PIC24FJXXXGA1/GB1

3.0 DEVICE PROGRAMMING – ICSP

ICSP mode is a special programming protocol that

allows you to read and write to the memory of the

PIC24FJXXXGA1/GB1 d evices. The ICSP mo de is the

most direct method used to program the device; note,

however, that Enhanced ICSP is faster. ICSP mode

also has the ability to read the contents of executive

memory to determine if the programming executive is

present. This capability is accomplished by applying

control codes and instructions, serially to the device,

using pins, PGCx and PGDx.

In ICSP mode, the system clock is taken from the

PGCx pin, regardless of the device’s oscillator Config-

uration bits. All instructions are shifted serially into an

inter nal buf fer , then l oaded into th e Instructi on Register

(IR) and executed. No program fetching occurs from

internal memory. Instructions are fed in 24 bits at a

time. PGDx is used to shift data in and PGCx is used

as both the serial shift clock and the CPU execution

clock.

3.1 Over view of the Programming

Process

Figure 3-1 shows the high-level overview of the

programming process. After entering ICSP mode, the

first action is to Chip Erase the device. Next, the code

memory is programmed, followed by the device

Configuration registers. Code memory (including the

Configuration registers) is then verified to ensure that

programming was successful. Then, program the

code-protect Configuration bits, if required.

FIGURE 3-1: HIGH-LEVEL ICSP™

PROGRAMMING FLOW

3.2 ICSP Operation

Upon entry into ICSP mode, the CPU is Idle. Execution

of the CPU is governed by an internal state machine. A

4-bit control code is clocked in using PGCx and PGDx,

and this control code is used to c ommand the CP U (see

Table 3-1).

The SIX control co de is used to send instru ctions to the

CPU for execution, and the REGOUT control code is

used to read data out of the device via the VISI register .

TABLE 3-1: CPU CONTROL CODES IN

ICSP™ MODE

Note: During ICSP operation, the operating

frequency of PGCx must not exceed

10 MHz.

4-Bit

Control Code Mnemonic Description

0000b SIX Shift in 24-bit instruc tion

and execute.

0001b REGOUT Shift out the VISI (0784h)

0010b-1111b N/A Reserved.

Start

Perform Chip

Erase

Program Memo ry

Verify Program

Done

Enter ICS P™

Program Configuration Bits

Verify Configuration Bits

Exit ICSP

PIC24FJXXXGA1/GB1

DS39907B-page 12  2011 Microchip Technology Inc.

3.2.1 SIX SERIAL INSTRUCTION

EXECUTION

The SIX control code allows execution of PIC24F family

assembly instructions. When the SIX code is received,

the CPU is suspended for 24 clock cycles, as the instruc-

tion is then clocked into the internal buffer. Once the

instruction is shif ted in, the st ate mach ine allow s it to be

executed over the next four PGC clock cycles. While the

received instruction is executed, the state machine

simultaneously shifts in the next 4-bit command (see

Figure 3-2).

Coming out of Reset, the first 4-bit control code is

always forced to SIX and a forced NOP instruction is

execute d by th e CPU. Five a ddi tional PGCx cl oc ks a re

needed on start-up, resulting in a 9-bit SIX command

instead of the normal 4-bit SIX command.

After the forced SIX is clocked in, ICSP operation

resumes as normal. That is, the next 24 clock cycles

load the first instruction word to the CPU.

FIGURE 3-2: SIX S ERIAL EXECUTION

3.2.1.1 Differences Between Execution of

SIX and Normal Instructions

There ar e some di fferences between executing ins truc-

tions normal ly and usi ng the SIX ICSP command. As a

result, the code examples in this specification may not

match those for performing the same func tions during

normal dev ic e opera tio n.

The important differences are:

• Two-word instructions require two SIX operations

to clock in all the necessary data.

Examples of two-word instructions are GOTO and

CALL.

• Two-cyc le instru ctions require two SIX ope rations .

The first SIX operation shifts in the instruction and

begins to execute it. A second SIX operation – which

should shift in a NOP to avoid losing data – provides

the CPU clocks required to finish executing the

instruction.

Examples of two-cycle instructions are table read

and table write instructions.

• The CPU does not automatically stall to account

for pipeline changes.

A CPU stall occurs when an instruction modifies a

following instruction.

During normal operation, the CPU will automatically

force a NOP while the new data is read. When us ing

ICSP, there is no automatic stall, so any indirect ref-

erences to a recently modified register should be

preceded by a NOP.

For example, the instructions, MOV #0x0,W0 and

MOV [W0],W1, must have a NOP inserted

between them.

If a two-cycle instruction modifies a register that is

used indirectly , it will requ ire two following NOPs: one

to exec ute the second half of the instruction and a

secon d to stall the CPU to c orre c t th e pipeline .

Instructions, such as TBLWTL [W0++],[W1],

should be foll ow ed by two NOPs.

• The device Program Counter (P C) continues to

automatically increment during ICSP instruction

execution, even though the Flash memory is not

being used.

As a result, the PC may be incremented to point to

invalid memory locations. Invalid memory spaces

include unimplemented Flash addresses and the

vector space (locations 0x0 to 0x1FF).

If the PC points to thes e locations, the device will

reset, possibly interrupting the ICSP operation. To

prevent this, instructions should be periodically

execute d to reset the PC to a safe spa ce. The opti-

mal method to accomplish this is to perform a

GOTO 0x200.

Note: To accoun t for this forced NOP, all example

code in this specification begins with a

NOP to ensure that no data is lost.

23 123 2324 1 2 3 4

PGCx P4A

PGDx

24-Bit Instruction Fetch

Execute PC – 1,

0000

Fetch SIX

45678 181920212217

LSB X X X X X X X X X X X X X X MSB

PGDx = Input

P3 P1B

P1A

789

0000000

Only for

Program

Memory Entry

Control Code

4 5

Execute 24-Bit

Instruction, Fetch

Next Control Code

 2011 Microchip Technology Inc. DS39907B-page 13

PIC24FJXXXGA1/GB1

3.2.2 REGOUT SERIAL INSTRUCTION

EXECUTION

The REGOUT control code allows for data to be

extracted from the device in ICSP mode. It is used to

clock the contents of the VISI register, out of the device,

over the PGDx pin. After the REGOUT control code is

received, the CPU is held Idle for 8 cycles. After these

8 cyc les, an additiona l 16 cyc les are required t o clock the

data out (see Figure 3-3).

The REG OUT c ode i s unique be cause the PGD x pi n is

an input when the control code is transmitted to the

device. However, after the control code is processed,

the PGDx pi n becomes an outpu t as the VISI register is

shifted out.

FIGU RE 3-3: REG OUT SERIAL EX ECU T ION

Note 1: After the contents of VISI are shifted out,

the PIC24FJXXXGA1/GB1 devices

maintain PGDx as an output until the first

rising edge of the next clock is received.

2: Data changes on the falling edge and

latches on the rising edge of PGCx. For

all data transmissions, the Least

Significant bit (LSb) is transmitted first.

1234 1278

PGCx P4

PGDx

PGDx = Input

Execute Previous Instruction, CPU Held in Idle Shift Out VISI Register<15:0>

PGDx = Output

123 1234

P4A

11 13 15 161412

No Execution Takes Place,

Fetch Next Control Code

00000

PGDx = Input

MSb

1234

456

LSb

141312

... 11100

Fetch REGOUT Control Code

PIC24FJXXXGA1/GB1

DS39907B-page 14  2011 Microchip Technology Inc.

3.3 Entering ICSP Mode

As show n in Figure 3-4, entering ICSP Program /Verify

mode requires three steps:

1. MCLR is briefly driv en high, then low.

2. A 32-bit key sequen ce is clocked into PGDx.

3. MCLR is then driven high within a specified

period of time a nd hel d.

The programming voltage applied to MCLR is VIH,

which is essentially VDD in the case of

PIC24FJXXXGA1/GB1 devices. There is no minimum

time requirement for holding at VIH. After VIH is

remove d, an interval o f at least P18 m ust elap se before

presenting the key sequence on PGDx.

The key sequence is a specific 32-bit pattern:

‘0100 1101 0100 0011 0100 1000 0101 0001’

(more easily remembered as 4D434851h in hexa-

decimal). The devi ce will enter P rogram/V erify mode only

if the sequen ce is valid. The Mos t Signi ficant bit (MSb) o f

the most signifi ca nt nibble m ust be s hi f te d in first.

Once the key sequence is complete, VIH must be

applied to MCLR and held at that level for as long as

Program/Verify mode is to be maint ained. An in terval of

at leas t ti me , P19 and P7, must e lapse before pre sent-

ing data on PGDx. Signals appearing on PGCx before

P7 has elapsed will not be interpreted as valid.

On successful entry, the program memory can be

accessed and programmed in serial fashion. While in

ICSP mode, all unused I/Os are placed in the

high-impedance state.

FIGU RE 3-4: ENT ERI NG ICSP ™ MODE

MCLR

PGDx

PGCx

VDD

P6 P14

b31 b30 b29 b28 b27 b2 b1 b0b3

...

Progr am/ Verify Entry Code = 4D43485 1h

P1A

P1B

P18

P19

0100 0 0

VIH

 2011 Microchip Technology Inc. DS39907B-page 15

PIC24FJXXXGA1/GB1

3.4 Flash Memory Programming in

ICSP Mode

3.4.1 PROGRAMMING OPERATI ONS

Flash memory write and erase operations are controlled

by the NVMCON register. Programming is performed by

setting NVMCON to select the type of erase operation

(Table 3-2) or write operation (Table 3-3) and initiating

the programming by setting the WR control bit

(NVMCON<15>).

In ICSP mode, all programming operations are

self-timed. There is an internal delay between the user

setting the WR control bit and the automatic clearing of

the WR control bit when the programming operation

is complete. Please refer to Section 7.0 “AC/DC

Characteristics and Timing Requirements” for

information about the delays associated with various

programming operations.

TABLE 3-2: NVMCON ERASE

OPERATIONS

TABLE 3-3: NVMCON WRITE

OPERATIONS

3.4.2 STARTING AND STOPPING A

PROGRAMMING CYCLE

The WR bit (NVMCON<15>) is used to start an erase or

write cycle. Setting the WR bit initiates the programming

cycle.

All erase and write cycles are self-timed. The WR bit

should be polled to determine if the era se or write cycle

has been completed. Starting a programming cycle is

performed as follows:

3.5 Erasing Program Memory

The procedure fo r erasing program memory (all of code

memory, data memory, executive memory and

code-protect bits) consists of setting NVMCON to

404Fh and executing the programming cycle.

A Chip Erase can erase all of user memory or all of both

the user and configuration memory. A table write

instruction should be executed prior to performing the

Chip Erase to se lect which sections are erased.

When this table write instruction is executed:

• If the TBLPAG register points to user space (is

less than 0x8 0), the C hip Erase will eras e onl y

user memo ry.

• If TBLPAG points to configuration memory space

(is greater than or equal to 0x80), the Chip Erase

will erase both user and configuration memory.

If configuration memory space is erased, the

internal oscillator Calibration Word, located at

0x807FE, will be erased. This location should be

stored pri or to per form ing a w ho le Chip Era s e an d

restored afterward to prevent internal oscillators

from becom ing unca lib rate d.

Figure 3-5 shows the ICSP programming process for

performing a Chip Erase. This process includes the

ICSP command code, which must be transmitted (for

each instruction), Least Significant bit first, using the

PGCx and PGDx pins (see Figure 3-2).

FIGURE 3-5: CHIP ERASE FLOW

NVMCON

Value Erase Operation

404Fh Erase all code memory, executive

memory and Configuration registers

(does not erase Unit ID or Device ID

registers).

4042h Erase a page of c ode mem ory or

executive memory.

NVMCON

Value Write Operation

4003h Write a Configuration Word register.

4001h Program 1 row (64 instruction words) of

code memory o r executive me mory.

BSET NVMCON, #WR

Note: Program memory must be erased before

writing any data to program memory.

Start

Done

Set the WR bit to In itiate Erase

Write 404Fh to NVMCON SFR

Delay P11 + P10 Time

PIC24FJXXXGA1/GB1

DS39907B-page 16  2011 Microchip Technology Inc.

TABLE 3-4: SERIAL INSTRUCTION EXECUTION FOR CHIP ERASE

Command

(Binary) Data

(Hex) Description

Step 1: Ex it the R ese t vector.

0000

000000

040200

000000

NOP

GOTO 0x200

NOP

Step 2: Set the NVMCON to erase all program memory.

0000

0000 2404FA

883B0A MOV #0x404F, W10

MOV W10, NVMCON

Step 3: Set TBLPAG and perform dummy table write to select what portions of memory are erased.

0000

200000

880190

200000

BB0800

000000

MOV #<PAGEVAL>, W0

MOV W0, TBLPAG

MOV #0x0000, W0

TBLWTL W0,[W0]

NOP

Step 4: Initiate the erase cycle.

0000

A8E761

000000

BSET NVMCON, #WR

NOP

Step 5: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.

0000

0001

0000

040200

000000

803B02

883C22

000000

<VISI>

000000

GOTO 0x200

NOP

MOV NVMCON, W2

MOV W2, VISI

NOP

Clock out contents of the VISI register.

NOP

 2011 Microchip Technology Inc. DS39907B-page 17

PIC24FJXXXGA1/GB1

3.6 Writing Code M emory

The proced ure for writi ng code me mory is the same as

the procedure for writing the Configuration registers,

exce pt that 64 ins tructio n words are p rogramme d at a

time. To facilitate this operation, working registers,

W0:W5, are used as temporary holdi ng registers for the

data to be programmed.

Table 3-5 shows the ICSP prog ramming detai ls, includ-

ing the serial pattern with the ICSP command code,

which must be transmitted, Least Significant bit first,

using the PGCx and PGDx pins (see Figure 3-2).

In Step 1, the Reset vector is exited. In Step 2, the

NVMCON register is initialized for programming a full

row of code memory. In Step 3, the 24-bit starting des-

tination address for programming is loaded into the

TBLPAG register and W7 register. (The upper byte of

the starting destination address is stored in TBLPAG

and the lower 16 bits of the destination address are

stored in W7.)

To minimize the programming tim e, a p acked ins truction

format is used (Figure 3-6).

In Step 4, four packed instruction words are stored in

working registers, W0:W5, using the MOV instruction,

and the Read Pointer , W6, is initialized. The content s of

W0:W 5 (h old ing the pa cked ins tru cti on wo rd data) are

shown in Figure 3-6.

In S tep 5, eight TBLWT i nstructions are used to c opy the

data from W0:W5 to the write latches of code memory.

Since code memory is programmed 64 instruction

words at a tim e, S teps 4 and 5 are repeat ed 16 times to

load all the write latches (Step 6).

After the write latches are loaded, programming is

initiated by writing to the NVMCON register in Steps 7

and 8. In Step 9, the internal PC is reset to 200h. This

is a precautionary measure to prevent the PC from

incrementing into unimplemented memory when large

devices are being programmed. Lastly, in Step 10,

Steps 3-9 are repeated until all of code memory is

programmed.

FIGURE 3-6: PACKED INSTRUCTION

WORDS IN W0:W5

15 8 7 0

W0 LSW0

W1 MSB1 MSB0

W2 LSW1

W3 LSW2

W4 MSB3 MSB2

W5 LSW3

TABLE 3-5: SERIAL INSTRUCTION EXECUTI ON FOR WRITING CODE MEMOR Y

Command

(Binary) Data

(Hex) Description

Step 1: Ex it the R ese t vector.

0000

000000

040200

000000

NOP

GOTO 0x200

NOP

Step 2: Set the NVMCON to program 64 instruction words.

0000

0000 24001A

883B0A MOV #0x4001, W10

MOV W10, NVMCON

Step 3: Initialize the Write Pointer (W7) for TBLWT instructi on .

0000

200xx0

880190

2xxxx7

MOV #<DestinationAddress23:16>, W0

MOV W0, TBLPAG

MOV #<DestinationAddress15:0>, W7

Step 4: Load W0:W5 with the next 4 instruction words to program.

0000

2xxxx0

2xxxx1

2xxxx2

2xxxx3

2xxxx4

2xxxx5

MOV #<LSW0>, W0

MOV #<MSB1:MSB0>, W1

MOV #<LSW1>, W2

MOV #<LSW2>, W3

MOV #<MSB3:MSB2>, W4

MOV #<LSW3>, W5

PIC24FJXXXGA1/GB1

DS39907B-page 18  2011 Microchip Technology Inc.

Step 5: Set the Read Pointer (W6) and load the (next set of) write latches.

0000

EB0300

000000

BB0BB6

000000

BBDBB6

000000

BBEBB6

000000

BB1BB6

000000

BB0BB6

000000

BBDBB6

000000

BBEBB6

000000

BB1BB6

000000

CLR W6

NOP

TBLWTL [W6++], [W7]

NOP

TBLWTH.B [W6++], [W7++]

NOP

TBLWTH.B [W6++], [++W7]

NOP

TBLWTL [W6++], [W7++]

NOP

TBLWTL [W6++], [W7]

NOP

TBLWTH.B [W6++], [W7++]

NOP

TBLWTH.B [W6++], [++W7]

NOP

TBLWTL [W6++], [W7++]

NOP

Step 6: Repeat Steps 4 and 5, sixteen times, to load the write latches for 64 instructions.

Step 7: Initiate the write cycle.

0000

A8E761

000000

BSET NVMCON, #WR

NOP

Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.

0000

0001

0000

040200

000000

803B02

883C22

000000

<VISI>

000000

GOTO 0x200

NOP

MOV NVMCON, W2

MOV W2, VISI

NOP

Clock out contents of the VISI register.

NOP

Step 9: Reset device internal PC.

0000

0000 040200

000000 GOTO 0x200

NOP

Step 10: Repeat Steps 3-9 until all code memory is programmed.

TABLE 3-5: SERIAL INSTRUCTION EXECUTI ON FOR WRITING CODE MEMOR Y (CONTINUED)

Command

(Binary) Data

(Hex) Description

 2011 Microchip Technology Inc. DS39907B-page 19

PIC24FJXXXGA1/GB1

FIGURE 3-7: PROGRAM CODE MEMORY FLOW

Start Write Sequence

All

locations

done?

Done

Start

Yes

Load 2 Bytes

to Write

Buffer at <Addr>

All

bytes

written?

Yes

and Poll for WR bit

to be Cleared

N = 1

LoopCount = 0

Configure

Device for

Writes

N = 1

LoopCount =

LoopCount + 1

N = N + 1

PIC24FJXXXGA1/GB1

DS39907B-page 20  2011 Microchip Technology Inc.

3.7 Writing Configuration Words

Device configuration for PIC24FJXXXGA1/GB1 devices

is stored in Flash Configuration Words at the end of the

user space program memory, and in multiple register

Configuration Words located in the test space. These

registers reflect values read at any Reset from program

memory locations. The values for the Configuration

Words for the default device configurations are listed in

Table 3-6.

The values can be changed only by programming the

content of the corresponding Flash Configuration Word

and resetting the device. The Reset forces an autom atic

reload of the Flash stored configuration values by

sequencing through the dedicated Flash Configuration

Words and transferring the data into the Configuration

registers.

For the PIC24FJXXXGA1/GB1 families, certain Config-

uration bits have default states that must always be

maintained to ensure device functionality, regardless of

the settings of other Configuration bits. These bits and

their values are listed in Table 3-7.

To change the values of the Flash Configuration Word

once it has been programm ed, the dev ice m ust be Chip

Erased, as described in Section 3.5 “Erasing Program

Memory”, and reprogrammed to the desired value. It is

not possible to program a ‘0’ to ‘1’, but they may be

programmed from a ‘1’ to ‘0’ to enable code protection.

TABLE 3-6: DEFAULT CONFIGURATION

TABLE 3-7: RESERVED CONFIGURATION

BIT LOCATIONS

Table 3-8 shows the ICSP programming details for pro-

gramming the Configuration Word locations, including

the serial pattern with the ICSP command code which

must be transmitted, Least Significant bit first, using the

PGCx and PGDx pins (see Figure 3-2).

In Step 1, the Reset vector is exited. In Step 2, the

NVMCON register is initialized for programming of

code memory. In Step 3, the 24-bit starting destination

address for programming is loaded into the TBLPAG

The TBLPAG register must be loaded with the

following:

• 64-Kby te dev ices : 00h

• 128, 192 and 256-Kbyte devices: 01h

To verify the data by reading the Configuration Words

after performing the write in order, the code protection

bits initially should be programmed to a ‘1’ to ensure

that the verification can be performed properly. After

verification is finished, the code protection bit can be

programmed to a ‘0’ by using a word write to the

appropriate Configuration Word.

Address Name Default Va lue

Last Word CW1 7FFFh

Last Word – 2 CW2 F7FFh

Last Word – 4 CW3 FFFFh

Bit Location Value

CW1<15> 0

CW1<10> 1

CW2<11> 0

CW2<2>(1) 1

Note 1: This bit is implemented as I2C2SEL on

PIC24FJXXXGA110 devices, and should

be programmed as required.

 2011 Microchip Technology Inc. DS39907B-page 21

PIC24FJXXXGA1/GB1

TABLE 3-8: SERIAL INSTRUCTION EXECUTION FOR WRITING CONFIGURATION REGISTERS

Command

(Binary) Data

(Hex) Description

Step 1: Ex it the R ese t vector.

0000

000000

040200

000000

NOP

GOTO 0x200

NOP

Step 2: Initialize the Write Pointer (W7) for the TBLWT instruction.

0000 2xxxx7 MOV <CW2Address15:0>, W7

Step 3: Set the NVMCON register to program CW2.

0000

0000 24003A

883B0A MOV #0x4003, W10

MOV W10, NVMCON

Step 4: Initialize the TBLPAG register.

0000

0000 200xx0

880190 MOV <CW2Address23:16>, W0

MOV W0, TBLPAG

Step 5: Load the Configuration register data to W6.

0000 2xxxx6 MOV #<CW2_VALUE>, W6

Step 6: Write the Configuration register data to the write latch and increment the Write Pointer.

0000

000000

BB1B86

000000

NOP

TBLWTL W6, [W7++]

NOP

Step 7: Initiate the write cycle.

0000

A8E761

000000

BSET NVMCON, #WR

NOP

Step 8: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.

0000

0001

0000

040200

000000

803B02

883C22

000000

<VISI>

000000

GOTO 0x200

NOP

MOV NVMCON, W2

MOV W2, VISI

NOP

Clock out contents of the VISI register.

NOP

Step 9: Reset device internal PC.

0000

0000 040200

000000 GOTO 0x200

NOP

Step 10: Repeat Steps 5-9 to write CW1.

PIC24FJXXXGA1/GB1

DS39907B-page 22  2011 Microchip Technology Inc.

3.8 Reading Code Memory

Readi ng from cod e me mo ry is perform ed by ex ec utin g

a series of TBLRD instructions and clocking out the data

using the REGOUT command.

Table 3-9 shows the ICSP programming details for

reading code memory. In Step 1, the Reset vector is

exited. In Step 2, the 24-bit starting source address for

reading is loaded into the TBLPAG register and W6

is sto red in TBLPAG and the lower 16 bits of the source

address are stored in W6.

To minimize the reading time, the packed instruction

word for mat tha t was uti lized for wri ting is also used f or

reading (see Figure 3-6). In Step 3, the Write Pointer,

W7, is initialized. In Step 4, two instruction words are

read from c od e me mo ry and clocked out of the device,

through the VISI register, using the REGOUT

command. Step 4 is repeated until the desired amount

of code memory is read.

TABLE 3-9: SERIAL INSTRUCTION EXECUTI ON FOR READ ING C ODE MEM ORY

Command

(Binary) Data

(Hex) Description

Step 1: Exit Reset vector .

0000

000000

040200

000000

NOP

GOTO 0x200

NOP

Step 2: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction.

0000

200xx0

880190

2xxxx6

MOV #<SourceAddress23:16>, W0

MOV W0, TBLPAG

MOV #<SourceAddress15:0>, W6

Step 3: Initialize the Write Pointer (W7) to point to the VISI register.

0000

0000 207847

000000 MOV #VISI, W7

NOP

Step 4: R ea d a nd cl oc k o ut the content s of the ne xt two locations of co de memory, through the VISI register, using

the REGOUT command.

0000

0001

0000

0001

0000

0001

0000

BA0B96

000000

<VISI>

000000

BADBB6

000000

BAD3D6

000000

<VISI>

000000

BA0BB6

000000

<VISI>

000000

TBLRDL [W6], [W7]

NOP

Clock out contents of VISI register

NOP

TBLRDH.B [W6++], [W7++]

NOP

TBLRDH.B [++W6], [W7--]

NOP

Clock out contents of VISI register

NOP

TBLRDL [W6++], [W7]

NOP

Clock out contents of VISI register

NOP

Step 5: Repeat Step 4 until all desired code memory is read.

Step 6: Reset device internal PC.

0000

0000 040200

000000 GOTO 0x200

NOP

 2011 Microchip Technology Inc. DS39907B-page 23

PIC24FJXXXGA1/GB1

3.9 Reading Configuration Words

The procedure for reading configuration memory is

similar to the procedure for reading code memory,

except that 16-bit data words are read (with the upper

byte read being all ‘0’s) instead of 24-bit words.

Configuration Words are read, one register at a time.

Table 3-10 shows the ICSP programming details for

reading the Configuration Words. Note that the

TBLPAG register must be loaded with 0 0h for 64-Kbyte

devices, 01h for 128-Kbyte devices and 02h for

192-Kbyte and 256-Kbyte devices (the upper byte

address of configuration memory), and the Read

Pointer, W6, is initialized to the lower 16 bits of the

Configuration Word location.

TABLE 3-10: SERIAL INSTRUCTION EXECUTI ON FOR READING ALL CONFIGURATION MEMOR Y

Command

(Binary) Data

(Hex) Description

Step 1: Exit Reset vector .

0000

000000

040200

000000

NOP

GOTO 0x200

NOP

Step 2: Initialize TBLPAG, the Read Pointer (W6) and the Write Pointer (W7) for TBLRD instruction.

0000

200xx0

880190

2xxxx6

207846

000000

MOV <CW3Address23:16>, W0

MOV W0, TBLPAG

MOV <CW3Address15:0>, W6

MOV #VISI, W7

NOP

Step 3: Read the Configuration register and write it to the VISI register (located at 784h), and clock out the

VISI register using the REGOUT command.

0000

0001

0000

BA0BB6

000000

<VISI>

000000

TBLRDL [W6++], [W7]

NOP

Clock out contents of VISI register

NOP

Step 4: Repeat Step 3 twice to read Configuration Word 2 and Configuration Word 1.

Step 5: Reset device internal PC.

0000

0000 040200

000000 GOTO 0x200

NOP

PIC24FJXXXGA1/GB1

DS39907B-page 24  2011 Microchip Technology Inc.

3.10 Verify Code Memory and

Configuration Word

The veri fy step invo lves read ing back the code memo ry

space and comparing it against the copy held in the

programmer’s buffer. The Configuration registers are

verified with the rest of the code.

The verify process is shown in the flowchart in

Figure 3-8. Memory reads oc cur a single by te at a time,

so two by tes must be re ad to comp are against the w ord

in the programmer’s buffer. Refer to Section 3.8

“Reading Code Memory” for implementation details

of reading code memory.

FIGURE 3-8: VERIFY CODE

MEMORY FLOW

3.11 Reading the Application ID Word

The Application ID Word is stored at address,

8007F0h, in executive code memory. To read this

memory loc ation, you mu st use th e SIX contr ol code to

move this program memory location to the VISI regis-

ter. Then, the REGOUT control code must be used to

clock the contents of the VISI register out of the device.

The corresponding control and instruction codes that

must be serially transmitted to the device to perform

this operation are shown in Table 3-11.

After the programmer has clocked out the Application

ID Word, it m ust be inspec ted. If the App licat ion ID has

the value, CBh, the programming executive is resident

in memory and the device can be programmed using

the mechanism described in Section 4.0 “Device

Programming – Enhanced ICSP”. However, if the

Application ID has any other value, the programming

executiv e is not resident in memory; it must be loaded

to memory befo re the de vice can be pro gramm ed. The

procedure for loading the programming executive to

me mo ry is described in Section 5.4 “Programming

the Prog ramm ing Exec uti ve t o Memo ry” .

3.12 Exiting ICSP Mode

Exiting Program/Verify mode is done by removing VIH

from MCLR, as shown in Figure 3-9. The only require-

ment for exit is that an interval, P16, should elapse

between the last clock and program signals on PGCx

and PGDx before removing VIH.

FIGURE 3-9: EXITING I CSP™ MODE

Note: Because the Configuration registers

include the device code protection bit,

code memory should be verified immedi-

ately after writing if code protection is

enabled. This is because the device will

not be readable or verifiable if a device

Reset occurs after the code-protect bit in

CW1 has been cleared.

Read Low Byte

Read High Byte

Does

Word = Expect

Data?

Failure,

Report

Error

All

code memory

verified?

Yes

Set TBLPTR = 0

Start

Yes

Done

with Post-Increment

MCLR

P16

PGDx

PGD = Input

PGCx

VDD

VIH

P17

 2011 Microchip Technology Inc. DS39907B-page 25

PIC24FJXXXGA1/GB1

TABLE 3-11: SERIAL INSTRUCTION EXECUTI ON FOR READIN G TH E APPLIC ATION ID W O RD

Command

(Binary) Data

(Hex) Description

Step 1: Exit Reset vector .

0000

000000

040200

000000

NOP

GOTO 0x200

NOP

Step 2: Initialize TBLPAG and the Read Pointer (W0) for TBLRD instruction.

0000

200800

880190

207F00

207841

000000

BA0890

000000

MOV #0x80, W0

MOV W0, TBLPAG

MOV #0x7F0, W0

MOV #VISI, W1

NOP

TBLRDL [W0], [W1]

NOP

Step 3: Output the VISI register using the REGOUT command.

0001

0000 <VISI>

000000 Clock out contents of the VISI register

NOP

PIC24FJXXXGA1/GB1

DS39907B-page 26  2011 Microchip Technology Inc.

4.0 DEVICE PROGRAMMING –

ENHANCED ICSP

This section discusses programming the device

through Enhanced ICSP and the programming execu-

tive. The programming executive resides in executive

memory (separate from code memory) and is executed

when Enhanced ICSP Programming mode is entered.

The programming executive provides the mechanism

for the program mer (host devic e) to program and verif y

the PIC24FJXXXGA1/GB1 devices using a simple

command set and communication protocol. There are

several basic functions provided by the programming

executive:

• Read Memory

• Erase Memory

• Program Memory

• Blank Check

• Read Executive Firmware Revision

The programming executive performs the low-level

tasks required for erasing, programming and verifying

a device. This allows the programmer to program the

device by is suin g th e appro priate comm ands a nd data.

Table 4-1 summarizes the commands. A detailed

description for each command is provided in

Section 5.2 “Programming Executive Commands”.

TABLE 4-1: COMMAND SET SUMMARY

The programming executive uses the device’s data

RAM for variab le sto rage and p rogram execu tion. Af ter

the programming executive has run, no assumptions

should be made about the contents of data RAM.

4.1 Overview of the Programming

Process

Figure 4-1 shows the high-level overview of the

programming process. After entering Enhanced ICSP

mode, the programming executive is verified. Next, the

device is erased. Then, the code memory is

programmed, followed by the configuration locations.

Code memory (including the Configuration registers) is

then verified to ensure that programming was successful.

After the programming executive has been verified

in memory (or loaded if not present), the

PIC24FJXXXGA1/GB1 families can be programmed

using the command set shown in Table 4-1.

FIGURE 4-1: HIGH-LEVEL ENHANCED

ICSP ™ PROGRAMMI NG F LOW

4.2 Confirming the Presence of the

Programming Executive

Befo re pr ogr ammi ng c an beg in, the pro gramm er must

confirm that the programming executive is stored in

executive memory. The procedure for this task is

shown in Figure 4-2.

First, In-Circuit Serial Programming mode (ICSP) is

enter ed . Then, th e un iq u e Ap pl ic ati on ID Word stor e d in

executive memory is read. If the programming executive

is resident, the Application ID Word is CBh, which means

programming can resume as normal. However, if the

Application ID Word is not CBh, the programming

executive must be programmed to executive code

memory using the method described in Section 5.4

“Programming the Programming Executive to

Memory”.

Section 3.0 “Device Programming – ICSP” descri bes

the ICSP p rogra mmi ng meth od. Se ct ion 3.1 1 “ Rea ding

the Application ID Word” describes the procedure for

readin g the Applicatio n ID Word i n IC SP m o de .

Command Description

SCHECK Sanity Check

READC Read Device ID Registers

READP Read Code Memory

PROGP Program One Row of Co de Memory

and Verify

PROGW Program One Wor d of Code Memory

and Verify

QBLANK Query if the Code Memory is Blank

QVER Query the Software Version

Start

Done

Perform Chip

Erase

Program Memo ry

Verify Progr am

Enter En hanced I CSP™

Program Configuration Bits

Verify Configuration Bits

Exit Enhanced ICSP

 2011 Microchip Technology Inc. DS39907B-page 27

PIC24FJXXXGA1/GB1

FIGURE 4-2: CONFIRMING PRESENCE

OF PROGRAMMING

EXECUTIVE

4.3 Entering Enhanced ICSP Mode

As shown in Figure 4-3, entering Enhanced ICSP

Program/Verify mode requires three steps :

1. The MCLR pin is briefly driven hi gh, then low.

2. A 32-bit key sequence is clocked into PGDx.

3. MCLR is then driven high within a specified

period of time and held.

The programming voltage applied to MCLR is VIH,

which is essentially VDD in the case of

PIC24FJXXXGA1/GB1 devices. There is no minimum

time requirement for holding at VIH. After VIH is

removed , an interval o f at least P18 m ust elapse b efore

presenting the key sequence on PGDx.

The key sequence is a specific 32-bit pattern:

‘0100 1101 0100 0011 0100 1000 0101 0000’

(more easily remembered as 4D434850h in hexa-

decimal format). The device will enter Program/Verify

mode only if the key sequence is valid. The Most

Signific ant b it (MSb ) of t he most sign ificant nib ble mus t

be shif ted in firs t.

Once the key sequence is complete, VIH must be

applied to MCLR and held at that level for as long as

Program/Verify mode is t o be maint ained. An interv al of

at leas t ti me , P19 and P7, must e lapse before pre sent-

ing data on PGDx. Signals appearing on PGDx before

P7 has elapsed will not be interpreted as valid.

On successful entry, the program memory can be

accessed and programmed in serial fashion. While in

the Program/ V eri fy mode, all un used I/Os are pla ced in

the high-impedance state.

FIGURE 4-3: ENTERING ENHANCED ICSP ™ MODE

Start

Ente r ICSP™ Mo de

Application ID

CBh?

Resident in Memory

Yes

Prog. Executive is

Application ID

Read the

be Programmed

Prog. Executive must

from Address

807F0h

Finish

MCLR

PGDx

PGCx

VDD

P6 P14

b31 b30 b29 b28 b27 b2 b1 b0b3

...

Program/Verify Entry Code = 4D434850h

P1A

P1B

P18

P19

01001 0000

VIH VIH

PIC24FJXXXGA1/GB1

DS39907B-page 28  2011 Microchip Technology Inc.

4.4 Blank Check

The term, “Blank Check”, implies verifying that the

device has been successfully erased and has no

programmed memory locations. A blank or erased

memory location is always read as ‘1’.

The Device ID registers (FF0002h:FF0000h) can be

ignored by the Blank Check since this region stores

device information that cannot be erased. The device

Configuration registers are also ignored by the Blank

Check. Additionally, all unimplemented memory space

should be ignored by the Blank Check.

The QBL ANK comm and i s us ed for t he Blan k C heck. It

determines if the code memory is erased by testing

these memory regions. A ‘BLANK’ or ‘NOT BLANK’

respons e is returne d. If it is de term in ed that the dev ice

is not blank, it must be erased before attempting to

program the chip.

4.5 Code Memory Programming

4.5.1 PROGRAMMING METHODOLOGY

Code memory is programmed with the PROGP

command. PROGP programs one row of code

memory, sta rting fro m the memory address specified i n

the command. The number of PROGP commands

required to program a device depends on the number

of write blocks that must be programmed in the device.

A flowchart for programming the code memory of the

PIC24FJXXXGA1/GB1 families is s hown i n Figure 4-4.

In this example, all 87K instruction words of a

256-Kbyte device are programmed. First, the number

of commands to send (called ‘RemainingCmds’ in the

flowchart) is set to 1368 and the destination address

(called ‘BaseAddress’) is set to ‘0’. Next, one write

block in the device is programmed with a PROGP

command. Each PROGP command contains data for

one row of code memory of the device. After the first

comma nd is proc essed suc cessfully, ‘Rema iningCmds’

is dec rem ented by 1 and co mpared with 0. Since there

are more PROGP commands to send, ‘BaseAddress’

is incremented by 80h to point to the next row of

memory.

On the second PROGP command, the second row is

programme d. This process is repeated until the entire

device is programmed. No special handling must be

performed when a panel boundar y is cr ossed.

FIGURE 4-4: FLOWCHART FOR

PROGRAMMING CODE

MEMORY

4. 5.2 PROGRAMMING VERIFICATION

After code memory is programmed, the contents of

memory can be verified to ensure that programming

was successful. Verification requires code memory to

be read back and compared against the copy held in

the programmer’s buffer.

The READP co mmand can be used to read back all of

the programmed code memory.

Alternatively, you can have the programmer perform

the verification after the entire device is programmed

using a checksum computation.

PROGP respons e

PASS?

Are

RemainingCmds

BaseAdd ress = 00h

RemainingCmds = 1368

RemainingCmds =

RemainingCmds – 1

BaseAddress =

BaseAddress + 80h

Yes

Start

Failure

Report Error

Send PROGP

Command to Program

BaseAddress

Finish

 2011 Microchip Technology Inc. DS39907B-page 29

PIC24FJXXXGA1/GB1

4.6 Configuration Bits Programming

4.6.1 OVERVIEW

The PIC24FJXXXGA1/GB1 families have Configura-

tion bits stored in the last three locations of imple-

mented program memory (see Table 2-2 for loc ations).

These bits can be set or cleared to select various

device configuratio ns . Th ere a r e t hree typ es of Co nfi g-

uration bits: system operation bits, code-protect bits

and unit ID bits. The system operation bits determine

the power-on settings for system level components,

such as oscillator and Watchdog Timer. The

code-protect bits prevent program memory from being

read and writte n.

The desc riptions for the Configuration bits in the Flash

Config urat ion Words are sho wn in Table 4-2.

Note: Although not implemented with a specific

function, some Configuration bit positions

have default states that must always be

maintained to ensure device functionality,

regardless of the settings of other Config-

uration bits. Refer to Table 3-7 for a list of

these bit positions and th eir default st ates.

TABLE 4-2: PIC24FJXXXGA1/GB1 CONFIGURATION BITS DESCRIPTION

Bit Field Register Descrip tion

DEBUG CW1<11> Background Debug Enab le bit

1 = Device will reset in User mode

0 = Device will reset in Debug mode

DISUVREG(1) CW2<3> Internal USB 3.3V Regulator Disable bit

1 = Regulator is disabled

0 = Regulator is enabled

FCKSM<1:0> CW2<7:6> Clock Switch ing Mode bits

1x = Clock switching is disabled, Fail-Safe Clock Monitor is disabled

01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled

00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled

FNOSC<2:0> CW2<10:8> Initial Oscillator Source Selection bits

111 = Internal Fast RC (FRCDIV) oscillator with postscaler

110 = Reserved

101 = Low-Power RC (LPRC) oscillator

100 = Secondary (SOSC) oscillator

011 = Primary (XTPLL, HSPLL, ECPLL) oscillator with PLL

010 = Primary (XT, HS, EC) oscillator

001 = Internal Fast RC (FRCPLL) oscillator with postscaler and PLL

000 = Fast RC (FRC) oscillator

FWDTEN CW1<7> Watchdog Timer Enable bit

1 = Watchdog Timer always enabled (LPRC oscillator cannot be disabled;

clearing the SWDTEN bit in the RCON register will have no effect)

0 = Watchdog Timer enabled/disabled by user software (LPRC can be

disabled by clearing the SWDTEN bit in the RCON register)

FWPSA CW1<4> Watchdog Timer Postscaler bit

1 = 1:128

0 = 1:32

GCP CW1<13> General Segment Code-Protect bit

1 = User program memory is not code-protected

0 = User program memory is code-protected

GWRP CW1<12> General Segment Write-Protect bi t

1 = User program memory is not write-protected

0 = User program memory is write-protected

Note 1: Available on PIC24FJXXXG B1XX devices only.

2: Available on PIC24FJXXXGA110 devices only. On other devices, always maintain this bit as ‘1’.

PIC24FJXXXGA1/GB1

DS39907B-page 30  2011 Microchip Technology Inc.

I2C2SEL(2) CW2<2> I2C2 Pin Select bit (PIC24FJXXXGA1XX devices only)

1 = Use SCL2/SDA2 pins for I2C™ Module 2

0 = Use ASCL2/ASDA2 pins for I2C Module 2

ICS<1:0> CW1<9:8> ICD Emulator Pin Placement Select bits

11 = Emulator functions are shared with PGEC1/PGED1

10 = Emulator functions are shared with PGEC2/PGED2

01 = Emulator functions are shared with PGEC3/PGED3

00 = Reserved; do not use

IESO CW2<15> Internal External Switchover bit

1 = Two-Speed Start-up is enabled

0 = Two-Speed Start-up is disabled

IOL1WAY CW2<4> IOLOCK Bit One-Way Set Enable bit

0 = The OSCCON<IOLOCK> bit can be set and cleared as needed

(provided an unlocking sequence is executed)

1 = The OSCCON<IOLOCK> bit can only be set once (provided an

unlocking sequence is executed). Once IOLOCK is set, this prevents

any possible future RP register changes

JTAGEN CW1<14> JTAG Enable bit

1 = JTAG is enabled

0 = JTAG is disabled

OSCIOFNC CW2<5> OSC2 Pin Function bit (except in XT and HS modes)

1 = OSC2 is a clock output

0 = OSC2 is a general purpose digital I/O pin

PLLDIV<2:0>(1) CW2<14:12> USB 96 MHz PLL Prescaler Select bits

111 = Oscillator input divided by 12 (48 MHz input)

110 = Oscillator input divided by 10 (40 MHz input)

101 = Oscillator input divided by 6 (24 MHz input)

100 = Oscillator input divided by 5 (20 MHz input)

011 = Oscillator input divided by 4 (16 MHz input)

010 = Oscillator input divided by 3 (12 MHz input)

001 = Oscillator input divided by 2 (8 MHz input)

000 = Oscillator input used directly (4 MHz input)

POSCMD<1:0> CW2<1:0> Primary Oscillator Mode Select bits

11 = Primary oscillator disabled

10 = HS Crystal Oscillator mode

01 = XT Crystal Oscillator mode

00 = EC (External Clock) mode

WDTPOST<3:0> CW1<3:0> Watchdog Timer Prescaler bits

1111 = 1:32,768

1110 = 1:16,384

0001 = 1:2

0000 = 1:1

TABLE 4-2: PIC24FJXXXGA1/GB1 CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field Register Descrip tion

Note 1: Available on PIC24FJXXXG B1XX devices only.

2: Available on PIC24FJXXXGA110 devices only. On other devices, always maintain this bit as ‘1’.

 2011 Microchip Technology Inc. DS39907B-page 31

PIC24FJXXXGA1/GB1

WINDIS CW1<6> Windowed WDT bit

1 = Watchdog Timer is in Non-Window mode

0 = Watchdog Timer is in Window mode; FWDTEN must be ‘1’

WPCFG CW3<14> Configuration Word Code Page Protection Select bit

1 = Last page (at the top of program memo ry) and Flash Configuration W ords

are not protect ed

0 = Last page and Flash Configuration Words are code-protected

WPDIS CW3<13> Segment Write Protection Disable bit

1 = Segmented code protection disabled

0 = Segmented code protection enabled; protected segment defined by

WPEND, WPCFG and WPFPx Configuration bits

WPEND CW3<15> Segment Write Protection End Page Select bit

1 = Protected code segment lower boundary is at the bottom of program

memory (000000h); upper boundary is the code page specified by

WPFP<8:0>

0 = Protected code segment upper boundary is at the last page of program

memory; lower boundary is the code page specified by WPFP<8:0>

WPFP<7:0> CW3<7:0> Protected Code Segment Boundary Page bits

Designates the 512 instruction words page boundary of the protected code

segment.

If WPEND = 1:

Specifies the lower page boundary of the code-protected segment; the last

page being the last implemented page in the device.

If WPEND = 0:

Specifies the upper page boundary of the code-protected segment; Page 0

being the lowe r bound ary.

TABLE 4-2: PIC24FJXXXGA1/GB1 CONFIGURATION BITS DESCRIPTION (CONTINUED)

Bit Field Register Descrip tion

Note 1: Available on PIC24FJXXXG B1XX devices only.

2: Available on PIC24FJXXXGA110 devices only. On other devices, always maintain this bit as ‘1’.

PIC24FJXXXGA1/GB1

DS39907B-page 32  2011 Microchip Technology Inc.

4.6.2 PROGRAMMING METHODOLOGY

Config uration bit s m ay be progra mmed a s ingle byte at

a time using the PROGP command. This command

specifies the configuration data and Configuration

programmed, any unimplemented or reserved bits

must be programmed with a ‘1’.

Two PROGP commands are required to program the

Configuration bits. A flowchart for Configuration bit

programming is shown in Figure 4-5.

4. 6.3 PROGRAMMING VERIFICATION

After the Configuration bits are programmed, the

contents of memory should be verified to ensure that

the programming was successful. Verification requires

the Configuration bits to be read back and compared

against the copy held in the programmer ’s buffer. The

READP command reads back the programmed

Configuration bits and verifies that the programming

was successful.

FIGURE 4-5: CONFIGURATION BIT PROGRAMMING FLOW

Note: If the General Segment Code-Protect bit

(GCP ) is programme d to ‘0’, code mem ory

is code-protected and can not be read.

Code memory must be verified before

enabling read protection. See

Section 4.6.4 “Code-Protect Configura-

tion Bits” for more information about

code-protect Configuration bits.

Send PROGP

Command

ConfigAddress = 0XXXFAh(1)

PROGP response

PASS?

Yes

Failure

Report Error

Start

Finish

Yes

ConfigAddress

0XXXFEh?(1)

ConfigAddress =

ConfigAddress + 2

Note 1: Refer to Table 2-2 for Flash Configuration Word addresses.

 2011 Microchip Technology Inc. DS39907B-page 33

PIC24FJXXXGA1/GB1

4.6.4 CODE-PROTECT CONFIGURATION

BITS

PIC24FJXXXGA1/GB1 family devices provide two

complimentary methods to protect application code

from overwrites and erasures. These also help to pro-

tect the device from inadvertent configuration changes

during run time. Additional information is available in

the product data sheet.

4.6.4.1 GENERAL SEGMENT

PROTECTION

For all devices in the PIC24FJXXXGA1/GB1 families,

the on-chip program memory space is treated as a

single block, known as the General Segment (GS).

Code protect ion for this block is con trolled by on e Co n-

figuration bit, GCP. This bit inhibits external reads and

writes to the program memory space. It has no direct

effect in normal execution mode.

Write protection is controlled by the GWRP bit in the

Configuration Word. When GWRP is programmed to

‘0’, internal write and erase operations to program

memory are blocked.

4.6.4.2 CODE SE GMENT PRO T E CT IO N

In addition to global General Segment protection, a

separate subrange of the program memory space can

be individually protected against writes and erases.

This area can be used for many purposes where a

separate block of write and erase-protected code is

needed, such as bootloader applications. Unlike

commo n boot block im plement ations, the sp ecially pro-

tected segment in PIC24FJXXXGA1/GB1 devices can

be loca ted by the user anyw here in t he prog ram sp ace,

and configured in a wide range of sizes.

Code segment protection provides an added level of

prote cti on t o a d es ign ated are a of program memo ry by

disabling the NVM safety interlock whenever a write or

erase add ress falls within a spec ified range. It do es not

override general segment protection controlled by the

GCP or GWRP bits. For example, if GCP and GWRP

are enabled, enabling segmented code protection for

the bottom half of program memory does not undo

general se gment protection for the top half.

4.7 Exiting Enhanced ICSP Mode

Exiting Program/Verify mode is done by removing VIH

from MCLR, as shown in Figure 4-6. The only require-

ment for exit is that an interval, P16, should elapse

between the last clock and program signals on PGCx

and PGDx, before removing VIH.

FIGURE 4-6: EXITING ENHANCED

ICSP™ MODE

Note: Bulk Erasing in ICS P mode is the onl y way

to repro gram co de-prote ct bits fr om an ON

state (‘0’) to an OFF state (‘1’).

MCLR

P16

PGDx

PGDx = Input

PGCx

VDD

VIH

P17

PIC24FJXXXGA1/GB1

DS39907B-page 34  2011 Microchip Technology Inc.

5.0 THE PROGRAMMING

EXECUTIVE

5.1 Programming Executive

Communication

The programmer and programming executive have a

master-slave relationship, where the programmer is

the master programming device and the programming

executive is the slave.

All communication is initiated by the programmer in the

form of a c o mma n d. O nl y on e comm an d at a t i me c an

be sent to the programming executive. In turn, the

programming executive only sends one response to

the programmer after receiving and processing a

command. The programming executive command set

is des cribed in Section 5.2 “Programm ing Exe cutive

Commands”. The response set is described in

Section 5.3 “Pr ogramming Executive Responses”.

5.1.1 COMMUNICATION INTERFACE

AND PROTOCOL

The Enhanced ICSP interface is a 2-wire SPI,

implemented using the PGCx and PGDx pins. The

PGCx pin is used as a clock input pin and the clock

source must be provided by the programmer. The

PGDx pin is used for sending command data to, and

receiving response data from, the programming

executive.

Dat a tran sm its to the device mu st c hange on the rising

edge and hold on the falling edge. Data receives from

the devi ce must chang e on the falli ng edge and hold on

the rising edge.

All data transmissions are sent to the Most Significant

bit (MSb) first, using 16-bit mode (see Figure 5-1).

FIGURE 5-1: PROGRAMMING

EXECUTIVE SERIAL

TIMING FOR DATA

RECEIVED FROM DEVICE

FIGURE 5-2: PROGRAMMING

EXECUTIVE SERIAL TIMING

FOR DATA TRANSMITTED

TO DEVICE

Since a 2-wire SPI is us ed , and data t rans mi ss io ns a r e

half duplex, a simple protocol is used to control the

directio n of PGD x . Whe n the pro gram m er compl etes a

command transmission, it releases the PGDx line and

allows the programming executive to drive this line

high. Th e progra mmin g exec utive keep s th e PGDx line

high to indicate that it is processing the command.

After the programming executive has processed the

comman d, it b rin gs PGDx low fo r 15 s to indicate to the

programmer that the response is available to be clocked

out. The programmer can begin to clock out the response

23 s after PGDx is brought low, and it must provide the

necessary amount of clock pulses to receive the entire

response from t he pr ogramming ex ec ut iv e.

After the entire response is clocked out, the program-

mer should terminate the clock on PGCx until it is time

to send another command to the programming

executiv e. This protocol is shown in Figure 5-3.

5.1.2 SPI RATE

In Enhanced ICSP mode, the PIC24FJXXXGA1/GB1

devices operate from the Internal Fast RC oscillator

(FRCDIV), which has a nominal frequency of 8 MHz.

This oscillator frequency yields an effective system

clock frequ en cy of 4 MHz. To ensure that th e pro gram -

mer does not clock too fast, it is recommended that a

4 MHz clock be provided by the programmer.

5.1.3 TIME-OUTS

The programming executive uses no Watchdog Timer

or time-out for transmitting responses to the program-

mer. If the programmer does not follow the flow control

mechanism using PGCx, as described in Section 5.1.1

“Communication Interface and Protocol”, it is

possible that the programming executive will behave

unexpectedly while trying to send a response to the

programmer. Since the programming executive has no

time-out, it is imperative that the programmer correctly

follow the described communication protocol.

As a safety measure, the programmer should use the

command time-outs identified in Table 5-1. If the

command time-out expires, the programmer should

reset the programming executive and start

programming the device again.

PGCx

PGDx

123 11 13 15 16

LSb

14 13 12 11

45 6

MSb 123

... 45

P1B

P1A

PGCx

PGDx

123 11 13 15 16

LSb

14 13 12 11

45 6

MSb 123

... 45

P1B

P1A

 2011 Microchip Technology Inc. DS39907B-page 35

PIC24FJXXXGA1/GB1

FIGURE 5-3: PROGRAMMING EXECUTIVE – PROGRAMMER COMMUNICATION PROTOCOL

5.2 Programming Executive

Commands

The programming executive command set is shown in

Table 5-1. This table contains the opcode, mnemonic,

length, time-out and description for each command.

Functional details on each command are provided in

Section 5.2.4 “Command Descriptions”.

5.2.1 COMMAND FORMAT

All programming executive commands have a general

format consisting of a 16-bit header and any required

data for the command (see Figure 5-4). The 16-bit

header co nsist s of a 4-bit opcode fi eld, which is use d to

identify the command, followed by a 12-bit command

length field.

FIGURE 5-4: COMMAND FORMAT

The comm and opcode must match one of those in the

command set. Any command that is received which

does no t match the l ist in Table 5-1 will return a “NACK”

response (see Section 5.3.1.1 “O pc ode Field ” ).

The command length is represented in 16-bit words

since the SPI operates in 16-bit mode. The program-

ming executive uses the command length field to

determine the number of words to read from the SPI

port. If the value of this field is incorrect, the command

will not be properly received by the programming

executive.

5.2.2 PAC KED DATA FORMAT

When 24-bit instruction words are transferred across

the 16-bit SPI interface, they are packed to conserve

space using the format shown in Figure 5-5. This

format minimizes traffic over the SPI and provides the

programming executive with data that is properly

aligned for performing table write operations.

FIGURE 5-5: PACKED INSTRUCTION

WORD FORMAT

5.2.3 PROGRAMMING EXECUTIVE

ERROR HANDLING

The programming executive will “NACK” all

unsupported commands. Additionally, due to the

memory constraints of the programming executive, no

checking is performed on the data contained in the

programmer command. It is the responsibility of the

programmer to command the programming executive

with valid command arguments or the programming

operation may fail. Additional information on error

handling is provided in Section 5.3.1.3 “QE_Code

Field”.

1 2 15 16 1 2 15 16

PGCx

PGDx

PGCx = Input PGCx = Input (Idle)

Host Transmits

Last Command Word

PGDx = Input PGDx = Output

12 1516

MSB X X X LSB MSB X X X LSB MSB X X X LSB

1 0

P20

PGCx = Input

PGDx = Output

Progra mm ing Ex ecutive

Processes Command Host Clocks Out Response

P21

15 12 11 0

Opcode Length

Command Dat a First W ord (if require d)

•

Command Dat a Las t W ord (if require d)

Note: When the number of instruction words

transferred is odd, MSB2 is zero and

LSW2 can not be transmitted.

15 8 7 0

LSW1

MSB2 MSB1

LSW2

LSWx: Least Significant 16 bits of instruction word

MSBx: Most Significant Bytes of instruction word

PIC24FJXXXGA1/GB1

DS39907B-page 36  2011 Microchip Technology Inc.

TABLE 5-1: PROGRAMMING EXE CUTIV E COMMAN D SET

5.2.4 COMMAND DESCRIPTIONS

All commands supported by the progra mming executive

are described in Section 5.2.5 “SCHECK Co mmand”

through Section 5.2.12 “QVER Command”.

5.2.5 SCHECK COMMAND

The SCHECK command instructs the programming

exec utiv e to do not hing b ut ge nera te a re spon se. This

comma nd is use d as a “Sani ty Che ck” to ve rify that the

programming executive is operational.

Expected Response (2 words):

1000h

0002h

Opcode Mnemonic Length

(16-bit words) Time-out Description

0h SCHECK 1 1 ms Sanity check.

1h READC 3 1 ms Read an 8-bit word from the specified Device ID register.

2h READP 4 1 ms/row Read N 24-bit instruction words of code memory starting from

the specified address.

3h RESERVED N/A N/A This command is reserved. It will return a NACK.

4h PROGC 4 5 ms Write an 8-bit word to the specified Device ID registers.

5h PROGP 99 5 ms Program one row of code memory at the specified address,

then verify.(1)

Dh PROGW 4 5 ms Program one ins tructi on wo rd of co de mem ory at t he speci fied

address, the n verify.

7h RESERVED N/A N/A This command is reserved. It will return a NACK.

8h RESERVED N/A N/A This command is reserved. It will return a NACK.

9h RESERVED N/A N/A This command is reserved. It will return a NACK.

Ah QBLANK 3 TBD Query if the code memory is blank.

Bh QVER 1 1 ms Query the programming executive software version.

Legend: TBD = To Be Determined

Note 1: One row of code memory consists of (64) 24-bit words. Refer to Table 2-2 for device-specific information.

15 12 11 0

Opcode Length

Field Description

Opcode 0h

Length 1h

Note: This instruction is not required for

programming but is provided for

development purposes onl y.

 2011 Microchip Technology Inc. DS39907B-page 37

PIC24FJXXXGA1/GB1

5.2.6 READC COMMAND

The READC command instructs the programming

executive to read N or Device ID registers, starting from

the 24-bit address specified by Addr_MSB and

Addr_LS. Thi s command ca n only be used to rea d 8-bit

or 16-bit data.

When this command is used to read Device ID

the programming executive is 00h and the lower byte

contains the Device ID register value.

Expected Response (4 + 3 * (N – 1)/2 words for N odd):

1100h

2 + N

Device ID Register 1

...

Device ID Register N

5.2.7 READP COMMAND

The READP command instructs the programming

executive to read N 24-bit words of code memory,

inc ludi ng Co nf igura tio n Words , s tart ing from the 24- bit

address specified by Addr_MSB and Addr_LS. This

comma nd can only be used t o read 2 4-bit d ata. Al l dat a

returned i n response to this co mmand us es the p acked

data format described in Section 5.2.2 “Packed Data

Format”.

Expected Response (2 + 3 * N/2 words for N even):

1200h

2 + 3 * N/2

Least significant program memory word 1

...

Least significant data word N

Expected Response (4 + 3 * (N – 1)/2 words for N odd):

1200h

4 + 3 * (N – 1)/2

Least significant program memory word 1

...

MSB of progra m mem ory w ord N (zero p a dde d)

15 12 11 8 7 0

Opcode Length

NAddr_MSB

Addr_LS

Field Description

Opcode 1h

Length 3h

N Number of 8-bit Device ID registers to

read (max. of 256)

Addr_MSB MSB of 24-bit source address

Addr_LS Least Significant 16 bits of 24-bit

source add res s

Note: Reading unimplemented memory will

cause the programming executive to

reset. Please ensure that only memory

locations present on a particular device

are accessed.

15 12 11 8 7 0

Opcode Length

Reserved Addr_MSB

Addr_LS

Field Description

Opcode 2h

Length 4h

N Number of 24-bit instructions to read

(max. of 32768)

Reserved 0h

Addr_MSB MSB of 24-bit source address

Addr_LS Least Significant 16 bits of 24-bit

source address

Note: Reading unimplemented memory will

cause the programming executive to

reset. Please ensure that only memory

locations present on a particular device

are accessed.

PIC24FJXXXGA1/GB1

DS39907B-page 38  2011 Microchip Technology Inc.

5.2.8 PROGC COMMAND

The PROGC command instructs the programming

executive to program a single Device ID register

located at the specified memory address.

Aft er the speci fie d data word has been programmed to

code memory, the programming executive verifies the

programmed data against the data in the command.

Expected Response (2 words):

1400h

0002h

5.2.9 PROGP COMMAND

The PROGP command instructs the programming

executive to program one row of code memory, includ-

ing Configuration Words (64 instruction words), to the

specified memory address. Programming begins with

the row address specified in the command. The

destination address should be a multiple of 80h.

The data to program to memory, located in command

words, D_1 th rou gh D _ 96, m ust b e arra nge d u sin g th e

packed instruction word format shown in Figure 5-5.

After all data has been programmed to code memory,

the programming executive verifies the programmed

data against the data in the command.

Expected Response (2 words):

1500h

0002h

15 12 11 8 7 0

Opcode Length

Reserved Addr_MSB

Addr_LS

Data

Field Description

Opcode 4h

Length 4h

Reserved 0h

Addr_MSB MSB of 24-bit destination address

Addr_LS Least S igni fican t 16 bits of 24-bit

destination address

Data 8-bit data word

15 12 11 8 7 0

Opcode Length

Reserved Addr_MSB

Addr_LS

D_1

D_2

...

D_96

Field Description

Opcode 5h

Length 63h

Reserved 0h

Addr_MSB MSB of 24-bit destination address

Addr_LS Least Significant 16 bits of 24-bit

destinati on add res s

D_1 16-bit Data W o rd 1

D_2 16-bit Data W o rd 2

... 16-bit Data Word 3 through 95

D_96 16-bit Data Word 96

Note: Refer to Table 2-2 for code memory size

information.

 2011 Microchip Technology Inc. DS39907B-page 39

PIC24FJXXXGA1/GB1

5.2.10 PROGW COMMAND

The PROGW command instructs the programming

executive to program one word of code memory

(3 bytes) to the specific memory address.

Aft er the word ha s been pro gramm ed to cod e memo ry,

the programming executive verifies the programmed

data against the data in the command.

Expected Response (2 words):

1600h

0002h

5.2.11 QBLANK COMMAND

The QBLANK command queries the programming

executive to determine if the contents of code memory

and code-protect Configuration bits (GCP and GWRP)

are bla nk (cont ain al l ‘1’ s). The s ize of co de mem ory to

check must be specified in the command.

The Blank Check for code memory begins at 0h and

advances toward larger addresses for the specified

number of instruction words.

QBLANK returns a QE_Code of F0h if the specified

code memory and code-protect bits are blank;

otherwise, QBLANK returns a QE_Code of 0Fh.

Expected Response (2 words for blank device):

1AF0h

0002h

Expected Response (2 words for non-blank device):

1A0Fh

0002h

15 12 11 8 7 2 1 0

Opcode Length

Data_MSB Addr_MSB

Addr_LS

Data_LS

Field Description

Opcode Dh

Length 4h

Reserved 0h

Addr_MSB MSB of 24-bit destination address

Addr_LS Least Significant 16 bits of 24-bit

destination address

Data_MSB MSB of 24-bit data

Data_LS Least Significant 16 bits of 24-bit data

15 12 11 0

Opcode Length

PSize_MSW

PSize_LSW

Field Description

Opcode Ah

Length 3h

PSize Length of program memory to check

in 24-bit words plus one (max. of

49152)

Note: QBLANK does not check the system

operation Configuration bits, since these

bits are not set to ‘1’ when a Chip Erase is

performed.

PIC24FJXXXGA1/GB1

DS39907B-page 40  2011 Microchip Technology Inc.

5.2.12 QVER COMMAND

The QVER command queries the version of the

programming executive software stored in test

memory. The “version.revision” inform ation is returned

in the res ponse’ s QE_Code u sing a single by te with the

following format: main version in upper nibble and

revisio n in the lower nib ble (i.e., 23 h means V ersion 2.3

of programming executive software).

Expected Response (2 words):

1BMNh (where “MN” stands for version M.N)

0002h

5.3 Programming Executive

Responses

The programming executive sends a response to the

programmer for each command that it receives. The

response indicates if the command was processed

correctly. It includes any required response data or

error data.

The programming executive response set is shown in

Table 5-2. This table contains the opcode, mnemonic

and description for each response. The response format

is described in Section 5.3.1 “Response Format”.

TABLE 5-2: PROGRAMMING EXECUTIVE

RESPONSE OP CODES

5.3.1 RESPONSE FORMAT

All programming executive responses have a general

format consisting of a two-word header and any

required data for the command.

5.3.1.1 Opcode Field

The opcode is a 4-bit field in the first word of the

response. The opcode indicates how the command

was processed (see Table 5-2). If the command was

process ed successfu lly, the response op code is PASS.

If there was an error in processing the command, the

response opcode is FAIL and the QE_Code indicates

the reason for the failure. If the command sent to

the programming executive is not identified, the

programming executive returns a NACK response.

5.3.1.2 Last_Cmd Fiel d

The Last_Cmd is a 4-bit field in the first word of

the response and indicates the command that the

programming exec utive processed. Since the pro gram-

ming executive can only process one command at a

time, this field is technically not required. However, it

can be used to verify that the programming executive

correctly received the command that the programmer

transmitted.

15 12 11 0

Opcode Length

Field Description

Opcode Bh

Length 1h

Opcode Mnemonic Description

1h PASS Command successfully

processed

2h FAIL Command unsuccessfully

processed

3h NACK Command not known

Field Description

Opcode Response opcode

Last_Cmd Programmer command that

generated the respon se

QE_Code Query code or error code.

Length Response length in 16-bit words

(includes 2 header words)

D_1 First 16-bit data word (if applicable)

D_N Last 16-bit data word (if applicable)

15 12 11 8 7 0

Opcode L ast_Cmd QE_Code

Length

D_1 (if applicable)

...

D_N (if applicable)

 2011 Microchip Technology Inc. DS39907B-page 41

PIC24FJXXXGA1/GB1

5.3.1.3 QE_Code Field

The QE_Code is a byte in the first word of the

response. This byte is used to return data for query

commands and error codes f or all o ther commands.

When the programming e xecutive processes one of the

two query commands (QBLANK or QVER), the

returned opcode is always PASS and the QE_Code

holds the query response data. The format of the

QE_Code for both queries is shown in Table 5-3.

TABLE 5-3: QE_Code FOR QUERIES

When the programming executive processes any

command other th an a query, the QE_ Code repr esent s

an error code. Supported error codes are shown in

Table 5-4. If a comm and i s su cces sfully proc essed , th e

returned QE_Code is set to 0h, which indicates that

there was no error in the command processing. If the

verify of the programming for the PROGP or PROGC

command fails, the QE_Code is set to 1h. For all other

programming executive errors, the QE_Code is 2h.

TABLE 5-4: QE_Code FOR NON-QUERY

COMMANDS

5.3.1.4 Response Length

The response length indicates the length of the

programming executive’s response in 16-bit words.

This fi eld incl udes the 2 words of the re sponse header.

With the exception of the response for the READP

command, the length of each response is only 2 words.

The response to the READP command uses the

packed instruction word format described in

Section 5.2.2 “Packed Data Format”. When reading

an odd num ber of pro gram me mory w ords (N od d), the

response to the READP command is (3 * (N + 1)/2 + 2)

words. When reading an even number of program

memory words (N even), the response to the READP

comm and is (3 * N/2 + 2) words.

Query QE_Code

QBLANK 0Fh = Code memo ry is N OT blank

F0h = Code memo ry is bla nk

QVER 0xMN, where programming executive

software version = M.N (i.e., 32h means

software version 3.2 )

QE_Code Description

0h No error

1h Verify failed

2h Other error

PIC24FJXXXGA1/GB1

DS39907B-page 42  2011 Microchip Technology Inc.

5.4 Programming the Programming

Executive to Memory

5.4.1 OVERVIEW

If it is determined that the programming executive is

not present in executive memory (as described

in Section 4.2 “Confirming the Presence of the

Programming Executive”), it must be programmed

into executive memory using ICSP, as described in

Secti on 3 .0 “Dev ic e Pr ogr a mmi ng – IC SP” .

Storing the programming executive to executive

memory is similar to normal programming of code

memory. Namely, the executive memory must be

erased, and then the programming executive must be

programmed 64 words at a time. Erasing the last page

of executive memory will cause the FRC oscillator

calibration settings and device diagnostic data in the

Diagnostic and Calibration Words, at addresses,

8007F0h to 8007FEh, to be erased. In order to retain

this ca libration, these memor y locations sh ould be read

and stored prior to erasing executive memory. They

should the n be rep r ogra mmed in the las t words of pro-

gram memory. This control flow is summarized in

Table 5-5.

TABLE 5-5: PROGRAMMING THE PROGRAMMING EXECUTIVE

Command

(Binary) Data

(Hex) Description

Step 1: Exit Reset vector and erase executive memory.

0000

000000

040200

000000

NOP

GOTO 0x200

NOP

Step 2: Initialize pointers to read Diagnostic and Calibration Words for storage in W6-W13.

0000

200800

880190

207F01

2000C2

000000

MOV #0x80, W0

MOV W0, TBLPAG

MOV #0x07F0, W1

MOV #0xC, W2

NOP

Step 3: Repeat t his st ep 8 times to re ad Diagnostic and Calibration Words, storin g them in W register s, W6-W13.

0000

BA1931

000000

TBLRDL [W1++].[W2++]

NOP

Step 4: Initialize the NVMCON to erase executiv e memory.

0000

0000 240420

883B00 MOV #0x4042, W0

MOV W0, NVMCON

Step 5: Initialize Erase Pointers to first page of executive and then initiate the erase cycle.

0000

00000

0000

200800

880190

200001

000000

BB0881

000000

A8E761

000000

MOV #0x80, W0

MOV W0, TBLPAG

MOV #0x0, W1

NOP

TBLWTL W1, [W1]

NOP

BSET NVMCON, #15

NOP

Step 6: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.

0000

0001

0000

040200

000000

803B02

883C22

000000

<VISI>

000000

GOTO 0x200

NOP

MOV NVMCON, W2

MOV W2, VISI

NOP

Clock out co ntent s of t he VI SI reg ister .

NOP

 2011 Microchip Technology Inc. DS39907B-page 43

PIC24FJXXXGA1/GB1

Step 7: Repeat Steps 5 and 6 to erase the second page of executive memory. The W1 Pointer should be

incremented by 400h to point to the second page.

Step 8: Initialize TBLPAG and NVMCON to write stored diagnostic and calibration as single words. Initialize W1

and W2 as Write and Read Pointers to rewrite stored Diagnostic and Calibration Words.

0000

200800

880190

240031

883B01

207F01

2000C2

000000

MOV #0x80, W0

MOV W0, TBLPAG

MOV #0x4003, W1

MOV W1, NVMCON

MOV #0x07F0, W1

MOV #0xC, W2

NOP

Step 9: Perform write of a si ngle word of calibration data and initiate single-word write cycle.

0000

BB18B2

000000

A8E761

000000

TBLWTL [W2++], [W1++]

NOP

BSET NVMCON, #15

NOP

Step 10: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.

0000

0001

0000

040200

000000

803B00

883C20

000000

<VISI>

000000

GOTO 0x200

NOP

MOV NVMCON, W0

MOV W0, VISI

NOP

Clock out contents of VISI register.

NOP

Step 11: Repeat Steps 9-10 seven more times to program the remainder of the Diagnostic and Calibration Words

back into program me mory.

Step 12: Initialize the NVMCON to program 64 instruction words.

0000

0000 240010

883B00 MOV #0x4001, W0

MOV W0, NVMCON

Step 13: Initialize TBLPAG and the Write Pointer (W7).

0000

200800

880190

EB0380

000000

MOV #0x80, W0

MOV W0, TBLPAG

CLR W7

NOP

Step 14: Load W0:W5 with the next four words of packed programming executive code and initialize W6 for pro-

grammi ng. Programm ing start s from the ba se of executiv e memory (80 0000h) usin g W6 as a Read Pointe r

and W7 as a Wri te Pointer.

0000

2<LSW0>0

2<MSB1:MSB0>1

2<LSW1>2

2<LSW2>3

2<MSB3:MSB2>4

2<LSW3>5

MOV #<LSW0>, W0

MOV #<MSB1:MSB0>, W1

MOV #<LSW1>, W2

MOV #<LSW2>, W3

MOV #<MSB3:MSB2>, W4

MOV #<LSW3>, W5

TABLE 5-5: PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED)

Command

(Binary) Data

(Hex) Description

PIC24FJXXXGA1/GB1

DS39907B-page 44  2011 Microchip Technology Inc.

Step 15: Set the Read Pointer (W6) and load the (nex t four write) latches.

0000

EB0300

000000

BB0BB6

000000

BBDBB6

000000

BBEBB6

000000

BB1BB6

000000

BB0BB6

000000

BBDBB6

000000

BBEBB6

000000

BB1BB6

000000

CLR W6

NOP

TBLWTL [W6++], [W7]

NOP

TBLWTH.B [W6++], [W7++]

NOP

TBLWTH.B [W6++], [++W7]

NOP

TBLWTL [W6++], [W7++]

NOP

TBLWTL [W6++], [W7]

NOP

TBLWTH.B [W6++], [W7++]

NOP

TBLWTH.B [W6++], [++W7]

NOP

TBLWTL [W6++], [W7++]

NOP

Step 16: Repeat Steps 14-15, si xteen times, to load the write latches for the 64 instructions.

Step 17: Initiate the programming cycle.

0000

A8E761

000000

BSET NVMCON, #15

NOP

Step 18: Repeat this step to poll the WR bit (bit 15 of NVMCON) until it is cleared by the hardware.

0000

0001

0000

040200

000000

803B02

883C22

000000

<VISI>

000000

GOTO 0x200

NOP

MOV NVMCON, W2

MOV W2, VISI

NOP

Clock out co ntent s of t he VI SI reg ister .

NOP

Step 19: Reset the device internal PC.

0000

0000 040200

000000 GOTO 0x200

NOP

Step 20: Repeat Steps 14-1 9 u ntil al l 16 rows of exe cu tiv e m emory h ave been programm ed. On the final row, make

sure to in itialize the write latches at the Diagnostic and Calibration Words locations with 0xFFFFFF to

ensure that the calibration is not overwritten.

TABLE 5-5: PROGRAMMING THE PROGRAMMING EXECUTIVE (CONTINUED)

Command

(Binary) Data

(Hex) Description

 2011 Microchip Technology Inc. DS39907B-page 45

PIC24FJXXXGA1/GB1

5.4.2 PROGRAMMING VERIFICATION

After the programming executive has been

programmed to executive memory using ICSP, it must

be verifie d. Verificati on is perfo rmed by reading ou t the

contents of executive memory and comparing it with

the image of the programming executive stored in the

programmer.

Reading the contents of executive memory can be

performed using the same technique described in

Section 3.8 “Reading Code Memory”. A procedure

for reading executive memory is shown in Table 5-6.

Note that in Step 2, the TBLPAG register is set to 80h,

such that executive memory may be read. The last

eight words of executive memory should be verified

with stored values of the Diagnostic and Calibration

Words to ensure accuracy.

TABLE 5-6: READING EXECUTIVE MEMORY

Command

(Binary) Data

(Hex) Description

Step 1: Ex it the R ese t vector.

0000

000000

040200

000000

NOP

GOTO 0x200

NOP

Step 2: Initialize TBLPAG and the Read Pointer (W6) for TBLRD instruction.

0000

200800

880190

EB0300

MOV #0x80, W0

MOV W0, TBLPAG

CLR W6

Step 3: Initialize the Write Pointer (W7) to point to the VISI register.

0000

0000 207847

000000 MOV #VISI, W7

NOP

Step 4: Read and clock out the contents of the ne xt two locations of executive memory through the VISI register

using the REGOUT command.

0000

0001

0000

0001

0000

0001

0000

BA0B96

000000

<VISI>

000000

BADBB6

000000

BAD3D6

000000

<VISI>

000000

BA0BB6

000000

<VISI>

000000

TBLRDL [W6], [W7]

NOP

Clock out contents of VISI register

NOP

TBLRDH.B [W6++], [W7++]

NOP

TBLRDH.B [++W6], [W7--]

NOP

Clock out contents of VISI register

NOP

TBLRDL [W6++], [W7]

NOP

Clock out contents of VISI register

NOP

Step 5: Rese t the device internal PC.

0000

0000 040200

000000 GOTO 0x200

NOP

Step 6: Repeat Steps 4-5 until all 1024 instruction words of executive memory are read.

PIC24FJXXXGA1/GB1

DS39907B-page 46  2011 Microchip Technology Inc.

6.0 DEVICE DETAILS

6.1 Device ID

The Device ID region of memory can be used to

determine mask, variant and manufacturing

information about the chip. The Device ID region is

2 x 16 bits and it can be read using the READC

comma nd. Th is re gio n of memory is rea d-o nly a nd can

also be read when code protection is enabled.

Table 6-1 shows the Device ID for each device, Table 6-2

shows the Device ID registers and Table 6-3 describes

the bit field of each register.

TABLE 6-2: PIC24FJXXXGA1/GB1 DEVICE ID REGISTERS

TABLE 6-3: DEVICE ID BIT DESCRIPTIONS

TABLE 6-1: DEVICE IDs

Device DEVID

PIC24FJ64GA106 1000h

PIC24FJ128GA106 1008h

PIC24FJ192GA106 1010h

PIC24FJ256GA106 1018h

PIC24FJ64GA108 1002h

PIC24FJ128GA108 100Ah

PIC24FJ192GA108 1012h

PIC24FJ256GA108 101Ah

PIC24FJ64GA110 1006h

PIC24FJ128GA110 100Eh

PIC24FJ192GA110 1016h

PIC24FJ256GA110 101Eh

PIC24FJ64GB106 1001h

PIC24FJ128GB106 1009h

PIC24FJ192GB106 1011h

PIC24FJ256GB106 1019h

PIC24FJ64GB108 1003h

PIC24FJ128GB108 100Bh

PIC24FJ192GB108 1013h

PIC24FJ256GB108 101Bh

PIC24FJ64GB110 1007h

PIC24FJ128GB110 100Fh

PIC24FJ192GB110 1017h

PIC24FJ256GB110 101Fh

Address Name Bit

1514131211109876543210

FF0000h DEVID — FAMID<7:0> DEV<5:0>

FF0002h DEVREV —MAJRV<2:0>—DOT<2:0>

Bit Field Register Description

FAMID<7:0> DEVID Encodes the family ID of the device

DEV<5:0> DEVID Encodes the individual ID of the device

MAJRV<2:0> DEVREV Encodes the major revision number of the device

DOT<2:0> DEVREV Encodes the minor revision number of the device

 2011 Microchip Technology Inc. DS39907B-page 47

PIC24FJXXXGA1/GB1

6.2 Checksum Comput ation

Checksums f or the PIC24FJ XXXGA1/GB1 fam ilies are

16 bits in size. The checksum is calculated by su mming

the following:

• Contents of code memory locations

• Contents of Configuration registers

Table 6-4 describes how to calcul ate the checksum for

each device. All memory locations are summed, one

byte at a time, using only their native data size. More

specifically, Configuration registers are summed by

adding the lower two bytes of these locations (the

upper byte is ignored), while code memory is summed

by adding all three bytes of code memory.

TABLE 6-4: CHECKSUM COMPUTATION

Device Read Code

Protection Checksum Computation Erased

Checksum

Value

Checksum with

0xAAAAAA at

0x0 and Last

Code Address

PIC24FJ64 GA1 06 Disabled CFGB + SUM(0:ABF 9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ128GA106 Disabled CFGB + SUM(0:157F9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ192GA106 Disabled CFGB + SUM(0:20BF9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ256GA106 Disabled CFGB + SUM(0:2ABF9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ64 GA1 08 Disabled CFGB + SUM(0:ABF 9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ128GA108 Disabled CFGB + SUM(0:157F9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ192GA108 Disabled CFGB + SUM(0:20BF9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ256GA108 Disabled CFGB + SUM(0:2ABF9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ64 GA110 Disabled CF GB + SUM(0:ABF 9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ128GA110 Disabled CFGB + SUM(0:157F9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ192GA110 Disabled CFGB + SUM(0:20BF9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ256GA110 Disabled CFGB + SUM(0:2ABF9) TBD TBD

Enabled 0 TBD TBD

Legend: Item Description

SUM[a:b] = Byte sum of locations, a to b inclusive (all 3 bytes of code memory)

CFGB = CFGB = Configuration Block (masked) Byte sum of (CW1 & 0x7BDF + CW2 & 0xF7FF +

CW3 & 0xE1FF)

TBD = To Be Determined

Note: CW1 address is last location of implemented program memory; CW2 is (last location – 2); CW3 is (last

loc ation – 4).

PIC24FJXXXGA1/GB1

DS39907B-page 48  2011 Microchip Technology Inc.

PIC24FJ64 GB1 06 Disabled CFGB + SUM(0:ABF 9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ128GB106 Disabled CFGB + SUM(0:157F9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ192GB106 Disabled CFGB + SUM(0:20BF9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ256GB106 Disabled CFGB + SUM(0:2ABF9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ64 GB1 08 Disabled CFGB + SUM(0:ABF 9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ128GB108 Disabled CFGB + SUM(0:157F9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ192GB108 Disabled CFGB + SUM(0:2ABF9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ256GB108 Disabled CFGB + SUM(0:20BF9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ64 GB110 Disabled CF GB + SUM(0:ABF 9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ128GB110 Disabled CFGB + SUM(0:157F9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ192GB110 Disabled CFGB + SUM(0:20BF9) TBD TBD

Enabled 0 TBD TBD

PIC24FJ256GB110 Disabled CFGB + SUM(0:2ABF9) TBD TBD

Enabled 0 TBD TBD

TABLE 6-4: CHECKSUM COMPUTATION (CONTINUED)

Device Read Code

Protection Checksum Computation Erased

Checksum

Value

Checksum with

0xAAAAAA at

0x0 and Last

Code Address

Legend: Item Description

SUM[a:b] = Byte sum of locations, a to b inclusive (all 3 bytes of code memory)

CFGB = CFGB = Configuratio n Block ( masked) Byte sum of (CW1 & 0x7BDF + CW2 & 0xF7FF +

CW3 & 0xE1FF)

TBD = To Be Determined

Note: CW1 address is last location of implemented program memory; CW2 is (last location – 2); CW3 is (last

loc ation – 4).

 2011 Microchip Technology Inc. DS39907B-page 49

PIC24FJXXXGA1/GB1

7.0 AC/DC CHARACTERISTICS AND TIMING REQUIREMENTS

Standard Operating Condition s

Oper ati ng Temperatu re : 0C to +70C. Progr am m ing at +25C is recommended.

Param

No. Symbol Characteristic Min Max Units Conditions

D111 VDD Supply Voltage During Progra m m in g VDDCORE + 0.1 3.60 V Normal programmin g(1,2)

D111B — Supply Voltage on V DDCORE Duri ng

Programming 2.25 2.75 V

D112 IPP Programming Current on MCLR —5A

D113 IDDP Supply Current Dur i ng Pr og ra m m in g — 2 mA

D031 VIL Input Low Voltage VSS 0.2 VDD V

D041 VIH Input High Voltage 0.8 VDD VDD V

D080 VOL Output Lo w Voltage — 0.4 V IOL = 8.5 mA @ 3. 6V

D090 VOH Output High Voltage 3.0 — V IOH = -3.0 mA @ 3.6V

D012 CIO Capacitive Loading on I/O pin (PGDx) — 50 pF To meet AC specifications

D013 CFFilter Capacitor Value on VCAP 4.7 10 F Required for controller core

P1 TPGC Serial Clock (PGCx) Period 100 — ns

P1A TPGCL Serial Cloc k (PGCx) Low Time 40 — ns

P1B TPGCH Serial Clock (P GCx) High Time 40 — ns

P2 TSET1 Input Data Setup Time to Serial Clock 15 — ns

P3 THLD1 Input Data Hold Time from PGCx 15 — ns

P4 TDLY1 Delay Bet ween 4-Bit Com m and and

Comma nd O perand 40 — ns

P4A TDLY1ADelay Betwee n 4- Bit Command O per and

and Next 4- Bi t Co m m and 40 — ns

P5 TDLY2 Delay Between Last PGCx  of Command

Byte to First PGCx  of Read of Data Word 20 — ns

P6 TSET2VDD Setup Time to MCLR 100 — ns

P7 THLD2 Input Data Hold Time from MCLR 25 — ms

P8 TDLY3 Delay Between Last PGCx  of Command

Byte to PGDx  by Programm ing Executive 12 — s

P9 TDLY4 Programming Executive Command

Processing Time 40 — s

P10 TDLY6 PGCx Low Time After Pr ogramming 400 — ns

P11 TDLY7 Chip Er ase Tim e 400 — ms

P12 TDLY8 Page Erase Time 40 — ms

P13 TDLY9 Row Programm in g Time 2 — ms

P14 TRMCLR Rise Time to Enter ICSP™ mode — 1.0 s

P15 TVALID Data Out Valid from PGCx 10 — ns

P16 TDLY10 Delay Between Last PGCx  and MCLR 0—s

P17 THLD3MCLR to VDD 100 — ns

P18 TKEY1 Delay from First MCLR to First PGCx for

Key Sequence on PGDx 40 — ns

P19 TKEY2 Delay from Last PGCx for Key Sequence

on PGDx to Second MCLR  1—ms

P20 TDLY11 Delay Between PGDx  by Programmi ng

Executive to PGDx Driven by Host 23 — µs

Note 1: VDDCORE must be supplied to the VDDCORE/VCAP pin if the on-chip voltage regulator is disabled. See Section 2.1

“Power Requirements” for more information. (Minimum VDDCORE allowing Flas h pr ogramming i s 2. 25V.)

2: VDD must also be supplied to the AVDD pins du ri ng p ro gr ammi ng . AVDD and AVSS should always be within ±0.3V

of VDD and VSS, respec tively.

PIC24FJXXXGA1/GB1

DS39907B-page 50  2011 Microchip Technology Inc.

P21 TDLY12 Delay Between Programming Executive

Command Response Words 8—ns

Standard Operating Condition s

Oper ati ng Temperatu re : 0C to +70C. Programming at +25C is recommended.

Param

No. Symbol Characteristic Min Max Units Conditions

Note 1: VDDCORE must be supplied to the VDDCORE/VCAP pin if the on-chip voltage regulator is disabled. See Section 2.1

“Power Requirements” for more information. (Minimum VDDCORE allowing Flas h pr ogrammin g is 2. 25V.)

2: VDD must also be supplied to the AVDD pins du ri ng p ro gr ammi ng . AVDD and AVSS should always be with in ±0.3V

of VDD and VSS, respec tively.

 2011 Microchip Technology Inc. DS39907B-page 51

PIC24FJXXXGA1/GB1

APPENDIX A: REVISION HISTORY

Rev A Document (12/2007)

Initial release of this document.

Rev B Document (3/2011)

Adds 64-Kbyte general purpose devices

(PIC24FJ 64GA1XX) to the specification.

Adds revi sion history as a new feature.

Minor typographic edits throughout the document.

PIC24FJXXXGA1/GB1

DS39907B-page 52  2011 Microchip Technology Inc.

NOTES:

 2011 Microchip Technology Inc. DS39907B-page 53

Information contained in this publication regarding device

applications and the lik e is p rovided on ly for yo ur c on ve n ien ce

and may be superseded by updates . I t is y our respo ns ibility to

ensure that your application meets with your specifications.

MICROCHIP MAKES NO REPRESENTATIONS OR

WARRANTIES OF ANY KIND WHETHER EXPRESS OR

IMPLIED, WRITTEN OR ORAL, STATUTORY OR

OTHERWISE, RELATED TO THE INFORMATION,

INCLUDING BUT NOT LIMITED TO ITS CONDITION,

QUALITY, PERFORMANCE, MERCHANTABILITY OR

FITNESS FOR PURPOSE. Microchip disclaims all liability

arising from this information and its use. Use of Microchip

devices in life support and/or safety applications is entirely at

the buyer’s risk, and the buyer agrees to defend, indemnify and

hold harmless Microchip from any and all damages, claims,

suits, or expenses resulting from such use. No licenses are

conveyed, implicitly or otherwise, under any Microchip

intellectual property rights.

Trademarks

The Microchip name and logo, the Microchip logo, dsPIC,

KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PI CSTART,

PIC32 logo, rfPIC and UNI/O are registered trademarks of

Microchip Technology Incorporated in the U.S.A. and other

countries.

FilterLab, Hampshire, HI-TECH C, Linear Active Thermistor,

MXDEV, M XLA B, SEEVAL and The Em bedded Control

Solutions Company are registered trademarks of Microchip

Technology Incorporated in the U.S.A.

Analog-for-the-Digital Age, Application Maestro, CodeGuard,

dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,

ECONOMONIT OR, FanSens e , HI- TIDE, In-Cir c u it Se r i a l

Programming, ICSP, Mindi, MiWi, MPASM, MPLA B Certified

logo, MPLIB, MPLINK, mTouch, Omniscient Code

Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,

PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,

TSHARC, UniWinDriver, WiperLock and ZENA are

trademarks of Microchip Technology Incorporated in the

U.S.A. and other countries.

SQTP is a service mark of Microchip T echnology Incorporated

in the U.S.A.

All other trademarks mentioned herein are property of their

respective companies.

Printed on recycled paper.

ISBN: 978-1-61341-019-6

Note the following details of the code protection feature on Microchip devices:

• Microchip products meet the specification cont ained in their particular Microchip Data Sheet.

• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the

intended manner and under normal conditions.

• The re are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our

knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data

Sheets. Most likely, the person doing so is engaged in theft of intellectual property.

• Microchip is willing to work with the customer who is concerned about the integrity of their code.

• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not

mean that we are guaranteeing the product as “unbreakable.”

Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our

products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts

allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.

Microchip received ISO/TS-16949:2002 certification for its worldwide

headquarters, design and wafer fabrication facilities in Chandler and

Tempe, Arizona; Gresham, Oregon and design centers in California

and India. The Company’s quality system processes and procedures

are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping

devices, Serial EEPROMs, microperiph erals, nonvolatile memory and

analog products. In addition, Microchip’s quality system for the design

and manufacture of development systems is ISO 9001:2000 certified.

DS39907B-page 54  2011 Microchip Technology Inc.

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