XC3030-100PC44C - Xilinx Inc.

2-153

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XC3000

Logic Cell Array Family

Features

•Industry-leading FPGA family with five device types

– Logic densities from 1,000 to 6,000 gates

– Up to 144 user-definable I/Os

•Guaranteed 70- to 125-MHz toggle rates, 9 to 5.5 ns

logic delays

•Advanced CMOS static memory technology

– Low quiescent and active power consumption

•XC3000-specific features

– Ultra-low current option in Power-Down mode

– 4-mA output sink and source current

– Broad range of package options includes plastic and

ceramic quad flat packs, plastic leaded chip carriers

and pin grid arrays

– 100% bitstream compatible with the XC3100 family

– Commercial, industrial, military, “high rel”, and MIL-

STD-883 Class B grade devices

– Easy migration to XC3300 series of HardWire mask-

programmed devices for high-volume production

User I/Os Horizontal Configuration

Device CLBs Array Max Flip-Flops Longlines Data Bits

XC3020 64 8 x 8 64 256 16 14,779

XC3030 100 10 x 10 80 360 20 22,176

XC3042 144 12 x 12 96 480 24 30,784

XC3064 224 16 x 14 120 688 32 46,064

XC3090 320 16 x 20 144 928 40 64,160

Product Specification

Description

XC3000 is the original family of devices in the XC3000

class of Field Programmable Gate Array (FPGA) architec-

tures. The XC3000 family has a proven track record in

addressing a wide range of design applications, including

general logic replacement and sub-systems integration.

For a thorough description of the XC3000 architecture see

the preceding pages of this data book.

The XC3000 Family covers a range of nominal device

densities from 2,000 to 9,000 gates, practically achievable

densities from 1,000 to 6,000 gates. Device speeds,

described in terms of maximum guaranteed toggle fre-

quencies, range from 70 to 125 MHz. The performance of

a completed design depends upon placement and routing

implementation, so, like with any gate array, the final

verification of device utilization and performance can only

be known after the design has been placed and routed.

IMPORTANT NOTICE

All new designs should use XC3000A.

Information on XC3000 is presented here

as a reference for existing designs.

XC3000 bitstreams are upward compatible

to XC3000A without modification.

XC3000 Logic Cell Array Family

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Symbol

Description Units

VCC Supply voltage relative to GND –0.5 to +7.0 V

VIN Input voltage with respect to GND –0.5 to VCC +0.5 V

VTS Voltage applied to 3-state output –0.5 to VCC +0.5 V

TSTG Storage temperature (ambient) –65 to +150 °C

TSOL Maximum soldering temperature (10 s @ 1/16 in.) +260 °C

Junction temperature plastic +125 °C

TJJunction temperature ceramic +150 °C

Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device.

These are stress ratings only, and functional operation of the device at these or any other conditions beyond

those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum

Ratings conditions for extended periods of time may affect device reliability.

Symbol Description Min Max Units

VCC Supply voltage relative to GND Commercial 0°C to +85°C junction 4.75 5.25 V

Supply voltage relative to GND Industrial -40°C to +100°C junction 4.5 5.5 V

VIHT High-level input voltage — TTL configuration 2.0 VCC V

VILT Low-level input voltage — TTL configuration 0 0.8 V

VIHC High-level input voltage — CMOS configuration 70% 100% VCC

VILC Low-level input voltage — CMOS configuration 0 20% VCC

TIN Input signal transition time 250 ns

Absolute Maximum Ratings

Operating Conditions

Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently

released device performance parameters, please request a copy of the current test-specification revision.

At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per °C.

2-155

Symbol Description Min Max Units

VOH High-level output voltage (@ IOH = –4.0 mA, VCC min) 3.86 V

VOL Low-level output voltage (@ IOL = 4.0 mA, VCC min) 0.40 V

VOH High-level output voltage (@ IOH = –4.0 mA, VCC min)3.76 V

VOL Low-level output voltage (@ IOL = 4.0 mA, VCC min)0.40 V

VCCPD Power-down supply voltage (PWRDWN must be Low) 2.30 V

ICCPD Power-down supply current (VCC(MAX) @ TMAX)1XC3020 50 µA

XC3030 80 µA

XC3042 120 µA

XC3064 170 µA

XC3090 250 µA

ICCO Quiescent LCA supply current in addition to ICCPD2

Chip thresholds programmed as CMOS levels 500 µA

Chip thresholds programmed as TTL levels 10 mA

IIL Input Leakage Current –10 +10 µA

CIN Input capacitance, all packages except PGA175

(sample tested)

All Pins except XTL1 and XTL2 10 pF

XTL1 and XTL2 15 pF

Input capacitance, PGA 175

(sample tested)

All Pins except XTL1 and XTL2 15 pF

XTL1 and XTL2 20 pF

IRIN Pad pull-up (when selected) @ VIN = 0 V (sample tested) 0.02 0.17 mA

IRLL Horizontal Longline pull-up (when selected) @ logic Low 3.4 mA

Note: 1. Devices with much lower ICCPD tested and guaranteed at VCC = 3.2 V, T = 25°C can be ordered with a

Special Product Code. XC3020 SPC0107: ICCPD = 1 µA

XC3030 SPC0107: ICCPD = 2 µA

XC3042 SPC0107: ICCPD = 3 µA

XC3064 SPC0107: ICCPD= 4 µA

XC3090 SPC0107: ICCPD= 5 µA

2. With no output current loads, no active input or Longline pull-up resistors, all package pins at VCC or GND,

and the LCA configured with a MakeBits tie option.

Industrial

Commercial

DC Characteristics Over Operating Conditions

XC3000 Logic Cell Array Family

2-156

Speed Grade -70 -100 -125 Units

Description Symbol Max Max Max

Global and Alternate Clock Distribution*

Either: Normal IOB input pad through clock buffer

to any CLB or IOB clock input TPID 8.0 7.5 7.0 ns

Or: Fast (CMOS only) input pad through clock

buffer to any CLB or IOB clock input TPIDC 6.5 6.0 5.7 ns

TBUF driving a Horizontal Longline (L.L.)*

I to L.L. while T is Low (buffer active) TIO 5.0 4.7 4.5 ns

T↓ to L.L. active and valid with single pull-up resistor TON 11.0 10.0 9.0 ns

T↓ to L.L. active and valid with pair of pull-up resistors TON 12.0 11.0 10.0 ns

T↑ to L.L. High with single pull-up resistor TPUS 24.0 22.0 17.0 ns

T↑ to L.L. High with pair of pull-up resistors TPUF 17.0 15.0 12.0 ns

BIDI

Bidirectional buffer delay TBIDI 2.0 1.8 1.7 ns

CLB Switching Characteristic Guidelines

Buffer (Internal) Switching Characteristic Guidelines

* Timing is based on the XC3042, for other devices see XACT timing calculator.

1 TILO

2 TICK 3 TCKI

11 TCH

5 TCKDI

12 TCL

4 TDICK

6 TECCK 7 TCKEC

8 TCKO

13 TRPW

9 TRIO

CLB Output (X, Y)

(Combinatorial)

CLB Input

(A,B,C,D,E)

CLB Clock

CLB Input

(Direct In)

CLB Input

(Enable Clock)

CLB Output

(Flip-Flop)

CLB Input

(Reset Direct)

CLB Output

(Flip-Flop) X5388

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Speed Grade -70 -100 -125

Description Symbol Min Max Min Max Min Max Units

Combinatorial Delay

Logic Variables A, B, C, D, E, to outputs X or Y 1 TILO 9.0 7.0 5.5 ns

Sequential delay

Clock k to outputs X or Y 8 TCKO 6.0 5.0 4.5 ns

Clock k to outputs X or Y when Q is returned

through function generators F or G to drive X or Y TQLO 13.0 10.0 8.0 ns

Set-up time before clock K

Logic Variables A, B, C, D, E 2 TICK 8.0 7.0 5.5 ns

Data In DI 4 TDICK 5.0 4.0 3.0 ns

Enable Clock EC 6 TECCK 7.0 5.0 4.5 ns

Reset Direct inactive RD 1.0 1.0 1.0 ns

Hold Time after clock K

Logic Variables A, B, C, D, E 3 TCKI 00 0ns

Data In DI 5 TCKDI 4.0 2.0 1.5 ns

Enable Clock EC 7 TCKEC 000ns

Clock

Clock High time 11 TCH 5.0 4.0 3.0 ns

Clock Low time 12 TCL 5.0 4.0 3.0 ns

Max flip-flop toggle rate FCLK 70 100 125 MHz

Reset Direct (RD)

RD width 13 TRPW 8.0 7.0 6.0 ns

delay from rd to outputs X or Y 9 TRIO 8.0 7.0 6.0 ns

Global Reset (RESET Pad)*

RESET width (Low) TMRW 25.0 21.0 20.0 ns

delay from RESET pad to outputs X or Y TMRQ 23.0 19.0 17.0 ns

CLB Switching Characteristic Guidelines (continued)

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%

functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing

patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more

precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.

*Timing is based on the XC3042, for other devices see XACT timing calculator.

Note: The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than

the Data In hold time requirement (TCKDI, #5) of any CLB on the same die.

XC3000 Logic Cell Array Family

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IOB Switching Characteristic Guidelines

FLIP

FLOP

SLEW

RATE PASSIVE

PULL UP

OUTPUT

SELECT

3-STATE

INVERT

OUT

INVERT

FLIP

FLOP

LATCH

REGISTERED IN

DIRECT IN

OUT

3- STATE

(OUTPUT ENABLE)

TTL or

CMOS

INPUT

THRESHOLD

OUTPUT

BUFFER

(GLOBAL RESET)

CK1

X3029

I/O PAD

Vcc

PROGRAM-CONTROLLED MEMORY CELLS

PROGRAMMABLE INTERCONNECTION POINT or PIP

IKOK

PROGRAM

CONTROLLED

MULTIPLEXER

CK2

PID

I/O Block (I)

I/O Pad Input

I/O Clock (IK/OK)

I/O Block (RI)

RESET

I/O Block (O)

I/O Pad TS

I/O Pad Output

I/O Pad Output

(Direct)

I/O Pad Output

(Registered)

X5425

OOK

12 T

IOL

PICK

11 T

IOH

IKRI

15 T

RPO

13 T

RRI

OKO

TSHZ

10 T

OKPO

TSON

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Speed Grade -70 -100 -125 Units

Description Symbol Min Max Min Max Min Max

Propagation Delays (Input)

Pad to Direct In (I) 3 TPID 643ns

Pad to Registered In (Q) with latch transparent TPTG 21 17 16 ns

Clock (IK) to Registered In (Q) 4 TIKRI 5.5 4 3 ns

Set-up Time (Input)

Pad to Clock (IK) set-up time 1 TPICK 20 17 16 ns

Propagation Delays (Output)

Clock (OK) to Pad (fast) 7 TOKPO 13 10 9 ns

same (slew rate limited) 7 TOKPO 33 27 24 ns

Output (O) to Pad (fast) 10 TOPF 965ns

same (slew-rate limited) 10 TOPS 29 23 20 ns

3-state to Pad begin hi-Z (fast) 9 TTSHZ 887ns

same (slew-rate limited) 9 TTSHZ 28 25 24 ns

3-state to Pad active and valid (fast) 8 TTSON 14 12 11 ns

same (slew -rate limited) 8 TTSON 34 29 27 ns

Set-up and Hold Times (Output)

Output (O) to clock (OK) set-up time 5 TOOK 10 9 8 ns

Output (O) to clock (OK) hold time 6 TOKO 000ns

Clock

Clock High time 11 TIOH 54 3ns

Clock Low time 12 TIOL 54 3ns

Max. flip-flop toggle rate FCLK 70 100 125 MHz

Global Reset Delays (based on XC3042)

RESET Pad to Registered In (Q) 13 TRRI 25 24 23 ns

RESET Pad to output pad (fast) 15 TRPO 35 33 29 ns

(slew-rate limited) 15 TRPO 53 45 42 ns

IOB Switching Characteristic Guidelines (continued)

Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100%

functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing

patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more

precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator.

Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads,

see XAPP 024. Typical slew rate limited output rise/fall times are approximately four times longer.

2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the

internal pull-up resistor or alternatively configured as a driven output or driven from an external source.

3. Input pad setup time and hold times are specified with respect to the internal clock (IK). To calculate system setup time,

subtract clock delay (clock pad to IK) from the specified input pad setup time value, but the subtracted value cannot be

less than zero (i.e., negative hold time). Negative hold time means that the delay in the input data is adequate for the

external system hold time to be zero, provided the input clock uses the Global signal distribution from pad to IK .

XC3000 Logic Cell Array Family

2-160

For a detailed description of the device architecture, see pages 2-105 through 2-123.

For a detailed description of the configuration modes and their timing, see pages 2-124 through 2-132.

For detailed lists of package pin-outs, see pages 2-140 through 2-150.

For package physical dimensions and thermal data, see Section 4.

Ordering Information

Package Type

Example: XC3030-70PC44C

Toggle Rate

Device Type

Component Availability

Number of Pins

Temperature Range

PINS

44 64 68 84 100 132 144 160 164 175 176 208 223

TOP- TOP-

TYPE PLAST. PLAST. PLAST. PLAST. CERAM. PLAST. PLAST. PLAST. BRAZED PLAST. CERAM. PLAST. PLAST. BRAZED PLAST. CERAM. PLAST. PLAST. CERAM.

PLCC VQFP PLCC PLCC PGA PQFP TQFP VQFP CQFP PGA PGA TQFP PQFP CQFP PGA PGA TQFP PQFP PGA

CODE

PC44 VQ64 PC68 PC84 PG84 PQ100 TQ100 VQ100 CB100 PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223

-50

M B M B

-70

C I C I C I M B C I C M B

-100

C I C I C I M B C I C M B

-125

CCCC

-50

-70

C I C I C I C I M C I C

-100

C I C I C I C I M C I C

-125

C CCCCC

-50

M B M B M B

-70

C I C I M B C I C C M B C C I M B

-100

C I C I M B C I C C M B C C I M B

-125

CCCC CC

-50

-70

C I C I C I M C I

-100

C I C I C I M C I

-125

CCCC

-50

M B M B

-70

C I C I C M B C I C I M B C I

-100

C I C I C M B C I C I M B C I

-125

CCCCC

C = Commercial = 0° to +70° C I = Industrial = -40° to +85° C M = Mil Temp = -55° to +125° C B = MIL-STD-883C Class B

Parentheses indicate future product plans

XC3090

XC3064

XC3042

XC3030

XC3020