80/sec Yaw Rate Gyroscope with SPI ADIS16080 FEATURES GENERAL DESCRIPTION Complete angular rate gyroscope Z-axis (yaw rate) response SPI digital output interface High vibration rejection over wide frequency 2000 g-powered shock survivability Externally controlled self-test Internal temperature sensor output Dual auxiliary 12-bit ADC inputs Absolute rate output for precision applications 5 V single-supply operation 8.2 mm x 8.2 mm x 5.2 mm package RoHS compliant The ADIS16080 is a gyroscope that uses the Analog Devices, Inc. surface-micromachining process to make a functionally complete angular rate sensor with an integrated serial peripheral interface (SPI). The digital data available at the SPI port is proportional to the angular rate about the axis that is normal to the top surface of the package (see Figure 20). A single external resistor can be used to increase the measurement range. An external capacitor can be used to lower the bandwidth. Access to an internal temperature sensor measurement is provided, through the SPI, for compensation techniques. Two pins are available for the user to input analog signals for digitization. An additional output pin provides a precision voltage reference. Two digital self-test inputs electromechanically excite the sensor to test the operation of the sensor and the signal-conditioning circuits. APPLICATIONS Platform stabilization Image stabilization Guidance and control Inertia measurement units Robotics The ADIS16080 is available in an 8.2 mm x 8.2 mm x 5.2 mm, 16-terminal, peripheral land grid array (LGA) package. FUNCTIONAL BLOCK DIAGRAM COUT FILT RATE ADIS16080 80/sec GYROSCOPE TEMPERATURE SENSOR SCLK 4-CHANNEL SPI MUX/ADC DIN CS DOUT AIN2 AIN1 REFERENCE ST1 ST2 VCC 5V COM VDRIVE 3V TO 5V 06045-001 VREF Figure 1. Rev. $ Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarks and registered trademarks are the property of their respective owners. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 (c)2006-20 Analog Devices, Inc. All rights reserved. ADIS16080 TABLE OF CONTENTS Features .............................................................................................. 1 Increasing Measurement Range ............................................... 11 Applications ....................................................................................... 1 Setting Bandwidth ...................................................................... 11 General Description ......................................................................... 1 Self-Test Function ...................................................................... 11 Functional Block Diagram .............................................................. 1 Continuous Self-Test.................................................................. 11 Revision History ............................................................................... 2 Rate Sensitive Axis ..................................................................... 11 Specifications..................................................................................... 3 Basic Operation .............................................................................. 12 Timing Specifications .................................................................. 5 Serial Peripheral Interface (SPI) ............................................... 12 Absolute Maximum Ratings............................................................ 6 Applications Information .............................................................. 14 ESD Caution .................................................................................. 6 Assembly...................................................................................... 14 Pin Configuration and Function Descriptions ............................. 7 Interface board............................................................................ 14 Typical Performance Characteristics ............................................. 8 Outline Dimensions ....................................................................... 15 Theory of Operation ...................................................................... 11 Ordering Guide .......................................................................... 15 Supply and Common Considerations ..................................... 11 REVISION HISTORY 1/10--Rev. B to Rev. C Changes to Noise Performance, Total Noise Parameter, Table 1 ................................................................................................ 3 6/09--Rev. A to Rev. B Changes to Table 1 ............................................................................ 3 Changes to Figure 7 and Figure 8 ................................................... 8 Changes to Table 7, Table 9, Table 10, and Table 11 .................. 13 Added Applications Information Section ................................... 14 4/07--Rev. 0 to Rev. A Changes to Table 1 ............................................................................ 3 Changes to Table 4 ............................................................................ 7 Added Figure 5 .................................................................................. 7 Changes to Setting Bandwidth Section........................................ 11 Changes to Rate Sensitive Axis Section ....................................... 11 Deleted Control Register Section ................................................. 12 Added Basic Operation Section .................................................... 12 Updated Outline Dimensions ....................................................... 14 7/06--Revision 0: Initial Version Rev. C | Page 2 of 16 ADIS16080 SPECIFICATIONS TA = 25C, VCC = VDRIVE = 5 V, angular rate = 0/sec, COUT = 0 F, 1 g, unless otherwise noted. Table 1. Parameter SENSITIVITY Dynamic Range2 Initial Change over Temperature3 Nonlinearity Voltage Sensitivity NULL Initial Change Over Temperature3 Turn-On Time Linear Acceleration Effect Voltage Sensitivity NOISE PERFORMANCE Total Noise Rate Noise Density FREQUENCY RESPONSE 3 dB Bandwidth (User-Selectable)4 Sensor Resonant Frequency SELF-TEST INPUTS ST1 Rateout Response5 ST2 Rateout Response5 Logic 1 Input Voltage Logic 0 Input Voltage Input Impedance TEMPERATURE SENSOR Reading at 298 K Scale Factor 2.5 V REFERENCE Voltage Value Load Drive to Ground Load Regulation Power Supply Rejection Temperature Drift LOGIC INPUTS Input High Voltage, VINH Input Low Voltage, VINL Input Current, IIN Input Capacitance, CIN ANALOG INPUTS Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error Input Voltage Range Leakage Current Input Capacitance Full Power Bandwidth Conditions Min1 Typ Max1 Unit Full-scale range over specifications range Clockwise rotation is positive output, TA = -40C to +85C VCC = VDRIVE = 4.75 V to 5.25 V Best fit straight line VCC = VDRIVE = 4.75 V to 5.25 V 80 0.08881 0.09766 0.10858 /sec /sec/LSB Nominal 0/sec output is 2048 LSB VCC = VDRIVE = 4.75 V to 5.25 V Power on to 0.5/sec of final value Any axis VCC = VDRIVE = 4.75 V to 5.25 V -41 5 0.15 0.5 +41 /sec /sec ms /sec/g /sec/V 0.81 /sec rms /sec/Hz 8.3 35 0.2 1 0.1 Hz to 40 Hz, no averaging @ 25C 0.42 0.05 COUT = 0 F 40 14 ST1 pin from Logic 0 to Logic 1 ST2 pin from Logic 0 to Logic 1 Standard high logic level definition Standard low logic level definition To common % %FS %/V -328 +328 3.3 -540 +540 Hz kHz -819 +819 50 LSB LSB V V k 2048 0.1453 LSB K/LSB 1.7 Proportional to absolute temperature 2.45 Source 0 A < IOUT < 100 A VCC = VDRIVE = 4.75 V to 5.25 V Delta from 25C 2.5 100 5.0 1.0 5.0 2.55 0.7 x VDRIVE Typically 10 nA 0.3 x VDRIVE +1 -1 10 V A mV/mA mV/V mV V V A pF For VIN < VCC 12 -2 -2 -8 -2 0 -1 +2 +2 +8 +2 VREF x 2 +1 20 8 Rev. C | Page 3 of 16 Bits LSB LSB LSB LSB V A pF MHz ADIS16080 Parameter DIGITAL OUTPUTS Output High Voltage (VOH) Output Low Voltage (VOL) CONVERSION RATE Conversion Time Throughput Rate POWER SUPPLY VCC VDRIVE VCC Quiescent Supply Current VDRIVE Quiescent Supply Current Power Dissipation TEMPERATURE RANGE Specified Performance Conditions Min 1 ISOURCE = 200 A ISINK = 200 A VDRIVE - 0.2 Typ 16 SCLK cycles with SCLK at 20 MHz Max1 Unit 0.4 V V 800 1 ns MSPS 5.25 5.25 9.0 500 V V mA A mW +85 C All at TA = -40C to +85C 4.75 2.7 VCC @ 5 V, fSCLK = 50 kSPS VDRIVE @ 5 V, fSCLK = 50 kSPS VCC and VDRIVE @ 5 V, fSCLK = 50 kSPS Tested to max and min specifications 1 5 7.0 70 40 -40 All minimum and maximum specifications are guaranteed. Typical specifications are neither tested nor guaranteed. Dynamic range is the maximum full-scale measurement range possible, including output swing range, initial offset, sensitivity, offset drift, and sensitivity drift at 5 V supply. Defined as the output change from ambient to maximum temperature, or ambient to minimum temperature. 4 Frequency at which the response is 3 dB down from dc response. Bandwidth = 1/(2 x x 180 k x (22 nF + COUT)). For COUT = 0, bandwidth = 40 Hz. For COUT = 1 F, bandwidth = 0.87 Hz. 5 Self-test response varies with temperature. 2 3 Rev. $ | Page 4 of 16 ADIS16080 TIMING SPECIFICATIONS TA = 25C, angular rate = 0/sec, unless otherwise noted. 1 Table 2. Parameter fSCLK 2 tCONVERT tQUIET t2 t3 3 t43 t5 t6 t7 t8 4 t9 t10 t11 VCC = VDRIVE = 5 V 10 20 16 x tSCLK 50 10 30 40 0.4 x tSCLK 0.4 x tSCLK 10 15/35 10 5 20 Unit kHz min MHz max Description ns min ns min ns max ns max ns min ns min ns min ns min/max ns min ns min ns min Minimum quiet time required between CS rising edge and start of next conversion. CS to SCLK setup time. Delay from CS until DOUT three-state disabled. Data access time after SCLK falling edge. SCLK low pulse width. SCLK high pulse width. SCLK to DOUT valid hold time. SCLK falling edge to DOUT high impedance. DIN setup time prior to SCLK falling edge. DIN hold time after SCLK falling edge. 16th SCLK falling edge to CS high. 1 Guaranteed by design. All input signals are specified with tR and tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. The 5 V operating range spans from 4.75 V to 5.25 V. 2 Mark/space ratio for the SCLK input is 40/60 to 60/40. 3 Measured with the load circuit in Figure 3 and defined as the time required for the output to cross 0.4 V, or 0.7 x VDRIVE. 4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 3. The measured number is then extrapolated back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish time of the part and is independent of the bus loading. CS t2 3 t3 4 5 ADD1 ADD0 DB11 WRITE LOW 12 13 14 15 16 t5 t11 t8 DB10 DB4 DB3 DB2 DB1 tQUIET DB0 THREE-STATE ADDRESS BITS t10 9 DIN 11 t7 t4 ZERO DOUT THREE-STATE ZERO t B 6 DONTC DONTC ADD1 ADD0 CODING DONTC DONTC Figure 2. Gyroscope Serial Interface Timing Diagram 200A TO OUTPUT PIN IOL 1.6V CL 50pF 200A IOH Figure 3. Load Circuit for Digital Output Timing Specifications Rev. $ | Page 5 of 16 DONTC DONTC 06045-002 2 06045-003 1 SCLK tCONVERT t6 ADIS16080 ABSOLUTE MAXIMUM RATINGS Table 3. Parameter Acceleration (Any Axis, Unpowered, 0.5 ms) Acceleration (Any Axis, Powered, 0.5 ms) VCC to COM VDRIVE to COM Analog Input Voltage to COM Digital Input Voltage to COM Digital Output Voltage to COM ST1/ST2 Input Voltage to COM Operating Temperature Range Storage Temperature Range Rating 2000 g 2000 g -0.3 V to +6.0 V -0.3 V to VCC + 0.3 V -0.3 V to VCC + 0.3 V -0.3 V to +7.0 V -0.3 V to VCC + 0.3 V -0.3 V to VCC + 0.3 V -55C to +125C -65C to +150C Stresses above those listed under the Absolute Maximum Ratings may cause permanent damage to the device. This is a stress rating only; functional operation of the device at these or any other conditions above those indicated in the operational section of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Drops onto hard surfaces can cause shocks of greater than 2000 g and exceed the absolute maximum rating of the device. Care should be exercised in handling to avoid damage. ESD CAUTION Rev. $ | Page 6 of 16 ADIS16080 NC 4 DOUT 3 SCLK DIN RATE FILT VDRIVE AIN1 PIN CONFIGURATION AND FUNCTION DESCRIPTIONS 5 6 7 8 9 AIN2 10 COM 2 11 VREF 1 12 ST2 BOTTOM VIEW (Not to Scale) 13 ST1 14 VCC 15 NC NC = NO CONNECT CS 16 06045-004 ADIS16080 Figure 4. Pin Configuration Table 4. Pin Function Descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Type1 I I O O I S I I S O I I S I Description SPI Data Input. SPI Serial Clock. SPI Data Output. No Connect. Buffered Analog Output. Represents the angular rate signal. External Capacitor Connection to Control Bandwidth. SPI Power Supply. This can be the receive processing circuit's supply to simplify interfacing. External Analog Input Channel 1. See ADD0 and ADD1 address bits in Table 5. External Analog Input Channel 2. See ADD0 and ADD1 address bits in Table 5. Common. Reference point for all circuitry in the ADIS16080. Precision 2.5 V Reference. Self-Test Input 2. Self-Test Input 1. Analog Power. No Connect. Chip Select. Active low. This input frames the serial data transfer and initiates the conversion process. I = input; O = output; S = power supply. 2.5050 BSC 8x 3.6865 BSC 8x 0.6700 BSC 12x 7.373 BSC 2x 5.010 BSC 4x 1.000 BSC 16x .5000 BSC 16x Figure 5. Second-Level Assembly Pad Layout Rev. C | Page 7 of 16 06045-020 1 Mnemonic DIN SCLK DOUT NC RATE FILT VDRIVE AIN1 AIN2 COM VREF ST2 ST1 VCC NC CS ADIS16080 TYPICAL PERFORMANCE CHARACTERISTICS 25 70 AVERAGE = 6.4mA STD. DEVIATION = 0.2mA AVERAGE = 2014.38 STD. DEVIATION = 99.3236 PERCENT OF POPULATION (%) PERCENT OF POPULATION (%) 60 20 15 10 5 50 40 30 20 8.75 9.00 -450 600 06045-008 8.50 -460 590 8.25 -470 580 8.00 -480 570 7.75 7.50 7.25 7.00 6.75 6.50 6.25 20 AVERAGE = -519.6 LSB 18 STD. DEVIATION = 21.892 LSB -40C PERCENT OF POPULATION (%) 2070 2060 2050 2040 +25C 2030 2020 +85C 2010 16 14 12 10 8 6 4 06045-009 -490 -500 -510 Figure 10. Self-Test 1 Histogram 25 30 PART AVERAGE, VCC = 4.75V 30 PART AVERAGE, VCC = 5.00V 30 PART AVERAGE, VCC = 5.25V AVERAGE = 522.47 LSB STD. DEVIATION = 19.9086 LSB PERCENT OF POPULATION (%) 2070 -520 ST1 (LSB) Figure 7. Null Level vs. Supply Voltage 2080 -530 VCC (V) 0 -540 5.3 -550 5.2 -560 5.1 -570 5.0 -580 4.9 06045-006 4.8 -590 2 -600 2060 2050 2040 2030 2020 20 15 10 5 Figure 8. Null Level vs. Temperature 560 550 540 0 530 110 ST2 (LSB) Figure 11. Self-Test 2 Histogram Rev. $ | Page 8 of 16 06045-010 TEMPERATURE (C) 90 520 70 510 50 500 30 490 10 480 -10 460 -30 450 2000 -50 06045-007 2010 470 NULL LEVEL (LSB) 6.00 Figure 9. Supply Current Histogram 2080 NULL LEVEL (LSB) 5.75 SUPPLY CURRENT (mA) Figure 6. Initial Null Histogram 2000 4.7 5.50 06045-005 NULL (LSB) 5.25 0 0 5.00 10 ADIS16080 -400 600 -420 30 PART AVERAGE, TA = -40C 580 560 SELF-TEST LEVEL (LSB) -460 -480 -500 30 PART AVERAGE, TA = +25C -520 -540 30 PART AVERAGE, TA = +85C -560 520 500 480 460 440 -580 4.9 5.0 5.1 5.2 5.3 VCC (V) 400 -50 -30 -10 10 30 50 70 90 110 90 110 06045-015 4.8 110 TEMPERATURE (C) Figure 12. Self-Test 1 vs. Supply Voltage 06045-014 420 06045-011 -600 4.7 540 06045-016 SELF-TEST LEVEL (LSB) -440 30 PART AVERAGE, VCC = 4.75V 30 PART AVERAGE, VCC = 5.00V 30 PART AVERAGE, VCC = 5.25V Figure 15. Self-Test 2 vs. Temperature 600 0 30 PART AVERAGE, TA = +85C 30 PART AVERAGE, 30 PART AVERAGE, 30 PART AVERAGE, VCC = 4.75V VCC = 5.00V VCC = 5.25V OFFSET LEVEL (LSB) SELF-TEST LEVEL (LSB) -0.5 550 30 PART AVERAGE, TA = +25C 500 -1.5 450 30 PART AVERAGE, TA = -40C 4.8 4.9 5.0 -2.0 5.1 5.2 5.3 VCC (V) -2.5 -50 06045-012 400 4.7 -400 30 PART AVERAGE, 30 PART AVERAGE, 30 PART AVERAGE, -420 -30 -10 10 30 50 70 TEMPERATURE (C) Figure 13. Self-Test 2 vs. Supply Voltage Figure 16. ADC Offset vs. Temperature and Supply Voltage 1.0 VCC = 4.75V VCC = 5.00V VCC = 5.25V 0.9 30 PART AVERAGE, VCC = 4.75V 30 PART AVERAGE, VCC = 5.00V 30 PART AVERAGE, VCC = 5.25V 0.8 GAIN ERROR (LSB) -440 -460 -480 -500 -520 -540 0.7 0.6 0.5 0.4 0.3 0.2 -560 0.1 -580 -50 -40 -30 -20 -10 0 10 20 30 40 50 60 70 80 90 100 TEMPERATURE (C) 06045-013 SELF-TEST LEVEL (LSB) -1.0 Figure 14. Self-Test 1 vs. Temperature 0 -50 -30 -10 10 30 50 70 90 TEMPERATURE (C) Figure 17. ADC Gain Error vs. Temperature (Excluding VREF) Rev. $ | Page 9 of 16 ADIS16080 2.486 1825 30 PART AVERAGE, TA = +25C 2.485 1820 30 PART AVERAGE, TA = -40C 1815 2.483 1810 2.482 30 PART AVERAGE, TA = +85C 2.481 1805 2.480 4.8 4.9 5.0 5.1 VCC (V) 5.2 5.3 Figure 18. VREF vs. Supply Voltage 0 1000 2000 3000 4000 5000 6000 7000 000001110000010X 000001110000011X 000001110000100X 000001110000101X 000001110000110X 000001110000111X 000001110001000X 000001110001001X 000001110001010X 000001110001011X 000001110001100X 000001110001101X 000001110001110X 000001110001111X 000001110010000X 000001110010010X SAMPLES = 8192, MAX CODE = 1827, MIN CODE = 1796, SPREAD = 32, STD DEV = 4.057, MEAN = 1811.803 Figure 19. Noise Histogram Rev. $ | Page 10 of 16 8000 3 19 39 87 249 844 1136 1303 1702 1229 924 447 150 43 13 4 06045-018 2.479 4.7 1800 06045-017 VREF LEVEL (V) 2.484 ADIS16080 THEORY OF OPERATION The electrostatic resonator requires 14 V to 16 V for operation. Because only 5 V is typically available in most applications, a charge pump is included on-chip. After the demodulation stage, there is a single-pole, low-pass filter included on-chip that is used to limit high frequency artifacts before final amplification. The frequency response is dominated by the second low-pass filter, which is set at 40 Hz. For additional bandwidth reduction options, see the Setting Bandwidth section. SUPPLY AND COMMON CONSIDERATIONS Power supply noise and transient behaviors can influence the accuracy and stability of any sensor-based measurement system. When considering the power supply for the ADIS16080, it is important to understand that the ADIS16080 provides 0.2 F of decoupling capacitance on the VCC pin. Depending on the level of noise present in the system power supply, the ADIS16080 may not require any additional decoupling capacitance for this supply. The analog supply, VCC, and the digital drive supply, VDRIVE, are segmented to allow multiple logic levels to be used in receiving the digital output data. VDRIVE is intended for the down-stream logic power supply and supports standard 3.3 V and 5 V logic families. The VDRIVE supply does not have internal decoupling capacitors. INCREASING MEASUREMENT RANGE The full-scale measurement range of the ADIS16080 is increased by placing an external resistor between the RATE pin and FILT pin, which results in a parallel connection with the internal 180 k, 1% resistor. For example, a 330 k external resistor gives ~50% increase in the full-scale range. This is effective for up to a 4x increase in the full-scale range (minimum value of the parallel resistor allowed is 45 k). The internal circuitry headroom requirements prevent further increase in the linear full-scale output range. The trade-offs associated with increasing the full-scale range are potential increase in output null drift (as much as 2/sec over temperature) and introducing initial null bias errors that must be calibrated. SETTING BANDWIDTH An external capacitor can be used in combination with an onchip resistor to create a low-pass filter to limit the bandwidth of the ADIS16080 rate response. The -3 dB frequency is defined as f OUT = 1/(2 x x ROUT x (COUT + 0.022 F )) where: ROUT is the internal impedance that was trimmed during manufacturing to 180 k 1%. COUT is the external capacitance across the RATE and FILT pins. Any external resistor applied between the RATE pin and the FILT pin results in ROUT = (180 k x R EXT ) / (180 k + R EXT ) where REXT is the external resistor. With COUT = 0 F, a default -3 dB frequency response of 40 Hz is obtained based upon an internal 0.022 F capacitor implemented on-chip. SELF-TEST FUNCTION The ADIS16080 includes a self-test feature that actuates each of the sensing structures and associated electronics in the same manner as if subjected to an angular rate. It provides a simple method for exercising the mechanical structure of the sensor, along with the entire signal processing circuit. It is activated by standard logic high levels applied to Input ST1, Input ST2, or both. ST1 causes a change in the digital output equivalent to typically -540 LSB, and ST2 causes an opposite +540 LSB change. The self-test response follows the viscosity temperature dependence of the package atmosphere, approximately 0.25%/C. Activating both ST1 and ST2 simultaneously is not damaging. Because ST1 and ST2 are not necessarily closely matched, actuating both simultaneously can result in an apparent null bias shift. CONTINUOUS SELF-TEST As an additional failure detection measure, a power-on self-test can be performed. However, some applications warrant a continuous self-test while sensing rate. RATE SENSITIVE AXIS Rev. $ | Page 11 of 16 RATE OUT RATE AXIS 0 LSB LONGITUDINAL AXIS CLOCK-WISE ROTATION 8 4 5 1 4095 LSB LATERAL AXIS RATE IN Figure 20. Rate Signal Increases with Clockwise Rotation 06045-019 The ADIS16080 operates on the principle of a resonator gyroscope. Two polysilicon sensing structures each contain a dither frame that is electrostatically driven to resonance. This produces the necessary velocity element to produce a Coriolis force while rotating. At two of the outer extremes of each frame, orthogonal to the dither motion, are movable fingers that are placed between fixed pickoff fingers to form a capacitive pickoff structure that senses Coriolis motion. The resulting signal is fed to a series of gain and demodulation stages that produce the electrical rate signal output. The rate signal is then converted to a digital representation of the output on the SPI pins. The dualsensor design rejects external g forces and vibration. Fabricating the sensor with the signal conditioning electronics preserves signal integrity in noisy environments. ADIS16080 BASIC OPERATION ADC Conversion The ADIS16080 is designed for simple integration into industrial system designs, requiring only a 5.0 V power supply and a four-wire, industry standard serial peripheral interface (SPI). The SPI handles all digital I/O communication in the ADIS16080. The chip select (CS) and serial clock (SCLK) lines control the on-board A/D conversion process. When the chip select line goes low, the DOUT line comes out of three-state mode, the track-and-hold goes into hold mode, and the ADC samples the analog input at this point. The track-and-hold returns to track mode on the 14th falling edge of the SCLK line. The serial clock drives the internal ADC conversion clock, using its falling edge for control of this process. All 16 SCLK cycles are required for a complete conversion. If a data frame has less than 16 SCLK cycles, the conversion cannot complete and does not update the output data for the next data frame cycle. SERIAL PERIPHERAL INTERFACE (SPI) The ADIS16080 SPI port includes four signals: chip select (CS), serial clock (SCLK), data input (DIN), and data output (DOUT). The CS line enables the ADIS16080 SPI port and frames each SPI event. When this signal is high, the DOUT lines are in a high impedance state and the signals on DIN and SCLK have no impact on operation. A complete data frame contains 16 clock cycles. Because the SPI port operates in full duplex mode, it supports simultaneous, 16-bit receive (DIN) and transmit (DOUT) functions within the same data frame. Output Data Access The DOUT sequence starts with two zeros, one that clocks out after the falling edge of CS, and a second one that clocks out on the first SCLK falling edge. The next 14 bits, ADD0, ADD1 and the 12 data bits, clock out on SCLK falling edges. After the 16th falling edge, the DOUT line moves to a three-state mode. Control Register The DIN control register provides controls for two operational settings: the output data source and the coding (twos complement vs. offset binary). Table 5 and Figure 22 provide the proper bit definitions for control register configuration. The DIN sequence starts with a 1 for configuration sequences and a 0 for read sequences. When this bit is 0, the remaining DIN bits do not change the control register and the next sample's output data reflects the existing configuration. Data loads from the DIN pin into the ADIS16080 on the falling edge of SCLK. Once the 16-SCLK sequence is complete, the control register is updated and ready for the next read sequence. If a data frame has less than 16 SCLK cycles, the control register does not update and maintains its previous configuration. The DIN bit definitions in Table 5, which have either 0 or 1 assigned to them, are critical for proper operation. When setting up the system process to receive data from the ADIS16080, use a clock phase setting of 0 and a clock polarity setting of 1. These settings reflect the timing displayed in Figure 22. To maintain proper communication at the maximum specified clock rates, the system processor must be able to support the setup time requirement, listed in Figure 2 and Table 2 (t9). DATA FRAME CS DATA FRAME SCLK DIN CONFIGURATION COMMAND FOR NEXT OUTPUT SEQUENCE 06045-021 DOUT NEXT COMMAND, IF NECESSARY DATA OUTPUT, BASED ON PREVIOUS CONFIGURATION Figure 21. Configuration and Read Sequence ADC PLACED IN HOLD MODE 1 SCLK DIN DOUT 2 WRITE 0 0 0 ADC PLACED IN TRACK MODE 3 4 5 6 D/C D/C ADD1 ADD0 ADD1 ADD0 D11 D10 7 8 1 D9 1 D8 9 D/C D7 10 11 D/C D6 0 D5 12 CODE D4 Figure 22. SPI Sequence, Clock Polarity = 1, Clock Phase = 0 Rev. $ | Page 12 of 16 13 D/C D3 14 D/C D2 15 D/C D1 16 D/C D0 06045-022 CS ADIS16080 Table 5. DIN Bit Assignments Table 8. Temperature Data Coding, Twos Complement Bit No. 15 Mnemonic WRITE Temperature (C) 85 Code 585 Bit Pattern 0001001001001001 14 13, 12 11, 10 0 D/C ADD1, ADD0 25 + 0.2906 25 + 0.1453 25 25 - 0.1453 25 - 0.2906 2 1 0 -1 -2 0001000000000010 0001000000000001 0001000000000000 0001111111111111 0001111111111110 -40 -447 0001111001000001 9, 8 7, 6 5 4 3 to 0 1 D/C 0 CODE D/C Comment 1: Write contents on DIN to control register. 0: No changes to control register. Low state for normal operation. Don't care. Data source setting. 00: Gyroscope output. 01: Temperature output. 10: Analog input 1. 11: Analog input 2. High state for normal operation. Don't care. Low state for normal operation. Output data format setting. 0: Twos complement. 1: Offset binary. Don't care. Output Coding Examples Table 9. Temperature Data Coding, Offset Binary Temperature (C) 85 Code 2633 Bit Pattern 0001101001001001 25 + 0.2906 25 + 0.1453 25 25 - 0.1453 25 - 0.2906 2050 2049 2048 2047 2046 0001100000000010 0001100000000001 0001100000000000 0001011111111111 0001011111111110 -40 1601 0001011001000001 Table 6. Gyroscope Data Coding, Twos Complement Angular Rate (/sec) 80 ... 0.19532 0.09766 0 -0.09766 -0.19532 ... -80 Code 819 ... 2 1 0 -1 -2 ... -819 Bit Pattern 0000001100110011 ... 0000000000000010 0000000000000001 0000000000000000 0000111111111111 0000111111111110 ... 0000110011001101 Table 10. ADC Data Coding, Twos Complement Input Level (V) 4.5 Code1 1638 Bit Pattern 0010011001100110 2.5 + 0.002442 2.5 + 0.001221 2.5 2.5 - 0.001221 2.5 - 0.002442 2 1 0 -1 -2 0010000000000010 0010000000000001 0010000000000000 0010111111111111 0010111111111110 0.5 -1638 0010100110011010 Table 7. Gyroscope Data Coding, Offset Binary Angular Rate (/sec) 80 ... 0.19532 0.09766 0 -0.09766 -0.19532 ... -80 Code 2867 ... 2050 2049 2048 2047 2046 ... 1229 Bit Pattern 0000101100110011 ... 0000100000000010 0000100000000001 0000100000000000 0000011111111111 0000011111111110 ... 0000010011001101 1 Code for AIN1 used in 3rd and 4th bits (11 for AIN2). Table 11. ADC Data Coding, Offset Binary Input Level (V) 4.5 Code1 3686 Bit Pattern 0010011001100110 2.5 + 0.002442 2.5 + 0.001221 2.5 2.5 - 0.001221 2.5 - 0.002442 2050 2049 2048 2047 2046 0010100000000010 0010100000000001 0010100000000000 0010011111111111 0010011111111110 0.5 410 0010000110011010 1 Code for AIN1 used in 3rd and 4th bits (11 for AIN2). Rev. $ | Page 13 of 16 ADIS16080 APPLICATIONS INFORMATION ASSEMBLY ADIS16080 INTERFACE BOARD 12 J1 1 2 3 4 2 16 3 13 5 7 9 1 6 FILT C1 1F 2 5 3 4 4 5 6 7 8 9 10 11 12 CS DOUT RATE ST1 DIN NC 10 12 1 C3 1F 8 7 6 SCLK NC 14 11 ST2 VCC VDRIVE J2 15 10 GND 8 AIN1 9 AIN2 11 VREF C4 1F C2 1F 06045-118 The ADIS16080 is a system-in-package (SIP) that integrates multiple components in a land grid array (LGA). This configuration offers the convenience of solder-reflow installation on printed circuit boards (PCBs). When developing a process flow for installing ADIS16080 devices on PCBs, see JEDEC standard document, J-STD-020C, for reflow temperature profile and processing information. The ADIS16080 can use either the Sn-PB eutectic process or the Pb-free eutectic process from this standard. See JEDEC J-STD-033 for moisture sensitivity (MSL) handling requirements. The MSL rating for these devices is marked on the antistatic bags, which protect these devices from ESD during shipping and handling. Prior to assembly, review the process flow for information about introducing shock levels that exceed the ADIS16080's absolute maximum ratings. Some PCB separation and ultrasonic cleaning processes are common areas that can introduce high levels of shock to these devices. 1.100 Figure 23. Electrical Schematic 1.050 a 2 x 0.925 J2 J1 U1 2 x 0.673 iSensor 4 x O0.087 M2x0.4 C1 2 x 0.000 Figure 24. PCB Assembly View and Dimensions Rev. $ | Page 14 of 16 06045-117 0.865 2 x 0.900 0.035 2 x 0.000 0.150 0.200 The ADIS16080/PCBZ (see the Ordering Guide) provides the ADIS16080 functionality on a 1.2 inch x 1.3 inch printed circuit board, which simplifies the connection to an existing processor system. The four mounting holes accommodate either M2 (2 mm) or 2-56 machine screws. These boards are made of IS410 material and are 0.063 inches thick. The second level assembly uses a SAC305-compatible solder composition, which has a presolder reflow thickness of approximately 0.005 inches. The pad pattern on the ADIS16080/PCBZ matches Figure 5. J1 and J2 are dualrow, 2 mm (pitch) connectors that work with several ribbon cable systems, including 3M Part Number 152212-0100-GB (ribbon-crimp connector) and 3M Part Number 3625/12 (ribbon cable). ADIS16080 OUTLINE DIMENSIONS 5.010 BSC (4x) 2.505 BSC (8x) 8.35 MAX 13 PIN 1 INDICATOR 12 8.20 TYP 0.873 BSC (16x) 16 1 7.373 BSC (2x) 0.797 BSC (12x) 9 4 8 0.200 MIN (ALL SIDES) TOP VIEW 5 BOTTOM VIEW 0.373 BSC (16x) 7.00 TYP 022107-B 5.20 MAX SIDE VIEW Figure 25. 16-Terminal Stacked Land Grid Array [LGA] (CC-16-1) Dimensions shown in millimeters ORDERING GUIDE Model1 ADIS16080ACCZ ADIS16080/PCBZ 1 Temperature Range -40C to +85C Package Description 16-Terminal Stacked Land Grid Array (LGA) Evaluation Board Z = RoHS Compliant Part. Rev. C | Page 15 of 16 Package Option CC-16-1 ADIS16080 NOTES (c)2006-20 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06045-0-/($) Rev. $ | Page 16 of 16 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Analog Devices Inc.: ADIS16080ACCZ ADIS16080/PCBZ