±80°/sec Yaw Rate Gyroscope with SPI
ADIS16080
Rev. $
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FEATURES
Complete angular rate gyroscope
Z-axis (yaw rate) response
SPI digital output interface
High vibration rejection over wide frequency
2000 g-powered shock survivability
Externally controlled self-test
Internal temperature sensor output
Dual auxiliary 12-bit ADC inputs
Absolute rate output for precision applications
5 V single-supply operation
8.2 mm × 8.2 mm × 5.2 mm package
RoHS compliant
APPLICATIONS
Platform stabilization
Image stabilization
Guidance and control
Inertia measurement units
Robotics
GENERAL DESCRIPTION
The ADIS16080 is a gyroscope that uses the Analog Devices,
Inc. surface-micromachining process to make a functionally
complete angular rate sensor with an integrated serial periph-
eral interface (SPI).
The digital data available at the SPI port is proportional to the
angular rate about the axis that is normal to the top surface of
the package (see Figure 20). A single external resistor can be
used to increase the measurement range. An external capacitor
can be used to lower the bandwidth.
Access to an internal temperature sensor measurement is
provided, through the SPI, for compensation techniques.
Two pins are available for the user to input analog signals for
digitization. An additional output pin provides a precision
voltage reference. Two digital self-test inputs electromechanically
excite the sensor to test the operation of the sensor and the
signal-conditioning circuits.
The ADIS16080 is available in an 8.2 mm × 8.2 mm × 5.2 mm,
16-terminal, peripheral land grid array (LGA) package.
FUNCTIONAL BLOCK DIAGRAM
4-CHANNEL
SPI
MUX/ADC
C
OUT
FILT RATE
ADIS16080
±80°/sec
GYROSCOPE SCLK
DIN
TEMPERATURE
SENSOR
AIN2
CS
DOUT
AIN1
ST1
V
REF
ST2 V
CC
5V COM V
DRIVE
3V TO 5V
REFERENCE
06045-001
Figure 1.
ADIS16080
Rev. C | Page 2 of 16
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Functional Block Diagram .............................................................. 1
Revision History ............................................................................... 2
Specifications ..................................................................................... 3
Timing Specifications .................................................................. 5
Absolute Maximum Ratings ............................................................ 6
ESD Caution .................................................................................. 6
Pin Configuration and Function Descriptions ............................. 7
Typical Performance Characteristics ............................................. 8
Theory of Operation ...................................................................... 11
Supply and Common Considerations ..................................... 11
Increasing Measurement Range ............................................... 11
Setting Bandwidth ...................................................................... 11
Self-Test Function ...................................................................... 11
Continuous Self-Test .................................................................. 11
Rate Sensitive Axis ..................................................................... 11
Basic Operation .............................................................................. 12
Serial Peripheral Interface (SPI) ............................................... 12
Applications Information .............................................................. 14
Assembly ...................................................................................... 14
Interface board ............................................................................ 14
Outline Dimensions ....................................................................... 15
Ordering Guide .......................................................................... 15
REVISION HISTORY
1/10—Rev. B to Rev. C
Changes to Noise Performance, Total Noise Parameter,
Table 1 ................................................................................................ 3
6/09—Rev. A to Rev. B
Changes to Table 1 ............................................................................ 3
Changes to Figure 7 and Figure 8 ................................................... 8
Changes to Table 7, Table 9, Table 10, and Table 11 .................. 13
Added Applications Information Section ................................... 14
4/07—Rev. 0 to Rev. A
Changes to Table 1 ............................................................................ 3
Changes to Table 4 ............................................................................ 7
Added Figure 5 .................................................................................. 7
Changes to Setting Bandwidth Section ........................................ 11
Changes to Rate Sensitive Axis Section ....................................... 11
Deleted Control Register Section ................................................. 12
Added Basic Operation Section .................................................... 12
Updated Outline Dimensions ....................................................... 14
7/06—Revision 0: Initial Version
ADIS16080
Rev. C | Page 3 of 16
SPECIFICATIONS
TA = 25°C, VCC = VDRIVE = 5 V, angular rate = 0°/sec, COUT = 0 μF, ±1 g, unless otherwise noted.
Table 1.
Parameter Conditions Min1 Typ
Max1 Unit
SENSITIVITY
Dynamic Range2 Full-scale range over specifications range ±80 °/sec
Initial Clockwise rotation is positive output,
TA = −40°C to +85°C
0.08881 0.09766 0.10858 °/sec/LSB
Change over Temperature3 V
CC = VDRIVE = 4.75 V to 5.25 V ±5 %
Nonlinearity Best fit straight line 0.15 %FS
Voltage Sensitivity VCC = VDRIVE = 4.75 V to 5.25 V 0.5 %/V
NULL
Initial Nominal 0°/sec output is 2048 LSB −41 +41 °/sec
Change Over Temperature3 VCC = VDRIVE = 4.75 V to 5.25 V ±8.3 °/sec
Turn-On Time Power on to ±0.5°/sec of final value 35 ms
Linear Acceleration Effect Any axis 0.2 °/sec/g
Voltage Sensitivity VCC = VDRIVE = 4.75 V to 5.25 V ±1 °/sec/V
NOISE PERFORMANCE
Total Noise 0.1 Hz to 40 Hz, no averaging 0.42 0.81 °/sec rms
Rate Noise Density @ 25°C 0.05 °/sec/√Hz
FREQUENCY RESPONSE
3 dB Bandwidth (User-Selectable)4 C
OUT = 0 μF 40 Hz
Sensor Resonant Frequency 14 kHz
SELF-TEST INPUTS
ST1 Rateout Response5 ST1 pin from Logic 0 to Logic 1 −328 −540 −819 LSB
ST2 Rateout Response5 ST2 pin from Logic 0 to Logic 1 +328 +540 +819 LSB
Logic 1 Input Voltage Standard high logic level definition 3.3 V
Logic 0 Input Voltage Standard low logic level definition 1.7 V
Input Impedance To common 50 kΩ
TEMPERATURE SENSOR
Reading at 298 K 2048 LSB
Scale Factor Proportional to absolute temperature 0.1453 K/LSB
2.5 V REFERENCE
Voltage Value 2.45 2.5 2.55 V
Load Drive to Ground Source 100 μA
Load Regulation 0 μA < IOUT < 100 μA 5.0 mV/mA
Power Supply Rejection VCC = VDRIVE = 4.75 V to 5.25 V 1.0 mV/V
Temperature Drift Delta from 25°C 5.0 mV
LOGIC INPUTS
Input High Voltage, VINH 0.7 × VDRIVE V
Input Low Voltage, VINL 0.3 × VDRIVE V
Input Current, IIN Typically 10 nA −1 +1 μA
Input Capacitance, CIN 10 pF
ANALOG INPUTS For VIN < VCC
Resolution 12 Bits
Integral Nonlinearity −2 +2 LSB
Differential Nonlinearity −2 +2 LSB
Offset Error −8 +8 LSB
Gain Error −2 +2 LSB
Input Voltage Range 0 VREF × 2 V
Leakage Current −1 +1 μA
Input Capacitance 20 pF
Full Power Bandwidth 8 MHz
ADIS16080
Rev. $ | Page 4 of 16
Parameter Conditions Min1Typ Max1
Unit
DIGITAL OUTPUTS
Output High Voltage (VOH) ISOURCE = 200 μA VDRIVE − 0.2 V
Output Low Voltage (VOL) ISINK = 200 μA 0.4 V
CONVERSION RATE
Conversion Time 16 SCLK cycles with SCLK at 20 MHz 800 ns
Throughput Rate 1 MSPS
POWER SUPPLY All at TA = −40°C to +85°C
VCC 4.75 5 5.25 V
VDRIVE 2.7 5.25 V
VCC Quiescent Supply Current VCC @ 5 V, fSCLK = 50 kSPS 7.0 9.0 mA
VDRIVE Quiescent Supply Current VDRIVE @ 5 V, fSCLK = 50 kSPS 70 500 μA
Power Dissipation VCC and VDRIVE @ 5 V, fSCLK = 50 kSPS 40 mW
TEMPERATURE RANGE
Specified Performance Tested to max and min specifications −40 +85 °C
1 All minimum and maximum specifications are guaranteed. Typical specifications are neither tested nor guaranteed.
2 Dynamic range is the maximum full-scale measurement range possible, including output swing range, initial offset, sensitivity, offset drift, and sensitivity drift at 5 V supply.
3 Defined as the output change from ambient to maximum temperature, or ambient to minimum temperature.
4 Frequency at which the response is 3 dB down from dc response. Bandwidth = 1/(2 × π × 180 kΩ × (22 nF + COUT)). For COUT = 0, bandwidth = 40 Hz. For COUT = 1 μF,
bandwidth = 0.87 Hz.
5 Self-test response varies with temperature.
ADIS16080
Rev. $ | Page 5 of 16
TIMING SPECIFICATIONS
TA = 25°C, angular rate = 0°/sec, unless otherwise noted.1
Table 2.
Parameter VCC = VDRIVE = 5 V Unit Description
fSCLK210 kHz min
20 MHz max
tCONVERT 16 × tSCLK
tQUIET 50 ns min
Minimum quiet time required between CS rising edge and start of next conversion.
t2 10 ns min
CS to SCLK setup time.
t3330 ns max
Delay from CS until DOUT three-state disabled.
t43
40 ns max Data access time after SCLK falling edge.
t5 0.4 × tSCLK ns min SCLK low pulse width.
t6 0.4 × tSCLK ns min SCLK high pulse width.
t7 10 ns min SCLK to DOUT valid hold time.
t8415/35 ns min/max SCLK falling edge to DOUT high impedance.
t9 10 ns min DIN setup time prior to SCLK falling edge.
t10 5 ns min DIN hold time after SCLK falling edge.
t11 20 ns min
16th SCLK falling edge to CS high.
1 Guaranteed by design. All input signals are specified with tR and tF = 5 ns (10% to 90% of VCC) and timed from a voltage level of 1.6 V. The 5 V operating range spans
from 4.75 V to 5.25 V.
2 Mark/space ratio for the SCLK input is 40/60 to 60/40.
3 Measured with the load circuit in Figure 3 and defined as the time required for the output to cross 0.4 V, or 0.7 × VDRIVE.
4 t8 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit in Figure 3. The measured number is then extrapolated
back to remove the effects of charging or discharging the 50 pF capacitor. This means that the time, t8, quoted in the timing characteristics is the true bus relinquish
time of the part and is independent of the bus loading.
1 2 3 4 5 6 11 12 13 14 15 16
B
SCLK
DOUT
DIN
CS
ZERO ADD1 ADD0 DB2 DB1 DB0
LOWWRITE DONTC DONTC DONTC DONTC DONTC
DB11 DB10 DB4 DB3
ADD1 ADD0 CODING DONTC
ADDRESS BI TS
ZERO
THREE-STATE THREE-STATE
t2
t3t4
t9
t6
t7
tCONVERT
t5t8
t11
tQUIET
t10
06045-002
Figure 2. Gyroscope Serial Interface Timing Diagram
200µA I
OL
200µA I
OH
1.6V
TO OUTPUT
PIN C
L
50pF
06045-003
Figure 3. Load Circuit for Digital Output Timing Specifications
ADIS16080
Rev. $ | Page 6 of 16
ABSOLUTE MAXIMUM RATINGS
Table 3.
Parameter Rating
Acceleration (Any Axis, Unpowered, 0.5 ms) 2000 g
Acceleration (Any Axis, Powered, 0.5 ms) 2000 g
VCC to COM −0.3 V to +6.0 V
VDRIVE to COM −0.3 V to VCC + 0.3 V
Analog Input Voltage to COM −0.3 V to VCC + 0.3 V
Digital Input Voltage to COM −0.3 V to +7.0 V
Digital Output Voltage to COM −0.3 V to VCC + 0.3 V
ST1/ST2 Input Voltage to COM −0.3 V to VCC + 0.3 V
Operating Temperature Range −55°C to +125°C
Storage Temperature Range −65°C to +150°C
Stresses above those listed under the Absolute Maximum
Ratings may cause permanent damage to the device. This is a
stress rating only; functional operation of the device at these or
any other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
Drops onto hard surfaces can cause shocks of greater than
2000 g and exceed the absolute maximum rating of the device.
Care should be exercised in handling to avoid damage.
ESD CAUTION
ADIS16080
Rev. C | Page 7 of 16
PIN CONFIGURATION AND FUNCTION DESCRIPTIONS
FILT
RATE
V
DRIVE
AIN1
NC
CS
V
CC
ST1
NC = NO CONNECT
NC
DOUT
SCLK
DIN
AIN2
COM
V
REF
ST2
ADIS16080
BOTTOM
VIEW
(No t to S cale)
9
10
11
4
1
2
3
12
1314
15
16
8567
06045-004
Figure 4. Pin Configuration
Table 4. Pin Function Descriptions
Pin No. Mnemonic Type1 Description
1 DIN I SPI Data Input.
2 SCLK I SPI Serial Clock.
3 DOUT O SPI Data Output.
4 NC No Connect.
5 RATE O Buffered Analog Output. Represents the angular rate signal.
6 FILT I External Capacitor Connection to Control Bandwidth.
7 VDRIVE S SPI Power Supply. This can be the receive processing circuit’s supply to simplify interfacing.
8 AIN1 I External Analog Input Channel 1. See ADD0 and ADD1 address bits in Table 5.
9 AIN2 I External Analog Input Channel 2. See ADD0 and ADD1 address bits in Table 5.
10 COM S Common. Reference point for all circuitry in the ADIS16080.
11 VREF O Precision 2.5 V Reference.
12 ST2 I Self-Test Input 2.
13 ST1 I Self-Test Input 1.
14 VCC S Analog Power.
15 NC No Connect.
16 CS I Chip Select. Active low. This input frames the serial data transfer and initiates the conversion process.
1 I = input; O = output; S = power supply.
0.6700 BSC
12×
3.6865 BS C
8×
2.5050 BSC
8×
.5000 BSC
16×
1.000 BS C
16×
5.010 BSC
4×
7.373 BSC
2×
06045-020
Figure 5. Second-Level Assembly Pad Layout
ADIS16080
Rev. $ | Page 8 of 16
TYPICAL PERFORMANCE CHARACTERISTICS
25
20
15
10
5
0
PERCENT OF POPUL ATION (%)
NULL ( LSB)
AVERAG E = 2014.38
STD. DEV IAT IO N = 99.3236
0604
2080
2070
2060
2050
2040
2030
2020
2010
2000
–40°C
+25°C
+85°C
NULL LEVEL (LSB)
5-005
4.7 5.35.25.15.04.94.8
Figure 6. Initial Null Histogram
V
CC
(V)
06045-006
Figure 7. Null Level vs. Supply Voltage
2080
2070
2060
2050
2040
2030
2020
2010
2000
NULL LEVEL (LSB)
–50 –30 –10 10 30 50 70 90 110
TEM P ERATURE (°C)
30 PART AVERAGE, V
CC
= 4. 75V
30 PART AVERAGE, V
CC
= 5. 00V
30 PART AVERAGE, V
CC
= 5. 25V
06045-007
70
0
10
20
30
40
50
60
5.00
9.00
8.50
8.00
7.50
7.00
6.50
6.00
5.50
8.75
8.25
7.75
7.25
6.75
6.25
5.75
5.25
SUPPL Y CURRENT (mA)
PERCENT OF POPULATION (%)
AVERAGE = 6.4mA
STD. DEVIAT IO N = 0.2mA
06045-008
Figure 8. Null Level vs. Temperature
Figure 9. Supply Current Histogram
20
18
16
14
12
10
8
6
4
2
0
–600
–590
–450
–470
–490
–510
–530
–550
–570
–460
–480
–500
–520
–540
–560
–580
ST1 (LSB)
PERCENT OF POPULATION (%)
AVERAG E = –519. 6 L S B
ST D. DEV IAT ION = 21. 8 92 LSB
6045-0090
Figure 10. Self-Test 1 Histogram
25
20
15
10
5
0
450
600
590
570
550
530
510
490
470
580
560
540
520
500
480
460
PERCENT OF POPULATION (%)
AVERAGE = 522.4 7 LSB
STD. DEV IATIO N = 19.9086 LSB
45-010
ST2 (LS B)
060
Figure 11. Self-Test 2 Histogram
ADIS16080
Rev. $ | Page 9 of
–
16
400
–420
–440
–460
–480
–500
–520
–540
–560
–580
SELF-TEST LEVEL (LSB)
–600
4.7 5.35.25.15.04.94.8
V
CC
(V)
600
580
560
540
520
500
480
460
440
420
400
–50 –30 –10 10 30 50 70 90 110
TEM P ERATURE (°C)
SELF-TEST LEVEL (LSB)
30 PART AV E RAGE, VCC = 4.75 V
30 PART AV E RAGE, VCC = 5.00 V
30 PART AVERAGE, T
A
= –40°C
30 PART AVERAGE, T
A
= +25°C
30 PART AVERAGE, T
A
= +85°C
30 PART AV E RAGE, VCC = 5.25 V
06045-011
6045-0140
Figure 12. Self-Test 1 vs. Supply Voltage
600
450
500
550
SELF-TEST LEVEL (LSB)
400
4.7 5.35.25.15.04.94.8
V
CC
(V)
30 PART AVERAGE, T
A
= –40°C
30 PART AVE RAGE, T
A
= +25°C
30 PART AVE RAGE, T
A
= +85°C
06045-012
Figure 13. Self-Test 2 vs. Supply Voltage
–400
–420
–440
–460
–480
–500
–520
–540
–560
–580
–50 1009080706050403020100–10–20–30–40
TEM P ERATURE (°C)
SELF-TEST LEVEL (LSB)
30 PART AVERAGE, VCC = 4.75V
30 PART AVERAGE, VCC = 5.00V
30 PART AVERAGE, VCC = 5.25V
06045-013
Figure 14. Self-Test 1 vs. Temperature
Figure 15. Self-Test 2 vs. Temperature
0
–2.5
–2.0
–1.5
–1.0
–0.5
–50 –30 –10 10 30 50 70 90 110
TEM P ERATURE (°C)
OFFSET L EVEL (LSB)
30 PART AVERAGE, VCC = 4.75V
30 PART AVERAGE, VCC = 5.00V
30 PART AVERAGE, VCC = 5.25V
06045-015
1.0
0.9
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
GAI N E RRO R (LS B)
Figure 16. ADC Offset vs. Temperature and Supply Voltage
0
–50 –30 –10 10 30 50 70 90 110
TEM P ERATURE (°C)
30 PART AVERAG E , V CC = 4.75V
30 PART AVERAG E , V CC = 5.00V
30 PART AVERAG E , V CC = 5.25V
06045-016
Figure 17. ADC Gain Error vs. Temperature (Excluding VREF)
ADIS16080
Rev. $ | Page 10 of 16
2.479
4.7 5.35.25.15.04.94.8
V
CC
(V)
2.486
2.485
2.484
2.483
2.482
2.481
2.480
V
REF
LEVEL (V)
30 PART AVE RAGE, T
A
= +25°C
30 PART AVE RAGE, T
A
= +85°C
30 PART AVE RAGE, T
A
= –40° C
06045-017
Figure 18. VREF vs. Supply Voltage
01000 2000 3000 4000 5000 6000 7000 8000
000001110000010X 3
000001110000011X 19
000001110000100X 39
000001110000101X 87
000001110000110X 249
000001110000111X 844
000001110001000X 1136
000001110001001X 1303
000001110001010X 1702
000001110001011X 1229
000001110001100X 924
000001110001101X 447
000001110001110X 150
000001110001111X 43
000001110010000X 13
000001110010010X 4
SAMP LES = 8192, MAX CODE = 1827 , MI N CODE = 1 796,
SPRE AD = 3 2, STD DEV = 4.057 , ME AN = 1811.803
06045-018
1825
1820
1815
1810
1805
1800
Figure 19. Noise Histogram
ADIS16080
Rev. $ | Page 11 of 16
THEORY OF OPERATION
The ADIS16080 operates on the principle of a resonator
gyroscope. Two polysilicon sensing structures each contain a
dither frame that is electrostatically driven to resonance. This
produces the necessary velocity element to produce a Coriolis
force while rotating. At two of the outer extremes of each frame,
orthogonal to the dither motion, are movable fingers that are
placed between fixed pickoff fingers to form a capacitive pickoff
structure that senses Coriolis motion. The resulting signal is fed
to a series of gain and demodulation stages that produce the
electrical rate signal output. The rate signal is then converted to
a digital representation of the output on the SPI pins. The dual-
sensor design rejects external g forces and vibration. Fabricating
the sensor with the signal conditioning electronics preserves
signal integrity in noisy environments.
The electrostatic resonator requires 14 V to 16 V for operation.
Because only 5 V is typically available in most applications, a
charge pump is included on-chip. After the demodulation stage,
there is a single-pole, low-pass filter included on-chip that is used
to limit high frequency artifacts before final amplification. The
frequency response is dominated by the second low-pass filter,
which is set at 40 Hz. For additional bandwidth reduction
options, see the Setting Bandwidth section.
SUPPLY AND COMMON CONSIDERATIONS
Power supply noise and transient behaviors can influence the
accuracy and stability of any sensor-based measurement system.
When considering the power supply for the ADIS16080, it is
important to understand that the ADIS16080 provides 0.2 F of
decoupling capacitance on the VCC pin. Depending on the level
of noise present in the system power supply, the ADIS16080
may not require any additional decoupling capacitance for this
supply. The analog supply, VCC, and the digital drive supply,
VDRIVE, are segmented to allow multiple logic levels to be used in
receiving the digital output data. VDRIVE is intended for the
down-stream logic power supply and supports standard 3.3 V
and 5 V logic families. The VDRIVE supply does not have internal
decoupling capacitors.
INCREASING MEASUREMENT RANGE
The full-scale measurement range of the ADIS16080 is increased
by placing an external resistor between the RATE pin and FILT
pin, which results in a parallel connection with the internal
180 kΩ, 1% resistor. For example, a 330 kΩ external resistor
gives ~50% increase in the full-scale range. This is effective for
up to a 4× increase in the full-scale range (minimum value of
the parallel resistor allowed is 45 kΩ). The internal circuitry
headroom requirements prevent further increase in the linear
full-scale output range. The trade-offs associated with increas-
ing the full-scale range are potential increase in output null drift
(as much as 2°/sec over temperature) and introducing initial
null bias errors that must be calibrated.
SETTING BANDWIDTH
An external capacitor can be used in combination with an on-
chip resistor to create a low-pass filter to limit the bandwidth of
the ADIS16080 rate response.
The −3 dB frequency is defined as
( ( ))
=F0.022π21/ +× × × OUTOUTOUT CRf
where:
ROUT is the internal impedance that was trimmed during
manufacturing to 180 kΩ ± 1%.
COUT is the external capacitance across the RATE and FILT pins.
Any external resistor applied between the RATE pin and the
FILT pin results in
( ) ( )
EXTEXTOUT RRR +×= k180/k180
06045-019
where REXT is the external resistor.
With COUT = 0 F, a default −3 dB frequency response of 40 Hz
is obtained based upon an internal 0.022 F capacitor
implemented on-chip.
SELF-TEST FUNCTION
The ADIS16080 includes a self-test feature that actuates each of
the sensing structures and associated electronics in the same
manner as if subjected to an angular rate. It provides a simple
method for exercising the mechanical structure of the sensor,
along with the entire signal processing circuit. It is activated by
standard logic high levels applied to Input ST1, Input ST2, or
both. ST1 causes a change in the digital output equivalent to
typically −540 LSB, and ST2 causes an opposite +540 LSB change.
The self-test response follows the viscosity temperature dependence
of the package atmosphere, approximately 0.25%/°C. Activating
both ST1 and ST2 simultaneously is not damaging. Because ST1
and ST2 are not necessarily closely matched, actuating both
simultaneously can result in an apparent null bias shift.
CONTINUOUS SELF-TEST
As an additional failure detection measure, a power-on self-test
can be performed. However, some applications warrant a
continuous self-test while sensing rate.
RATE SENSITIVE AXIS
RATE OUT
RATE IN
0 LS B
4095 LS B
145
8
LONGITUDINAL
AXIS
RATE
AXIS
CLOCK-WISE
ROTATION
LATERAL
AXIS
Figure 20. Rate Signal Increases with Clockwise Rotation
ADIS16080
Rev. $ | Page 12 of 16
BASIC OPERATION
The ADIS16080 is designed for simple integration into indus-
trial system designs, requiring only a 5.0 V power supply and a
four-wire, industry standard serial peripheral interface (SPI). The
SPI handles all digital I/O communication in the ADIS16080.
SERIAL PERIPHERAL INTERFACE (SPI)
The ADIS16080 SPI port includes four signals: chip select (CS),
serial clock (SCLK), data input (DIN), and data output
(DOUT). The CS line enables the ADIS16080 SPI port and
frames each SPI event. When this signal is high, the DOUT
lines are in a high impedance state and the signals on DIN and
SCLK have no impact on operation. A complete data frame
contains 16 clock cycles. Because the SPI port operates in full
duplex mode, it supports simultaneous, 16-bit receive (DIN) and
transmit (DOUT) functions within the same data frame.
Control Register
The DIN control register provides controls for two operational
settings: the output data source and the coding (twos comple-
ment vs. offset binary). Table 5 and Figure 22 provide the
proper bit definitions for control register configuration. The
DIN sequence starts with a 1 for configuration sequences and a
0 for read sequences. When this bit is 0, the remaining DIN bits
do not change the control register and the next sample’s output
data reflects the existing configuration. Data loads from
the DIN pin into the ADIS16080 on the falling edge of SCLK.
Once the 16-SCLK sequence is complete, the control register is
updated and ready for the next read sequence. If a data frame
has less than 16 SCLK cycles, the control register does not
update and maintains its previous configuration. The DIN bit
definitions in Table 5, which have either 0 or 1 assigned to
them, are critical for proper operation.
ADC Conversion
The chip select (CS) and serial clock (SCLK) lines control the
on-board A/D conversion process. When the chip select line
goes low, the DOUT line comes out of three-state mode, the
track-and-hold goes into hold mode, and the ADC samples the
analog input at this point. The track-and-hold returns to track
mode on the 14th falling edge of the SCLK line. The serial clock
drives the internal ADC conversion clock, using its falling edge
for control of this process. All 16 SCLK cycles are required for a
complete conversion. If a data frame has less than 16 SCLK
cycles, the conversion cannot complete and does not update the
output data for the next data frame cycle.
Output Data Access
The DOUT sequence starts with two zeros, one that clocks out
after the falling edge of CS, and a second one that clocks out on
the first SCLK falling edge. The next 14 bits, ADD0, ADD1 and
the 12 data bits, clock out on SCLK falling edges. After the 16th
falling edge, the DOUT line moves to a three-state mode.
When setting up the system process to receive data from the
ADIS16080, use a clock phase setting of 0 and a clock polarity
setting of 1. These settings reflect the timing displayed in
Figure 22. To maintain proper communication at the maximum
specified clock rates, the system processor must be able to
support the setup time requirement, listed in Figure 2 and
Table 2 (t9).
CS
SCLK
DIN
DOUT
CO NF IG U RAT ION COM MAND F OR NEX T O U TP UT SEQUEN CE
DATA F RAM E DATA F RAM E
NEXT COMM AND, IF NE CESSARY
DATA O UT P UT, BA SED ON P REV IOUS CONFIGURAT ION
06045-021
Figure 21. Configuration and Read Sequence
D/CD/CD/CD/CD/CD/CD/C ADD1 ADD0D/C 110 0
CS
SCLK
DIN
ADC PLACED IN HO L D M ODE ADC PLACED IN TRACK M ODE
WRITE CODE
1 2 3 4 5 6 7 8 9 10111213141516
06045-022
D11ADD0ADD100 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
DOUT
Figure 22. SPI Sequence, Clock Polarity = 1, Clock Phase = 0
ADIS16080
Rev. $ | Page 13 of 16
Table 5. DIN Bit Assignments
Bit No. Mnemonic Comment
15 WRITE 1: Write contents on DIN to control
register.
0: No changes to control register.
14 0 Low state for normal operation.
13, 12 D/C Don’t care.
11, 10 ADD1, ADD0 Data source setting.
00: Gyroscope output.
01: Temperature output.
10: Analog input 1.
11: Analog input 2.
9, 8 1 High state for normal operation.
7, 6 D/C Don’t care.
5 0 Low state for normal operation.
4 CODE Output data format setting.
0: Twos complement.
1: Offset binary.
3 to 0 D/C Don’t care.
Output Coding Examples
Table 6. Gyroscope Data Coding, Twos Complement
Angular Rate (°/sec) Code Bit Pattern
80 819 0000001100110011
… … …
0.19532 2 0000000000000010
0.09766 1 0000000000000001
0 0 0000000000000000
−0.09766 −1 0000111111111111
−0.19532 −2 0000111111111110
… … …
−80 −819 0000110011001101
Table 7. Gyroscope Data Coding, Offset Binary
Angular Rate (°/sec) Code Bit Pattern
80 2867 0000101100110011
… … …
0.19532 2050 0000100000000010
0.09766 2049 0000100000000001
0 2048 0000100000000000
−0.09766 2047 0000011111111111
−0.19532 2046 0000011111111110
… … …
−80 1229 0000010011001101
Table 8. Temperature Data Coding, Twos Complement
Temperature (°C) Code Bit Pattern
85 585 0001001001001001
25 + 0.2906 2 0001000000000010
25 + 0.1453 1 0001000000000001
25 0 0001000000000000
25 − 0.1453 −1 0001111111111111
25 − 0.2906 −2 0001111111111110
−40 −447 0001111001000001
Table 9. Temperature Data Coding, Offset Binary
Temperature (°C) Code Bit Pattern
85 2633 0001101001001001
25 + 0.2906 2050 0001100000000010
25 + 0.1453 2049 0001100000000001
25 2048 0001100000000000
25 − 0.1453 2047 0001011111111111
25 − 0.2906 2046 0001011111111110
−40 1601 0001011001000001
Table 10. ADC Data Coding, Twos Complement
Input Level (V) Code1 Bit Pattern
4.5 1638 0010011001100110
2.5 + 0.002442 2 0010000000000010
2.5 + 0.001221 1 0010000000000001
2.5 0 0010000000000000
2.5 − 0.001221 −1 0010111111111111
2.5 − 0.002442 −2 0010111111111110
0.5 −1638 0010100110011010
1 Code for AIN1 used in 3rd and 4th bits (11 for AIN2).
Table 11. ADC Data Coding, Offset Binary
Input Level (V) Code1 Bit Pattern
4.5 3686 0010011001100110
2.5 + 0.002442 2050 0010100000000010
2.5 + 0.001221 2049 0010100000000001
2.5 2048 0010100000000000
2.5 − 0.001221 2047 0010011111111111
2.5 − 0.002442 2046 0010011111111110
0.5 410 0010000110011010
1 Code for AIN1 used in 3rd and 4th bits (11 for AIN2).
ADIS16080
Rev. $ | Page 14
2SCLK
3DOUT
13
DIN
16
1
12 ST2
of 16
APPLICATIONS INFORMATION
ASSEMBLY
The ADIS16080 is a system-in-package (SIP) that integrates
multiple components in a land grid array (LGA). This
configuration offers the convenience of solder-reflow
installation on printed circuit boards (PCBs). When developing
a process flow for installing ADIS16080 devices on PCBs, see
JEDEC standard document, J-STD-020C, for reflow temper-
ature profile and processing information. The ADIS16080 can
use either the Sn-PB eutectic process or the Pb-free eutectic
process from this standard. See JEDEC J-STD-033 for moisture
sensitivity (MSL) handling requirements. The MSL rating for
these devices is marked on the antistatic bags, which protect
these devices from ESD during shipping and handling. Prior to
assembly, review the process flow for information about
introducing shock levels that exceed the ADIS16080’s absolute
maximum ratings. Some PCB separation and ultrasonic
cleaning processes are common areas that can introduce high
levels of shock to these devices.
INTERFACE BOARD
The ADIS16080/PCBZ (see the Ordering Guide) provides the
ADIS16080 functionality on a 1.2 inch × 1.3 inch printed circuit
board, which simplifies the connection to an existing processor
system. The four mounting holes accommodate either M2 (2 mm)
or 2-56 machine screws. These boards are made of IS410 material
and are 0.063 inches thick. The second level assembly uses a
SAC305-compatible solder composition, which has a presolder
reflow thickness of approximately 0.005 inches. The pad pattern
on the ADIS16080/PCBZ matches Figure 5. J1 and J2 are dual-
row, 2 mm (pitch) connectors that work with several ribbon
cable systems, including 3M Part Number 152212-0100-GB
(ribbon-crimp connector) and 3M Part Number 3625/12
(ribbon cable).
11
VREF
8
AIN1 9
AIN2
6
FILT
5
RATE
4
15
ADIS16080
10
7VDRIVE
NC
NC
GND
11 12
910
7 8
5 6
3 4
1 2
CS
ST1
C1
1µF
14 VCC
C4
1µF C2
1µF
C3
1µF
11 12
910
7 8
5 6
3 4
1 2
J1 J2
06045-118
i
Sensor
U1
Figure 23. Electrical Schematic
1.100
1.050
2 × 0.925
J1
C1
J2
a
2 × 0.673
2 × 0.000
0.150
0.200
0.035
2 × 0.000
0.865
2 × 0.900
4 × Ø0.087
M2×0.4
06045-117
Figure 24. PCB Assembly View and Dimensions
ADIS16080
Rev. C | Page 15 of 16
OUTLINE DIMENSIONS
022107-B
SIDE VIEW
TOP VIEW BOTTO M VI E W
PIN 1
INDICATOR
0.873 BSC
(16×)
5.20
MAX
8.20
TYP
1
4
58
9
1213 16
8.35
MAX
5.010
BSC
(4×)
2.505
BSC
(8×)
7.00
TYP
7.373
BSC
(2×)
0.200
MIN
(ALL SIDES)
0.797 BSC
(12×)
0.373 BS C
(16×)
Figure 25. 16-Terminal Stacked Land Grid Array [LGA]
(CC-16-1)
Dimensions shown in millimeters
ORDERING GUIDE
Model1 Temperature Range Package Description Package Option
ADIS16080ACCZ −40°C to +85°C 16-Terminal Stacked Land Grid Array (LGA) CC-16-1
ADIS16080/PCBZ Evaluation Board
1 Z = RoHS Compliant Part.
ADIS16080
Rev. $ | Page 16 of 16
NOTES
©2006–20 Analog Devices, Inc. All rights reserved. Trademarks and
registered trademarks are the property of their respective owners.
D06045-0-/($)
