2000 Aug 07 853–0169 24291

The Philips 80C51/87C51/80C52/87C52 is a high-performance

static 80C51 design fabricated with Philips high-density CMOS

technology with operation from 2.7 V to 5.5 V.

The 8xC51 and 8xC52 contain a 128 × 8 RAM and 256 ×8 RAM

respectively, 32 I/O lines, three 16-bit counter/timers, a six-source,

four-priority level nested interrupt structure, a serial I/O port for

UART, and on-chip oscillator and clock circuits.

freezes the oscillator, causing all other chip functions to be

inoperative. Since the design is static, the clock can be stopped

without loss of user data and then the execution resumed from the

point the clock was stopped.

Note: 80C31/80C32 is specified in separate data sheet.

0K/8K/16K/32K 256 No No

0K/8K/16K/32K 512 Yes Yes

OTP P87C51SBPN

,

OTP P87C51SBAA

,

,

+

,

OTP P87C51UBAA

,

OTP P87C51UBPN

ROM P80C51 S = 16 MHz B = 0_ to +70_CAA = PLCC

OTP P87C52SBPN

,

OTP P87C52SBAA

,

,

+

,

OTP P87C52UBAA

,

OTP P87C52UBPN

address during an access to external memory. In normal operation, ALE is emitted at a

TL1 T imer Low 1 8BH 00H

TL2# T imer Low 2 CCH 00H

Unused register bits that are not defined should not be set by the user’s program. If violated, the device could function incor rectly.

# SFRs are modified from or added to the 80C51 SFRs.

XTAL1 and XTAL2 are the input and output, respectively, of an

on the duty cycle of the external clock signal, because the input to

A reset is accomplished by holding the RST pin high for at least two

To insure a good power-up reset, the RST pin must be high long

enough to allow the oscillator time to start up (normally a few

In idle mode (see Table 2), the CPU puts itself to sleep while all of

the on-chip peripherals stay active. The instruction to invoke the idle

interrupt (at which time the process is picked up at the interrupt

service routine and continued), or by a hardware reset which starts

the processor in the same manner as a power-on reset.

Mode is terminated.

interrupt can be used to exit from Power Down. Reset redefines all

the SFRs but does not change the on-chip RAM. An external

interrupt allows both the SFRs and the on-chip RAM to retain their

values. WUPD (AUXR1.3–W akeup from Power Down) enables or

oscillator but bringing the pin back high completes the exit. Once the

interrupt is serviced, the next instruction to be executed after RETI

Power Down.

4 V. The LPEP bit (AUXR.4), when set, will powerdown these analog

circuits resulting in a reduced supply current. This bit should be set

event, but access to the port pins is not inhibited. To eliminate the

be one that writes to a port pin or to external memory.

the circuit. The ONCE Mode is invoked by:

1. Pull ALE low while the device is in reset and PSEN is high;

2. Hold ALE low as RST is deactivated.

and 1 and exclude Slave 2 use address 1110 0100, since it is

Upon reset SADDR (SFR address 0A9H) and SADEN (SFR

RB8 In modes 2 and 3, the 9th data bit that was received. In Mode 1, if SM2 = 0, RB8 is the stop bit that was received.

Bit: 76543210

The 80C51/87C51 and 80C52/87C52 have a 6-source four-level

interrupt structure. They are the IE, IP and IPH. (See Figures 10, 11,

and 12.) The IPH (Interrupt Priority High) register that makes the

The function of the IPH SFR is simple and when combined with the

IP SFR determines the priority of each interrupt. The priority of each

interrupt is determined as shown in the following table:

or higher level priority is being serviced, the new interrupt will wait

until it is finished before being serviced. If a lower priority level

serviced. When the new interrupt is finished, the lower priority level

interrupt that was stopped will be completed.

T0 2 TP0 Y 0BH

Enable Bit = 0 disables it.

IE.7 EA Global disable bit. If EA = 0, all interrupts are disabled. If EA = 1, each interrupt can be individually

IE.6 — Not implemented. Reserved for future use.

ET0EX1ET1ESET2—EA

Priority Bit = 1 assigns higher priority

Priority Bit = 0 assigns lower priority

IP.7 — Not implemented, reserved for future use.

IP.6 — Not implemented, reserved for future use.

IP.5 PT2 T imer 2 interrupt priority bit.

IP.4 PS Serial Port interrupt priority bit.

IP.3 PT1 T imer 1 interrupt priority bit.

IP.2 PX1 External interrupt 1 priority bit.

Priority Bit = 0 assigns lower priority

IPH.7 — Not implemented, reserved for future use.

IPH.6 — Not implemented, reserved for future use.

IPH.5 PT2H Timer 2 interrupt priority bit high.

IPH.4 PSH Serial Port interrupt priority bit high.

IPH.3 PT1H Timer 1 interrupt priority bit high.

IPH.2 PX1H External interrupt 1 priority bit high.

IPH.1 PT0H Timer 0 interrupt priority bit high.

IPH.0 PX0H External interrupt 0 priority bit high.

All port pins of the 8xC51 and 8xC52 have slew rate controlled

outputs. This is to limit noise generated by quickly switching output

signals. The slew rate is factory set to approximately 10 ns rise and

The dual DPTR structure (see Figure 13) enables a way to specify

16-bit DPTR registers that address the external memory, and a

single bit called DPS = AUXR1/bit0 that allows the program code to

Select Reg DPS

The DPS bit status should be saved by software when switching

between DPTR0 and DPTR1.

Note that bit 2 is not writable and is always read as a zero. This

allows the DPS bit to be quickly toggled simply by executing an INC

DPTR instruction without affecting the WOPD or LPEP bits.

10.Pin capacitance is characterized but not tested. Pin capacitance is less than 25 pF. Pin capacitance of ceramic package is less than 15 pF

11. To improve noise rejection a nominal 100 ns glitch rejection circuitry has been added to the RST pin, and a nominal 15 ns glitch rejection

IIL Logical 0 input current, ports 1, 2, 3 VIN = 0.4 V –1 –50 µA

3. Capacitive loading on ports 0 and 2 may cause the VOH on ALE and PSEN to momentarily fall below the VCC–0.7 specification when the

6. This value applies to Tamb = 0°C to +70°C. For Tamb = –40°C to +85°C, ITL = –750 µA.

8. Under steady state (non-transient) conditions, IOL must be externally limited as follows:

9. ALE is tested to VOH1, except when ALE is off then VOH is the voltage specification.

tLHLL 14 ALE pulse width 85 2tCLCL–40 ns

tAVLL 14 Address valid to ALE low 22 tCLCL–40 ns

tLLAX 14 Address hold after ALE low 32 tCLCL–30 ns

tLLIV 14 ALE low to valid instruction in 150 4tCLCL–100 ns

tLLPL 14 ALE low to PSEN low 32 tCLCL–30 ns

tPLPH 14 PSEN pulse width 142 3tCLCL–45 ns

tPLIV 14 PSEN low to valid instruction in 82 3tCLCL–105 ns

tPXIX 14 Input instruction hold after PSEN 0 0 ns

tRLDV 15, 16 RD low to valid data in 147 5tCLCL–165 ns

tRHDX 15, 16 Data hold after RD 0 0 ns

tRHDZ 15, 16 Data float after RD 65 2tCLCL–60 ns

tLLDV 15, 16 ALE low to valid data in 350 8tCLCL–150 ns

tAVDV 15, 16 Address to valid data in 397 9tCLCL–165 ns

tLLWL 15, 16 ALE low to RD or WR low 137 239 3tCLCL–50 3tCLCL+50 ns

tAVWL 15, 16 Address valid to WR low or RD low 122 4tCLCL–130 ns

tQVWX 15, 16 Data valid to WR transition 13 tCLCL–50 ns

tWHQX 15, 16 Data hold after WR 13 tCLCL–50 ns

tQVWH 16 Data valid to WR high 287 7tCLCL–150 ns

tRLAZ 15, 16 RD low to address float 0 0 ns

tWHLH 15, 16 RD or WR high to ALE high 23 103 tCLCL–40 tCLCL+40 ns

tXLXL 17 Serial port clock cycle time 750 12tCLCL ns

tQVXH 17 Output data setup to clock rising edge 492 10tCLCL–133 ns

tXHQX 17 Output data hold after clock rising edge 8 2tCLCL–117 ns

tXHDX 17 Input data hold after clock rising edge 0 0 ns

tXHDV 17 Clock rising edge to input data valid 492 10tCLCL–133 ns

3. Interfacing the 87C51, 80C51, 87C52, or 80C52 to devices with float times up to 45 ns is permitted. This limited bus contention will not

tLHLL 14 ALE pulse width 2tCLCL–40 21 ns

tAVLL 14 Address valid to ALE low tCLCL–25 5 ns

tLLAX 14 Address hold after ALE low tCLCL–25 ns

tLLIV 14 ALE low to valid instruction in 4tCLCL–65 55 ns

tLLPL 14 ALE low to PSEN low tCLCL–25 5 ns

tPLPH 14 PSEN pulse width 3tCLCL–45 45 ns

tPLIV 14 PSEN low to valid instruction in 3tCLCL–60 30 ns

tPXIX 14 Input instruction hold after PSEN 0 0 ns

tPXIZ 14 Input instruction float after PSEN tCLCL–25 5 ns

tAVIV 14 Address to valid instruction in 5tCLCL–80 70 ns

tPLAZ 14 PSEN low to address float 10 10 ns

tLLDV 15, 16 ALE low to valid data in 8tCLCL–150 90 ns

tAVDV 15, 16 Address to valid data in 9tCLCL–165 105 ns

tLLWL 15, 16 ALE low to RD or WR low 3tCLCL–50 3tCLCL+50 40 140 ns

tAVWL 15, 16 Address valid to WR low or RD low 4tCLCL–75 45 ns

tQVWX 15, 16 Data valid to WR transition tCLCL–30 0 ns

tWHQX 15, 16 Data hold after WR tCLCL–25 5 ns

tQVWH 16 Data valid to WR high 7tCLCL–130 80 ns

tRLAZ 15, 16 RD low to address float 0 0 ns

tWHLH 15, 16 RD or WR high to ALE high tCLCL–25 tCLCL+25 5 55 ns

tXHQX 17 Output data hold after clock rising edge 2tCLCL–80 ns

tXHDX 17 Input data hold after clock rising edge 0 0 ns

tXHDV 17 Clock rising edge to input data valid 10tCLCL–133 167 ns

3. Interfacing the 87C51, 80C51, 87C52 or 80C52 to devices with float times up to 45ns is permitted. This limited bus contention will not cause

4. Variable clock is specified for oscillator frequencies greater than 16 MHz to 33 MHz. For frequencies equal or less than 16 MHz, see 16 MHz

Tamb = 21°C to +27°C, VCC = 5 V±10%, VSS = 0 V (See Figure 29)

tELQV

tGLGH tGHGL

tAVGL tGHAX

tDVGL tGHDX

With none of the security bits programmed the code in the program

code will be encrypted when verified. When only security bit 1 (see

external program memory are disabled from fetching code bytes

2. Any other combination of the security bits is not defined.

1. 4k byte user ROM data

2. 64 byte ROM encryption key

Security Bit 1: When programmed, this bit has two effects on masked ROM parts:

Security Bit 2: When programmed, this bit inhibits V erify User ROM.

NOTE: Security Bit 2 cannot be enabled unless Security Bit 1 is enabled.

For each of the following, check the appropriate box, and send to Philips along with the code:

0000H to 1FFFH DATA 7:0 User ROM Data