Avalanche Rugged Technology
Rugged Gate Oxide Technology
Lower Input Capacitance
Improved Gate Charge
Extended Safe Operating Area
Lower Leakage Current : 10 A (Max.) @ VDS = 200V
Lower RDS(ON) : 0.144 (Typ.)
Advanced Power MOSFET
Thermal Resistance
Junction-to-Case
Case-to-Sink
Junction-to-Ambient
RJC
RCS
RJA
Characteristic Max. UnitsSymbol Typ.
FEATURES
Absolute Maximum Ratings
Drain-to-Source Voltage
Continuous Drain Current (TC=25 )
Continuous Drain Current (TC=100 )
Drain Current-Pulsed
Gate-to-Source Voltage
Single Pulsed Avalanche Energy
Avalanche Current
Repetitive Avalanche Energy
Peak Diode Recovery dv/dt
Total Power Dissipation (TC=25 )
Linear Derating Factor
Operating Junction and
Storage Temperature Range
Maximum Lead Temp. for Soldering
Purposes, 1/8 “ from case for 5-seconds
Characteristic Value UnitsSymbol
IDM
VGS
EAS
IAR
EAR
dv/dt
ID
PD
TJ , TSTG
TL
A
V
mJ
A
mJ
V/ns
W
A
VDSS V
TO-220
1.Gate 2. Drain 3. Source
3
2
1
IRF640A
BVDSS = 200 V
RDS(on) = 0.18
ID = 18 A
200
18
11.4
72
216
18
13.9
5.0
139
1.11
- 55 to +150
300
0.9
--
62.5
--
0.5
--
30
+
_
O
1
O
2
O
3
O
1
O
1
oC
oC
oC
oC
θ
θ
θ
Ω
Ωµ
W/oC
oC/W
©1 999 Fair c hild Sem iconductor Corpora tion
Rev. B
N-CHANNEL
POWER MOSFET
Electrical Characteristics (TC=25 unless otherwise specified)
Drain-Source Breakdown Voltage
Breakdown Voltage Temp. Coeff.
Gate Threshold Voltage
Gate-Source Leakage , Forward
Gate-Source Leakage , Reverse
CharacteristicSymbol Max. UnitsTyp.Min. Test Condition
Static Drain-Source
On-State Resistance
Forward Transconductance
Input Capacitance
Output Capacitance
Reverse Transfer Capacitance
Turn-On Delay Time
Rise Time
Turn-Off Delay Time
Fall Time
Total Gate Charge
Gate-Source Charge
Gate-Drain(“Miller”) Charge
gfs
Ciss
Coss
Crss
td(on)
tr
td(off)
tf
Qg
Qgs
Qgd
BVDSS
BV/ TJ
VGS(th)
RDS(on)
IGSS
IDSS
V
V
nA
A
pF
ns
nC
--
--
--
--
--
--
--
--
--
--
--
--
--
VGS=0V,ID=250 A
ID=250 A See Fig 7
VDS=5V,ID=250 A
VGS=30V
VGS=-30V
VDS=200V
VDS=160V,TC=125
VGS=10V,ID=9A
VDS=40V,ID=9A
VDD=100V,ID=18A,
RG=9.1
See Fig 13
VDS=160V,VGS=10V,
ID=18A
See Fig 6 & Fig 12
Drain-to-Source Leakage Current
VGS=0V,VDS=25V,f =1MHz
See Fig 5
Source-Drain Diode Ratings and Characteristics
Continuous Source Current
Pulsed-Source Current
Diode Forward Voltage
Reverse Recovery Time
Reverse Recovery Charge
IS
ISM
VSD
trr
Qrr
CharacteristicSymbol Max. UnitsTyp.Min. Test Condition
--
--
--
--
--
A
V
ns
C
Integral reverse pn-diode
in the MOSFET
TJ=25 ,IS=18A,VGS=0V
TJ=25 ,IF=18A
diF/dt=100A/ s
IRF640A
200
--
2.0
--
--
--
--
--
0.26
--
--
--
--
--
210
94
17
16
48
24
44
10.4
27.1
--
--
4.0
100
-100
10
100
0.18
--
1500
250
110
40
40
110
60
58
--
--
9.61
1160
--
--
--
195
1.35
18
72
1.5
--
--
Notes ;
Repetitive Rating : Pulse Width Limited by Maximum Junction Temperature
L=1mH, IAS=18A, VDD=50V, RG=27 , Starting TJ =25
ISD 18A, di/dt 260A/ s, VDD BVDSS , Starting TJ =25
Pulse Test : Pulse Width = 250 s, Duty Cycle 2%
Essentially Independent of Operating Temperature
<
_<
_
<
_<
_
O
1
O
2
O
3
O
4
O
5
ΩoC
oC
µµ
oC
V/oCµ
µ
µ
µµ
O
1
O
4
O
4
oC
oC
O
4
O
4O
5
O
4
O
4O
5
Ω
Ω
Ω
oC
µ
∆ ∆
N-CHANNEL
POWER MOSFET
Fig 1. Output Characteristics Fig 2. Transfer Characteristics
Fig 6. Gate Charge vs. Gate-Source VoltageFig 5. Capacitance vs. Drain-Source Voltage
Fig 4. Source-Drain Diode Forward VoltageFig 3. On-Resistance vs. Drain Current
IRF640A
10-1 100101
10-1
100
101
@ Notes :
1. 250 µs Pulse Test
2. TC = 25 oC
VGS
Top : 1 5 V
1 0 V
8.0 V
7.0 V
6.0 V
5.5 V
5.0 V
Bottom : 4.5 V
ID , Drain Current [A]
VDS , Drain-Source Voltage [V]
2 4 6 8 10
10-1
100
101
25 oC
150 oC
- 55 oC
@ Notes :
1. VGS = 0 V
2. VDS = 40 V
3. 250 µs Pulse Test
ID , Drain Current [A]
VGS , Gate-Source Voltage [V]
020 40 60 80
0.0
0.1
0.2
0.3
0.4
@ Note : TJ = 25 oC
V
GS = 20 V
V
GS = 10 V
RDS(on)
, [
Ω]
Drain-Source On-Resistance
ID
, Drain Current [A] 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0
10-1
100
101
150 oC25 oC
@ Notes :
1. VGS = 0 V
2. 250 µs Pulse Test
IDR
, Reverse Drain Current [A]
V
SD , Source-Drain Voltage [V]
100101
0
500
1000
1500
2000 C
iss= Cgs+ Cgd ( C
ds= shorted )
C
oss= Cds+ Cgd
C
rss= Cgd
@ Notes :
1. VGS = 0 V
2. f = 1 MHz
C rss
C oss
C iss
Capacitance [pF]
V
DS , Drain-Source Voltage [V] 010 20 30 40 50
0
5
10
V
DS = 160 V
V
DS = 100 V
V
DS = 40 V
@ Notes : ID = 18.0 A
VGS
, Gate-Source Voltage [V]
QG
, Total Gate Charge [nC]
N-CHANNEL
POWER MOSFET
Fig 7. Breakdown Voltage vs. Temperature Fig 8. On-Resistance vs. Temperature
Fig 11. Thermal Response
Fig 10. Max. Drain Current vs. Case TemperatureFig 9. Max. Safe Operating Area
PDM
t1t2
IRF640A
-75 -50 -25 025 50 75 100 125 150 175
0.8
0.9
1.0
1.1
1.2
@ Notes :
1. VGS = 0 V
2. ID = 250 µA
BVDSS
, (Normalized)
Drain-Source Breakdown Voltage
T
J , Junction Temperature [ oC]
-75 -50 -25 025 50 75 100 125 150 175
0.0
0.5
1.0
1.5
2.0
2.5
3.0
@ Notes :
1. VGS = 10 V
2. ID = 9.0 A
RDS(on)
, (Normalized)
Drain-Source On-Resistance
T
J , Junction Temperature [ oC]
25 50 75 100 125 150
0
5
10
15
20
ID , Drain Current [A]
Tc
, Case Temperature [ o
C]
10-5 10-4 10-3 10-2 10-1 100101
10-2
10-1
100
single pulse
0.2
0.1
0.01
0.02
0.05
D=0.5
@ Notes :
1. ZθJC(t)=0.9 oC/W Max.
2. Duty Factor, D=t
1/t2
3. TJM-TC=PDM*ZθJC(t)
ZθJC
(t) , Thermal Response
t1 , Square Wave Pulse Duration [sec]
100101102
10-1
100
101
102
DC
100 µs
1 ms
10 ms
@ Notes :
1. TC = 25 oC
2. TJ = 150 oC
3. Single Pulse
Operation in This Area
is Limited by R DS(on)
ID , Drain Current [A]
V
DS , Drain-Source Voltage [V]
N-CHANNEL
POWER MOSFET
Fig 12. Gate Charge Test Circuit & Waveform
Fig 13. Resistive Switching Test Circuit & Waveforms
Fig 14. Unclamped Inductive Switching Test Circuit & Waveforms
EAS = LL IAS2
----
2
1--------------------
BVDSS -- VDD
BVDSS
Vin
Vout
10%
90%
td(on) tr
t on t off
td(off) tf
Charge
VGS
10V
Qg
Qgs Qgd
Vary t p to obtain
required peak ID
10V
VDD
C
LL
VDS
ID
RG
t p
DUT
BVDSS
t p
VDD
IAS
VDS (t)
ID (t)
Time
VDD
( 0.5 rated VDS )
10V
Vout
Vin
RL
DUT
RG
3mA
VGS
Current Sampling (IG)
Resistor Current Sampling (ID)
Resistor
DUT
VDS
300nF
50KΩ
200nF12V
Same Type
as DUT
“ Current Regulator ”
R1R2
IRF640A
N-CHANNEL
POWER MOSFET
Fig 15. Peak Diode Recovery dv/dt Test Circuit & Waveforms
DUT
VDS
+
--
L
I S
Driver
VGS
RGSame Type
as DUT
VGS • dv/dt controlled by “RG”
• IS controlled by Duty Factor “D”
VDD
10V
VGS
( Driver )
I S
( DUT )
VDS
( DUT )
VDD
Body Diode
Forward Voltage Drop
Vf
IFM , Body Diode Forward Current
Body Diode Reverse Current
IRM
Body Diode Recovery dv/dt
di/dt
D = Gate Pulse Width
Gate Pulse Period
--------------------------
IRF640A
TRADEMARKS
ACEx™
CoolFET™
CROSSVOLT™
E2CMOSTM
FACT™
FACT Quiet Series™
FAST®
FASTr™
GTO™
HiSeC™
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not intended to be an exhaustive list of all such trademarks.
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FAIRCHILD’S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT
DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROV AL OF FAIRCHILD SEMICONDUCTOR CORPORA TION.
As used herein:
ISOPLANAR™
MICROWIRE™
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PowerTrench™
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Quiet Series™
SuperSOT™-3
SuperSOT™-6
SuperSOT™-8
TinyLogic™
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systems which, (a) are intended for surgical implant into
the body, or (b) support or sustain life, or (c) whose
failure to perform when properly used in accordance
with instructions for use provided in the labeling, can be
reasonably expected to result in significant injury to the
user.
2. A critical component is any component of a life
support device or system whose failure to perform can
be reasonably expected to cause the failure of the life
support device or system, or to affect its safety or
effectiveness.
PRODUCT ST A TUS DEFINITIONS
Definition of Terms
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Advance Information
Preliminary
No Identification Needed
Obsolete
This datasheet contains the design specifications for
product development. Specifications may change in
any manner without notice.
This datasheet contains preliminary data, and
supplementary data will be published at a later date.
Fairchild Semiconductor reserves the right to make
changes at any time without notice in order to improve
design.
This datasheet contains final specifications. Fairchild
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any time without notice in order to improve design.
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that has been discontinued by Fairchild semiconductor.
The datasheet is printed for reference information only.
Formative or
In Design
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