Semiconductor Components Industries, LLC, 2000
April, 2000 – Rev. 1 1Publication Order Number:
LM308A/D
LM308A
Precision Operational
Amplifier
The LM308A operational amplifier provides high input impedance,
low input offset and temperature drift, and low noise. These
characteristics are made possible by use of a special Super Beta
processing technology. This amplifier is particularly useful for
applications where high accuracy and low drift performance are
essential. In addition high speed performance may be improved by
employing feedforward compensation techniques to maximize slew
rate without compromising other performance criteria.
The LM308A offers extremely low input offset voltage and drift
specifications allowing usage in even the most critical applications
without external offset nulling.
•Operation from a Wide Range of Power Supply Voltages
•Low Input Bias and Offset Currents
•Low Input Offset Voltage and Guaranteed Offset Voltage Drift
Performance
•High Input Impedance
R2
Frequency Compensation
Standard Compensation Modified Compensation
R2
R1
R3
Compen A
Output
Compen B
Inverting
Input
Noninverting
Input
Cf ≥ 30 1
1 + R2
R1
Cf
Standard Feedforward
Compensation Feedforward Compensations for
Decoupling Load Capacitance
Input
10k 5.0pF
10
k
Output
CompenB
3.0k
10pF
CompenA
500pF
Input
500
10pFC2*
Compen B
10pF
500pF 3.0k CL
75pF
to
0.01µ
F
*C2 > 5 x 105pF
R1
R3
Compen B
Inverting
Input
Noninverting
Input
100pF
R2
RS > 10k 100k
0.01µF
CompenA
+
++
+
Output
Device Package Shipping
ORDERING INFORMATION
LM308AN PDIP–8 50 Units/Rail
LM308AD SO–8
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98 Units/Rail
Compen A Compen B
Inputs Output
VCC
NC
VEE
(Top View)
1
2
3
4
8
7
6
5
PIN CONNECTIONS
+
–
PDIP–8
N SUFFIX
CASE 626
1
8
SO–8
D SUFFIX
CASE 751
1
8
MARKING
DIAGRAMS
ALYWA
LM308
1
8
AWL
LM308AN
1
8
YYWW
A = Assembly Location
WL, L = Wafer Lot
YY, Y = Year
WW, W = Work Week
LM308ADR2 SO–8 2500 Tape & Reel
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MAXIMUM RATINGS (TA = +25°C, unless otherwise noted.)
Rating Symbol Value Unit
Power Supply Voltage VCC, VEE ±18 Vdc
Input Voltage (Note 1.) VI±15 V
Input Differential Current (Note 2.) IID ±10 mA
Output Short Circuit Duration tSC Indefinite –
Operating Ambient Temperature Range TA0 to +70 °C
Storage Temperature Range Tstg –65 to +150 °C
Junction Temperature TJ+150 °C
1. For supply voltages less than ±15 V, the maximum input voltage is equal to the supply voltage.
2. The inputs are shunted with back–to–back diodes for overvoltage protection. Therefore, excessive current will flow if a differential input
voltage in excess of 1.0 V is applied between the inputs, unless some limiting resistance is used.
ELECTRICAL CHARACTERISTICS (Unless otherwise noted these specifications apply for supply voltages of +5.0 V ≤ VCC ≤
+15 V and –5.0 V ≥ VEE ≥–15 V, TA = +25°C.)
Characteristic Symbol Min Typ Max Unit
Input Offset Voltage VIO – 0.3 0.5 mV
Input Offset Current IIO – 0.2 1.0 nA
Input Bias Current IIB – 1.5 7.0 nA
Input Resistance ri10 40 – MΩ
Power Supply Currents ICC, IEE –±0.3 ±0.8 mA
(VCC = +15 V, VEE = –15 V)
Large Signal Voltage Gain AVOL 80 300 – V/mV
(VCC = +15 V, VEE = –15 V, VO = ±10 V, RL ≥ 10 kΩ)
The following specifications apply over the operating temperature range.
Input Offset Voltage VIO – – 0.73 mV
Input Offset Current IIO – – 1.5 nA
Average Temperature Coefficient of Input Offset Voltage ∆VIO/∆T – 1.0 5.0 µV/°C
TA (min) ≤ TA ≤ TA (max)
Average Temperature Coefficient of Input Offset Current ∆IIO/∆T – 2.0 10 pA/°C
Input Bias Current IIB – – 10 nA
Large Signal Voltage Gain AVOL 60 – – V/mV
(VCC +15 V, VEE = –15 V, VO = ±10 V, RL ≥ 10 kΩ)
Input Voltage Range VICR ±14 – – V
(VCC = +15 V, VEE = –15 V)
Common Mode Rejection CMR 96 110 – dB
(RS ≤ 50 kΩ)
Supply Voltage Rejection PSR 96 110 – dB
(RS ≤ 50 kΩ)
Output Voltage Range
(VCC = +15 V, VEE = –15 V, RL = 10 kΩ)VOR ±13 ±14 – V
LM308A
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200
AVOL, VOLTAGE GAIN (dB)
ICC
=
IEE , SUPPLY CURRENTS ( A)µ
VOR, OUTPUT VOLTAGE RANGE ( V±p-p)
VCC = VEE, SUPPLY VOLTAGES (V)
f, FREQUENCY (Hz) f, FREQUENCY (Hz)
130
120
110
100
90
80
0 5.0 10 15 20
500
400
300
100
00 5.0 10
VCC = VEE, SUPPLY VOLTAGES (V)
140
120
100
80
60
40
20
0
-20
1.0 10 100 1.0 k 10 k 100 k 1.0 M 10 M 100 M
20
16
12
8.0
4.0
0
1.0 k 10 k 100 k 1.0 M
15 20
AVOL, VOLTAGE GAIN (dB)
Figure 1. Input Bias and Input Offset Currents Figure 2. Maximum Equivalent Input Offset
Voltage Error versus Input Resistance
IIB, INPUT BIAS CURRENT (nA)
EQUIVALENT INPUT OFFSET VOLTAGE (mV)
T, TEMPERATURE (°C) ri, INPUT RESISTANCE (Ω)
2.0
1.8
1.6
1.4
1.2
1.0
0.8
0.6
0.4
0.2
0
-60 -40 -20 0 20 40 60 80 100 120 140
0.25
0.20
0.15
0.10
0.05
0
100
10
1.0
0.1
100 k 1.0 M 10 M 100 M
IIO, INPUT OFFSET CURRENT (nA)
CF = 3.0 pF
Figure 3. Voltage Gain versus Supply Voltages Figure 4. Power Supply Currents versus
Power Supply Voltages
Figure 5. Open Loop Frequency Response Figure 6. Large Signal Frequency Response
IIO
IIB
CF = 30 pF
CF = 100 pF
CF = 0
f = 100 Hz
0°C
TA = 0°C
+25°C
-55°C
+70°C
+125°C
TA = -55°C
+25°C
+70°C
+125°C
CF = 30 pF
CF = 3.0 pF
VCC = +15 V
VEE = -15 V
TA = +25°C
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SUGGESTED DESIGN APPLICATIONS
INPUT GUARDING
Special care must be taken in the assembly of printed
circuit boards to take full advantage of the low input currents
of the LM308A amplifier. Boards must be thoroughly
cleaned with alcohol and blown dry with compressed air.
After cleaning, the boards should be coated with epoxy or
silicone rubber to prevent contamination.
Even with properly cleaned and coated boards, leakage
currents may cause trouble at +125°C, particularly since the
input pins are adjacent to pins that are at supply potentials.
This leakage can be significantly reduced by using guarding
to lower the voltage difference between the inputs and
adjacent metal runs. The guard, which is a conductive ring
surrounding the inputs, is connected to a low–impedance
point that is at approximately the same voltage as the inputs.
Leakage currents from high voltage pins are then absorbed
by the guard.
(1) Power Bandwidth: 250 kHz
Small Signal Bandwidth:
3.5 MHz
Slew Rate: 10 V/µs
(2) C5 = 6 X 10-8
R1
(3) In addition to increasing speed,
the LM101A raises high and low
frequency gain, increases output
drive capability and eliminates
thermal feedback.
RS C5 (2)
Input
R1 R4
150pF
1
6
2
3
1.0M
Output
LM101A(3)
or equiv
Compen B
1 M
R2
LM308A
0.002µF
0.002
µF
300pF
150k
Figure 7. Fast (1) Summing Amplifier with
Low Input Current
(1) Teflon, Polyethylene or Polycarbonate
Dielectric Capacitor
Output
30pF
Q1
Q2
Input
Sample
VCC
1.0M
1.0µF (1)
Figure 8. Sample and Hold
Inverting Amplifier Follower Noninverting Amplifier
(1) Used to compensate for large source resistances. Note: R1 R2
R1 +R2 must be an impedance.
C1
R1 R2
Input
Output
R3 (1)
C1
Input
Output
R3 (1)
C1
R2
Input
Output
R1
R3 (1)
Figure 9. Connection of Input Guards
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Representative Circuit Schematic
VCC
Output
Compensation A Compensation B
200
65
150
VEE
1.0k
1.4k
7.5k5.6k3.5k
7.0k
1.0k
VCC
VEE
20k
362 1.2k 50k
80k
10k
2.0k
17.4k
15pF
Inputs
2.0k
7.5k
1.0k
17.4k
LM308A
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PACKAGE DIMENSIONS
PDIP–8
N SUFFIX
CASE 626–05
ISSUE K
NOTES:
1. DIMENSION L TO CENTER OF LEAD WHEN
FORMED PARALLEL.
2. PACKAGE CONTOUR OPTIONAL (ROUND OR
SQUARE CORNERS).
3. DIMENSIONING AND TOLERANCING PER ANSI
Y14.5M, 1982.
14
58
F
NOTE 2 –A–
–B–
–T–
SEATING
PLANE
H
J
GDK
N
C
L
M
M
A
M
0.13 (0.005) B M
T
DIM MIN MAX MIN MAX
INCHESMILLIMETERS
A9.40 10.16 0.370 0.400
B6.10 6.60 0.240 0.260
C3.94 4.45 0.155 0.175
D0.38 0.51 0.015 0.020
F1.02 1.78 0.040 0.070
G2.54 BSC 0.100 BSC
H0.76 1.27 0.030 0.050
J0.20 0.30 0.008 0.012
K2.92 3.43 0.115 0.135
L7.62 BSC 0.300 BSC
M--- 10 --- 10
N0.76 1.01 0.030 0.040

SO–8
D SUFFIX
CASE 751–06
ISSUE T
SEATING
PLANE
1
4
58
A0.25 MCB SS
0.25 MBM
h
C
X 45
L
DIM MIN MAX
MILLIMETERS
A1.35 1.75
A1 0.10 0.25
B0.35 0.49
C0.19 0.25
D4.80 5.00
E
1.27 BSCe
3.80 4.00
H5.80 6.20
h
0 7
L0.40 1.25
0.25 0.50
NOTES:
1. DIMENSIONING AND TOLERANCING PER ASME
Y14.5M, 1994.
2. DIMENSIONS ARE IN MILLIMETER.
3. DIMENSION D AND E DO NOT INCLUDE MOLD
PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 PER SIDE.
5. DIMENSION B DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 TOTAL IN EXCESS
OF THE B DIMENSION AT MAXIMUM MATERIAL
CONDITION.
D
EH
A
Be
B
A1
CA
0.10
LM308A
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Notes
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8
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LM308A/D
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