1
Features
•CPU32+Processor(4.5MIPSat25MHz)
– 32-bitVersionoftheCPU32Core(FullyCompatiblewiththeCPU32)
– BackgroundDebugMode
– Byte-misalignedAddressing
•Upto32-bitDataBus(DynamicBusSizingfor8and16Bits)
•Upto32AddressLines(AtLeast28AlwaysAvailable)
•CompleteStaticDesign(0-25MHzOperation)
•SlaveModetoDisableCPU32+(AllowsUsewithExternalProcessors)
– MultipleQUICCsCanShareOneSystemBus(OneMaster)
– TS68040CompanionModeAllowsQUICCtobeaTS68040CompanionChipand
IntelligentPeripheral(22MIPSat25MHz)
– PeripheralDeviceofTSPC603e(seeDC415/Dnote)
•FourGeneral-purposeTimers
– SupersetofMC68302Timers
– Four16-bitTimersorTwo32-bitTimers
– GateModeCanEnable/DisableCounting
•TwoIndependentDMAs(IDMAs)
•SystemIntegrationModule(SIM60)
•CommunicationsProcessorModule(CPM)
•FourBaudRateGenerators
•FourSCCs(Ethernet/IEEE802.3OptionalonSCC1-Full10MbpsSupport)
•TwoSMC
•VCC=+5V±5%
•fmax=25MHzand33MHz
•MilitaryTemperatureRange:-55°C<TC<+125°C
•PD=1.4Wat25MHz;5.25V
2Wat33MHz;5.25V
Description
TheTS68EN360QUadIntegratedCommunicationController(QUICC™)isaversatile
one-chipintegratedmicroprocessorandperipheralcombinationthatcanbeusedina
varietyofcontrollerapplications.Itparticularlyexcelsincommunicationsactivities.
TheQUICC(pronounced“quick”)canbedescribedasanext-generationTS68302
withhigherperformanceinallareasofdeviceoperation,increasedflexibility,major
extensionsincapability,andhigherintegration.Theterm“quad”comesfromthefact
thattherearefourserialcommunicationscontrollers(SCCs)onthedevice;however,
thereareactuallysevenserialchannels:fourSCCs,twoserialmanagementcontrol-
lers(SMCs),andoneserialperipheralinterface(SPI).
Screening/Quality
Thisproductismanufacturedinfullcompliancewith:
• MIL-STD-883(classB)
• QML(classQ)
• oraccordingtoAtmelstandards
32-bitQuad
Integrated
Communication
Controller
TS68EN360
Rev.2113A–HIREL–03/02
2TS68EN360 2113A–HIREL–03/02
Introduction
QUICCArchitecture
Overview TheQUICCis32-bitcontrollerthatisanextensionofothermembersoftheTS68300
family.LikeothermembersoftheTS68300family,theQUICCincorporatestheinter-
modulebus(IMB).TheTS68302isanexception,havingan68000busonchip.TheIMB
providesacommoninterfaceforallmodulesoftheTS68300family,whichallowsthe
developmentofnewdevicesmorequicklybyusingthelibraryofexistingmodules.
AlthoughtheIMBdefinitionalwaysincludedanoptionforanon-chip32-bitbus,the
QUICCisthefirstdevicetoimplementthisoption.
TheQUICCiscomprisedofthreemodules:theCPU32+core,theSIM60,andtheCPM.
Eachmoduleutilizesthe32-bitIMB.
TheTS68EN360QUICCblockdiagramisshowninFigure1.
Figure1.QUICCBlockDiagram
R suffix
PGA 241
Ceramic Pin Grid Array Cavity Up
A suffix
CERQUAD 240
Ceramic Leaded Chip Carrier Cavity Down
EXTERNAL
BUS
INTERFACE
SYSTEM
PROTECTION
SIM 60
CPU32+
CORE
IMB (32 BIT)
RISC
CONTROLLER
SYSTEM
I/F
2.5-KBYTE
DUAL-PORT
RAM
DRAM
CONTROLLER
AND
CHIP SELECTS
CPM
PERIODIC
TIMER
CLOCK
GENERATION
OTHER
FEATURES
BREAKPOINT
LOGIC
JTAG
COMMUNICATIONS PROCESSOR
FOUR
GENERAL-
PURPOSE
TIMERS
INTERRUPT
CONTROLLER
OTHER
FEATURES
TIMER SLOT
ASSIGNER
SEVEN
SERIAL
CHANNELS
TWO
IDMAs FOURTEEN SERIAL
DMAs
3
TS68EN360
2113A–HIREL–03/02
PinAssignments
Figure2.241-leadPinGridArray(PGA)
Note: PinP9“NC”isforguidepurposesonly.
123456789101112131415161718
A
B
C
D
E
F
G
H
J
K
L
M
N
P
Q
R
S
T
D2
PA15
D4
D7
D10
D13
D16
D19
CLKO2
CLKO1
D21
D24
D27
D30
FC2
SIZ1
SIZ0
D0
PA12
D3
D6
D9
D12
D15
D18
Vcc
D20
D23
D26
D29
FC3
FC1
A29
A28
XTAL
PA13
PA9
D1
D5
D8
D11
D14
D17
GND
D22
D25
D28
D31
FC0
A30
EXTAL
MODCK0
NC4
PA10
PA6
PA14
GND
GND
GND
GND
Vcc
Vccclk
GND
GND
Vcc
GND
A31
XFC
MODCK1
GND
A26
PA7
PA3
PA11
GND
Vcc
GND
GNDclk
Vcc
GND
Vccsyn
Vcc
A27
A25
A24
PA5
PA2
PA8
GND
GND
GNDsyn
GND
A23
A22
A21
PA1
PB17
PA4
Vcc
GND
A20
A19
A18
PB16
PB15
PA0
Vcc
Vcc
A17
A16
A15
PB13
PB12
PB14
GND
NC
GND
Vcc
A14
A13
A12
PB10
PB11
PB9
GND
GND
A8
A10
A11
PB7
PB8
PB6
Vcc
GND
A4
A7
A9
PB4
PB5
PB3
Vcc
GND
A0
A5
A6
PB1
PB2
PB0
GND
Vcc
Vcc
GND
CS7
A1
A3
PC10
PC11
PC8
GND
GND
GND
Vcc
GND
Vcc
GNDs1
Vcc
CS4
IRQ7
A2
PC7
PC9
PC4
GND
GND
GND
Vcc
GND
Vcc
GND
GNDs2
Vcc
GND
Vcc
GND
CS1
CS5
TRIS
PC3
PC6
PC0
IRQ5
HALT
AVEC
TD1
TRST
IRQ4
IFETCH
NC2
IPIPE0
PRTY2
NC3
CAS0
CAS3
CS2
CS6
PC1
PC5
IRQ3
BERR
RMC
TDO
TCK
BKPT
BGACK
NC1
BCLRO
AS
PRTY1
DSACK1
R/W
FREEZE
CAS2
CS3
IRQ2
PC2
IRQ1
RESETS
PERR
TMS
RESETH
IRQ6
BG
BR
OE
IPIPE1
PRTY0
PRTY3
DSACK0
DS
CAS1
CS0
TS68EN360
(BOTTOM VIEW)
4TS68EN360 2113A–HIREL–03/02
Figure3.240-leadCerquad
IRQ1 240
BERR
GND
HALT
RESETS
Vcc
RMC
AVEC
GND
PERR
TDO 230
TDI
TMS
TCK
TRST
RESETH
BKPT
GND
IRQ6
IRQ4
Vcc 220
BGACK
BG
GND
Vcc
BR
NC1
IFETCH
OE
GND
BCLRO 210
NC2
Vcc
IPIPE1
GNDs2
AS
IPIPE0
PRTY0
PRTY1
Vcc
GND 200
PRTY2
PRTY3
GND
DSACK1
GND
DSACK0
Vcc
NC3
R/W
GND 190
DS
FREEZE
CAS0
GND
CAS1
Vcc
CAS2
CAS3
GNDs1 181
D061 D1
GND
D2
D3
D4
Vcc
D5
D6
GND70 D7
D8
D9
D10
D11
GND
D12
D13
D14
Vcc80 D15
D16
GND
D17
D18
D19
CLKO2
GNDclk
Vccclk
CLKO190 D20
D21
D22
GND
D23
D24
D25
Vcc
D26
D27100 D28
GND
D29
D30
D31
GND
Vcc
FC3
FC2
FC1110 GND
FC0
SIZ1
SIZ0
Vcc
A31
A30
GND
A29
A28120
CS0
180
CS1
CS2
CS3
Vcc
GND
CS4
CS5
CS6
CS7
IRQ7
170
TRIS
A0
A1
GND
A2
A3
Vcc
A4
A5
GND
160
A6
A7
Vcc
GND
A8
A9
GND
A10
A11
Vcc
150
A12
A13
GND
A14
A15
A16
A17
A18
GND
A19
140
A20
A21
Vcc
A22
A23
A24
GND
A25
A26
A27
130
NC4
GND
MODCK1
MODCK0
XTAL
EXTAL
GNDsyn
XFC
Vccsyn
121
IRQ5
1
IRQ3
IRQ2
PC0
PC1
PC2
GND
PC3
PC4
PC5
10
PC6
Vcc
PC7
PC8
PC9
PC10
GND
PC11
PB0
PB1
20
PB2
PB3
PB4
PB5
PB6
GND
PB7
PB8
PB9
PB10
30
Vcc
PB11
PB12
PB13
PB14
GND
PB15
PB16
PB17
PA0
40
GND
Vcc
PA1
PA2
PA3
PA4
GND
PA5
PA6
PA7
50
PA8
Vcc
PA9
PA10
PA11
PA12
GND
PA13
PA14
PA15
60
TS68EN360
(TOP VIEW)
PIN ONE INDICATOR
5
TS68EN360
2113A–HIREL–03/02
SignalDescription
FunctionalSignalGroup
Figure4.QUICCFunctionalSignalGroups
QUICC
A31±A28/WE0±WE3
A27±A0
DATA BUSD31±D16
D15±D0
PRTY3/16BM
BUS CONTROL
SIZ0
SIZ1
R/W
AS
BUS ARBITRA TION
BR
BG
BCLRO/CONFIG1/RAS2DD
SYSTEM CONTROL
RESETH
RESETS
HALT
PERR
INTERRUPT CONTROL
AVEC/IACK5/AVECO
MEMORY CONTROLLER
CS6±CS0/RAS6±RAS0
CS/RAS7/IACK7
CAS3±CAS0/IACK6,3,2,1
TCK
TMS
TDI
TDO
TRST
CLOCK XTAL
EXTAL
XFC
MODCK1±MODCK0
CLKO2±CLKO1
ADDRESS BUS
RXD1/PA0
PORT A
TXD1/PA1
RXD2/PA2
TXD2/PA3
L1TXDB/RXD3/PA4
L1RXDB/TXD3/PA5
L1TXDA/RXD4/PA6
L1RXDA/TXD4/PA7
TIMERs/SCCs/SIs/CLOCKs/BRG
TIN1/L1RCLKA/BRGO1/CLK1/PA8
BRGCLK1/TOUT1/CLK2/PA9
TIN2/L1TCLKA/BRGO2/CLK3/PA10
TOUT2/CLK4/PA11
TIN3/BRGO3/CLK5/PA12
BRGCLK2/L1RCLKB/TOUT3/CLK6/PA13
TIN4/BRGO4/CLK7/PA14
L1TCLKB/TOUT4/CLK8/PA15
PORT B (PIP)
RRJCT1/SPISEL/PB0
RSTRT2/SPICLK/PB1
RRJCT2/SPIMOSI(SPITXD)/PB2
BRGO4/SPIMISO(SPIRXD)/PB3
DREQ1/BRGO1/PB4
DACK1/BRGO2/PB5
DONE1/SMTXD1/PB6
DONE2/SMRXD1/PB7
DREQ2/SMSYN1/PB8
DACK2/SMSYN2/PB9
L1CLKOB/SMTXD2/PB10
L1CLKOA/SMRXD2/PB11
L1ST1/RTS1/PB12
L1ST2/RTS2/PB13
L1ST3/L1RQB/RTS3/PB14
L1ST4/L1RQA/RTS4/PB15
STRBO/BRGO3/PB16
STRBI/RSTRT1/PB17
PORT C (INTERRUPT PARALLEL I/O)
L1ST1/RTS1/PC0
L1ST2/RTS2/PC1
L1ST3/L1RQB/RTS3/PC2
L1ST4/L1RQA/RTS4/PC3
CTS1/PC4
TGATE1/CD1/PC5
CTS2/PC6
TGATE2/CD2/PC7
SDACK2/L1TSYNCB/CTS3/PC8
L1RSYNCB/CD3/PC9
SDACK1/L1TSYNCA/CTS4/PC10
L1RSYNCA/CD4/PC11
TS68360
240 PINS
TEST
FC2±FC0/
TM2±TM0
FC3/
TT0
PRTY1±PRTY2/
IOUT1±IOUT2
PRTY2/IOUT0/
RQOUT
DSACK0/
TBI
DSACK1/
TA
DS/
TT1
OE/AMUX
RMC/CONFIG0/
LOCK
BGACK/
BB
BERR/
TEA
IRQ1/
OUT0
/RQOUTIRQ1/
OUT0
/RQOUT
IRQ4/
OUT1
IRQ6/
OUT2
IRQ2,3,5,7
TRIS/
TS
BKPT/
BKPT0
/DSCLK
FREEZE/CONFIG2/
MBARE
IPIPE1/RAS1DD/
BCLRI
IPIPE0/
BADD2
/DSO
IFETCH/
BADD3
/DSI
6TS68EN360 2113A–HIREL–03/02
SignalIndex
Table1.SystemBusSignalIndex(NormalOperation)
Group SignalName Mnemonic Function
Address AddressBus A27-A0 Lower27bitsofaddressbus.(I/O)
AddressBus/ByteWrite
Enables A31-A28
WE3-WE0 Upperfourbitsofaddressbus(I/O),orbytewriteenable
signals(O)foraccessestoexternalmemoryorperipherals.
FunctionCodes FC3-FC0 Identifiestheprocessorstateandtheaddressspaceofthe
currentbuscycle.(I/O)
Data DataBus31-16 D31-D16 Upper16-bitdatabususedtotransferbyteorworddata.
Usedin16-bitbusmode.(I/O)
DataBus15-0 D15-D0 Lower16-bitdatabususedtotransfer3-byteorlong-word
data.(I/O)
Notusedin16-bitbusmode.
Parity Parity2-0 PRTY2-PRTY0 Paritysignalsforbytewrites/readsfrom/toexternalmemory
module.(I/O)
Parity3/16BM PRTY3/16BM Paritysignalsforbytewrites/readsfrom/toexternalmemory
moduleordefines16-bitbusmode.(I/O)
ParityError PERR Indicatesaparityerrorduringareadcycle.(O)
Memory
Controller ChipSelect
RowAddressSelect7
InterruptAcknowledge7
CS
RAS7
IACK7
EnablesperipheralsorDRAMsatprogrammedaddresses
(O)orinterruptlevel7acknowledgeline.(O)
ChipSelect6-0
RowAddressSelect6-0 CS6-CS0
RAS6-RAS0 EnablesperipheralsorDRAMsatprogrammedaddresses.
(O)
ColumnAddressSelect
3-0/Interrupt
Acknowledge1,2,3,6
CAS3-CAS0/
IACK6,3,2,1 DRAMcolumnaddressselectorinterruptlevelacknowledge
lines.(O)
BusArbitration BusRequest BR Indicatesthatanexternaldevicerequiresbusmastership.(I)
BusGrant BG Indicatesthatthecurrentbuscycleiscompleteandthe
QUICChasrelinquishedthebus.(O)
BusGrandAcknowledge BGACK Indicatesthatanexternaldevicehasassumedbus
mastership.(I)
Read-Modify-WriteCycle
InitialConfiguration0 RMC
CONFIG0 Identifiesthebuscycleaspartofanindivisible
read-modify-writeoperation(I/O)orinitialQUICC
configurationselect.(I)
BusClearOut/Initial
Configuration1/Row
AddressSelect2
Double-Drive
BCLRO/CONFIG1/
RAS2DD Indicatesthataninternaldevicerequirestheexternalbus
(Open-DrainO)orinitialQUICCconfigurationselect(I)or
rowaddressselect2double-driveoutput.(O)
7
TS68EN360
2113A–HIREL–03/02
BusControl DataandSize
Acknowledge DSACK1-DSACK0 Providesasynchronousdatatransferacknowledgementand
dynamicbussizing(open-drainI/Obutdrivenhighbefore
three-stated).
AddressStrobe AS Indicatesthatavalidaddressisontheaddressbus.(I/O)
DataStrobe DS Duringareadcycle,DSindicatesthatanexternaldevice
shouldplacevaliddataonthedatabus.Duringawritecycle,
DSindicatesthatvaliddataisonthedatabus.(I/O)
Size SIZ1-SIZ0 Indicatesthenumberofbytesremainingtobetransferredfor
thiscycle.(I/O)
Read/Write R/W Indicatesthedirectionofdatatransferonthebus.(I/O)
OutputEnableAddress
Multiplex OE/AMUX Activeduringareadcycleindicatesthatanexternaldevice
shouldplacevaliddataonthedatabus(O)orprovidesa
strobeforexternaladdressmultiplexinginDRAMaccesses
ifinternalmultiplexingisnotused.(O)
Interrupt
Control InterruptRequest
Level 7-1 IRQ7-IRQ1 ProvidesexternalinterruptrequeststotheCPU32+at
prioritylevels7-1.(I)
Autovector/Interrupt
Acknowledge5 AVEC/IACK5 Autovectorrequestduringaninterruptacknowledgecycle
(open-drainI/O)orinterruptlevel5acknowledgeline.(O)
System
Control SoftReset RESETS Softsystemreset.(open-drainI/O)
HardReset RESETH Hardsystemreset.(open-drainI/O)
Halt HALT Suspendsexternalbusactivity.(open-drainI/O)
BusError BERR Indicatesanerroneousbusoperationisbeingattempted.
(open-drainI/O)
ClockandTest SystemClockOut1 CLKO1 Internalsystemclockoutput1.(O)
SystemClockOut2 CLKO2 Internalsystemclockoutput2-normally2xCLKO1.(O)
CrystalOscillator EXTAL,XTAL Connectionsforanexternalcrystaltotheinternaloscillator
circuit.EXTAL(I),XTAL(O).
ExternalFilterCapacitor XFC Connectionpinforanexternalcapacitortofilterthecircuitof
thePLL.(I)
ClockModeSelect1-0 MODCK1-MODCK0 Selectsthesourceoftheinternalsystemclock.(I)THESE
PINSSHOULDNOTBESETTO00
InstructionFetch/
DevelopmentSerialInput IFETCH/DSI IndicateswhentheCPU32+isperforminganinstruction
wordprefetch(O)orinputtotheCPU32+backgrounddebug
mode.(I)
InstructionPipe0/
DevelopmentSerial
Output
IPIPE0/DSO Usedtotrackmovementofwordsthroughtheinstruction
pipeline(O)oroutputfromtheCPU32+backgrounddebug
mode.(O)
InstructionPipe1/Row
AddressSelect1
Double-Drive
IPIPE1/RAS1DD Usedtotrackmovementofwordsthroughtheinstruction
pipeline(O),orarowaddressselect1“double-drive”output
(O).
Breakpoint/Development
SerialClock BKPT/DSCLK SignalsahardwarebreakpointtotheQUICC(open-drain
I/O),orclocksignalforCPU32+backgrounddebugmode(I).
Freeze/Initial
Configuration2 FREEZE/CONFIG2 IndicatesthattheCPU32+hasacknowledgedabreakpoint
(O),orinitialQUICCconfigurationselect(I).
Table1.SystemBusSignalIndex(NormalOperation)(Continued)
Group SignalName Mnemonic Function
8TS68EN360 2113A–HIREL–03/02
Note: 1. Idenotesinput,OdenotesoutputandI/Oisinput/output.
ClockandTest
(Cont’d) Three-State TRIS Usedtothree-stateallpinsifQUICCisconfiguredasa
master.AlwaysSampledexceptduringsystemreset.(I)
TestClock TCK ProvidesaclockforScantestlogic.(I)
TestModeSelect TMS Controlstestmodeoperations.(I)
TestDataIn TDI Serialtestinstructionsandtestdatasignal.(I)
TestDataOut TDO Serialtestinstructionsandtestdatasignal.(O)
TestReset TRST Providesanasynchronousresettothetestcontroller.(I)
Power ClockSynthesizerPower VCCSYN PowersupplytothePLLoftheclocksynthesizer.
ClockSynthesizerGround GNDSYN GroundsupplytothePLLoftheclocksynthesizer.
ClockOutPower VCCCLK Powersupplytoclockoutpins.
ClockOutGround GNDCLK Groundsupplytoclockoutpins.
SpecialGround1 GNDS1 SpecialgroundforfastACtimingoncertainsystembus
signals.
SpecialGround2 GNDS2 SpecialgroundforfastACtimingoncertainsystembus
signals.
SystemPowerSupplyand
Return VCC,GND PowersupplyandreturntotheQUICC.
-- NoConnect NC4-NC1 Fourno-connectpins.
Table1.SystemBusSignalIndex(NormalOperation)(Continued)
Group SignalName Mnemonic Function
9
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Table2.PeripheralsSignalIndex
Group SignalName Mnemonic Function
SCC ReceiveData RXD4-RXD1 SerialreceivedatainputtotheSCCs.(I)
TransmitData TXD4-TXD1 SerialtransmitdataoutputfromtheSCCs.(O)
RequesttoSend RTS4-RTS1 RequesttosendoutputsindicatethattheSCCisreadyto
transmitdata.(O)
CleartoSend CTS4-CTS1 CleartosendinputsindicatetotheSCCthatdata
transmissionmaybegin.(I)
CarrierDetect CD4-CD1 CarrierdetectinputsindicatethattheSCCshouldbegin
receptionofdata.(I)
ReceiveStart RSTRT1 ThisoutputfromSCC1identifiesthestartofareceiveframe.
CanbeusedbyanEthernetCAMtoperformaddress
matching.(O)
ReceiveReject RRJCT1 ThisinputtoSCC1allowsaCAMtorejectthecurrent
Ethernetframeafteritdeterminestheframeaddressdidnot
match.(I)
Clocks CLK8-CLK1 InputclockstotheSCCs,SCMs,SI,andthebaudrate
generators.(I)
IDMA DMARequest DREQ2-DREQ1 Arequest(input)toanIDMAchanneltostartanIDMA
transfer.(I)
DMAAcknowledge DACK2-DACK1 Anacknowledgement(output)bytheIDMAthatanIDMA
transferis
inprogress.(O)
DMADone DONE2-DONE1 AbidirectionalsignalthatindicatesthelastIDMAtransferin
ablockofdata.(I/O)
TIMER TimerGate TGATE2-TGATE1 Aninputtoatimerthatenables/disablesthecounting
function.(I)
TimerInput TIN4-TIN1 Timereferenceinputtothetimerthatallowsittofunctionas
acounter.(I)
TimerOutput TOUT4-TOUT1 Outputwaveform(pulseortoggle)fromthetimerasaresult
ofareferencevaluebeingreached.(O)
SPI SPIMasterInSlaveOut SPIMISO SerialdatainputtotheSPImaster(I);serialdataoutputfrom
anSPIslave.(O)
SPIMasterOutSlaveIn SPIMOSI SerialdataoutputfromtheSPImaster(O);serialdatainput
toanSPIslave.(I)
SPIClock SPICLK OutputclockfromtheSPImaster(O);inputclocktotheSPI
slave.(I)
SPISelect SPISEL SPIslaveselectinput.(I)
SMC SMCReceiveData SMRXD2-SMRXD1 SerialdatainputtotheSMCs.(I)
SMCTransmitData SMTXD2-SMTXD1 SerialdataoutputfromtheSMCs.(O)
SMCSync SMSYN2-SMSYN1 SMCsynchronizationsignal.(I)
10 TS68EN360 2113A–HIREL–03/02
Scope ThisdrawingdescribesthespecificrequirementsforthemicrocontrollerTS68EN360-
25MHzand33MHzincompliancewithMIL-STD-883classBorAtmelstandard
screening.
Applicable
Documents
MIL-STD-883 1. MIL-STD-883:testmethodsandproceduresforelectronics.
2. MIL-PRF-38535:generalspecificationsformicrocircuits.
3. DESC5962-SMD-97607
SI SIReceiveData L1RXDA,L1RXDB Serialinputtothetimedivisionmultiplexed(TDM)channelA
orchannelB.
SITransmitData L1TXDA,L1TXDB SerialoutputfromtheTDMchannelAorchannelB.
SIReceiveClock L1RCLKA,L1RCLKB InputreceiveclocktoTDMchannelAorchannelB.
SITransmitClock L1TCLKA,L1TCLKB InputtransmitclocktoTDMchannelAorchannelB.
SITransmitSyncSignals L1TSYNCA,
L1TSYNCB InputtransmitdatasyncsignaltoTDMchannelAor
channel B.
SIReceiveSyncSignals L1RSYNCA,
L1RSYNCB InputreceivedatasyncsignaltoTDMchannelAor
channel B.
IDLInterfaceRequest L1RQA,L1RQB IDLinterfacerequesttotransmitontheDchannel.Output
fromtheSI.
SIOutputClock L1CLKOA,L1CLKOB Outputserialdatarateclock.Canoutputadatarateclock
whentheinputclockis2xthedatarate.
SIDataStrobes L1ST4-L1ST1 Serialdatastrobeoutputscanbeusedtogateclocksto
externaldevicesthatdonothaveabuilt-intimeslotassigner
(TSA).
BRG BaudRateGenerator
Out 4-1 BRGO4-BRGO1 Baudrategeneratoroutputclockallowsbaudrategenerator
tobeusedexternally.
BRGInputClock CLK2,CLK6 BaudrategeneratorinputclockfromwhichBRGwillderive
thebaudrates.
PIP PortB15-0 PB15-BP0 PIPDataI/OPins.
StrobeOut STRBO ThisinputcausesthePIPoutputdatatobeplacedonthe
PIPdatapins.
StrobeIn STRBI ThisinputcausesdataonthePIPdatapinstobelatchedby
thePIPasinputdata.
SDMA SDMAAcknowledge2-1 SDACK2-SDACK1 SDMAoutputsignalsusedinRISCreceivertomarkfieldsin
theEthernetreceiveframe.
Table2.PeripheralsSignalIndex(Continued)
Group SignalName Mnemonic Function
11
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Requirements
General Thismicrocircuitsareinaccordancewiththeapplicabledocumentandasspecified
herein.
DesignandConstruction
TerminalConnections Dependingonthepackage,theterminalconnectionsshallbeasshowninFigure2and
Figure3.
LeadMaterialandFinish LeadmaterialandfinishshallbeasspecifiedinMIL-STD-883(seeenclosed“Ordering
Information”onpage79).
Package Themacrocircuitsarepackagedinhermeticallysealedceramicpackageswhichare
conformtocaseoutlinesofMIL-STD-1835orasfollow:
• PGAbutsee“241-pin–PGA”onpage77
•CERQUAD
Theprecisecaseoutlinesaredescribedattheendofthespecification(“Package
MechanicalData”onpage77)andintoMIL-STD-1835.
Electrical
Characteristics
Note: Thisdevicecontainsprotectivecircuitryagainstdamageduetohighstaticvoltagesorelectricalfields;however,itisadvised
thatnormalprecautionsbetakentoavoidapplicationofanyvoltageshigherthanmaximum-ratedvoltagestothishigh-imped-
ancecircuit.Reliabilityofoperationisenhancedifunusedinputsaretiedtoanappropriatelogicvoltagelevel(e.g.,eitherGND
orVDD).
Notes: 1. Permanentdamagecanoccurifmaximumratingsareexceeded.Exposuretovoltagesorcurrentsinexcessofrecom-
mendedvaluesaffectsdevicereliability.Devicemodulesmaynotoperatenormallywhilebeingexposedtoelectrical
extremes.
2. Althoughsectionsofthedevicecontaincircuitrytoprotectagainstdamagefromhighstaticvoltagesorelectricalfields,take
normalprecautionstoavoidexposuretovoltageshigherthanmaximum-ratedvoltages.
3. ThesupplyvoltageVCCmuststartandrestartfrom0.0V;otherwise,the360willnotcomeoutofresetproperly.Unlessother-
wisestated,allvoltagesarereferencedtothereferenceterminal.
Table3.AbsoluteMaximumRatings
Rating Symbol Value Unit
SupplyVoltage(1)(2) VCC -0.3to+6.5 V
InputVoltage(1)(2) VIN -0.3to+6.5 V
StorageTemperatureRange TSTG -55to+150 °C
12 TS68EN360 2113A–HIREL–03/02
TJ=TA+(PD·θJA)
PD=(VDD· IDD)+PI/O
WherePI/Oisthepowerdissipationonpins.
PowerConsiderations Theaveragechip-junctiontemperature,TJ,in°Ccanbeobtainedfrom:
TJ=TA÷(PD · ΘJA)(1)
where:
TA=AmbientTemperature,°C
ΘJA=PackageThermalResistance,
Junction-to-Ambient,C/W
PD=PINT+PI/O
PINT=ICC·VCC,Watts-chipInternalPower
PI/O=PowerDissipationonInputandOutputPins-UserDetermined
Formostapplications,PI/O<0.3·PINTandcanbeneglected.
AnapproximaterelationshipbetweenPDandTJ(ifPI/Oisneglected)is:
PD=K÷(TJ+273°C) (2)
SolvingEquations(1)and(2)forKgives:
K=PD·(TA+273°C)+ΘJA·PD2(3)
whereKisaconstantpertainingtotheparticularpart.KcanbedeterminedfromEqua-
tion(3)bymeasuringPD(atthermalequilibrium)foraknowTA.UsingthisvalueofK,
thevaluesofPDandTJcanbeobtainedbysolvingEquations(1)and(2)iterativelyfor
anyvalueofTA.
Table4.RecommendedConditionsOfUse
Unlessotherwisestated,allvoltagesarereferencedtothereferenceterminal.
Symbol Parameter Min. Typ. Max. Unit
VCC SupplyVoltageRange +4.75 +5.25 V
VIL LogicLowLevelInputVoltageRange GND +0.8 V
VIH LogicHighLevelInputVoltageRange +2.0 VCC V
Tcase OperatingTemperature -55 +125 °C
VOH HighLevelOutputVoltage +2.4 V
fsys SystemFrequency (For25MHzversion) 25 MHz
(For33MHzversion) 33 MHz
Table5.ThermalCharacteristics
Symbol Parameter Value Unit
θJC ThermalResistance-JunctiontoCase 240-pinCerquad 2 °C/W
241-pinPGA 7
θJA ThermalResistance-JunctiontoAmbient 240-pinCerquad 27.4 °C/W
241-pinPGA 22.8
13
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Mechanicaland
Environment Themicrocircuitsshallmeetallmechanicalenvironmentalrequirementsofeither
MIL-STD-883forclassBdevicesorforAtmelstandardscreening.
Marking Thedocumentwherearedefinedthemarkingareidentifiedintherelatedreferencedoc-
uments.Eachmicrocircuitarelegibleandpermanentlymarkedwiththefollowing
informationasminimum:
• Atmellogo
• Manufacturer’spartnumber
• ClassBidentification
• Date-codeofinspectionlot
• ESDidentifierifavailable
• Countryofmanufacturing
QualityConformance
Inspection
DESC/MIL-STD-883 IsinaccordancewithMIL-M-38535andmethod5005ofMIL-STD-883.GroupAandB
inspectionsareperformedoneachproductionlot.GroupCandDinspectionsareper-
formedonaperiodicalbasis.
Electrical
Characteristics
GeneralRequirements Allstaticanddynamicelectricalcharacteristicsspecifiedforinspectionpurposesandthe
relevantmeasurementconditionsaregivenbelow:
• Staticelectricalcharacteristicsfortheelectricalvariants
• DynamicelectricalcharacteristicsforTS68EN360
(25MHz,33MHz)
Forstaticcharacteristics,testmethodsrefertoIEC748-2methodnumber,where
existing.
Fordynamiccharacteristics,testmethodsrefertoclause“StaticCharacteristics”on
page14ofthisspecification.
14 TS68EN360 2113A–HIREL–03/02
DynamicCharacteristics TheACspecificationspresentedconsistofoutputdelays,inputsetupandholdtimes,
andsignalskewtimes.Allsignalsarespecifiedrelativetoanappropriateedgeofthe
clockandpossiblytooneormoreothersignals.
ThemeasurementoftheACspecificationsisdefinedbythewaveformsshowninFigure
5.TotesttheparametersguaranteedbyAtmelinputsmustbedriventothevoltagelev-
elsspecifiedinthefigure.Outputsarespecifiedwithminimumand/ormaximumlimits,
asappropriate,andaremeasuredasshown.Inputsarespecifiedwithminimumsetup
andholdtimesandaremeasuredasshown.Finally,themeasurementforsignal-to-sig-
nalspecificationsareshown.
NotethatthetestinglevelsusedtoverifyconformancetotheACspecificationsdonot
affecttheguaranteedDCoperationofthedeviceasspecifiedintheDCelectrical
characteristics.
StaticCharacteristics
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary.(Seenumberednotes).
Characteristic Symbol Min. Max. Unit
InputHighVoltage(exceptEXTAL) VIH 2.0 VCC V
InputLowVoltage(5VPart) VIL GND 0.8 V
InputLowVoltage(PartOnly;PA8-15,PB1,PC5,PC7,TCK) VIL GND 0.5 V
InputLowVoltage(PartOnly;AllOtherPins) VIL GND 0.8 V
EXTALInputHighVoltage VIHC 0.8*(VCC)V
CC+0.3 V
Undershoot ---0.8V
InputLeakageCurrent(AllInputOnlyPinsexceptforTMS,TDIandTRST)
Vin =0/5V Iin -2.5 2.5 µA
Hi-Z(Off-State)LeakageCurrent(AllNoncrystalOutputsandI/OPinsexcept
TMS,TDIandTRST)Vin=0/5V IOZ -2.5 -2.5 µA
SignalLowInputCurrentVIL=0.8V(TMS,TDIandTRSTPinsOnly)
SignalHighInputCurrentVIH=2.0V(TMS,TDIandTRSTPinsOnly) IL
IH
-0.5
-0.5 0.5
0.5 mA
mA
OutputHighVoltage
IOH=-0.8mA,VCC=4.75V
AIINoncrystalOutputsExceptOpenDrainPins VOH 2.4 - V
OutputLowVoltage
IOL=2.0mA,CLKO1-2,FREEZE,IPIPE0-1,IFETCH,BKPTO
IOL=3.2mA,A31-A0,D31-D0,FC3-0,SIZ0-1,PA0,2,4,6,8-15,PB0-5,
PB8-17,PC0-11,TDO,PERR,PRTY0-3,IOUT0-2,AVECO,AS,CAS3-0,
BLCRO,RAS0-7
IOL=5.3mA,DSACK0-1,R/W,DS,OE,RMC,BG,BGACK,BERR
IOL=7mA,TXD1-4
IOL=8.9mA,PB6,PB7,HALT,RESET,BR(Output)
VOL -
0.5
0.5
0.5
0.5
0.5
V
InputCapacitance
AIII/OPins Cin - 20 pF
LoadCapacitance(exceptCLKO1-2) CL- 100 pF
LoadCapacitance(CLKO1-2) CLc50 pF
Power VCC 4.75 5.25 V
15
TS68EN360
2113A–HIREL–03/02
Figure5.DriveLevelsandTestPointsForACSpecifications
Notes: 1. Thisoutputtimingisapplicabletoallparametersspecifiedrelativetotherisingedgeoftheclock.
2. Thisoutputtimingisapplicabletoallparametersspecifiedrelativetothefallingedgeoftheclock.
3. Thisinputtimingisapplicabletoallparametersspecifiedrelativetotherisingedgeoftheclock.
4. Thisinputtimingisapplicabletoallparametersspecifiedrelativetothefallingedgeoftheclock.
5. Thistimingisapplicabletoallparametersspecifiedrelativetotheassertion/negationofanothersignal.
Legend:
a)Maximumoutputdelayspecification.
b)Minimumoutputholdtime.
c)Minimuminputsetuptimespecification.
d)Minimuminputholdtimespecification.
e)Signalvalidtosignalvalidspecification(maximumorminimum).
f)Signalvalidtosignalinvalidspecification(maximumorminimum).
0.8V
2.0V
B
2.0V
0.8V
VALID
OUTPUT nVALID
OUTPUT n + 1
2.0V
0.8V
2.0V
0.8V
2.0V
0.8V
VALID
OUTPUT nVALID
OUTPUT n+1
2.0V
0.8V
B
A
VALID
INPUT
2.0V
0.8V
2.0V
0.8V
D
VALID
INPUT
2.0V
0.8V
2.0V
0.8V
D
DRIVE
TO 0.5V
DRIVE
TO 2.4V
2.0V
0.8V
2.0V
0.8V
F
CLKOUT
OUTPUTS(1)
OUTPUTS(2)
INPUTS(3)
INPUTS(4)
ALL SIGNALS(5)
E
A
C
C
16 TS68EN360 2113A–HIREL–03/02
ACPowerDissipation
Notes: 1. RevAmaskisC63T
2. RevBmasksareC69TandF35G
3. CurrentRevCmasksareE63C,E68CandF15W
4. EXTALfrequencyis32kHz
AllmeasurementsweretakenwithonlyCLKO1enabled,VCC=5.0V,VIL=0VandVIH=VCC
Notes: 1. RevAmaskisC63T
2. RevBmasksareC69TandF35G
3. CurrentRevCmasksareE63C,E68CandF15W
Table6.TypicalCurrentDrain
ModeofOperation Symbol SystemClock
Frequency BRGCLKClock
Frequency SyncCLKClock
Frequency Typ Unit
Normalmode(RevA(1)andRevB(2))I
DD 25MHz 25MHz 25MHz 250 mA
NormalMode(RevC(3)andNewer) IDD 25MHz 25MHz 25MHz 237 mA
NormalMode IDD 33MHz 33MHz 33MHz 327 mA
LowPowerMode IDDSB Divideby2
12.5MHz Divideby16
1.56MHz Divideby2
12.5MHz 150 mA
LowPowerMode IDDSB Divideby4
6.25MHz Divideby16
1.56MHz Divideby4
6.25MHz 85 mA
LowPowerMode IDDSB Divideby16
1.56MHz Divideby16
1.56MHz Divideby4
6.25MHz 35 mA
LowPowerMode IDDSB Divideby256
97.6kHz Divideby16
1.56MHz Divideby4
6.25MHz 20 mA
LowPowerMode IDDSB Divideby256
97.6kHz Divideby64
390kHz Divideby64
390kHz 13 mA
LowPowerStopVCOOff(4) IDDSP 0.5 mA
PLLSupplyCurrent
PLLDisabled
PLLEnabled IDDPD
IDDPE
TBD
TBD
Table7.MaximumPowerDissipation
SystemFrequency VCC MaxPDUnit Mask
25MHz 5.25V 1.80 W REVA(1)andREVB(2)
25MHz 5.25V 1.45 W REVC(3)andNewer
25MHz 3.6V 0.65 W REVC(3)andNewer
33MHz 5.25V 2.00 W REVC(3)andNewer
17
TS68EN360
2113A–HIREL–03/02
Note: 1. NotethattheminimumVCOfrequencyandthePLLdefaultvaluesputsomerestrictionsontheminimumsystemfrequency.
Thefollowingcalculationshouldbeusedtodeterminetheactualvalueforspecifications5B,5Cand5D.
5B: 25MHz ±(0.9ns+0.25x(risetime))(1.4ns@rise=2ns;1.9ns@rise=4ns)
33MHz ±(0.5ns+0.25x(risetime))(1ns@rise=2ns;1.5ns@rise=4ns)
5C: 25/33MHz ±(2ns+0.25x(risetime))(2.5ns@rise=2ns;3ns@rise=4ns)
5D: 25MHz ±(3ns+0.5x(risetime))(4ns@rise=2ns;5ns@rise=4ns)
33MHz ±(2.5ns+0.5x(risetime))(3.5ns@rise=2ns;4.5ns@rise=4ns)
ACElectricalSpecificationsControlTiming
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary(SeeFigure6).
Number Characteristic Symbol
25MHz 33.34MHz
UnitMin Max Min Max
SystemFrequency fsys dc(1) 25.00 33.34 MHz
CrystalFrequency fXTAL 25 6000 25 6000 kHz
On-ChipVCOSystemFrequency fsys 20 50 20 67 MHz
Start-upTime
Withexternalclock(oscillatordisabled)orafter
changingthemultiplicationfactorMF tpll 2500 clks
CLKO1-2stability ∆CLK TBD TBD %
1 CLKO1Period tcyc 40 - 30 - ns
1A EXTALDutyCycle,MF tdcyc 40 60 40 60 %
1C ExternalClockInputPeriod tEXTcyc 40 - 30 - ns
2,3 CLKO1PulseWidth(Measuredat1.5V) tCW1 19 - 14 - ns
2A,3A CLKO2PulseWidth(Measuredat1.5V) tCW2 9.5 - 7 - ns
4,5 CLKO1RiseandFallTimes(Fulldrive) tCrf1 -2-2ns
4A,5A CLKO2RiseandFallTimes(Fulldrive) tCrf2 -2-1.6ns
5B EXTALtoCLKO1Skew-PLLenabled(MF<5) tEXTP1 aans
5C EXTALtoCLKO2Skew-PLLenabled(MF<5) tEXTP2 aans
5D CLKO1toCLKO2Skew AtmelKW aans
18 TS68EN360 2113A–HIREL–03/02
Figure6.ClockTiming
Note: 1. MF-multiplicationfactor.
Examples:
Notes: 1. MODCK1pin=0,MF=1⇒CXFC=400pF
2. MODCK1pin=1,crystalis32.768kHz(or4.192MHz),initialMF=401,initialfrequency=13.14MHz,lateronMFis
changedto762tosupportafrequencyof25MHz.MinimumCXFCis:762x380=289nF,MaximumCXFCis:401x970=390
nF.TherecommendedCXFCfor25MHzis:762x540=414nF.289nF<CXFC<390nFandcloserto414nF.Theproper
availablevalueforCXFCis390nF.
3. MODCK1pin=1,crystalis32.768kHz(or4.192MHz),initialMF=401,initialfrequency=13.14MHz,lateronMFis
changedto1017tosupportafrequencyof33.34MHz.MinimumCXFCis:1017x380=386nF,MaximumCXFCis:401x
970=390nF⇒386nF<CXFC<390nF.TheproperavailablevalueforCXFCis390nF.
4. Inordertogethigherrange,highercrystalfrequencycanbeused(i.e.50kHz),inthiscase:
MinimumCXFCis:667x380=253nF,MaximumCXFCis:401x970=390nF⇒386nF<CXFC<390nF.
EXTAL
CLKO1
CLKO2
(INPUT)
(OUTPUT)
(OUTPUT)
5
4
1
1C
23
2A 3A
4A 5A
5C 5B
5D
VOLTAGE MIDPOINT
1A
ExternalCapacitorForPLL
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary.
Characteristic Symbol Min Max Unit
PLLExternalCapacitor(XFCtoVCCSYN) cXFC
MF<5(RecommendedvalueMFx400pF)(1) MFx340 MFx480 pF
MF>4(RecommendedvalueMFx540pF)(1) MFx380 MFx970 pF
19
TS68EN360
2113A–HIREL–03/02
BusOperationACTimingSpecifications
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure7toFigure23).
Number Characteristic Symbol
25MHz 33.34MHz
UnitMin Max Min Max
6 CLKO1HightoAddress,FC,SIZ,RMCValid tCHAV 015012ns
6A CLKO1HightoAddressValid(GAMX=1) tCHAV 020015ns
7CLKO1HightoAddress,Data,FC,SIZ,RMCHigh
Impedance tCHAZx 040030ns
8CLKO1HightoAddress,Data,FC,SIZ,RMC
Invalid tCHAZn -2 - -2 - ns
9CLKO1LowtoAS,DS,OE,WE,IFETCH,IPIPE,
IACKxAsserted tCLSA 320315ns
9(10) CLKO1LowtoCSx/RASxAsserted tCLSA 416412ns
9B(11) CLKO1HightoCSx/RASxAsserted tCHCA 416412ns
9A(2)(10) AStoDSorCSx/RASxorOEAsserted(Read) tSTSA -6 6 -5.625 5.625 ns
9C(2)(11) AStoCSx/RASxAsserted tSTCA 1426921ns
11(10) Address,FC,SIZ,RMC,validtoAS,CSx/RASx,
OE,WE,(andDSRead)Asserted tAVSA 10 - 8 - ns
11A(11) Address,FC,SIZ,RMC,ValidtoCSx/RASx
Asserted tAVCA 30 - 22.5 - ns
12 CLKO1LowtoAS,DS,OE,WE,IFETCH,IPIPE,
IACKxNegated tCLSN 320315ns
12(16) CLKO1LowtoCSx/RASxNegated tCLSN 416412ns
12A(13)(16) CLKO1HightoCSx/RASxNegated tCHCN 416412ns
12B CSnegatetoWEnegate(CSNTQ=1) AtmelTW 15 - 12 - ns
13(12) AS,DS,CSx,OE,WE,IACKxNegatedtoAddress,
FC,SIZInvalid(AddressHold) tSNAI 10 - 7.5 - ns
13A(13) CSxNegatedtoAddress,FC,SIZ,Invalid(Address
Hold) tCNAI 30 - 22.5 - ns
14(10)(12) AS,CSx,OE,WE(andDSRead)WidthAsserted tSWA 75 - 56.25 - ns
14C(11)(13) CSxWidthAsserted tCWA 35 - 26.25 - ns
14A DSWidthAsserted(Write) tSWAW 35 - 26.25 - ns
14B AS,CSx,OE,WE,IACKx,(andDSRead)Width
Asserted(FastTerminationCycle) tSWDW 35 - 26.25 - ns
14D(13) CSxWidthAsserted(FastTerminationCycle) tCWDW 15 - 10 - ns
15(3)(10)(12) AS,DS,CSx,OE,WEWidthNegated tSN 35 - 26.25 - ns
16 CLKO1HightoAS,DS,R/WHighImpedance tCHSZ - 40 - 30 ns
17(12) AS,DS,CSx,WENegatedtoR/WHigh tSNRN 10 - 7.5 - ns
17A(13) CSxNegatedtoR/WHigh tCNRN 30 - 22.5 - ns
18 CLKO1HightoR/WHigh tCHRH 020015ns
20 TS68EN360 2113A–HIREL–03/02
20 CLKO1HightoR/WLow tCHRL 320315ns
21(10) R/WHightoAS,CSx,OEAsserted tRAAA 10 - 7.5 - ns
21A(11) R/WHightoCSxAsserted tRACA 30 - - ns
22 R/WLowtoDSAsserted(Write) tRASA 47 - 36 - ns
23 CLKO1HightoData-Out tCHDO - 23 - 18 ns
23A CLKO1HightoParityValid tCHPV - 25 - 20 ns
23B ParityValidtoCASLow tPVCL 3-3-ns
24(12) Data-Out,Parity-OutValidtoNegatingEdgeofAS,
CSx,WE,(FastTerminationWrite) tDVASN 10 - 7.5 - ns
25(12) DS,CSX,WENegatedtoData-Out,Parity-Out
Invalid(Data-Out,Parity-OutHold) tSNDOI 10 - 7.5 - ns
25A(13) CSxNegatedtoData-Out,Parity-OutInvalid(Data-
Out,Parity-OutHold) tCNDOI 35 - 25 - ns
26 Data-Out,Parity-OutValidtoDSAsserted(Write) tDVSA 10 - 7.5 - ns
27(15) Data-In,Parity-IntoCLKO1Low(Data-Setup) tDICL 1-1-ns
27B(14) Data-In,Parity-InValidtoCLKO1Low(Data-Setup) tDICL 20 - 15 - ns
27A LateBERR,HALT,BKPTAssertedtoCLKO1Low
(SetupTime) tBELCL 10 - 7.5 - ns
28(18) AS,DSNegatedtoDSACKx,BERR,HALT
Negated tSNDN 050037.5ns
29(4) DS,CSx,OE,NegatedtoData-InParity-InInvalid
(Data-In,Parity-InHold) tSNDI 0-0-ns
29A(4) DS,CSx,OENegatedtoData-InHighImpedance tSHDI - 40 - 30 ns
30(4) CLKO1LowtoData-In,Parity-InInvalid(Fast
TerminationHold) tCLDI 10 - 7.5 - ns
30A(4) CLKO1LowtoData-InHighImpedance tCLDH - 60 - 45 ns
31(5)(15) DSACKxAssertedtoData-in,Parity-InValid tDADI - 32 - 24 ns
31A DSACKxAssertedtoDSACKxValid(Skew) tDADV -10-7.5ns
31B(5)(14) DSACKxAssertedtoData-in,Parity-InValid tDADI - 35 - 26 ns
32 HALTanRESETInputTransitionTime tHRrf - 140 - ns
33 CLKO1HightoBGAsserted tCLBA - 20 - 15 ns
34 CLKO1HightoBGNegated tCLBN - 2022.515 ns
35(6) BRAssertedtoBGAsserted(RMCNotAsserted) tBRAGA 1-1-CLKO1
37 BGACKAssertedtoBGNegated tGAGN 12.512.5CLKO1
39 BGWidthNegated tGH 2-2-CLKO1
39A BGWidthAsserted tGA 1-1-CLKO1
BusOperationACTimingSpecifications(Continued)
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure7toFigure23).
Number Characteristic Symbol
25MHz 33.34MHz
UnitMin Max Min Max
21
TS68EN360
2113A–HIREL–03/02
46 R/WWidthAsserted(WriteorRead) tRWA 100 - 75 - ns
46A R/WWidthAsserted(FastTerminationWriteor
Read) tRWAS 75 - 56 - ns
47A AsynchronousInputSetupTime tAIST 5-4-ns
47B AsynchronousInputHoldTime tAIHT 10 - 7.5 - ns
48(5)(7) DSACKxAssertedtoBERR,HALTAsserted tDABA - 30 - 22.5 ns
53 Data-Out,Parity-OutHoldfromCLKO1High tDOCH 0-0-ns
54 CLKO1HightoDat-Out,Parity-OutHigh
Impedance tCHDH - 20 - 15 ns
55 R/WAssertedtoDataBusImpedanceChange tRADC 25 - 19 - ns
56 RESETPulseWidth(ResetInstruction) tHRPW 512-512-CLKO1
56A RESETPulseWidth(InputfromExternalDevice) tRPWI 20 - 20 - CLKO1
57 BERRNegatedtoHALTNegated(Return) tBNHN 0-0-ns
58 CLKO1HightoBERR,RESETS,RESETHDriven
Low tCHBRL -30 26ns
58A CLKO1LowRESETSDrivenLow(uponReset
Instructionexecutiononly) tCLRL -30 26ns
58B CLKO1HightoBERR,RESETS,RESETH
tri-stated tCLRL - 20 - 15 ns
60 CLKO1HightoBCLROAsserted tCHBCA - 20 - 15 ns
61 CLKO1HightoBCLRONegated tCHBCN - 20 - 15 ns
62(9) BRSynchronousSetupTime tBRSU 5 - 3.75 - ns
63(9) BRSynchronousHoldTime tBRH 10 - 7.5 - ns
64(9) BGACKSynchronousSetupTime tBGSU 5 - 3.75 - ns
65(9) BGACKSynchronousHoldTime tBGH 10 - 7.5 - ns
66 BRLowtoCLKO1RisingEdge(040comp.mode) tBRCH 5-5-ns
70 CLKO1LowtoDataBusDriven(ShowCycle) tSCLDD 030022.5ns
71 DataSetupTimetoCLKO1Low(ShowCycle) tSCLDS 10 - 7.5 - ns
72 DataHoldfromCLKO1Low(ShowCycle) tSCLDH 6 - 3.75 - ns
73 BKPTInputSetupTime tBKST 10 - 7.5 - ns
74 BKPTInputHoldTime tBKHT 6 - 3.75 - ns
75 RESETHLowtoConfig2-0,MOD1-0,B16MValid tMST - 500 - 500 CLKO1
76 Config2-0 tMSH 0-0-ns
77 MOD1-0HoldTime,B16MHoldTime tMSH 10 - 10 - CLKO1
80 DSIInputSetupTime tDSISU 10 - 7.5 - ns
BusOperationACTimingSpecifications(Continued)
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure7toFigure23).
Number Characteristic Symbol
25MHz 33.34MHz
UnitMin Max Min Max
22 TS68EN360 2113A–HIREL–03/02
Notes: 1. AllACtimingisshownwithrespectto0.8Vand2.0Vlevelsunlessotherwisenoted.
2. Thisnumbercanbereducedto5nsifstrobeshaveequalloads.
3. Ifmultiplechipselectsareused,theCSxwidthnegated(#15)appliestothetimefromthenegationofaheavilyloadedchip
selecttotheassertionofalightlyloadedchipselect.
4. HoldtimesarespecifiedwithrespecttoDSorCSxonasynchronousreadsandwithrespecttoCLKO1onfasttermination
reads.Theuserisfreetouseeitherholdtimeforfastterminationreads.
5. Iftheasynchronoussetup(#17)requirementsaresatisfied,theDSACKxlowtodatasetuptime(#31)andDSACKxlowto
BERRlowsetuptime(#48)canbeignored.Thedatamustonlysatisfythedata-intoCLKO1lowsetuptime(#27)forthefol-
lowingclockcycle:BERRmustonlysatisfythelateBERRlowtoCLKO1lowsetuptime(#27A)forthefollowingclockcycle.
6. Toensurecoherencyduringeveryoperandtransfer,BGwillnotbeassertedinresponsetoBRuntilaftercyclesofthecur-
rentoperandtransferarecompleteandRMCisnegated.
7. IntheabsenceofDSACKx,BERRisanasynchronousinputusingtheasynchronoussetuptime(#47).
8. Duringinterruptacknowledgecycles,theprocessormayinsertuptotwowaitstatesbetweenstatesS0andS1.
9. SpecsareforSynchronousArbitrationonly.ASTM=1.
10. CSxspecsareforTRLX=0.
11. CSxspecsareforTRLX=1.
12. CSxspecsareforCSNTQ=0.
13. CSxspecsareforCSNTQ=1;orRASxspecsforDRAMaccesses.
14.SpecsarereadcycleswithparitycheckandPBEE=1.
15.SpecsarereadcycleswithparitycheckandPBEE=0,PAREN=1.
16.RASxspecsareforpagemisscase.
17. SpecificationsonlyapplytoCSx/RASxpins.
18.Specificationappliestononfastterminationcycles.Infastterminationcycles,theBERRsignalmustbenegatedby20ns
afternegationofAS,DS.
81 DSIInputHoldTime tDSIH 6 - 3.75 - ns
82 DSCLCSetupTime tDSCSU 10 - 7.5 - ns
83 DSCLCHoldTime tDSCH 6 - 3.75 - ns
84 DSODelayTime tDSOD -tcyc+2
0-tcyc+2
0ns
85 DSCLKCycle tDSCCYC 2-2-CLKO1
86 CLKO1HightoFreezeAsserted tFRZA 0 35 0 26.25 ns
87 CLKO1HightoFreezeNegated tFRZN 0 35 0 26.25 ns
88 CLKO1HightoIFETCHHighImpedance tIFZ 0 35 0 26.25 ns
89 CLKO1HightoIFETCHValid tIF 0 35 0 26.25 ns
90 CLKO1HightoPERRAsserted tCHPA 020015ns
91 CLKO1HightoPERRNegated tCHPN 020015ns
92 VCCRamp-UpTimeAtPower-OnReset tRMIN 5-5-ns
BusOperationACTimingSpecifications(Continued)
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure7toFigure23).
Number Characteristic Symbol
25MHz 33.34MHz
UnitMin Max Min Max
23
TS68EN360
2113A–HIREL–03/02
Figure7.ReadCycle
Note: Alltimingisshownwithrespectto0.8Vand2.0Vlevels.
DSACK0
R/W
DS
BERR,
FC3-FC0
A31-A0
CLKO1
S0 S2 S4S1 S3 S5
6 8
11
AS
14
16
9
9A
12 13
20
18
46
47A 28
29
29A
D31-D0
27
27A
48
9
47B
47A
SIZ1-SIZ0
DSACK1
IFETCH
IPIPE1,0
ASYNCHRONOUS
INPUTS
HALT
31
BKPT
OE
RMC
CSx
21
12
74
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(INPUT)
(OUTPUT)
(INPUT)
(INPUT)
(I/O)
(I/O)
73
(OUTPUT)
12
31A
15
24 TS68EN360 2113A–HIREL–03/02
Figure8.FastTerminationReadCycle(ParityCheckPAREN=1,PBEE=0)
AS
(OUTPUT)
A31-A0
(OUTPUT)
CLKO1
(OUTPUT)
S0 S4 S0
S1 S5
8
6
9
DS
(OUTPUT)
D31-D0
(INPUT)
12
14B
46A
30
27
30A
R/W
(OUTPUT)
CSx
(OUTPUT)
18
BKPT
(INPUT)
FC3-FC0
(OUTPUT)
SIZ1-SIZ0
(OUTPUT)
OE
(OUTPUT)
PERR
(OUTPUT)
91
90
73 74
CPU CLEARS PERn BIT
S0
25
TS68EN360
2113A–HIREL–03/02
Figure9.ReadCycle(WithParityCheck,PBEE=1)
Note: Alltimingisshownwithrespectto0.8Vand2.0Vlevels.
R/W
(OUTPUT)
DS
(OUTPUT)
AS
(OUTPUT)
A31-A0, FC3-FC0,
SIZ1-SIZ0 (OUTPUT)
11
14
9
9A
12
20
21
46
CSx
(OUTPUIT)
DSACK1
(I/O)
BERR
(INPUT)
D31-D0
(INPUT)
47A
29
27A
48
12
12
9
47A
HALT
(INPUT)
IFETCH
(OUTPUT)
ASYNCHRONOUS
INPUTS
BKPT
(INPUT)
RMC
(OUTPUT)
47B
29A
CLKO1
(OUTPUT)
S0 S2 S4S1 S3 S5
8
18
DSACK0
(I/O)
6
13
OE
(OUTPUT)
16
28
31B
PRTY0-PRTY3
(INPUT)
73 74
27B
31A
IPIPE1,0
(OUTPUT)
15
26 TS68EN360 2113A–HIREL–03/02
Figure10.SRAM:ReadCycle(TRLX=1)
DSACK0
(I/O)
R/W
(OUTPUT)
AS
(OUTPUT)
DS
(OUTPUT)
A31-A0
(OUTPUT)
CLKO1
(OUTPUT)
S0 S1 S2 S3 S5S4
68
20
13
12
28
29
FC3-FC0
(OUTPUT)
SIZ1-SIZ0
(OUTPUT)
29A
27
D31-D0
(INPUT)
47A
DSACK1
(I/O)
RMC
(OUTPUT)
9C
31
31A
11A
CSx
(OUTPUT)
9B
21A
OE
(OUTPUT) 18
46
16
15
27
TS68EN360
2113A–HIREL–03/02
Figure11.CPU32+IACKCycle
Note: UptotwowaitstatesmaybeinsertedbytheprocessorbetweenstatesS0andS1.
DSACK0
(I/O)
R/W
(OUTPUT)
AS
(OUTPUT)
DS
(OUTPUT)
A31-A0
(OUTPUT)
CLKO1
(OUTPUT)
S0 S1 S2 S3 S5S4
68
14
11
20
13
12
9
9A
21
18
46
IACKx
(OUTPUT)
28
31
29
FC3-FC0
(OUTPUT)
29A
27
D31-D0
(INPUT)
47A
31A
DSACK1
(I/O)
0-2 CLOCKS*
A1 A2 A3 A4
16
OE
(OUTPUT)
SIZ1-SIZ0
(OUTPUT)
15
28 TS68EN360 2113A–HIREL–03/02
Figure12.WriteCycle
Note: Alltimingisshownwithrespectto0.8Vand2.0Vlevels.
R/W
(OUTPUT)
AS
(OUTPUT)
DS
(OUTPUT)
A31-A0
(OUTPUT)
CLKO1
(OUTPUT)
S0 S2 S4
S1 S3 S5
68
11
14 15
912 13
22
CSn
(OUTPUT)
9
14A
17
DSACK0
(I/O)
BERR
(INPUT)
D31-D0
(OUTPUT)
47A
28
73
48
HALT
(INPUT)
25
53
55
26
23 54
BKPT
(INPUT)
46
DSACK1
(I/O)
FC3-FC0
(OUTPUT)
SIZ1-SIZ0
(OUTPUT)
WEn
(OUTPUT) 20
74
31A
PRTY3-PRTY0
(OUTPUT)
18
29
TS68EN360
2113A–HIREL–03/02
Figure13.FastTerminationWriteCycle
Figure14.SRAM:FastTerminationWriteCycle(CSNTQ=1)
AS
A31-A0
CLKO1
S0 S1 S0
R/W
DS
S4 S5
D31-D0
WEx
SIZ1-SIZ0
FC3-FC0
CSx
BKPT
PRTY3-PRTY0
(INPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
R/W
8
6
12
914B
20 46A
25
24
23
74
73
18
AS
(OUTPUT)
A31-A0
(OUTPUT)
CLKO1
(OUTPUT)
S0 S1 S0
R/W
DS
(OUTPUT)
S4 S5
D31-D0
WEx
SIZ1-SIZ0
(OUTPUT)
FC3-FC0
(OUTPUT)
CSx
(OUTPUT)
PRTY3-PRTY0
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
23
12A
20
18
25A
8
9
46A
6
14D
30 TS68EN360 2113A–HIREL–03/02
Figure15.SRAM:WriteCycle(TRLX=1,CSNTQ=1,TCYC=0)
Note: Alltimingisshownwithrespectto0.8Vand2.0Vlevels.
Figure16.ASYNCBusArbitration–IDLEBusCase
R/W
(OUTPUT)
AS
(OUTPUT)
DS
(OUTPUT)
A31-A0
(OUTPUT)
CLKO1
(OUTPUT)
S0 S2 S4
S1 S3 S5
9C
CSx
(OUTPUT)
DSACK0
(I/O)
D31-D0
(OUTPUT)
DSACK1
(I/O)
WEx
(OUTPUT)
PRTY0-PRTY3
(OUTPUT)
9B 12A
13A
17A
11A
25A
20
22
46
47A
31A
55
26
23
14C
CLKO1
(OUTPUT)
AS
(OUTPUT)
D31-D0
(OUTPUT)
A31-A0
(OUTPUT)
BR
(INPUT)
BG
(OUTPUT)
BCLRO
(OUTPUT)
47A
37
35
33 34
47A
6160
47A
47A
BGACK
(INPUT)
31
TS68EN360
2113A–HIREL–03/02
Figure17.ASYNCBusArbitration–ActiveBusCase
Figure18.SYNCBusArbitration–IDLEBusCase
CLKO1
(OUTPUT)
A31-A0
(OUTPUT)
R/W
(OUTPUT)
AS
(OUTPUT)
DS
(OUTPUT)
D31-D0
(OUTPUT)
DSACK1
(I/O)
BR
(INPUT)
BG
(OUTPUT)
BGACK
(INPUT)
S0 S1 S2 S3 S4
33
16
7
S5
39A
34
35
37
DSACK0
(I/O)
BCLRO
(OUTPUT)
47A 47A
60
47A
CLKO1
(OUTPUT)
AS
(OUTPUT)
D31-D0
(OUTPUT)
A31-A0
(OUTPUT)
BR
(INPUT)
BG
(OUTPUT)
BGACK
(INPUT)
37
35
33 34
61
60
BCLRO
(OUTPUT)
64
65
63
62
32 TS68EN360 2113A–HIREL–03/02
Figure19.SYNCBusArbitration–ActiveBusCase
Figure20.ConfigurationandClockModeSelectTiming
CLKO1
(OUTPUT)
A31-A0
(OUTPUT)
R/W
(OUTPUT)
AS
(OUTPUT)
DS
(OUTPUT)
D31-D0
(OUTPUT)
DSACK1
(I/O)
BR
(INPUT)
BG
(OUTPUT)
BGACK
(INPUT)
S0 S1 S2 S3 S4
62
33
16
7
S5
39A35
37
DSACK0
(I/O)
S98
BCLRO
(OUTPUT)
34
64
60
RESETH
CONFIG2-CONFIG0,
76
MODCK1-MODCK0,
16BM 75 77
33
TS68EN360
2113A–HIREL–03/02
Figure21.ShowCycle
Figure22.BackgroundDebugModeFREEZETiming
Figure23.BackgroundDebugModeSerialPortTiming
AS
A31-A0
CLKO1
S0 S42 S1S41 S43 S2
S0
8
6
18
20
15
9
12
70 72
71
R/W
DS
D31-D0
BKPT
27A
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(INPUT)
SHOW CYCLE START OF EXTERNAL CYCLE
FREEZE
CLKO1
IFETCH/DSI
86
88
87
89
FREEZE
CLKO1
82 83
80
81
84
85
BKPT/DSCLK
IFETCH
IPIPE0/DSO
DSI
80
34 TS68EN360 2113A–HIREL–03/02
BusOperation-DRAMAccessesACTimingSpecification
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure24toFigure28).
Number Characteristic
25.0MHz 33.34MHz Unit
Min Max Min Max
100 RASxAssertedtoRowAddressInvalid 15 11.25 ns
101 RASxAssertedtocolumnAddressValid 20 15 ns
102 RASxWidthAsserted 75 56.25 ns
103A RASxwidthNegated(BacktobackCycle)Nonpagemode@
WBTQ =0 75 56.25 ns
103B RASxwidthNegated(BacktobackCycle)Pagemode@WBTQ= 0 55 41.25 ns
103C RASxwidthNegated(BacktobackCycle)Nonpagemode@
WBTQ =1 115 86.25 ns
103D RASxwidthNegated(BacktobackCycle)Pagemode@WBTQ= 1 95 69.23 ns
104 RASxAssertedtoCASxAsserted 35 26.25 ns
105 CLKO1LowtoCASxAsserted 3 13 2 10 ns
105A CLKO1HightoCASxAsserted(RefreshCycle) 3 13 2 10 ns
106 CLKO1HightoCASxNegated 3 13 2 10 ns
107 ColumnAddressValidtoCASxAsserted 15 11.25 ns
108 CASxAssertedtoColumnAddressNegated 40 30 ns
109 CASxAssertedtoRASxNegated 35 27 ns
110 CASxWidthAsserted 50 37.5 ns
1111CASxWidthNegated(BacktoBackCycles) 95 71.25 ns
111A CASxWidthNegated(PageMode) 20 15 ns
113 WELowtoCASxAsserted 35 27 ns
114 CASxAssertedtoWENegated 35 27 ns
115 R/WLowtoCASxAsserted(Write) 52.5 40 ns
116 CASxAssertedtoR/WHigh(Write) 55 41.25 ns
117 Data-Out,Parity-OutValidtoCASxAsserted 10 7.5 ns
119 CLKO1HightoAMUXNegated 3 16 2 12 ns
120 CLKO1HightoAMUXAsserted 3 16 2 12 ns
121 AMUXHightoRASxAsserted 15 11.25 ns
122 RASxAssertedtoAMUXLow 15 11.25 ns
123 AMUXLowtoCASxAsserted 15 11.25 ns
124 CASxAssertedtoAMUXHigh 55 41.25 ns
125 RAS/CASxNegatedtoR/Wchange 0 0 ns
35
TS68EN360
2113A–HIREL–03/02
Figure24.DRAM:NormalReadCycle(InternalMux,TRLX=0)
Note: Alltimingisshownwithrespectto0.8Vand2.0Vlevels.
AS
A31-A0
CLKO1
S0 S2 S4S1 S3 S5
8
OE
RASx
PARITY3-PARITY0
CAS3-CAS0
106
109
11
102 103
S0
R/W 18
D31-D0
27
21
29
S2S1 S3 SW SW
105
104
9
6A
6
DSACK1,0
D31ÐD0
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(I/O)
(INPUT)
(INPUT)
(INPUT)
9
110 111
27B
101
100
107
108
12
PBEE = 0
PBEE = 1
36 TS68EN360 2113A–HIREL–03/02
Figure25.DRAM:NormalWriteCycle
Note: Alltimingisshownwithrespectto0.8Vand2.0Vlevels.
R/W
AS
A31-A0
CLKO1
S0 S2 S4
S1 S3 S5
8
912
WEx
DSACK1,0
20
17
D31-D0
RASx
PARITY0-PARITY3
CAS3-CAS0
11
S0
66A
23 53
(OUTPUT)
(I/O)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
108
106
102
105
114
110
113
115 116
117
100
101
107
37
TS68EN360
2113A–HIREL–03/02
Figure26.DRAM:RefreshCycle
Note: Alltimingisshownwithrespectto0.8Vand2.0Vlevels.
Figure27.DRAM:PageMode–Page-Hit
Note: Alltimingisshownwithrespectto0.8Vand2.0Vlevels.
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
A31-A0
CLKO1
RASx
NOT IN PAGE MODE PAGE MODE
RASx
S4 S5 S0 S1
105A
106
12
12
12A
CAS3-CAS0
9
AS
A31-A0
CLKO1
RASx
AMUX
INTERNAL MUX
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
S0 S2 S4S1 S3 S5
8
9
108
100
105
107
106
11
S0 S4S1 S5 S0 S1
107
105
6A
124
122 123
120
121
119
101
6A
111A
INTERNAL MUX
EXTERNAL MUX
CAS3-CAS0
38 TS68EN360 2113A–HIREL–03/02
Figure28.DRAM:PageMode–Page-Miss
Note: Alltimingisshownwithrespectto0.8Vand2.0Vlevels.
AS
A31-A0
CLKO1
RASn
AMUX
INTERNAL MUX
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
S0 S2 S4S1 S3 S5 S0 S1 S2 SWS3 SW
8
105
123
106
11
120 119 120
12A
6A
6A
CAS3-CAS0
9
EXTERNAL MUX
122
39
TS68EN360
2113A–HIREL–03/02
Note: 1. BGremainslowuntileithertheSDMAortheIDMArequeststheexternalbus.
Figure29.TS68040CompanionModeArbitration
Notes: 1. TS68040TransferAttributeSignals=SIZx,TTx,TMx,R/W,LOCK.
2. BGalwaysremainsasserteduntileithertheSDMAortheIDMArequeststheexternalbus.
040BusTypeSlaveModeBusArbitrationACElectricalSpecifications
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary(SeeFigure29).
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
231 Address,TransferAttributesHighImpedancetoClockHigh 7 - 6 - ns
232(1) ClockHightoBGLow - 20 - 15 ns
233 ClockHightoBGHigh 4 20 4 15 ns
234 BBHightoClockHigh(040output) 7 - 6 - ns
235 BBHighImpedancetoClockHigh(040output) 0 - 0 - ns
236 ClockHightoBBLow(360Output) - 20 - 15 ns
237 ClockHightoBBHigh(360Output) - 20 - 15 ns
238 ClockLowtoBBHighImpedance(360output) - 20 - 15 ns
(OUTPUT)
BCLRO
BG
(OUTPUT)
BB
(I/O)
A31-A0
(I/O)
CLKO1
TRANSFER
ATTRIBUTES
(INPUT)
(OUTPUT)
(INPUT)
BCLRI
S0 S1 S2 S3 S4 S5
C2
C1
238
040 BUS MASTER 360 BUS MASTER
60
61
237
234
231
233 232
235
140 141
236
40 TS68EN360 2113A–HIREL–03/02
Notes: 1. Transferattributessignals=SIZx,TTx,TMx,R/WandLOCK.
2. WhenTS68040isaccessingtheinternalregisters,specification258isfromclocklownotclockhigh.
3. TheclockreferenceisEXTAL,notCLK01.TS68040InternalRegistersReadCycles
040BusTypeSlaveModeInternalRead/Write/LackCyclesACElectricalSpecifications
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure30toFigure33)
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
251(1) Address,TransferAttributesValidtoClockLow 15 - 11.25 - ns
252 TSLowtoClockHigh 7 - 6 - ns
253 ClockHightoTSHigh 5 - 3 - ns
254 ClockhightoAddress,TransferAttributesInvalid 0 - 0 - ns
255 Data-In,MBAREValidtoClockHigh(040Write) 0 - 0 - ns
256 ClockHightoData-In,MBAREHoldTime 0 - 0 - ns
257 ClockHightoTA,TBILow(ExternaltoExternal) 4 20 4 15 ns
257 ClockHightoTA,TBILow(ExternaltoInternal) 4 23 4 18 ns
258(2)(3) ClockHightoTA,TBIHigh 420415ns
259 TA,TBIHightoTA,TBIHighImpedance - 15 - 11.25 ns
260 ClockLowtoData-OutValid(040Read) - 20 - 15 ns
262 ClockLowtoData-OutInvalid - 20 - 15 ns
263 ClockLowtoData-OutHighImpedance - 15 - ns
264 ClockHightoAVECOLow - 20 - 15 ns
265 ClockLowtoAVECOHighImpedance - 30 - 23 ns
266 ClockLowtoIACKLow - 30 - 23 ns
267 ClockHightoIACKHigh - 30 - 23 ns
268 ClockLowtoAVECLow - 30 - 23 ns
41
TS68EN360
2113A–HIREL–03/02
Figure30.TS68040InternalRegistersReadCycles
Notes: 1. ThreewaitstatesareinsertedwhenreadingtheSIM,dual-portRAM,andCPM.Fourwaitstatesareinsertedwhenreading
theSIRAM.AdditionalwaitstatesmaybeinsertedwhentheSHEN1-SHEN0=10andoneoftheinternalmastersis
accessinganinternalperipheral.
2. TS68040TransferAttributeSignals=SIZx,TTx,TMx,R/W,LOCK.
Figure31.TS68040InternalRegistersWriteCycles
Notes: 1. Twowaitstatesareinsertedwhenwriting.Threewaitstatesareinsertedwhenwritingtothedual-portRAMandCPM.Four
waitstatesareinsertedwhenwritingtotheSIRAM.AdditionalwaitstatesmaybeinsertedwhentheSHEN1-SHEN0=10
andoneoftheinternalmastersisaccessinganinternalperipheral.
2. TS68040TransferAttributeSignals=SIZx,TTx,TMx,R/W,LOCK.
CLKO1
TS
(INPUT)
A31-A0
(INPUT)
TRANSFER
ATTRIBUTES
(INPUT)
C1 C2 CW CW
TA
(OUTPUT)
D31-D0
(040 WRITE)
TBI
(OUTPUT)
3Ð4 CLOCKS
(OUTPUT)
252 253
251
254
263
258
257
CW CW
260
C1
259
(INPUT)
CLKO1
TS
A31-A0
TRANSFER
ATTRIBUTES
(INPUT)
TA
D31-D0
(040 WRITE)
MBARE
TBI
2Ñ4 CLOCKS
(OUTPUT)
(INPUT)
252 253
251
255
255
254
258
257
C1 C2 CW CW CW C1
(INPUT)
(INPUT)
(INPUT)
(OUTPUT)
(OUTPUT)
256
256
259
42 TS68EN360 2113A–HIREL–03/02
Figure32.TS68040IACKCycles(VectorDriven)
Notes: 1. TS68040TransferAttributeSignals=SIZx,TTx,TMx,R/W,LOCK.
2. Uptotwowaitstatesmaybeinsertedforinternalperipheral.
Figure33.TS68040IACKCycles(NoVectorDriven)
Note: TS68040TransferAttributeSignals=SIZx,TTx,TMx,R/W,LOCK.
CLKO1
253
TS
A31-A0
(INPUT)
TRANSFER
ATTRIBUTES
C1 C2 CW CW CW
TA
D31-D0
TBI
CW CW
266
IACK7-1
0Ð2 CLOCKS
(OUTPUT)
(OUTPUT)
252
254
263
262
258
257
260
267
251
(INPUT)
(INPUT)
(OUTPUT)
(OUTPUT)
(OUTPUT)
259
CLKO1
253
TS
(INPUT)
A31-A0
(INPUT)
TRANSFER
ATTRIBUTES
(INPUT)
C1 C2 CW CW
TA
(INPUT)
TBI
(OUTPUT)
266
IACK7-1
(OUTPUT)
(OUTPUT)
252
254
290
267
251
289
257 250
AVECO
(OUTPUT)
264 265
43
TS68EN360
2113A–HIREL–03/02
Notes: 1. Transferattributessignals=SIZx,TTx,TMx,R/WandLOCK.
2. TEA/TAshouldnotbeassertedonaDRAMburstaccess,oronthesameclockorbeforeRASx/CSxisasserted.
3. TheclockreferenceisEXTAL,notCLK01.
040BusTypeSRAM/DRAMCyclesACElectricalSpecifications
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure34toFigure38).
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
280 AddressValidtoBADD2-3Valid - 20 - 15 ns
280A BADD2-3ValidtoCASAssertion 15 - 10 - ns
281 AddressInvalidtoBADD2-3Invalid 0 - 0 - ns
282 ClockHightoCSx/RASxLow(TSS40=0) 4 16 4 12 ns
283 ClockHightoCSx/RASxHigh(CSNT40=0) 4 16 4 12 ns
284 ClockHightoBRKLow - 20 - 15 ns
284A ClockLowtoBRKLow - 20 - 15 ns
285 ClockhightoBRKHigh - 20 - 15 ns
286 ClockLowtoCSx/RASxLow(TSS40=1) 4 16 4 12 ns
287 ClockLowtoCSx/RASxHigh(CSNT40=1) 4 16 4 12 ns
288(1) AddressTransferAttributesValidtoClockHigh(TSS40=0) 10 - 10 - ns
289(2) TALowtoClockHigh(ExternalTermination) 11 - 9 - ns
290(2) ClockHightoTAHigh(ExternalTermination) - 20 - 15 ns
291 ClockHightoOELow(ReadCycles) - 20 - 15 ns
292 ClockHightoOEHigh(ReadCycles) - 20 - 15 ns
293 ClockHightoWELow(WriteCycles) - 20 - 15 ns
294 ClockHightoWEHigh(WriteCycles) - 20 - 15 ns
295 ClockHightoCASxLow 4 13 4 10 ns
295A ClockLowtoCASxLow(040BurstReadonly) 4 13 4 10 ns
296(3) ClockHightoCASxHigh 4 13 4 10 ns
297 ClockLowtoAMUXLow 3 16 3 12 ns
298 ClockHightoAMUXHigh 3 16 3 12 ns
299 ClockHightoBADD2-3Valid(040BurstCycles) 4 20 4 15 ns
300(2) TEALowtoClockHigh 11 - - ns
301(2) ClockHightoTEAHigh 2 20 2 15 ns
302 Data,ParityValidtoClockHigh(Data,ParitySetup) 7 - 6 - ns
303 ClockHightoData,ParityInvalid(Data,ParityHold) 7 - 5 - ns
305 CLKO1High(AfterTSLow)toParityValid - 20 - 15 ns
306 CLKO1High(AfterTALow)toParityHi-Z 4 20 15 ns
44 TS68EN360 2113A–HIREL–03/02
Figure34.TS68040SRAMRead/WriteCycles(TSS40=0,CSNT40=0)
Note: TS68040TransferAttributeSignals=SIZx,TTx,TMx,R/W,LOCK.
CLKO1
(OUTPUT)
TS
(INPUT)
A31-A0
(INPUT)
TRANSFER
ATTRIBUTES
(INPUT)
C1 C2
TA
(OUTPUT)
TBI
(OUTPUT)
CSx
(OUTPUT)
BADD3-
BADD2
(OUTPUT)
BKPTO
(OUTPUT)
OE
(OUTPUT)
(READ
CYCLES)
WE
(OUTPUT)
TEA
(INPUT)
288
254
281
253
280
282
258
257
284 285
292
291
293 294
301
252
283
300
259
(WRITE
CYCLES)
45
TS68EN360
2113A–HIREL–03/02
Figure35.TS68040SRAMRead/WriteCycles(TSS40=1,CSNT40=1)
C1 C2
CLKO1
(OUTPUT)
TS
(INPUT)
A31-A0
(INPUT)
TRANSFER
ATTRIBUTES
(INPUT)
BADD3-
BADD2
(OUTPUT)
C3
BKPTO
(OUTPUT)
TEA
(INPUT)
CSn
(OUTPUT)
TA
(INPUT)
251
280
252 253
254
281
289 290
300 301
285
284A
TBI
(OUTPUT)
258
TA
(OUTPUT)
257
286
287
259
46 TS68EN360 2113A–HIREL–03/02
Figure36.ExternalTS68040DRAMCyclesTimingDiagram
C1 C2Cw
CLKO1
(OUTPUT)
WE
(WRITE CYCLE
OUTPUT)
CAS3-
CAS0
AMUX
TS
(INPUT)
A31-A0
(INPUT)
TRANSFER
ATTRIBUTES
(INPUT)
RASx
(OUTPUT)
BADD3-
BADD2
(OUTPUT)
C1
TA
(OUTPUT)
TBI
(OUTPUT)
(OUTPUT)
(OUTPUT)
TEA
(INPUT)
288
280
252 253
282
121
298
122
123
295
254
281
283
296
298
294
293
297
259
258
257
300 301
47
TS68EN360
2113A–HIREL–03/02
Figure37.ExternalTS68040DRAMBurstCyclesTimingDiagram
C1 C2Cw
CLKO1
(OUTPUT)
WE
(WRITE
CYCLE
OUTPUT)
CAS3-
CAS0
AMUX
TS
(INPUT)
A31-A0
(INPUT)
TRANSFER
ATTRIBUTES
(INPUT)
RASx
(OUTPUT)
BADD3-
BADD2
(OUTPUT)
C1
TA
(OUTPUT)
TBI
(OUTPUT)
C2
(OUTPUT)
(OUTPUT)
299299
288
280
252 253
282
295
296
295
296
297
293
257
258
257
258
295A
48 TS68EN360 2113A–HIREL–03/02
Figure38.ExternalTS68040ParityBitCheckingTimingDiagram
(a) Generation Timing Diagram
213
212
D31-D0
(INPUT)
PRTY3-
PRTY0
(OUTPUT)
(b) Checking Timing Diagram
CLKO1
(OUTPUT)
TS
(INPUT)
A31-A0
(INPUT)
TRANSFER
ATTRIBUTES
(INPUT)
C1 C2
TA
(OUTPUT)
BADD3-
BADD2
(OUTPUT)
PERR
(OUTPUT)
CPU Clears PERn Bit
C1
D31-D0,
(INPUT)
302
303
90 91
PRTY3-
PRTY0
(INPUT)
305
306
49
TS68EN360
2113A–HIREL–03/02
Notes: 1. Thesespecificationsareforasynchronousmode.
2. Thesespecificationsareforsynchronousmode.
IDMAACElectricalSpecifications
GND=0VDC,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure39andFigure40).
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
1 CLKO1LowtoDACK,DONEAsserted 3 24 3 18 ns
2 CLKO1LowtoDACK,DONENegated 3 24 3 18 ns
3(1) DREQxAssertedtoASAsserted(forDMABusCycle) 3tcyc+tAIST+tCLSA
4(1) AsynchronousInputSetupTimetoCLKO1Low 12 - 9 - ns
5(1) AsynchronousInputHoldTimefromCLKO1Low 0 - 0 - ns
6AS
toDACKAssertionSkew 0 20 0 15 ns
7DACK
toDONEAssertionSkew -8 8 -6 6 ns
8AS
,DACK,DONEWidthAsserted 70 - 52.5 - ns
8A AS,DACK,DONEWidthAsserted(FastTerminationCycle) 28 - 20.5 - ns
10(1) AsynchronousInputSetupTimetoCLKO1Low 5 - 4 - ns
11(1) AsynchronousInputHoldTimefromCLKO1Low 10 - 7.5 - ns
12(2) DREQInputSetupTimetoCLKO1Low 20 - 15 - ns
13(2) DREQInputHoldTimefromCLKO1Low 5 - 3.75 - ns
14(2) DONEInputSetupTimetoCLKO1Low 20 - 15 - ns
15(2) DONEInputHoldTimeFromCLKO1Low 5 - 3.75 - ns
16(2) DREQAssertedtoASAsserted 2 - 2 - clk
50 TS68EN360 2113A–HIREL–03/02
Figure39.IDMASignalAsynchronousTimingDiagram
Figure40.IDMASignalSynchronousTimingDiagram
AS
CLKO1
DREQ
41
8
2
1
6
3
7
1
DACK
DONE
(OUTPUT)
DONE
(INPUT)
S0 S2 S4 S0 S2 S4
S1 S3 S5 S1 S3 S5
CPU_CYCLE
(IDMA REQUEST) IDMA_CYCLE
10
5
11
(OUTPUT)
(INPUT)
(OUTPUT)
(OUTPUT)
AS
CLKO1
DREQ
12 1
8
21
6
16
7
1
DACK
DONE
(OUTPUT)
DONE
(INPUT)
S0 S2 S4 S0 S2 S4
S1 S3 S5 S1 S3 S5
CPU_CYCLE
(IDMA REQUEST) IDMA_CYCLE
14
13
15
(OUTPUT)
(INPUT)
(OUTPUT)
(OUTPUT)
51
TS68EN360
2113A–HIREL–03/02
Note: 1. t3=spec.3on“ACElectricalSpecificationsControlTiming”onpage17.
Figure41.PIPRx(InterlockMode)
PIP/PIOElectricalSpecifications
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure41toFigure45).
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
21 Data-InSetupTimetoSTBILow 0 - 0 - ns
22 Data-InHoldTimetoSTBIHigh 2.5-t3 - 2.5-t3 - clk
23 STBIPulseWidth 1.5 - 1.5 - clk
24 STBOPulseWidth 1CLKO1-
5ns -1CLKO1-
5ns --
25 Data-OutSetupTimetoSTBOLow 2 - 2 - clk
26 Data-OutHoldTimefromSTBOHigh 5 - 5 - clk
27 STBILowtoSTBOLow(RxInterlock) - 2 - 2 clk
28 STBILowtoSTBOHigh(TxInterlock) 2 - 2 - clk
29 Data-InSetupTimetoClockLow 20 - 15 - ns
30 Data-InHoldTimefromClockLow 10 - 7.5 - ns
ClockHightoData-OutValid(CPUWritesData,
Control,orDirection) - 25 - 25 ns
DATA OUT
STRBO
STRBI
(INPUT)
(OUTPUT)
25
28
26
23
52 TS68EN360 2113A–HIREL–03/02
Figure42.PIPTx(InterlockMode)
Figure43.PIPTx(PulseMode)
DATA IN
STRBI
STRBO
(INPUT)
(OUTPUT)
21
23
22
24
DATA IN
STBI
STBO
(INPUT)
(OUTPUT)
21
23
22
24
53
TS68EN360
2113A–HIREL–03/02
Figure44.PIPTx(PulseMode)
Figure45.ParallelI/OData-in/Data-outTimingDiagram
DATA OUT
STBO
STBI
(INPUT)
(OUTPUT)
25
24
26
23
DATA OUT
DATA IN
30
CPU WRITE S4
31
CLKO1
(OUTPUT)
29
InterruptControllerACElectricalSpecifications
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary.
(SeeFigure46andFigure47).
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
35 PortCInterruptPulseWidthLow(EdgeTriggeredMode) 70 - 55 - ns
36 MinimumTimeBetweenActiveEdgesPortC 70 - 55 - clk
37 ClockHightoIOUTValid(SlaveMode) - 20 - 17 ns
38 ClockHightoRQOUTValid(SlaveMode) - 20 - 17 ns
54 TS68EN360 2113A–HIREL–03/02
Figure46.InterruptsTimingDiagram
Figure47.SlaveMode:InterruptsTimingDiagram
Figure48.BaudRateGeneratorOutputSignals
Port C
(INPUT)
35
36
IOUT2-
IOUT0
CLKO1
RQOUT
(OUTPUT)
(OUTPUT)
(OUTPUT)
37
38
BAUDRateGeneratorACElectricalSpecifications
GND=0VDC,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary(SeeFigure48).
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
50 BRGORiseandFallTime - 10 - 7.5 ns
51 BRGODutyCycle 40 60 40 60 %
52 BRGOCycle 40 30 ns
50
51 51
BRGOx
52
50
55
TS68EN360
2113A–HIREL–03/02
TimerElectricalSpecifications
GND=0VDC,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary(SeeFigure49).
Figure49.CPMGeneral-purposeTimers
Number Characteristic Symbol
25.0MHz 33.34MHz
UnitMin Max Min Max
61 TIN/TGATERiseandFallTime trf 10 - 10 - ns
62 TIN/TGATELowTime - 1 - 1 - clk
63 TIN/TGATEHighTime - 2 - 2 - clk
64 TIN/TGATECycleTime - 3 - 3 - clk
65 CLKO1HightoTOUTValid tTO 325322ns
62
65
63
64
61
61
60
CLKO1
(OUTPUT)
TIN/TGATE
(INPUT)
TOUT
(OUTPUT)
56 TS68EN360 2113A–HIREL–03/02
Notes: 1. TheratioSyncCLK/L1RCLKmustbegreaterthan2.5/1.
2. WhereP=1/CLKO1.Thusfora25MHzCLKO1rate,P=40ns.
3. ThesespecsarevalidforIDLmodeonly.
4. ThestrobesandTxdonthefirstbitoftheframebecomevalidafterL1CLKedgeorL1SYNC,whicheverislater.
SIElectricalSpecifications
GND=0VDC,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure50toFigure54).
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
70(1)(3) L1RCLK,L1TCLKFrequency(DCS=0) - 10 - 10 MHz
71(1) L1RCLK,L1TCLKWidthLow(DCS=0) P+10 - P+10 - ns
71A(2) L1RCLK,L1TCLKWidthHigh(DCS=0) P+10 - P+10 - ns
72 L1TXD,L1ST(1-4),L1RQ,L1CLKORise/FallTime - 15 - 15 ns
73 L1RSYNC,L1TSYNCValidtoL1CLKEdge(SYNCSetupTime) 20 - 20 - ns
74 L1CLKEdgetoL1RSYNC,L1TSYNCInvalid(SYNCHoldTime) 35 - 35 - ns
75 L1RSYNC,L1TSYNCRise/FallTime - 15 - 15 ns
76 L1RXDValidtoL1CLKEdge(L1RXDSetupTime) 42 - 42 - ns
77 L1CLKEdgetoL1RXDInvalid(L1RXDHoldTime) 35 - 35 - ns
78 L1CLKEdgetoL1ST(1-4)Valid 10 45 10 45 ns
78A(4) L1SYNCValidtoL1ST(1-4)Valid 10 45 10 45 ns
79 L1CLKEdgetoL1ST(1-4)Invalid 10 45 10 45 ns
80 L1CLKEdgetoL1TXDValid 10 65 10 65 ns
80A(4) L1TSYNCValidtoL1TXDValid 10 65 10 65 ns
81 L1CLKEdgetoL1TXDHighImpedance 0 42 0 42 ns
82 L1RCLK,L1TCLKFrequency(DSC=1) - 12.5 - 16 MHz
83 L1RCLK,L1TCLKWidthLow(DSC=1) P+10 - P+10 - ns
83A(2) L1RCLK,L1TCLKWidthHigh(DSC=1) P+10 - P+10 - ns
84 L1CLKEdgetoL1CLKOValid(DSC=1) - 30 - 30 ns
85(3) L1RQValidBeforeFallingEdgeofL1TSYNC 1 - 1 - L1TCLK
86(3) L1GRSetupTime 42 - 42 - ns
87(3) L1RGHoldTime 42 - 42 - ns
88 L1CLKEdgetoL1SYNCValid(FSD=00,CNT=0000,BYT=0,
DSC=0) -0-0ns
57
TS68EN360
2113A–HIREL–03/02
Figure50.SIReceiveTimingwithNormalClocking(DSC=0)
L1RSYNC
(INPUT)
71
L1ST (4-1)
(OUTPUT)
RFCD = 1
70
73 74
75
L1RXD
(INPUT)
78
76
BIT0
L1RCLK
(FE =1,CE = 1)
(INPUT)
72
L1RCLK
(FE = 0,CE = 0)
(INPUT)
77
79
58 TS68EN360 2113A–HIREL–03/02
Figure51.SIReceiveTimingwithDoubleSpeedClocking(DSC=1)
L1RSYNC
(INPUT)
L1ST (4-1)
(OUTPUT)
79
RFCD = 1
73 74
75
L1RXD
(INPUT)
77
76
BIT0
L1RCLK
(FE = 1,
CE = 1)
(INPUT)
L1RCLK
(FE = 0,
CE = 0)
(INPUT) 82
72 83A
L1CLKO
(OUTPUT)
84
78
59
TS68EN360
2113A–HIREL–03/02
Figure52.SITransmitTimingwithNormalClocking(DSC=0)
L1TXD
(INPUT) BIT0
81
L1TSYNC
(OUTPUT)
71
L1ST (4-1)
(OUTPUT)
78
79
TFCD = 0
70
73 74
75
L1TCLK
(FE = 1,
CE = 1)
(INPUT)
72
L1TCLK
(FE = 0,
CE = 0)
(INPUT)
80A
80
78A
60 TS68EN360 2113A–HIREL–03/02
Figure53.SITransmitTimingwithDoubleSpeedClocking(DSC=1)
L1TXD
(OUTPUT) BIT0
81
L1TSYNC
(INPUT)
L1ST (1-4)
(OUTPUT)
78
79
TFCD = 0
73 74
75
80A
80
78A
L1RCLK
(FE = 1,
CE = 1)
(INPUT)
L1RCLK
(FE = 0,
CE = 0)
(INPUT)
82
72 83A
L1CLKO
(OUTPUT)
84
61
TS68EN360
2113A–HIREL–03/02
Figure54.IDLTimingSITransmitTimingwithDoubleSpeedClocking(DSC=1)
Notes: 1. TheratioSyncCLK/RCLK1andSyncCLK/TCLK1mustbegreaterorequalto2.25/1.
2. AlsoappliestoCDandCTSholdtimewhentheyareusedasexternalsyncsignals.
SCCinNMSIMode-externalClockElectricalSpecifications
GND=0VDC,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure55toFigure57).
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
100(1) RCLK1andTCLK1WidthHigh CLKO1 - CLKO1 -
101 RCLK1andTCLK1WidthLow CLKO1+
5ns -CLKO1+
5ns -
102 RCLK1andTCLK1Rise/FallTime - 15 - 15 ns
103 TXD1ActiveDelay(FromTCLK1FallingEdge) 0 50 0 50 ns
104 RTS1Active/InactiveDelay(FromTCLK1FallingEdge) 0 50 0 50 ns
105 CTS1SetupTimetoTCLK1RisingEdge 40 - 40 - ns
106 RXD1SetupTimetoRCLK1RisingEdge 40 - 40 - ns
107(2) RXD1HoldTimefromRCLK1RisingEdge 0 - 0 - ns
108 CD1SetupTimetoRCLK1RisingEdge 40 - 40 - ns
62 TS68EN360 2113A–HIREL–03/02
Notes: 1. TheratioSyncCLK/RCLK1andSyncCLK/TCLK1mustbegreaterorequalto3/1.
2. AlsoappliestoCDandCTSholdtimewhentheyareusedasexternalsyncsignals.
Figure55.SCCNMSIReceive
SCCinNMSIMode-internalClockElectricalSpecifications
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure55toFigure57).
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
100(1) RCLK1andTCLK1Frequency 0 8.3 0 11 MHz
102RCLK1andTCLK1Rise/FallTime ----ns
103 TXD1ActiveDelay(FromTCLK1FallingEdge) 0 30 0 30 ns
104 RTS1Active/InactiveDelay(FromTCLK1FallingEdge) 0 30 40 - ns
105 CTS1SetupTimetoTCLK1RisingEdge 40 - 40 - ns
106 RXD1SetupTimetoRCLK1RisingEdge 40 - 0 - ns
107(2) RXD1HoldTimefromRCLK1RisingEdge 0 - 40 - ns
108 CD1SetupTimetoRCLK1RisingEdge 40 - 0 30 ns
RXD1
(INPUT)
RCLK1
108
107
106
102 102
100
101
CD1
(INPUT)
107
CD1
(SYNC-
INPUT)
63
TS68EN360
2113A–HIREL–03/02
Figure56.SCCNMSITransmit
Figure57.HDLCBUSTiming
TXD1
(OUTPUT
)
TCLK1
102
CTS1
(INPUT)
RTS1
(OUTPUT
)
104
CTS1
(SYNC
-
INPUT)
102
101
100
103
104
105
107
TXD1
(
OUTPUT)
TCLK1
104
100
101
102
102
105
RTS1
(
OUTPUT)
104
CTS1
(ECHO
INPUT)
103
107
64 TS68EN360 2113A–HIREL–03/02
Notes: 1. SyncCLK/RCLK1andSyncCLK/TCLK1mustbegreaterorequalto2.25/1
2. SDACKisassertedwhenevertheSDMAwritestheincomingframeDAintomemory.
Figure58.EthernetCollisionTiming
EthernetElectricalSpecifications
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure58toFigure63).
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
120 CLSNWidthHigh 40 - 40 - ns
121 RCLK1Rise/FallTime - 15 - 15 ns
122 RCLK1WidthLow CLKO1+
5ns -CLKO1+
5ns -
123(1) RCLK1WidthHigh CLKO1 - CLKO1 -
124 RXD1SetupTime 20 - 20 - ns
125 RXD1HoldTime 5 - 5 - ns
126 RENAActiveDelay(fromRCLK1risingedgeofthelast
databit) 10 - 10 - ns
127 RENAWidthLow 100 - 100 - ns
128 TCLK1Rise/FallTime - 15 - 15 ns
129 TCLK1WidthLow CLKO1+
5ns -CLKO1+
5ns -
130(1) TCLK1WidthHigh CLKO1 - CLKO1 -
131 TXD1ActiveDelay(fromTCLK1risingedge) 10 50 10 50 ns
132 TXD1InactiveDelay(fromTCLK1risingedge) 10 50 10 50 ns
133 TENAActiveDelay(fromTCLK1risingedge) 10 50 10 50 ns
134 TENAInactiveDelay(fromTCLK1risingedge) 10 50 10 50 ns
135 RSTRTActiveDelay(fromTCLK1fallingedge) 10 50 10 50 ns
136 RSTRTInactiveDelay(fromTCLK1fallingedge) 10 50 10 50 ns
137 RRJCTWidthLow 1 - 1 - CLKO1
138(2) CLKO1LowtoSDACKAsserted - 20 - 20 ns
139(2) CLKO1LowtoSDACKNegated - 20 - 20 ns
CLSN (CTS1)
(INPUT)
120
65
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Figure59.EthernetReceiveTiming
Figure60.EthernetTransmitTiming
Notes: 1. Transmitclockinvert(TCI)bitinGSMRisset.
2. IfRENAisdeassertedbeforeTENA,orRENAisnotassertedatallduringtransit,thenCSLbitissetinthebufferdescriptor
attheendofframetransmission.
RXD1
(INPUT)
RCLK1
125
124
121
123
122
RENA (CD1)
(INPUT)
LAST BIT
127
126
121
TXD1
(OUTPUT)
TCLK1
(NOTE 1)
132
131
128 128
130
129
TENA (RTS1)
(OUTPUT)
RENA (CD1)
(INPUT)
(NOTE 2)
133
134
66 TS68EN360 2113A–HIREL–03/02
Figure61.CAMInterfaceReceiveStartTiming
Note: Validfortheethernetprotocolonly.
Figure62.CAMInterfaceRejectTiming
Note: Validfortheethernetprotocolonly.
Figure63.SDACKTimingDiagram
Note: SDACKxisassertedwhentheSDMAwritesthereceivedEthernetframeintomemory.
RXD1
(INPUT)
RCLK1
RSTRT
(OUTPUT)
011
START FRAME DELIMITER
Bit # 1 Bit # 2
135 136
RRJCT
(INPUT)
137
AS
CLKO1
138
SDACKx
S0 S2 S4S1 S3 S5
SDMA CYCLE
(OUTPUT)
(OUTPUT)
(OUTPUT)
139
SMCTransparentModeElectricalSpecifications
GND=0VDC,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary(SeeFigure64).
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
150(1) SMCLKClockPeriod 100 - 100 - ns
151 SMCLKWidthLow 50 - 50 - ns
151A SMCLKWidthHigh 50 - 50 - ns
67
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Note: 1. TheratioSyncCLK/SMCLKmustbegreaterorequalto2/1.SMCTransparent.
Figure64.SMCTransparent
Note: Thisdelayisequaltoanintegernumberof“Characterlength”clocks.
152 SMCLKRise/FallTime - 15 - 15 ns
153 SMTXDActiveDelay(fromSMCLKfallingedge) 10 50 10 50 ns
154 SMRXD/SYNC1SetupTime 20 - 20 - ns
155 SMRXD/SYNC1HoldTime 5 - 5 - ns
SMCTransparentModeElectricalSpecifications
GND=0VDC,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary(SeeFigure64).
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
RXD1
(INPUT)
155
154
TXD1
(OUTPUT)
153
150
151
152
152
SYNC1
154
155
Note 1
SMCLK
151A
68 TS68EN360 2113A–HIREL–03/02
Figure65.SPIMaster(CP=0)
SPIMasterElectricalSpecifications
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure65andFigure66).
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
160 MasterCycleTime 4 1024 4 1024 tcyc
161 MasterClock(SPICLK)HighorLowTime 2 512 2 512 tcyc
162 MasterDataSetupTime(Inputs) 50 - 50 - ns
163 MasterDataHoldTime(Inputs) 0 - 0 - ns
164 MasterDataValid(afterSPICLKEdge) - 20 - 20 ns
165 MasterDataHoldTime(Outputs) 0 - 0 - ns
166 RiseTime:Output 15 15 ns
167 FallTime:Output 15 15 ns
MSB IN
MSB OUT
MSB OUT DATA LSB OUT "1"
"1"
DATA LSB IN
MSB IN
SPICLK
CI=0
OUTPUT
SPICLK
CI=1
OUTPUT
SPIMISO
INPUT
SPIMOSI
OUTPUT
167
166
161 160
161 166
165
167 166
167
163
162
164
69
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Figure66.SPIMaster(CP=1)
MSB
MSBMSB OUT DATA LSB OUT "1"
"1"
DATA LSB IN
MSB IN
SPICLK
CI=0
OUTPUT
SPICLK
CI=1
OUTPUT
SPIMISO
INPUT
SPIMOSI
OUTPUT
167
166
161 160
161 166
162
160
163
164
165
167 166
SPISlaveElectricalSpecifications
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure67andFigure68).
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
170 SlaveCycleTime 2 - 2 - tcyc
171 SlaveEnableLeadTime 15 15 ns
172 SlaveEnableLagTime 15 15 ns
173 SlaveClock(SPICLK)HighorLowTime 1 - 1 - tcyc
174 SlaveSequentialTransferDelay(DoesNotRequireDeselect) 1 1 tcyc
175 SlaveDataSetupTime(Inputs) 20 - 20 - ns
176 SlaveDataHoldTime(Inputs) 20 - 20 - ns
177 SlaveAccessTime 50 50 ns
178 SlaveSPIMISODisableTime 50 50 ns
179 SlaveDataValid(afterSPICLKEdge) - 50 - 50 ns
180 SlaveDataHoldTime(Outputs) 0 - 0 - ns
181 RiseTime:Input 15 15 ns
182 FallTime:Input 15 15 ns
70 TS68EN360 2113A–HIREL–03/02
Figure67.SPISlave(CP=0)
Figure68.SPISlave(CP=1)
DATA LSB OUT UNDEF. MSB OUT
MSB IN
MSB OUT
MSB IN DATA LSB IN
SPISEL
INPUT
SPICLK
CI=0
INPUT
SPICLK
CI=1
INPUT
SPIMISO
OUTPUT
SPIMOSI
INPUT
172 171
174
182
181
173 170
173 181 182 180 178
179
182181
180
176
177
175
MSB OUT DATA SLAVE
LSB OUT UNDEF.UNDEF.
MSB IN DATA LSB IN
SPISEL
INPUT
SPICLK
CI=0
INPUT
SPICLK
CI=1
INPUT
SPIMISO
OUTPUT
SPIMOSI
INPUT
174
182
181
173
182
181
178
179
181
179
177
175
170 173
171 172
180
176
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Figure69.TestClockInputTimingDiagram
Figure70.TRSTTimingDiagram
JTAGElectricalSpecifications
GND=0Vdc,TC=-55to+125°C.Theelectricalspecificationsinthisdocumentarepreliminary
(SeeFigure69andFigure72).
Number Characteristic
25.0MHz 33.34MHz
UnitMin Max Min Max
TCKFrequencyofOperation 0 25 0 25 MHz
1 TCKCycleTimeinCrystalMode 40 - 40 - ns
2 TCKClockPulseWidthMeasuredat1.5V 18 - 18 - ns
3 TCKriseandFallTimes 0 3 0 3 ns
6 BoundaryScanInputDataSetupTime 10 - 10 - ns
7 BoundaryScanInputDataHoldTime 18 - 18 - ns
8 TCKLowtoOutputDataValid 0 30 0 30 ns
9 TCKLowtoOutputHighImpedance 0 40 0 40 ns
10 TMS,TDIDataSetupTime 10 - 10 - ns
11 TMS,TDIDataHoldTime 10 - 10 - ns
12 TCKLowtoTDODataValid 0 20 0 20 ns
13 TCKLowtoTDOHighImpedance 0 20 0 20 ns
14 TRSTAssertTime 100-100- ns
15 TRSTSetupTimetoTCKLow 40 - 40 - ns
V
V
TCK
1
22
3
3
VM VM
IH
IL
(INPUT)
TCK
TRST
(INPUT)
(INPUT)
15
14
72 TS68EN360 2113A–HIREL–03/02
Figure71.BoundaryScan(JTAG)TimingDiagram
Figure72.TestAccessPortTimingDiagram
TC
K
V
V
DATA
OUTPUT
S
DATA
INPUTS
OUTPUT DATA VALID
DATA
OUTPUT
S
OUTPUT DATA VALID
DATA
OUTPUT
S
IL
IH
INPUT DATA VALID
67
8
9
8
(INPUT)
TC
K
V
V
TDO
TDI
TMS
OUTPUT DATA VALID
TDO OUTPUT DATA VALID
TDO
IL
IH
INPUT DATA VALID
1
0
11
1
2
1
3
1
2
(INPUT)
(INPUT)
(OUTPUT
)
(OUTPUT
)
(OUTPUT
)
73
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Functional
Description
CPU32+Core TheCPU32+coreisaCPU32thathasbeenmodifiedtoconnectdirectlytothe32-bit
IMBandapplythelargerbuswidth.AlthoughtheoriginalCPU32corehada32-bitinter-
naldatapathand32-bitarithmetichardware,itsinterfacetotheIMBwas16bits.The
CPU32+corecanoperateon32-bitexternaloperandswithonebuscycle.Thisallows
theCPU32+coretofetchalong-wordinstructioninonebuscycleantofetchtwoword-
lengthinstructionsinonebuscycle,fillingtheinternalinstructionqueuemorequickly.
TheCPU32+corecanalsoreadandwrite32-bitsofdatainonebuscycle.
AlthoughtheCPU32+instructiontimingsareimproved,itsinstructionsetisidenticalto
thatoftheCPU32.Itwillalsoexecutetheentire68000instructionset.Itcontainsthe
samebackgrounddebugmode(BDM)featuresastheCPU32.Nonewcompilers,
assemblersorothersoftwaresupporttoolsneedbeimplementedfortheCPU32+;stan-
dardCPU32toolscanbeused.
TheCPU32+deliversapproximately4.5MIPSat25MHz,basedonthestandard
(accepted)assumptionthata10-MHz68000delivers1VAXMIPS.Ifanapplication
requiresmoreperformance,theCPU32+canbedisabled,allowingtherestofthe
QUICCtooperateasanintelligentperipheraltoafasterprocessor.TheQUICCpro-
videsaspecialmodecalledTS68040companionmodetoallowittoconveniently
interfacetomembersoftheTS68040family.Thistwo-chipsolutionprovidesa22-MIPS
performanceat25MHz.
TheCPU32+alsooffersautomaticbytealignmentfeaturesthatarenotofferedonthe
CPU32.Thesefeaturesallow16-or32-bitdatatobereadorwrittenatanoddaddress.
TheCPU32+automaticallyperformsthenumberofbuscyclesrequired.
SystemIntegration
Module(SIM60) TheSIM60integratesgeneral-purposefeaturesthatwouldbeusefulinalmostany32-
bitprocessorsystem.Theterm“SIM60”isderivedfromtheQUICCpartnumber,
TS68EN360.TheSIM60isanenhancedversionoftheSIM40thatexistsonthe
TS68332device.
First,newfeatures,suchasaDRAMcontrollerandbreakpointlogic,havebeenadded.
Second,theSIM40wasmodifiedtosupporta32-bitIMBaswellasa32-bitexternal
systembus.Third,newconfigurations,suchasslavemodeandinternalaccessesbyan
externalmaster,aresupported.
AlthoughtheQUICCisalwaysa32-bitdeviceinternally,itmaybeconfiguredtooperate
witha16-bitdatabus.Regardlessofthechoiceofthesystembussize,dynamicbus
sizingissupported.Bussizingallows8-16-,and32-bitperipheralsandmemorytoexist
inthe32-bitsystembusmodeand8-and16-bitperipheralsandmemorytoexistinthe
16-bitsystembusmode.
Communications
ProcessorModule(CPM) TheCPMcontainsfeaturesthatallowtheQUICCtoexcelincommunicationsandcon-
trolapplications.Thesefeaturesmaybedividedintothreesub-groups:
• CommunicationsProcessor(CP)
• TwoIDMAControllers
• FourGeneral-purposeTimers
74 TS68EN360 2113A–HIREL–03/02
TheCPprovidesthecommunicationfeaturesoftheQUICC.IncludedareaRISCpro-
cessor,fourSCCs,twoSMCs,oneSPI,2.5Kbytesofdual-portRAM,aninterrupt
controller,atimeslotassigner,threeparallelports,aparallelinterfaceport,fourinde-
pendentbaudrategenerators,andfourteenserialDMAchannelstosupporttheSCCs,
SMCs,andSPI.
TheIDMAsprovidetwochannelsofgeneral-purposeDMAcapability.Theyofferhigh-
speedtransfers,32-bitdatamovement,bufferchaining,andindependentrequestand
acknowledgelogic.TheRISCcontrollermayaccesstheIDMAregistersdirectlyinthe
bufferchainingmodes.TheQUICCIDMAsaresimilarto,yetenhancementsof,theone
IDMAchannelfoundontheTS68302.
Thefourgeneral-purposetimersontheQUICCarefunctionallysimilartothetwogen-
eral-purposetimersfoundontheTS68302.However,theyoffersomeminor
enhancements,suchastheinternalcascadingoftwotimerstoforma32-bittimer.The
QUICCalsocontainsaperiodicintervaltimerintheSIM60,bringingthetotaltofive
on-chiptimers.
EthernetonQUICC TheEthernetprotocolisavailableonlyontheEthernetversionoftheQUICCcalledthe
TS68EN360.Thenon-EthernetversionoftheQUICCistheMC68360.Theterm
“QUICC”istheoveralldevicenamethatdenotesallversionsofthedevice.
TheTS68EN360isasupersetoftheMC68360,havingtheadditionaloptionallowing
EthernetoperationonanyofthefourSCCs.DuetoperformancereasonnotassSCCs
canbeconfiguredasEthernetcontrolleratthesametime.TheTS68EN360isnot
restrictedonlytoEthernetoperation.HDLC,UART,andotherprotocolsmaybeusedto
allowdynamicswitchingbetweenprotocols.SeeAppendixASerialPerformancefor
availableSCCperformance.
WhentheMODEbitsoftheSCCGSMRselecttheEthernetprotocol,thenthatSCC
performsthefullsetofIEEE802.3/EthernetCSMA/CDmediaaccesscontrolandchan-
nelinterfacefunctions(seeFigure73).
Figure73.EthernetBlockDiagram
IMB
CONTROL
REGISTERS
SLOT TIME
AND DEFER
COUNTER
CLOCK
GENERATOR
PERIPHERAL BUS
RECEIVER
CONTROL
UNIT
RECEIVE
DATA
FIFO
TRANSMITTER
CONTROL
UNIT
TRANSMIT
DATA
FIFO
SHIFTER SHIFTER TXD
RXD
RRJCT
RSTRT
CD = RENA CD = RENA
CTS = CLSN CTS = CLSN
RTS = TENA
INTERNAL CLOCKS
RX CLOCK
TX CLOCK
RANDOM NO.
75
TS68EN360
2113A–HIREL–03/02
UpgradingDesignsfrom
theTS68302 SincetheQUICCisanext-generationTS68302,manydesignerscurrentlyusingthe
TS68302maywishtousetheQUICCinafollow-ondesign.Thefollowingparagraphs
brieflydiscussthisendeavorintermsofarchitecturalapproach,hardwareissues,and
softwareissues.
ArchitecturalApproach TheQUICCisthelogicalextensionoftheTS86302,buttheoverallarchitectureandphi-
losophyoftheTS86302designremainsintactintheQUICC.TheQUICCkeepsthebest
featuresoftheTS86302,whilemakingthechangesrequiredtoprovideforthe
increasedflexibility,integration,andperformancerequestedbycustomers.Becausethe
CPMisprobablythemostdifficultmoduletolearn,anyonewhohasusedtheTS86302
caneasilybecomefamiliarwiththeQUICCsincetheCPMarchitecturalapproach
remainsintact.
ThemostsignificantarchitecturalchangemadeontheQUICCwasthetranslationofthe
designintothestandard68300familyIMBarchitecture,resultinginafasterCPUand
differentsystemintegrationfeatures.
AlthoughthefeaturesoftheSIM60donotexactlycorrespondtothoseoftheTS86302
SIM,theyareverysimilar.
BecauseofthesimilarityoftheQUICCSIM60andCPUtoothermembersofthe68300
family,suchastheTS68332,previoususersofthesedeviceswillbecomfortablewith
thesesamefeaturesontheQUICC.
HardwareCompatibility
Issues ThefollowinglistsummarizesthehardwaredifferencesbetweentheTS86302andthe
QUICC:
• Pinout–Thepinoutisnotthesame.TheQUICChas240pins;theTS86302has
132pins.
• Package–BothdevicesofferPGAandPQFPpackages.However,theQUICCQFP
packagehasa20-milpitch;whereas,theTS86302QFPpackagehasa25-mil
pitch.
• SystemBus–ThesystembussignalsnowlooklikethoseoftheTS68020as
opposedtothoseofthe68000.Itisstillpossibletointerface68000peripheralsto
theQUICC,utilizingthesametechniquesusedtointerfacethemtoaTS68020.
• SystemBusinSlaveMode–AnumberofQUICCpinstakeonnewfunctionalityin
slavemodetosupportanexternalTS68EC040.OntheTS68302,thepinnames
generallyremainedthesameinslavemode.
• PeripheralTiming–Theexternaltimingsoftheperipherals(SCCs,timers,etc.)are
verysimilar(ifnotidentical)tocorrespondingperipheralsontheTS68302.
• PinAssignments–TheassignmentofperipheralfunctionstoI/Opinsisdifferentin
severalways.First,theQUICCcontainsmoregeneral-purposeparallelI/Opins
thantheTS68302.However,theQUICCoffersmanymorefunctionsthanevena
240-pinpackagewouldnormallyallow,resultinginmoremultifunctionalpinsthan
theTS68302.
76 TS68EN360 2113A–HIREL–03/02
SoftwareCompatibilityIssues ThefollowinglistsummarizesthemajorsoftwaredifferencesbetweentheTS68302and
theQUICC:
• SincetheCPU32+isasupersetofthe68000instructionset,allpreviouslywritten
codewillrun.However,ifsuchcodeisaccessingtheTS68302peripherals,itwill
requiresomemodification.
• TheQUICCcontainsan8-Kbyteblockofmemoryasopposedtoa4-Kbyteblockon
theTS68302.Theregisteraddresseswithinthatmemorymaparedifferent.
• ThecodeusedtoinitializethesystemintegrationfeaturesoftheTS68302hastobe
modifiedtowritethecorrespondingfeaturesontheQUICCSIM60.
• Asmuchaspossible,QUICCCPMfeaturesweremadeidenticaltothoseofthe
TS68302CP.Themostimportantbenefitisthatthecodeflow(ifnotthecodeitself)
willporteasilyfromtheTS68302totheQUICC.Thenuanceslearnedfromthe
TS68302willstillbeusefulintheQUICC.
• AlthoughtheregistersusedtoinitializetheQUICCCPMarenew(forexample,the
SCMontheTS68302isreplacedwiththeGSMRandPSMRontheQUICC),most
registersretaintheiroriginalpurposesuchastheSCCevent,SCCmask,SCC
status,andcommandregisters.TheparameterRAMoftheSCCsisverysimilar,
andmostparameterRAMregisternamesandusageareretained.Moreimportantly,
thebasicstructureofabufferdescriptor(BD)ontheQUICCisidenticaltothatofthe
TS68302,exceptforafewnewbitfunctionsthatwereadded.(Inafewcases,abit
inaBDstatuswordhadtobeshifted.)
• WhenportingcodefromtheTS68302CPtotheQUICCCPM,thesoftwarewriter
mayfindthattheQUICChasnewoptionstosimplifywhatusedtobeamorecode-
intensiveprocess.Forspecificexamples,seetheINITTXANDRXPARAMETERS,
GRACEFULSTOPTRANSMIT,andCLOSEBDcommands.
Preparationfor
Delivery
Packaging MicrocircuitsarepreparedfordeliveryinaccordancewithMIL-PRF-38535orAtmel
standards.
CertificateofCompliance Atmeloffersacertificateofcomplianceswitheachshipmentofparts,affirmingtheprod-
uctsareincomplianceeitherwithMIL-STD-883orAtmelstandardandguarantyingthe
parametersnottestedattemperatureextremesfortheentiretemperaturerange.
Handling MOSdevicesmustbehandledwithcertainprecautionstoavoiddamageduetoaccu-
mulationofstaticcharge.Inputprotectiondeviceshavebeendesignedinthechipto
minimizetheeffectofthisstaticbuildup.However,thefollowinghandlingpracticesare
recommended:
a) Devicesshouldbehandledonbencheswithconductiveandgroundedsurfaces.
b) Groundtestequipment,toolsandoperator.
c) Donothandledevicesbytheleads.
d) Storedevicesinconductivefoamorcarriers.
e) Avoiduseofplastic,rubber,orsilkinMOSareas.
f) Maintainrelativehumidityabove50%ifpractical.
77
TS68EN360
2113A–HIREL–03/02
PackageMechanicalData
241-pin–PGA
(top view)
A
Dim
Inches Millimeters
Min Max Min Max
A 1.840 1.880 46.74 47.75
C 0.110 0.140 2.79 3.56
D 0.016 0.020 0.41 0.51
E 0.045 0.055 1.143 1.4
F 0.045 0.055 1.143 1.4
G 0.100BASIC 2.54BASIC
K 0.150 0.170 3.81 4.32
118
A
T
(BOTTOM VIEW)
A1
A
G
C
K
E
G
DF
78 TS68EN360 2113A–HIREL–03/02
240-pin–CERQUAD
240
181
61
120
180 121
160
U
S
Y
V
0.25 (0.010) T L–N M MH
S
L–N
S
0.20 (0.008)
M
W
E
C
0.10 (0.004)
–H–
DATUM
PLANE
SEATING
PLANE
VIEW AC
4 PLACES
AB
θ2
K
AA
VIEW AE
–H–
DATUM
PLANE
VIEW AE
–T–
4 x 60 TIPS
–L–
–M– A
–N– B
G
P
–X–
AD
AD
X = L, M or N
VIEW AC
F
J
D
Z
T M S
L–N S
0.08 (0.003) M
SECTION AD
240 PLACES
DIM
MILLIMETERS INCHES
MIN MAX MIN MAX
A 30.86 31.75 1.215 1.250
B 30.86 31.75 1.215 1.250
C 3.67 4.15 0.144 0.163
D 0.18 0.30 0.007 0.012
E 3.10 3.90 0.122 0.154
F 0.17 0.23 0.007 0.009
G 0.50BSC 0.019BSC
J 0.13 0.175 0.005 0.007
K 0.45 0.55 0.018 0.021
P 0.25BSC 0.010BSC
R 0.15BSC 0.006BSC
S 34.41 34.75 1.355 1.37
U 17.30BSC 0.681BSC
V 34.41 34.75 1.355 1.37
W 0.25 0.75 0.01 0.03
Y 17.30BSC 0.681BSC
Z 0.12 0.13 0.005 0.005
AA 1.80REF 0.071REF
AB 0.95REF 0.037REF
θ21°7°1°7°
Notes: 1. DimensioningandtolerancingperASMEY14.5,1994.
2. Controllingdimension:millimeter.
3. Datumplane-H-islocatedatbottomofleadandiscoincidentwiththe
leadwheretheleadexitstheceramicbodyatthebottomoftheparting
line.
4. Datums-L-,-M-and-N-tobedeterminedatdatumplane-H-.
5. DimensionsSandVtobedeterminedatseatingplane-T-.
6. Dimensions A and B define maximum ceramic body dimensions
includingglassprotrusionandtopandbottommismatch.
79
TS68EN360
2113A–HIREL–03/02
OrderingInformation
Hi-RELProduct
CommercialAtmel
Part-Number Norms Package Temperature
RangeTc(°C) Frequency
(MHz) DrawingNumber
TS68EN360MRB/C25L MIL-STD-883 PGA241Gold -55/+125 25 -
TS68EN360MRB/C33L MIL-STD-883 PGA241Gold -55/+125 33 -
TS68EN360MR1B/C25L MIL-STD-883 PGA241Tinned -55/+125 25 -
TS68EN360MR1B/C33L MIL-STD-883 PGA241Tinned -55/+125 33 -
TS68EN360MAB/C25L MIL-STD-883 CERQUAD240 -55/+125 25 -
TS68EN360MAB/C33L MIL-STD-883 CERQUAD240 -55/+125 33 -
TS68EN360DES01MXCL DSCC PGA241Gold -55/+125 25 5962-9760701MXC
TS68EN360DES02MXCL DSCC PGA241Gold -55/+125 33 5962-9760702MXC
TS68EN360DES01MXAL DSCC PGA241Tinned -55/+125 25 5962-9760701MXA
TS68EN360DES02MXAL DSCC PGA241Tinned -55/+125 33 5962-9760702MXA
TS68EN360DES01MYAL DSCC CERQUAD240 -55/+125 25 5962-9760701MYA
TS68EN360DES02MYAL DSCC CERQUAD240 -55/+125 33 5962-9760702MYA
StandardProduct
CommercialAtmel
Part-Number Norms Package Temperature
RangeTc(°C) Frequency
(MHz) Drawing Number
TS68EN360VR25L AtmelStandard PGA241 -40/+85 25 Internal
TS68EN360MR25L AtmelStandard PGA241 -55/+125 25 Internal
TS68EN360VA25L AtmelStandard CERQUAD240 -40/+85 25 Internal
TS68EN360MA25L AtmelStandard CERQUAD240 -55/+125 25 Internal
TS68EN360VR33L AtmelStandard PGA241 -40/+85 33 Internal
TS68EN360MR33L AtmelStandard PGA241 -55/+125 33 Internal
TS68EN360VA33L AtmelStandard CERQUAD240 -40/+85 33 Internal
TS68EN360MA33L AtmelStandard CERQUAD240 -55/+125 33 Internal
80 TS68EN360 2113A–HIREL–03/02
Operating frequency :
Generic
TS68EN360 M R B/C
M : -55°C, +125°C
V : -40°C, +110°C
C : 0°C, +70°C
25 X
Temperature range : (TC )
R = Pin grid array 241 (gold)
A = CERQUAD 240 (tin)
Package : 25 : 25 MHz
33 : 33 MHz
Revision level
L:
___ = Standard
B/C = MIL STD 883 Class B
B/T = According to MIL-STD883
D/T = Standard + Burn in
Screening :
_ = Gold (for PGA)
_ = Hot solder dip (for CERQUAD)
1 = Hot solder dip (for PGA - On request)
Hirel lead finish :
(TSX)
Prototype version
1
81
TS68EN360
2113A–HIREL–03/02
©AtmelCorporation2002.
AtmelCorporationmakesnowarrantyfortheuseofitsproducts,otherthanthoseexpresslycontainedintheCompany’sstandardwarranty
whichisdetailedinAtmel’sTermsandConditionslocatedontheCompany’swebsite.TheCompanyassumesnoresponsibilityforanyerrors
whichmayappearinthisdocument,reservestherighttochangedevicesorspecificationsdetailedhereinatanytimewithoutnotice,anddoes
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2113A–HIREL–03/02 0M
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Othertermsandproductnamesmaybethetrademarksofothers.