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LM6132
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LM6134
SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014
LM6132/LM6134 Dual and Quad Low Power 10 MHz Rail-to-Rail I/O Operational Amplifiers
1 Features 3 Description
The LM6132/34 provides new levels of speed vs.
1• (For 5V Supply, Typ Unless Noted) power performance in applications where low voltage
• Rail-to-Rail Input CMVR −0.25 V to 5.25 V supplies or power limitations previously made
• Rail-to-Rail Output Swing 0.01V to 4.99V compromise necessary. With only 360 μA/amp supply
current, the 10 MHz gain-bandwidth of this device
• High Gain-Bandwidth, 10 MHz at 20 kHz supports new portable applications where higher
• Slew Rate 12 V/μspower devices unacceptably drain battery life.
• Low Supply Current 360 μA/Amp The LM6132/34 can be driven by voltages that
• Wide Supply Range 2.7 V to over 24 V exceed both power supply rails, thus eliminating
• CMRR 100 dB concerns over exceeding the common-mode voltage
range. The rail-to-rail output swing capability provides
• Gain 100 dB with RL= 10 k the maximum possible dynamic range at the output.
• PSRR 82 dB This is particularly important when operating on low
supply voltages. The LM6132/34 can also drive large
2 Applications capacitive loads without oscillating.
• Battery Operated Instrumentation Operating on supplies from 2.7 V to over 24 V, the
• Instrumentation Amplifiers LM6132/34 is excellent for a very wide range of
applications, from battery operated systems with
• Portable Scanners large bandwidth requirements to high speed
• Wireless Communications instrumentation.
• Flat Panel Display Driver Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LM6132 SOIC (8) 4.90 mm x 3.91 mm
LM6132 PDIP (8) 9.81 mm x 6.35 mm
LM6134 SOIC (14) 8.65 mm x 3.91 mm
LM6134 PDIP (14) 19.177 mm x 6.35 mm
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
Offset Voltage vs. Supply Voltage
Supply Current vs. Supply Voltage
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM6132
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SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014
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Table of Contents
6.9 2.7V AC Electrical Characteristics............................ 6
1 Features.................................................................. 16.10 24V DC Electrical Characteristics........................... 7
2 Applications ........................................................... 16.11 24V AC Electrical Characteristics........................... 7
3 Description............................................................. 16.12 Typical Performance Characteristics ...................... 8
4 Revision History..................................................... 27 Application and Implementation ........................ 13
5 Pin Configuration and Functions......................... 37.1 Application Information............................................ 13
6 Specifications......................................................... 47.2 Enhanced Slew Rate .............................................. 13
6.1 Absolute Maximum Ratings ...................................... 47.3 Typical Applications ................................................ 17
6.2 Handling Ratings....................................................... 48 Device and Documentation Support.................. 18
6.3 Recommended Operating Conditions(1) ................... 48.1 Related Links .......................................................... 18
6.4 Thermal Information, 8-Pin ....................................... 48.2 Trademarks............................................................. 18
6.5 Thermal Information, 14-Pin ..................................... 48.3 Electrostatic Discharge Caution.............................. 18
6.6 5.0V DC Electrical Characteristics............................ 58.4 Glossary.................................................................. 18
6.7 5.0V AC Electrical Characteristics............................ 69 Mechanical, Packaging, and Orderable
6.8 2.7V DC Electrical Characteristics............................ 6Information ........................................................... 18
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision D (February 2013) to Revision E Page
• Changed "Junction Temperature Range" to "Operating Temperature Range" and deleted "TJ"........................................... 4
• Deleted TJ= 25°C for Electrical Characteristics tables.......................................................................................................... 5
Changes from Revision C (February 2013) to Revision D Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 17
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SNOS751E –APRIL 2000–REVISED SEPTEMBER 2014
5 Pin Configuration and Functions
8-Pin SOIC/PDIP 14-Pin SOIC/PDIP
Packages D and P Packages D and NFF
Top View Top View
Pin Functions
PIN
LM6132 LM6134 I/O DESCRIPTION
NAME D/NFF0014
D/P A
-IN A 2 2 I ChA Inverting Input
+IN A 3 3 I ChA Non-inverting Input
-IN B 6 6 I ChB Inverting Input
+IN B 5 5 I ChB Non-inverting Input
-IN C 9 I ChC Inverting Input
+IN C 10 I ChC Non-inverting Input
-IN D 13 I ChD Inverting Input
+IN D 12 I ChD Non-inverting Input
OUT A 1 1 O ChA Output
OUT B 7 7 O ChB Output
OUT C 8 O ChC Output
OUT D 14 O ChD Output
V-4 11 I Negative Supply
V+8 4 I Positive Supply
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6 Specifications
6.1 Absolute Maximum Ratings(1)(2)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
Differential Input Voltage ±15 V
(V+)+0.3
Voltage at Input/Output Pin V
(V−)−0.3
Supply Voltage (V+–V−) 35 V
Current at Input Pin ±10 mA
Current at Output Pin(3) ±25 mA
Current at Power Supply Pin 50 mA
Lead Temp. (soldering, 10 sec.) 260 °C
Junction Temperature(4) 150 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical characteristics.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and
specifications.
(3) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(4) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) −TA)/RθJA. All numbers apply for packages soldered directly into a PC board.
6.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range −65 +150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, all 2500
V(ESD) Electrostatic discharge V
pins(1)
(1) Human Body Model, 1.5 kΩin series with 100 pF .JEDEC document JEP155 states that 2500-V HBM allows safe manufacturing with a
standard ESD control process.
6.3 Recommended Operating Conditions(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
Supply Voltage 1.8 ≤V+≤24 V
Operating Temperature Range: LM6132, LM6134 −40 +85 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not guaranteed. For guaranteed specifications and the test
conditions, see the Electrical characteristics.
6.4 Thermal Information, 8-Pin D (SOIC) P (PDIP)
THERMAL METRIC(1) UNIT
8 PINS 8 PINS
RθJA Junction-to-ambient thermal resistance 193 115 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
6.5 Thermal Information, 14-Pin D (SOIC) NFF (PDIP)
THERMAL METRIC(1) UNIT
14 PINS 14 PINS
RθJA Junction-to-ambient thermal resistance 126 81 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
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6.6 5.0V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for V+= 5.0V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩto V+/2. Boldface
limits apply at the temperature extremes LM6134AI LM6134BI
PARAMETER TEST CONDITIONS TYP(1) LM6132AI LM6132BI UNIT
LIMIT(2) LIMIT(2)
VOS Input Offset Voltage 2 6 mV
0.25 4 8 max
TCVOS Input Offset Voltage Average Drift 5μV/C
IBInput Bias Current 0V ≤VCM ≤5V 140 180 nA
110 300 350 max
IOS Input Offset Current 30 30 nA
3.4 50 50 max
RIN Input Resistance, CM 104 MΩ
CMRR Common Mode Rejection Ratio 0V ≤VCM ≤4V 75 75
100 70 70 dB
min
0V ≤VCM ≤5V 60 60
80 55 55
PSRR Power Supply Rejection Ratio ±2.5V ≤V+≤±12V 78 78 dB
82 75 75 min
VCM −0.25 0 0
Input Common-Mode Voltage Range V
5.25 5.0 5.0
AVLarge Signal Voltage Gain RL= 10k 25 15 V/mV
100 8 6 min
VOOutput Swing 100k Load 4.98 4.98 V
4.992 4.93 4.93 min
0.017 0.017 V
0.007 0.019 0.019 max
10k Load 4.94 4.94 V
4.952 4.85 4.85 min
0.07 0.07 V
0.032 0.09 0.09 max
5k Load 4.90 4.90 V
4.923 4.85 4.85 min
0.095 0.095 V
0.051 0.12 0.12 max
ISC Output Short Circuit Current Sourcing 2 2 mA
4
LM6132 2 1 min
Sinking 1.8 1.8 mA
3.5 1.8 1 min
ISC Output Short Circuit Current Sourcing 2 2 mA
3
LM6134 1.6 1 min
Sinking 1.8 1.8 mA
3.5 1.3 1 min
ISSupply Current Per Amplifier 400 400 μA
360 450 450 max
(1) Typical Values represent the most likely parametric normal.
(2) All limits are guaranteed by testing or statistical analysis.
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6.7 5.0V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for V+= 5.0V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩto V+/2. Boldface
limits apply at the temperature extremes LM6134AI LM6134BI
PARAMETER TEST CONDITIONS TYP(1) LM6132AI LM6132BI UNIT
LIMIT(2) LIMIT(2)
SR Slew Rate ±4V @ VS= ±6V 8 8 V/μs
14
RS< 1 kΩ7 7 min
GBW Gain-Bandwidth Product f = 20 kHz 7.4 7.4 MHz
10 7 7 min
θm Phase Margin RL= 10k 33 deg
GmGain Margin RL= 10k 10 dB
enInput Referred Voltage Noise f = 1 kHz 27 nV/√Hz
inInput Referred Current Noise f = 1 kHz 0.18 pA/√Hz
(1) Typical Values represent the most likely parametric normal.
(2) All limits are guaranteed by testing or statistical analysis.
6.8 2.7V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for V+= 2.7V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩto V+/2. Boldface
limits apply at the temperature extreme LM6134AI LM6134BI
PARAMETER TEST CONDITIONS TYP(1) LM6132AI LM6132BI UNIT
LIMIT(2) LIMIT(2)
VOS Input Offset Voltage 2 6 mV
0.12 8 12 max
IBInput Bias Current 0V ≤VCM ≤2.7V 90 nA
IOS Input Offset Current 2.8 nA
RIN Input Resistance 134 MΩ
CMRR Common Mode Rejection Ratio 0V ≤VCM ≤2.7V 82 dB
PSRR Power Supply Rejection Ratio ±1.35V ≤V+≤±12V 80 dB
VCM Input Common-Mode Voltage Range 2.7 2.7 V
0 0
AVLarge Signal Voltage Gain RL= 10k 100 V/mV
VOOutput Swing RL= 100k 0.08 0.08 V
0.03 0.112 0.112 max
2.65 2.65 V
2.66 2.25 2.25 min
ISSupply Current Per Amplifier 330 μA
(1) Typical Values represent the most likely parametric normal.
(2) All limits are guaranteed by testing or statistical analysis.
6.9 2.7V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for V+= 2.7V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩto V+/2.
LM6134AI LM6134BI
TYP LM6132AI LM6132BI
PARAMETER TEST CONDITIONS UNIT
(1) LIMIT LIMIT
(2) (2)
GBW Gain-Bandwidth Product RL= 10k, f = 20 kHz 7 MHz
θmPhase Margin RL= 10k 23 deg
GmGain Margin 12 dB
(1) Typical Values represent the most likely parametric normal.
(2) All limits are guaranteed by testing or statistical analysis.
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6.10 24V DC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for V+= 24V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩto V+/2. Boldface
limits apply at the temperature extreme LM6134AI LM6134BI
PARAMETER TEST CONDITIONS TYP(1) LM6132AI LM6132BI UNIT
LIMIT(2) LIMIT(2)
VOS Input Offset Voltage 3 7 mV
1.7 5 9 max
IBInput Bias Current 0V ≤VCM ≤24V 125 nA
IOS Input Offset Current 4.8 nA
RIN Input Resistance 210 MΩ
CMRR Common Mode Rejection Ratio 0V ≤VCM ≤24V 80 dB
PSRR Power Supply Rejection Ratio 2.7V ≤V+≤24V 82 dB
VCM Input Common-Mode Voltage Range −0.25 0 0 V min
24.25 24 24 V max
AVLarge Signal Voltage Gain RL= 10k 102 V/mV
VOOutput Swing RL= 10k V
max
0.075 0.15 0.15
23.86 23.8 23.8 V
min
ISSupply Current Per Amplifier 450 450 μA
390 490 490 max
(1) Typical Values represent the most likely parametric normal.
(2) All limits are guaranteed by testing or statistical analysis.
6.11 24V AC Electrical Characteristics
Unless otherwise specified, all limits guaranteed for V+= 24V, V−= 0V, VCM = VO= V+/2 and RL> 1 MΩto V+/2.
LM6134AI LM6134BI
PARAMETER TEST CONDITIONS TYP(1) LM6132AI LM6132BI UNIT
LIMIT(2) LIMIT(2)
GBW Gain-Bandwidth Product RL= 10k, f = 20 kHz 11 MHz
θmPhase Margin RL= 10k 23 deg
GmGain Margin RL= 10k 12 dB
THD + N Total Harmonic Distortion and Noise AV= +1, VO= 20VP-P 0.0015%
f = 10 kHz
(1) Typical Values represent the most likely parametric normal.
(2) All limits are guaranteed by testing or statistical analysis.
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6.12 Typical Performance Characteristics
TA= 25°C, RL= 10 kΩunless otherwise specified
Figure 1. Supply Current vs. Supply Voltage Figure 2. Offset Voltage vs. Supply Voltage
Figure 3. dVOS vs. VCM Figure 4. dVOS vs. VCM
Figure 5. dVOS vs. VCM Figure 6. IBIAS vs. VCM
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Typical Performance Characteristics (continued)
TA= 25°C, RL= 10 kΩunless otherwise specified
Figure 7. IBIAS vs. VCM Figure 8. IBIAS vs. VCM
Figure 9. Input Bias Current vs. Supply Voltage Figure 10. Negative PSRR vs. Frequency
Figure 12. dVOS vs. Output Voltage
Figure 11. Positive PSSR vs. Frequency
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Typical Performance Characteristics (continued)
TA= 25°C, RL= 10 kΩunless otherwise specified
Figure 13. dVOS vs. Output Voltage Figure 14. dVOS vs. Output Voltage
Figure 15. CMRR vs. Frequency Figure 16. Output Voltage vs. Sinking Current
Figure 17. Output Voltage vs. Sinking Current Figure 18. Output Voltage vs. Sinking Current
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Typical Performance Characteristics (continued)
TA= 25°C, RL= 10 kΩunless otherwise specified
Figure 19. Output Voltage vs. Sourcing Current Figure 20. Output Voltage vs. Sourcing Current
Figure 22. Noise Voltage vs. Frequency
Figure 21. Output Voltage vs. Sourcing Current
Figure 23. Noise Current vs. Frequency Figure 24. NF vs. Source Resistance
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Typical Performance Characteristics (continued)
TA= 25°C, RL= 10 kΩunless otherwise specified
Figure 25. Gain and Phase vs. Frequency Figure 26. Gain and Phase vs. Frequency
Figure 27. Gain and Phase vs. Frequency Figure 28. GBW vs. Supply Voltage at 20 kHz
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7 Application and Implementation
7.1 Application Information
The LM6132 brings a new level of ease of use to op amp system design. Greater than rail-to-rail input voltage
eliminates concern over exceeding the common-mode voltage range.
Rail-to-rail output swing provides the maximum possible dynamic range at the output. This is particularly
important when operating on low supply voltages.
The high gain-bandwidth with low supply current opens new battery powered applications, where high power
consumption previously reduced battery life to unacceptable levels.
To take advantage of these features, some ideas should be kept in mind, which are outlined in subsequent
sections.
7.2 Enhanced Slew Rate
Unlike most bipolar op amps, the unique phase reversal prevention/speed-up circuit in the input stage eliminates
phase reversal and allows the slew rate to be a function of the input signal amplitude.
Figure 30 shows how excess input signal is routed around the input collector-base junctions directly to the
current mirrors.
The LM6132/34 input stage converts the input voltage change to a current change. This current change drives
the current mirrors through the collectors of Q1–Q2, Q3–Q4 when the input levels are normal.
If the input signal exceeds the slew rate of the input stage and the differential input voltage rises above a diode
drop, the excess signal bypasses the normal input transistors, (Q1–Q4), and is routed in correct phase through
the two additional transistors, (Q5, Q6), directly into the current mirrors.
The rerouting of excess signal allows the slew-rate to increase by a factor of 10 to 1 or more. (See Figure 29).
As the overdrive increases, the op amp reacts better than a conventional op amp. Large fast pulses will raise the
slew rate to around 25V to 30 V/μs.
Figure 29. Slew Rate vs. Differential VIN
VS= ±12V
This effect is most noticeable at higher supply voltages and lower gains where incoming signals are likely to be
large.
This speed-up action adds stability to the system when driving large capacitive loads.
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Enhanced Slew Rate (continued)
7.2.1 Driving Capacitive Loads
Capacitive loads decrease the phase margin of all op amps. This is caused by the output resistance of the
amplifier and the load capacitance forming an R-C phase lag network. This can lead to overshoot, ringing and
oscillation. Slew rate limiting can also cause additional lag. Most op amps with a fixed maximum slew-rate will lag
further and further behind when driving capacitive loads even though the differential input voltage raises. With the
LM6132, the lag causes the slew rate to raise. The increased slew-rate keeps the output following the input
much better. This effectively reduces phase lag. After the output has caught up with the input, the differential
input voltage drops down and the amplifier settles rapidly.
Figure 30. Internal Block Diagram
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Enhanced Slew Rate (continued)
These features allow the LM6132 to drive capacitive loads as large as 500 pF at unity gain and not oscillate. The
scope photos (Figure 31 and Figure 32) show the LM6132 driving a 500 pF load. In Figure 31 , the lower trace is
with no capacitive load and the upper trace is with a 500 pF load. Here we are operating on ±12V supplies with a
20 VPP pulse. Excellent response is obtained with a Cfof 39 pF. In Figure 32, the supplies have been reduced to
±2.5V, the pulse is 4 VPP and CFis 39 pF. The best value for the compensation capacitor should be established
after the board layout is finished because the value is dependent on board stray capacity, the value of the
feedback resistor, the closed loop gain and, to some extent, the supply voltage.
Another effect that is common to all op amps is the phase shift caused by the feedback resistor and the input
capacitance. This phase shift also reduces phase margin. This effect is taken care of at the same time as the
effect of the capacitive load when the capacitor is placed across the feedback resistor.
The circuit shown in Figure 33 was used for Figure 31 and Figure 32.
Figure 31. Twenty-Volt Step Response:
with Cap Load (Top Trace)
without Cap Load (Bottom Trace)
Figure 32. Four-Volt Step Response:
with Cap Load (Top Trace)
without Cap Load (Bottom Trace)
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Enhanced Slew Rate (continued)
Figure 33. Cap Load Test Circuit
Figure 34 shows a method for compensating for load capacitance (CO) effects by adding both an isolation
resistor ROat the output and a feedback capacitor CFdirectly between the output and the inverting input pin.
Feedback capacitor CFcompensates for the pole introduced by ROand CO, minimizing ringing in the output
waveform while the feedback resistor RFcompensates for dc inaccuracies introduced by RO. Depending on the
size of the load capacitance, the value of ROis typically chosen to be between 100 Ωto 1 kΩ.
Figure 34. Capacitive Loading Compensation Technique
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7.3 Typical Applications
7.3.1 Three Op Amp Instrumentation Amp with Rail-to-Rail Input and Output
Using the LM6134, a 3 op amp instrumentation amplifier with rail-to-rail inputs and rail to rail output can be made.
These features make these instrumentation amplifiers ideal for single supply systems.
Some manufacturers use a precision voltage divider array of 5 resistors to divide the common-mode voltage to
get an input range of rail-to-rail or greater. The problem with this method is that it also divides the signal, so to
even get unity gain, the amplifier must be run at high closed loop gains. This raises the noise and drift by the
internal gain factor and lowers the input impedance. Any mismatch in these precision resistors reduces the CMR
as well. Using the LM6134, all of these problems are eliminated.
In this example, amplifiers A and B act as buffers to the differential stage (Figure 35). These buffers assure that
the input impedance is over 100 MΩand they eliminate the requirement for precision matched resistors in the
input stage. They also assure that the difference amp is driven from a voltage source. This is necessary to
maintain the CMR set by the matching of R1–R2 with R3–R4.
Figure 35. Instrumentation Amplifier
7.3.2 Flat Panel Display Buffering
Three features of the LM6132/34 make it a superb choice for TFT LCD applications. First, its low current draw
(360 μA per amplifier at 5 V) makes it an ideal choice for battery powered applications such as in laptop
computers. Second, since the device operates down to 2.7 V, it is a natural choice for next generation 3V TFT
panels. Last, but not least, the large capacitive drive capability of the LM6132 comes in very handy in driving
highly capacitive loads that are characteristic of LCD display drivers.
The large capacitive drive capability of the LM6132/34 allows it to be used as buffers for the gamma correction
reference voltage inputs of resistor-DAC type column (Source) drivers in TFT LCD panels. This amplifier is also
useful for buffering only the center reference voltage input of Capacitor-DAC type column (Source) drivers such
as the LMC750X series.
Since for VGA and SVGA displays, the buffered voltages must settle within approximately 4 μs, the well known
technique of using a small isolation resistor in series with the amplifier's output very effectively dampens the
ringing at the output.
With its wide supply voltage range of 2.7 V to 24 V, the LM6132/34 can be used for a diverse range of
applications. The system designer is thus able to choose a single device type that serves many sub-circuits in
the system, eliminating the need to specify multiple devices in the bill of materials. Along with its sister parts, the
LM6142 and LM6152 that have the same wide supply voltage capability, choice of the LM6132 in a design
eliminates the need to search for multiple sources for new designs.
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8 Device and Documentation Support
8.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 1. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
LM6132 Click here Click here Click here Click here Click here
LM6134 Click here Click here Click here Click here Click here
8.2 Trademarks
All trademarks are the property of their respective owners.
8.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
8.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
9 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
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PACKAGE OPTION ADDENDUM
www.ti.com 22-Feb-2020
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM6132AIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LM61
32AIM
LM6132AIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LM61
32AIM
LM6132AIMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LM61
32AIM
LM6132AIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LM61
32AIM
LM6132BIM NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LM61
32BIM
LM6132BIM/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LM61
32BIM
LM6132BIMX NRND SOIC D 8 2500 TBD Call TI Call TI -40 to 85 LM61
32BIM
LM6132BIMX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LM61
32BIM
LM6132BIN/NOPB ACTIVE PDIP P 8 40 Green (RoHS
& no Sb/Br) Call TI | SN Level-1-NA-UNLIM -40 to 85 LM6132
BIN
LM6134AIM NRND SOIC D 14 55 TBD Call TI Call TI -40 to 85 LM6134AIM
LM6134AIM/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LM6134AIM
LM6134AIMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LM6134AIM
LM6134BIM NRND SOIC D 14 55 TBD Call TI Call TI -40 to 85 LM6134BIM
LM6134BIM/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LM6134BIM
LM6134BIMX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) SN Level-1-260C-UNLIM -40 to 85 LM6134BIM
LM6134BIN/NOPB ACTIVE PDIP NFF 14 25 Green (RoHS
& no Sb/Br) SN Level-1-NA-UNLIM -40 to 85 LM6134BIN
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PACKAGE OPTION ADDENDUM
www.ti.com 22-Feb-2020
Addendum-Page 2
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM6132AIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM6132AIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM6132BIMX SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM6132BIMX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LM6134AIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LM6134BIMX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM6132AIMX SOIC D 8 2500 367.0 367.0 35.0
LM6132AIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM6132BIMX SOIC D 8 2500 367.0 367.0 35.0
LM6132BIMX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LM6134AIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0
LM6134BIMX/NOPB SOIC D 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 29-Sep-2019
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
.228-.244 TYP
[5.80-6.19]
.069 MAX
[1.75]
6X .050
[1.27]
8X .012-.020
[0.31-0.51]
2X
.150
[3.81]
.005-.010 TYP
[0.13-0.25]
0 - 8 .004-.010
[0.11-0.25]
.010
[0.25]
.016-.050
[0.41-1.27]
4X (0 -15 )
A
.189-.197
[4.81-5.00]
NOTE 3
B .150-.157
[3.81-3.98]
NOTE 4
4X (0 -15 )
(.041)
[1.04]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES:
1. Linear dimensions are in inches [millimeters]. Dimensions in parenthesis are for reference only. Controlling dimensions are in inches.
Dimensioning and tolerancing per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not
exceed .006 [0.15] per side.
4. This dimension does not include interlead flash.
5. Reference JEDEC registration MS-012, variation AA.
18
.010 [0.25] C A B
5
4
PIN 1 ID AREA
SEATING PLANE
.004 [0.1] C
SEE DETAIL A
DETAIL A
TYPICAL
SCALE 2.800
www.ti.com
EXAMPLE BOARD LAYOUT
.0028 MAX
[0.07]
ALL AROUND
.0028 MIN
[0.07]
ALL AROUND
(.213)
[5.4]
6X (.050 )
[1.27]
8X (.061 )
[1.55]
8X (.024)
[0.6]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
6. Publication IPC-7351 may have alternate designs.
7. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
METAL SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
SOLDER MASK DETAILS
EXPOSED
METAL
OPENING
SOLDER MASK METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED
METAL
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:8X
SYMM
1
45
8
SEE
DETAILS
SYMM
www.ti.com
EXAMPLE STENCIL DESIGN
8X (.061 )
[1.55]
8X (.024)
[0.6]
6X (.050 )
[1.27] (.213)
[5.4]
(R.002 ) TYP
[0.05]
SOIC - 1.75 mm max heightD0008A
SMALL OUTLINE INTEGRATED CIRCUIT
4214825/C 02/2019
NOTES: (continued)
8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
9. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON .005 INCH [0.125 MM] THICK STENCIL
SCALE:8X
SYMM
SYMM
1
45
8
MECHANICAL DATA
N0014A
www.ti.com
N14A (Rev G)
NFF0014A
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