intel 2764A 64K (8K x 8) UV ERASABLE PROMs m Fast Access TimeHMOS* il E B intgligent Identifier Mode 180 ns Cerdip D2764A-1 @ Industry Standard Pinout ... JEDEC m Moisture Resistant Approved ... 28 Lead Package a Two-line Control (See Packaging Spec, Order #231369) The Intel 2764<A is a 5V only, 65,536-bit electrically programmable read-only memory (EPROM). The 2764A is fabricated with Intels HMOSII-E technology which significantly reduces die size and greatly improves the devices performance, power consumption, reliability and producibility. The 2764A provides access times to 180 ns (2764A-1). This is compatible with high-performance microproces- sors, such as Intels 8 MHz iAPX 186 allowing full speed operation without the addition of WAIT states. The 2764<A is also directly compatible with the 12 MHz 8051 family. Two-line control and JEDEC-approved, 28 pin packaging are standard features of Intel higher density EPROMs. This assures easy microprocessor interfacing and minimum design efforts when upgrading, adding, or choosing between non-volatile memory alternatives. *HMOS is a patented process of Intel Corporation. v DATA OUTPUTS cc Qo-0, GNO o___ a oT LTT OE e>| OUTPUT ENABLE }> PGM e| CHIP ENABLE ce AND OUTPUT BUFFERS PROG LOGIC 1 pECODER ae Y-GATING Ao~Ai2 . > ADORESS {> x : INPUTS J *| $ 65,536-BIT e| DECODER CELL MATRIX | e P > 230864-1 Figure 1. Block Diagram September 1989 5-18 Order Number: 230864-006intel 2764A Pin Names Ag-At2 Addresses CE Chip Enable OE Output Enable Oo-O7 Outputs PGM Program N.C. No Connect 27512 27256 27128A 27128A 27256 27512 71 270512 270256 270128 27328 2716 2716 2732A 270128 270256 270512 Ans Vpp Vpp Voc Vec Veo Ara Ai2 Ai2 PGM Ata Ara Ay A? Az Ay Az Voc Voc Aig Aig Aig Ae 46 Ag As As Ag Ag Ag Ag Ag As As As As As Ag Ag Ag Ag Ag Aa Ag Aa Aa Ag Vpp An An Ay Ay Ag Ag Ag Ag Ag OE | OE/Vpp OE OE OE/Vpp Aa Ag Aa Aa Az A1o Ato Ato Ai Ato Ay Ay Ay Ay Ay CE CE CE cE CE Ag Ag Ao Ao Ao 07 O7 O7 07 O7 Qo Qo Qo Oo Qo O6 Os Og O6 O6 O71 Oy Or 0; O1 Os Os Os Os Os Oe Oa Oo O02 Oo Og O4 O4 O4 Og GND GND GND GND GND Og Og Og O43 Og NOTE: Intel Universal Site-Compatible EPROM pin configurations are shown in the blocks adjacent to the 2764A pins. Figure 2. Cerdip Pin Configurationintel 2764A EXTENDED TEMPERATURE (EXPRESS) EPROMs The Intel EXPRESS EPROM family is a series of electrically programmable read only memories which have received additional processing to enhance product characteristics. EXPRESS processing is available for several densities of EPROM, allowing the choice of appropriate memory size to match sys- tem applications. EXPRESS EPROM products are EXPRESS EPROM PRODUCT FAMILY available with 168 +8 hour, 125C dynamic burn-in using Intels standard bias configuration. This pro- cess exceeds or meets most industry specifications of burn-in. The standard EXPRESS EPROM operat- ing temperature range is 0C to 70C. Extended op- erating temperature range ( 40C to + 85C) EX- PRESS products are available. Like all Intel EPROMs, the EXPRESS EPROM family is inspected to 0.1% electrical AQL. This may allow the user to reduce or eliminate incoming inspection testing. EXPRESS OPTIONS PRODUCT DEFINITIONS 2764A VERSIONS Type | Operating Temperature | Burn-in 125C (hr) Packaging Options Q OC to + 70C 168 +8 Speed Versions Cerdip T 40C to + 85C None 20 QTL L 40C to + 85C 168 +8 READ OPERATION D.C. CHARACTERISTICS Electrical parameters of EXPRESS EPROM products are identical to standard EPROM parameters except for: TD2764A Symbol Parameter LD2764A Test Conditions Min Max Isp Voc Standby Current (mA) 40 CE = Vin, OE = Vi Ico, Voc Active Current (mA) 100 OF = CE = Vit Voc Active Current 75 OE = CE = Vit at High Temperature (mA) Vep = Voc, Tambient = 85C NOTE: 4, The maximum current value is with outputs Op to O7 unloaded. Ys Vpp 281 Voc Ayo O42 271 Pow a, 3 26 NC Ag C44 25 Ag Ag (5 2410 Ag 4,6 23 Ant 4,017 222 OE dq a 7 Dao 4 C9 20E CE Yer Vee pod 10 19 N 07 Q N " 18 " % Oy N 12 17 Nw Os 02 13 16 " % Yss C14 18 N O3 230864-9 OE = +5V R=1KNQ Veg = +5V Vpp = +5V Vgg = GND CE = GND PGM = +5V 30 us PLP J-LSI e e Ate 230864-10 Binary Sequence from Ag to Ay2 Burn-in Bias and Timing Diagrams 5-20intel 2764A ABSOLUTE MAXIMUM RATINGS* Operating Temperature During Read .................05- oC to + 70C Temperature Under Bias......... 10C to + 80C Storage Temperature .......... 65C to + 125C All Inputs or Output Voltages with Respect to Ground........... 0.6V to + 6.25V Voltage on Pin 24 with Respect to Ground........... 0.6V to +13.5V Vpp Supply Voltage with Respect to Ground During Programming ......... 0.6V to + 14.0V READ OPERATION D.C. CHARACTERISTICS 0C < Ta < +70C Voc Supply Voltage with Respect to Ground ...............0.00 0.6V to +7.0V NOTICE: This is a production data sheet. The specifi- cations are subject to change without notice. *WARNING: Stressing the device beyond the Absolute Maximum Ratings may cause permanent damage. These are stress ratings only. Operation beyond the Operating Conditions is not recommended and ex- tended exposure beyond the Operating Conditions may affect device reliability. Symbol Parameter Limits Conditions Min Max Unit tu Input Load Current 10 BA Vin = OV to Voc lo Output Leakage Current 10 nA Vout = OV to Voc Ipp(2) Vpp Current Read 5 mA Vpp = 5.5V Isp Voc Current Standby 35 mA CE = Vin loc) Voc Current Active 75 mA CE = OF = Wit Vit input Low Voltage -0.1 +0.8 Vv VIH Input High Voltage 2.0 Voc + 1 v VoL Output Low Voltage 0.45 v lo, = 2.1 mA Von Output High Voltage 2.4 v lon = 400 pA Vpp(2) Vpp Read Voltage 3.8 Voc v Voc = 5.0V +0.25V A.C. CHARACTERISTICS 0C < Ta < +70C Versions(4) Veco + 5% 2764A-1 2764A-2 27644 Test Voc + 10% 2764A-20 2764A-25 Unit Conditions Symbol Parameter Min Max Min Max Min Max tacc Address to 180 200 250 ns CE=OE=ViL Output Delay tor CE to Output 180 200 250 ns OE=ViL Delay : toe OE to Output 65 75 100 ns CE=Vit Delay tor@) OE High to 0 55 0 55 0 60 ns CE=ViL Output Float ton) Output Hoid 0 0 0 ns CE=OE=ViL trom Address, CE or OE Whichever Occurred First NOTES: 1. Vec must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 2. Vpp may be connected directly to Voc except during programming. The supply current would then be the sum of loc and ipp. The maximum current value is with outputs Oo to O7 unloaded. 3. This parameter is only sampled and is not 100% tested. Output Data Float is defined as the point where data is no longer drivensee timing diagram on the following page. 4. Model Number Prefixes: No prefix = CERDIP. 5-212764A CAPACITANCEQ(2) (T, = 25C, f = 1 MHz) Symbol Parameter Typ (1) | Max | Unit | Conditions Cin Input Capacitance 4 6 pF | Vin = OV Cout Output Capacitance 8 12 pF | Vout = OV A.C. TESTING INPUT/OUTPUT WAVEFORM A.C. TESTING LOAD CIRCUIT 24 2.0 i 2.0 INPUT . TEST POINTS QUTPUT Kes = 4 <X 0.8 45 0.45 230864 -3 A.C. Testing; Inputs are Driven at 2.4V for a Logic 1 and 0.45V for a Logic 0. Timing Measurements are made at 2.0V for a Logic 1 and 0.8V for a Logic 0. 1.3 1NO14 3.3Ki2 DEVICE UNDER Test our Cy = 100 pF I 230864 -4 C, = 100 pF C, Includes Jig Capacitance A.C. WAVEFORMS Vin - eee - - ADORESS ADDRESSES VALID Vin N evee I CE a to > | Ve oe vm Lee Ale <1 _""_>} tace ton |?) } <_ io oo 0 HIGH Z TTT 7, HIGH Z OUTPUT VALID OUTPUT AAA. 230864 -5 NOTES: 1. Typical values are for Ta = 25C and nominal supply voltages. 2. This parameter is only sampled and is not 100% tested. 3. OE may be delayed up to tce-tog after the falling edge of CE without impact on tce. 5-22intel 2764A DEVICE OPERATION The modes of operation of the 2764A are listed in Table 1. A single 5V power supply is required in the read mode. All inputs are TTL levels except for Vop and 12V on Ag for intgligent identifier mode. Table 1. Mode Selection Pins| __ ee CE|OE|PGM! Ag | Ao | Vpp| Voc | Outputs Mode Read Vind Vic} Vin | XO] X [Vee] 5.0V] Dout Output Disable Vic} Vint Vin | X + X [Voc] 5.0V] High Z Standby Vint X | xX | xX |X [Vog]5.0v] High Z Programming VuiMetl Vi] X | X | (4) ] 4) Ow Program Verify Vic| Vir} Vin x X | (4) 1 (4) | Dour Program Inhibit Vif X41 X 7 x EX | a) | (4) | High Z intgligent Identifier(3) manufacturer Vir} Vic) Yiu |Vu(2)] Vi} Voc] 5.0V} 89H device Vic} Mir} Vig | Vu] Vie! oc] 5.0V} 08H NOTES: 1. X can be Viq or Vi. 2. VH = 12.0V+0.5V. 3. Ay-Ag, A1o-At2 = Vit. 4. See Table 2 for Voc and Vpp voltages. Read Mode The 2764A has two control functions, both of which must be logically active in order to obtain data at the outputs. Chip Enable (CE) is the power control and should be used for device selection. Output Enable (QE) is the output contro! and should be used to gate data from the output pins, independent of de- vice selection. Assuming that addresses are stable, the address access time (tacc) is equal to the delay from CE to output (tc). Data is available at the out- puts after a delay of tog from the falling edge of OE, assuming that CE has been low and addresses have been stable for at least tacc-toe. Standby Mode EPROMs can be placed in a standby mode which reduces the maximum current of the devices by ap- plying a TTL-high signal to the CE input. When in the standby mode, the outputs are in a high impedance state, independent of the OE input. Two Line Output Control Because EPROMs are usually used in larger memo- ry arrays, Intel has provided 2 control lines which accommodate this multiple memory connection. The two control lines allow for: a) the lowest possible memory power dissipation, and b) complete assurance that output bus contention will not occur. 5-23 To use these two control lines most efficiently, CE should be decoded and used as the primary device selecting function, while OE should be made a com- mon connection to all devices in the array and con- nected to the READ line from the system control bus. This assures that allt deselected memory devic- es are in their low power standby mode and that the output pins are active only when data is desired from a particular memory device. SYSTEM CONSIDERATIONS The power switching characteristics of EPROMs re- quire careful decoupling of the devices. The supply current, Icc, has three segments that are of interest to the system designerthe standby current level, the active current level, and the transient current peaks that are produced by the falling and rising edges of Chip Enable. The magnitude of these tran- sient current peaks is dependent on the output ca- pacitive and inductive loading of the device. The as- sociated transient voltage peaks can be suppressed by complying with Intels Two-Line Control and by properly selected decoupling capacitors. It is recom- mended that a 0.1 .F ceramic capacitor be used on every device between Voc and GND. This should be a high frequency capacitor of low inherent induc- tance and should be placed as close to the device as possible. In addition, a 4.7 wF bulk electrolytic capacitor should be used between Vcc and GND for every eight devices. The bulk capacitor should be located near where the power supply is connected to the array. The purpose of the bulk capacitor is to overcome the voltage droop caused by the inductive effect of PC board-traces. PROGRAMMING MODES Caution: Exceeding 14V on Vpp will permanently damage the device. Initially, all bits of the EPROM are in the 1 state. Data is introduced by selectively programming Os into the desired bit locations. Although only Os will be programmed, both 1s and Os can be present in the data word. The only way to change a 0 toa 1 is by ultraviolet light exposure (Cerdip EPROMs). The device is in the programming mode when Vpp is raised to its programming voltage (see Table 2) and CE and PGM are both at TTL-low. The data to be programmed is applied 8 bits in parallel to the data output pins. The levels required for the address and data inputs are TTL.intel 2764A Program Inhibit Programming of multiple EPROMs in parallel with different data is easily accomplished by using the Program Inhibit mode. A high-level CE or PGM input inhibits the other devices from being programmed. Except for CE, all like inputs (including OE) of the parallel EPROMs may be common. A TTL low-level pulse applied to the CE input with Vpp at its pro- gramming voltage (see Table 2) will program the se- lected device. Program Verify A verify should be performed on the programmed bits to determine that they have been correctly pro- grammed. The verify is performed with OE at Vi, PGM at Vi and Vpp and Vcc at their programming voltages. inteligent identifier Mode The inteligent Identifier Mode allows the reading out of a binary code from an EPROM that will identify its manufacturer and type. This mode is intended for use by programming equipment for the purpose of automatically matching the device to be pro- grammed with its corresponding programming aigo- rithm. This mode is functional in the 25C +5C am- bient temperature range that is required when pro- gramming the device. To activiate this mode, the programming equipment must force 11.5V to 12.5V on address line AQ of the EPROM. Two identifier bytes may then be se- quenced from the device outputs by toggling ad- 5-24 dress line AO from Vi, to Viy. All other address lines must be held at Vi, during intgligent Identifier Mode. Byte 0 (AO = Vj_) represents the manufacturer code and byte 1(AO = Vj) the device identifier code. These two identifier bytes are given in Table 1. ERASURE CHARACTERISTICS The erasure characteristics are such that erasure begins to occur upon exposure to light with wave- lerigths shorter than approximately 4000 Angstroms (A). It should be noted that sunlight and certain types of fluorescent lamps have wavelengths in the 3000-4000 A range. Data shows that constant ex- posure to room level fluorescent lighting could erase the EPROM in approximately three years, while it would take approximately one week to cause era- sure when exposed to direct sunlight. If the EPROM is to be exposed to these types of lighting conditions for extended periods of time, opaque labels should be placed over the window to prevent unintentional erasure. The recommended erasure procedure is exposure to shortwave ultraviolet light which has a wavelength of 2537 Angstroms (A). The integrated dose (i.e., UV intensity < exposure time) for erasure should be a minimum of fifteen (15) Wsec/cm?: The erasure time with this dosage is approximately 15 to 20 min- utes using an ultraviolet lamp with a 12,000 pW/cm2 power rating. The EPROM should be placed within one inch of the lamp tubes during erasure. The maxi- mum integrated dose an EPROM can be exposed to without damage is 7258 Wsec/cm2 (1 week @ 12000 W/cm2). Exposure of the EPROM to high intensity UV light for longer periods may cause per- manent damage.2764A START ADDA = FIRST LOCATION Voc = 6.0V Vee = 12.5 PROGRAM ONE | msec PULSE INCREMENT X INCREMENT ADOR COMPARE ALL BYTES TO ORIGINAL DATA DEVICE PASSED DEVICE FAILED DEVICE FAILED 230864-7 Figure 3. inteligent Programming Flowchart inteligent Programming Algorithm The intgligent Programming Algorithm, a standard in the industry for the past few years, is required for all of intels 12.5V CERDIP EPROMs. Plastic EPROMs may also be programmed using this method. A flow- chart of the intgligent Programming Algorithm is shown in Figure 3. The intgligent Programming Algorithm utilizes two different pulse types: initial and overprogram. The duration of the initial PGM pulse(s) is one millisec- ond, which will then be followed by a longer overpro- 5-25 gram pulse of length 3X msec. X is an iteration coun- ter and is equal to the number of the initial one milli- second puises applied to a particular location, be- fore a correct verify occurs. Up to 25 one-millisec- ond pulses per byte are provided for before the over- program pulse is applied. The entire sequence of program pulses and byte verifications is performed at Vcc = 6.0V and Vpp = 12.5V. When the intgligent Programming cy- cle has been completed, all bytes should be com- pared to the original data with Vcc = Vpp = 5.0V.intel 2764A Table 2 D.c. PROGRAMMING CHARACTERISTICS T, = 25C +5C Limits Test Conditions Symbol Parameter Min Max Unit (see Note 1) IL Input Current (All Inputs) 10 pA Vin = Vitor Vin Vit Input Low Level (All inputs) 0.1 0.8 Vv Vin Input High Level 2.0 Voc Vv VoL Output Low Voltage During Verify 0.45 v lon = 2.1MA VoH Output High Voltage During Verify 2.4 Vv lon = 400 pA Ieco4) Voc Supply Current (Program & Verify) 75 mA Ippol4) Vpp Supply Current (Program) 50 mA CE = Vi. Vip Ag intgligent Identifier Voltage 11.6 12.5 Vv Vpp intgligent Programming Algorithm 12.0 13.0 V CE = PGM = Vit Voc inteligent Programming Algorithm 5.75 6.25 Vv A.C. PROGRAMMING CHARACTERISTICS Ta = 25C +5C (see table 2 for Voc and Vpp voltages) Limits Test Conditions* Symbol Parameter Min Typ Max Unit (see Note 1) tas Address Setup Time 2 ps toes OE Setup Time 2 BS tps Data Setup Time 2 ps taH Address Hold Time 0 ys tow Data Hold Time 2 us tpFp OE High to Output 0 130 ns (See Note 3) Float Delay tyes Vpp Setup Time 2 ps tycs Voc Setup Time 2 ps tcEs CE Setup Time 2 BS tpw PGM Initial Program Pulse Width | 0.95 1.0 1.05 ms topw PGM Overprogram Pulse Width 2.85 78.75 ms (see Note 2) toe Data Valid from OE 150 ns NOTES: *A.C. CONDITIONS OF TEST Input Rise and Fall Times (10% t0 90%). cee eee 20 ns Input Pulse Levels .................. 0.46V to 2.4V Input Timing Reference Level ....... 0.8V and 2.0V Output Timing Reference Level ...... 0.8V and 2.0V 5-26 1. Voc must be applied simultaneously or before Vpp and removed simultaneously or after Vpp. 2. The length of the overprogram pulse may vary from 2.85 msec to 78.75 msec as a function of the iteration counter value X. 3. This parameter is only sampled and is not 100% tested. Output Float is defined as the point where data is no long- er drivensee timing diagram. 4. The maximum current value is with Outputs Og to O7 unloaded.intel 2764A PROGRAMMING WAVEFORMS PROGRAM VERIFY Vin i ADDRESSES x ADORESS STABLE Vie - ve e tas e] pe tan f " ve DATA pavainstaste |. High Z d DATA OUT VALID as q fae: tops om _~ Hm toep 12.5 y __/ 5.0V a typg o > 6.0V __/ Sov pa tycs e} Vin cE 2 Yin = ces Yh regen 2 re \ A Vn ~ itpw <? [> tots =| Vin po tor m OE ~| topw be \ Vu 230864 -8 NOTES: 1, The input timing reference level is 0.8V for Vi_ and 2V for a Vin. 2. tog and tprp are characteristics of the device but must be accommodated by the programmer. 3. When programming the 2764A, a 0.1 yF capacitor is required across Vpp and ground to suppress spurious voitage transients which can damage the device. REVISION HISTORY Number Description 06 Deleted Plastic DIP package. Deleted QuickPulse sections. Revised Pin Configuration. Revised Express options. Deleted ~3, 30, 4 and 45 speed bins. D.C. Characteristics - I_| Conditions are Viy = OV to Voc D.C. Characteristics - Lg Conditions are Vout = OV to Vcc 5-27