Hitachi Single-Chip Microcomputer
H8/3534
HD6433534
H8/3522
HD6433522
Hardware Manual
Notice
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the
whole or part of this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from
accidents or any other reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the
characteristics and performance of Hitachi’s semiconductor products. Hitachi assumes no
responsibility for any intellectual property claims or other problems that may result from
applications based on the examples described herein.
5. No license is granted by implication or otherwise under any patents or other rights of any
third party or Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales
company. Such use includes, but is not limited to, use in life support systems. Buyers of
Hitachi’s products are requested to notify the relevant Hitachi sales offices when planning to
use the products in MEDICAL APPLICATIONS.
i
Contents
Preface....... .....................................................................................................1
Section 1 Overview........................................................................................3
1.1 Overview ........................................................................................................................3
1.2 Block Diagram................................................................................................................6
1.3 Pin Assignments and Functions.......................................................................................8
1.3.1 Pin Arrangement................................................................................................8
1.3.2 Pin Functions.....................................................................................................11
Section 2 CPU................................................................................................23
2.1 Overview ........................................................................................................................23
2.1.1 Features.............................................................................................................23
2.1.2 Address Space....................................................................................................24
2.1.3 Register Configuration.......................................................................................24
2.2 Register Descriptions......................................................................................................25
2.2.1 General Registers...............................................................................................25
2.2.2 Control Registers...............................................................................................25
2.2.3 Initial Register Values .......................................................................................26
2.3 Data Formats...................................................................................................................27
2.3.1 Data Formats in General Registers.....................................................................28
2.3.2 Memory Data Formats.......................................................................................29
2.4 Addressing Modes...........................................................................................................30
2.4.1 Addressing Mode...............................................................................................30
2.4.2 Calculation of Effective Address........................................................................32
2.5 Instruction Set.................................................................................................................36
2.5.1 Data Transfer Instructions..................................................................................38
2.5.2 Arithmetic Operations........................................................................................42
2.5.3 Logic Operations ...............................................................................................43
2.5.4 Shift Operations.................................................................................................43
2.5.5 Bit Manipulations ..............................................................................................45
2.5.6 Branching Instructions.......................................................................................50
2.5.7 System Control Instructions...............................................................................52
2.5.8 Block Data Transfer Instruction.........................................................................53
2.6 CPU States......................................................................................................................55
2.6.1 Overview...........................................................................................................55
2.6.2 Program Execution State....................................................................................56
2.6.3 Exception-Handling State ..................................................................................56
2.6.4 Power-Down State.............................................................................................56
2.7 Access Timing and Bus Cycle.........................................................................................57
ii
2.7.1 Access to On-Chip Memory (RAM and ROM) ..................................................57
2.7.2 Access to On-Chip Supporting Modules and External Devices..........................59
Section 3 MCU Operating Modes and Address Space....................................63
3.1 Overview........................................................................................................................63
3.1.1 Mode Selection.................................................................................................. 63
3.1.2 Mode and System Control Registers ..................................................................64
3.2 System Control Register (SYSCR)..................................................................................64
3.3 Mode Control Register (MDCR)..................................................................................... 66
3.4 Address Space Map in Each Operating Mode.................................................................. 67
Section 4 Exception Handling........................................................................69
4.1 Overview........................................................................................................................69
4.2 Reset...............................................................................................................................69
4.2.1 Overview........................................................................................................... 69
4.2.2 Reset Sequence.................................................................................................. 69
4.2.3 Disabling of Interrupts after Reset .....................................................................72
4.3 Interrupts ........................................................................................................................72
4.3.1 Overview........................................................................................................... 72
4.3.2 Interrupt-Related Registers ................................................................................75
4.3.3 External Interrupts............................................................................................. 79
4.3.4 Internal Interrupts.............................................................................................. 80
4.3.5 Interrupt Handling .............................................................................................81
4.3.6 Interrupt Response Time....................................................................................86
4.3.7 Precaution.......................................................................................................... 86
4.4 Note on Stack Handling.................................................................................................. 87
Section 5 Wait-State Controller......................................................................89
5.1 Overview........................................................................................................................89
5.1.1 Features.............................................................................................................89
5.1.2 Block Diagram ..................................................................................................90
5.1.3 Input/Output Pins...............................................................................................91
5.1.4 Register Configuration.......................................................................................91
5.2 Register Description........................................................................................................91
5.2.1 Wait-State Control Register (WSCR)................................................................. 91
5.3 Wait Modes ....................................................................................................................93
Section 6 Clock Pulse Generator....................................................................97
6.1 Overview........................................................................................................................97
6.1.1 Block Diagram ..................................................................................................97
6.1.2 Wait-State Control Register (WSCR)................................................................. 98
6.2 Oscillator Circuit ............................................................................................................99
6.3 Duty Adjustment Circuit................................................................................................. 104
iii
6.4 Prescaler .........................................................................................................................104
Section 7 I/O Ports..........................................................................................105
7.1 Overview ........................................................................................................................105
7.2 Port 1..............................................................................................................................109
7.2.1 Overview...........................................................................................................109
7.2.2 Register Configuration and Descriptions............................................................111
7.2.3 Pin Functions in Each Mode ..............................................................................113
7.2.4 Input Pull-Up Transistors...................................................................................115
7.3 Port 2..............................................................................................................................116
7.3.1 Overview...........................................................................................................116
7.3.2 Register Configuration and Descriptions............................................................118
7.3.3 Pin Functions in Each Mode ..............................................................................120
7.3.4 Input Pull-Up Transistors...................................................................................123
7.4 Port 3..............................................................................................................................124
7.4.1 Overview...........................................................................................................124
7.4.2 Register Configuration and Descriptions............................................................126
7.4.3 Pin Functions in Each Mode ..............................................................................128
7.4.4 Input Pull-Up Transistors...................................................................................130
7.5 Port 4..............................................................................................................................131
7.5.1 Overview...........................................................................................................131
7.5.2 Register Configuration and Descriptions............................................................132
7.5.3 Pin Functions.....................................................................................................134
7.6 Port 5..............................................................................................................................136
7.6.1 Overview...........................................................................................................136
7.6.2 Register Configuration and Descriptions............................................................136
7.6.3 Pin Functions.....................................................................................................138
7.7 Port 6..............................................................................................................................139
7.7.1 Overview...........................................................................................................139
7.7.2 Register Configuration and Descriptions............................................................141
7.7.3 Pin Functions.....................................................................................................143
7.7.4 Input Pull-Up Transistors [H8/3534]..................................................................147
7.8 Port 7..............................................................................................................................148
7.8.1 Overview...........................................................................................................148
7.8.2 Register Configuration and Descriptions............................................................148
7.9 Port 8 [H8/3534].............................................................................................................149
7.9.1 Overview...........................................................................................................149
7.9.2 Register Configuration and Descriptions............................................................150
7.9.3 Pin Functions.....................................................................................................151
7.10 Port 9 [H8/3534] · Port 4 [H8/3522]..............................................................................152
7.10.1 Overview.........................................................................................................152
7.10.2 Register Configuration and Descriptions..........................................................153
7.10.3 Pin Functions...................................................................................................155
iv
Section 8 16-Bit Free-Running Timer............................................................157
8.1 Overview........................................................................................................................157
8.1.1 Features.............................................................................................................157
8.1.2 Block Diagram ..................................................................................................158
8.1.3 Input and Output Pins ........................................................................................159
8.1.4 Register Configuration.......................................................................................160
8.2 Register Descriptions...................................................................................................... 161
8.2.1 Free-Running Counter (FRC).............................................................................161
8.2.2 Output Compare Registers A and B (OCRA and OCRB) ...................................162
8.2.3 Input Capture Registers A to D (ICRA to ICRD) ...............................................162
8.2.4 Timer Interrupt Enable Register (TIER).............................................................164
8.2.5 Timer Control/Status Register (TCSR)...............................................................166
8.2.6 Timer Control Register (TCR)........................................................................... 169
8.2.7 Timer Output Compare Control Register (TOCR).............................................. 171
8.3 CPU Interface.................................................................................................................172
8.4 Operation........................................................................................................................175
8.4.1 FRC Increment Timing......................................................................................175
8.4.2 Output Compare Timing....................................................................................177
8.4.3 FRC Clear Timing.............................................................................................178
8.4.4 Input Capture Timing ........................................................................................179
8.4.5 Timing of Input Capture Flag (ICF) Setting....................................................... 182
8.4.6 Setting of Output Compare Flags A and B (OCFA and OCFB).......................... 183
8.4.7 Setting of Timer Overflow Flag (OVF)..............................................................184
8.5 Interrupts ........................................................................................................................184
8.6 Sample Application.........................................................................................................185
8.7 Application Notes...........................................................................................................186
Section 9 8-Bit Timers...................................................................................191
9.1 Overview........................................................................................................................191
9.1.1 Features.............................................................................................................191
9.1.2 Block Diagram ..................................................................................................192
9.1.3 Input and Output Pins ........................................................................................193
9.1.4 Register Configuration.......................................................................................193
9.2 Register Descriptions...................................................................................................... 194
9.2.1 Timer Counter (TCNT)......................................................................................194
9.2.2 Time Constant Registers A and B (TCORA and TCORB) .................................194
9.2.3 Timer Control Register (TCR)........................................................................... 195
9.2.4 Timer Control/Status Register (TCSR)...............................................................198
9.2.5 Serial/Timer Control Register (STCR)...............................................................200
9.3 Operation........................................................................................................................201
9.3.1 TCNT Increment Timing................................................................................... 201
9.3.2 Compare-Match Timing.....................................................................................203
9.3.3 External Reset of TCNT ....................................................................................205
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9.3.4 Setting of Overflow Flag (OVF).........................................................................205
9.4 Interrupts ........................................................................................................................206
9.5 Sample Application.........................................................................................................206
9.6 Application Notes ...........................................................................................................207
9.6.1 Contention between TCNT Write and Clear.......................................................207
9.6.2 Contention between TCNT Write and Increment ...............................................208
9.6.3 Contention between TCOR Write and Compare-Match......................................209
9.6.4 Contention between Compare-Match A and Compare-Match B.........................210
9.6.5 Increment Caused by Changing of Internal Clock Source...................................210
Section 10 PWM Timers (H8/3534 Only) ......................................................213
10.1 Overview ......................................................................................................................213
10.1.1 Features ...........................................................................................................213
10.1.2 Block Diagram.................................................................................................214
10.1.3 Input and Output Pins ......................................................................................215
10.1.4 Register Configuration.....................................................................................215
10.2 Register Descriptions ....................................................................................................216
10.2.1 Timer Counter (TCNT)....................................................................................216
10.2.2 Duty Register (DTR)........................................................................................216
10.2.3 Timer Control Register (TCR) .........................................................................217
10.3 Operation......................................................................................................................219
10.3.1 Timer Increment..............................................................................................219
10.3.2 PWM Operation...............................................................................................220
10.4 Application Notes .........................................................................................................221
Section 11 Watchdog Timer...........................................................................223
11.1 Overview ......................................................................................................................223
11.1.1 Features ...........................................................................................................223
11.1.2 Block Diagram.................................................................................................224
11.1.3 Register Configuration.....................................................................................224
11.2 Register Descriptions ....................................................................................................225
11.2.1 Timer Counter (TCNT)....................................................................................225
11.2.2 Timer Control/Status Register (TCSR).............................................................225
11.2.3 Register Access................................................................................................227
11.3 Operation......................................................................................................................228
11.3.1 Watchdog Timer Mode....................................................................................228
11.3.2 Interval Timer Mode........................................................................................230
11.3.3 Setting the Overflow Flag................................................................................230
11.4 Application Notes .........................................................................................................231
11.4.1 Contention between TCNT Write and Increment .............................................231
11.4.2 Changing the Clock Select Bits (CKS2 to CKS0).............................................231
11.4.3 Recovery from Software Standby Mode...........................................................231
vi
Section 12 Serial Communication Interface ...................................................233
12.1 Overview ......................................................................................................................233
12.1.1 Features...........................................................................................................233
12.1.2 Block Diagram.................................................................................................235
Figure 12-1 shows a block diagram of one serial communication interface channel.....235
12.1.3 Input and Output Pins ......................................................................................236
12.1.4 Register Configuration..................................................................................... 237
12.2 Register Descriptions....................................................................................................238
12.2.1 Receive Shift Register (RSR)...........................................................................238
12.2.2 Receive Data Register (RDR) ..........................................................................238
12.2.3 Transmit Shift Register (TSR) .........................................................................238
12.2.4 Transmit Data Register (TDR).........................................................................239
12.2.5 Serial Mode Register (SMR)............................................................................239
12.2.6 Serial Control Register (SCR)..........................................................................242
12.2.7 Serial Status Register (SSR).............................................................................245
12.2.8 Bit Rate Register (BRR) ..................................................................................248
12.2.9 Serial/Timer Control Register (STCR).............................................................253
12.3 Operation...................................................................................................................... 254
12.3.1 Overview.........................................................................................................254
12.3.2 Asynchronous Mode........................................................................................256
12.3.3 Synchronous Mode ..........................................................................................270
12.4 Interrupts ...................................................................................................................... 278
12.5 Application Notes .........................................................................................................278
Section 13 A/D Converter..............................................................................281
13.1 Overview ......................................................................................................................281
13.1.1 Features...........................................................................................................281
13.1.2 Block Diagram.................................................................................................282
13.1.3 Input Pins.........................................................................................................283
13.1.4 Register Configuration..................................................................................... 284
13.2 Register Descriptions....................................................................................................285
13.2.1 A/D Data Registers A to D (ADDRA to ADDRD)........................................... 285
13.2.2 A/D Control/Status Register (ADCSR) ............................................................286
13.2.3 A/D Control Register (ADCR)......................................................................... 289
13.3 CPU Interface ...............................................................................................................290
13.4 Operation...................................................................................................................... 292
13.4.1 Single Mode (SCAN = 0).................................................................................292
13.4.2 Scan Mode (SCAN = 1)................................................................................... 294
13.4.3 Input Sampling and A/D Conversion Time ......................................................296
13.4.4 External Trigger Input Timing......................................................................... 298
13.5 Interrupts ...................................................................................................................... 298
13.6 Usage Notes..................................................................................................................298
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Section 14 RAM.............................................................................................299
14.1 Overview ......................................................................................................................299
14.1.1 Block Diagram.................................................................................................299
14.1.2 RAM Enable Bit (RAME) in System Control Register (SYSCR) .....................300
14.2 Operation......................................................................................................................300
14.2.1 Expanded Modes (Modes 1 and 2) ...................................................................300
14.2.2 Single-Chip Mode (Mode 3) ............................................................................300
Section 15 ROM.............................................................................................301
15.1 Overview ......................................................................................................................301
15.1.1 Block Diagram.................................................................................................302
Section 16 Power-Down State........................................................................303
16.1 Overview ......................................................................................................................303
16.1.1 System Control Register (SYSCR)...................................................................304
16.2 Sleep Mode...................................................................................................................306
16.2.1 Transition to Sleep Mode.................................................................................306
16.2.2 Exit from Sleep Mode......................................................................................306
16.3 Software Standby Mode................................................................................................306
16.3.1 Transition to Software Standby Mode..............................................................306
16.3.2 Exit from Software Standby Mode...................................................................307
16.3.3 Clock Settling Time for Exit from Software Standby Mode .............................307
16.3.4 Sample Application of Software Standby Mode..............................................308
16.3.5 Application Notes...........................................................................................308
16.4 Hardware Standby Mode...............................................................................................309
16.4.1 Transition to Hardware Standby Mode.............................................................309
16.4.2 Recovery from Hardware Standby Mode..........................................................309
16.4.3 Timing Relationships in Hardware Standby Mode ...........................................310
Section 17 Electrical Specifications................................................................311
17.1 Absolute Maximum Ratings..........................................................................................311
17.2 Electrical Characteristics...............................................................................................312
17.2.1 DC Characteristics...........................................................................................312
17.2.2 AC Characteristics...........................................................................................319
17.2.3 A/D Converter Characteristics .........................................................................322
17.3 MCU Operational Timing .............................................................................................323
17.3.1 Bus Timing......................................................................................................324
17.3.2 Control Signal Timing .....................................................................................325
17.3.3 16-Bit Free-Running Timer Timing .................................................................327
17.3.4 8-Bit Timer Timing..........................................................................................328
17.3.5 Pulse Width Modulation Timer Timing [H8/3534]...........................................329
17.3.6 Serial Communication Interface Timing ..........................................................330
17.3.7 I/O Port Timing ...............................................................................................331
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17.3.8 External Clock Output Timing.........................................................................331
Appendix A CPU Instruction Set ...................................................................333
A.1 Instruction Set List.........................................................................................................333
A.2 Operation Code Map...................................................................................................... 341
A.3 Number of States Required for Execution ......................................................................343
Appendix B Internal I/O Register...................................................................349
B.1 Addresses.......................................................................................................................349
B.1.1 Addresses for H8/3534...................................................................................... 349
B.1.2 Addresses for H8/3522...................................................................................... 354
B.2 Function......................................................................................................................... 358
Appendix C I/O Port Block Diagrams.............................................................407
C.1 Port 1 Block Diagram.....................................................................................................407
C.2 Port 2 Block Diagram.....................................................................................................408
C.3 Port 3 Block Diagram.....................................................................................................409
C.4 Port 4 Block Diagrams [H8/3534] ..................................................................................410
C.5 Port 5 Block Diagrams ...................................................................................................412
C.6 Port 6 Block Diagrams ...................................................................................................415
C.7 Port 7 Block Diagram.....................................................................................................426
C.8 Port 8 Block Diagrams ...................................................................................................427
C.9 Port 9 Block Diagrams [H8/3534] and Port 4 Block Diagrams [H8/3522].......................431
Appendix D Port States in Each Mode............................................................437
Appendix E
Timing of Transition to and Recovery from Hardware Standby Mode .............439
Appendix F Product Code Lineup..................................................................441
Appendix G Package Dimensions ..................................................................443
1
Preface
The H8/3534 and H8/3522 are high-performance microcontrollers with a fast H8/300 CPU core
and a set of on-chip supporting functions optimized for embedded control. The 80-pin H8/3534
includes 32-kbyte ROM, 1-kbyte RAM, four types of timers, a serial communication interface,
A/D converter, I/O ports, and other on-chip supporting functions needed in control system
configurations, so that compact, high-performance systems can be implemented easily. The 64-
pin H8/3522 is a subset version of the H8/3534, with 16-kbyte ROM, 512-byte RAM, and fewer
on-chip supporting functions.
In program development for the H8/3534 and H8/3522, development tools should be used that
support the H8/3394 and H8/3292-functional supersets of the H8/3534 and H8/3522-
respectively. The H8/3534 and H8/3522 are also available in ZTAT™*1 (zero turn-around time)
versions-the H8/3334Y and H8/3294-which are functional supersets of the H8/3534 and
H8/3522, respectively. These can be used effectively in program development and the initial
stage of volume production.
The H8/3534 and H8/3522 have functional supersets in the H8/3397 Series and H8/3297 Series,
respectively. The differences in terms of functions are that the lineup includes only one kind of
ROM and one kind of RAM, the maximum operating frequency is 10 MHz, and the current
dissipation values are not guaranteed in standby mode, one of the modes in the power-down
state.
The H8/3534 and H8/3522 are single-chip microcomputers designed for consumer applications.
If there is a need for ZTAT version or F-ZTATTM*2 version for larger ROM/RAM capacity, for
fast processing up to a maximum of 16 MHz, for drastically lower power consumption in
standby mode in portable application systems, etc., or for high reliability in automotive or
industrial applications, for instance, then the H8/3397 Series or H8/3297 Series should be used.
This manual describes the hardware of the H8/3534 and H8/3522. Refer to the H8/300 Series
Programming Manual for a detailed description of the instruction set, and to the H8/3397 Series,
H8/3337 Series, and H8/3334Y F-ZTAT Hardware Manual and the H8/3297 Series Hardware
Manual for details of the high-end product series including the ZTAT version.
Notes: 1. ZTAT is a trademark of Hitachi, Ltd.
2. F-ZTAT is a trademark of Hitachi, Ltd.
2
3
Section 1 Overview
1.1 Overview
The H8/3534 and H8/3522 single-chip microcomputers (MCUs: microcomputer units) feature an
H8/300 CPU core and a complement of on-chip supporting modules required for system
configuration.
The H8/300 CPU is a high-speed processor with an architecture featuring powerful bit-
manipulation instructions, ideally suited to realtime control applications. On-chip supporting
modules in the 80-pin H8/3534 include 32-kbyte ROM, 1-kbyte RAM, four types of timers (16-
bit free-running timer, two 8-bit timer channels, two PWM timer channels, and a watchdog
timer), two serial communication interface (SCI) channels, an A/D converter, and I/O ports. The
64-pin H8/3522 is a subset version of the H8/3534, with 16-kbyte ROM and 512-byte RAM, no
PWM timer, and only one SCI channel.
These microcomputers can operate in single-chip mode or two expanded modes, depending on
the requirements of the application.
In program development for the H8/3534 and H8/3522, development tools should be used that
support the functional-superset H8/3394 and H8/3292, respectively. As ZTAT™*1 (zero turn-
around time) versions, the H8/3334Y and H8/3294 ZTAT versions should be used. In this case,
registers, etc., related to superset functions should not be accessed. In particular, take care not to
write 1 to the HIE bit in SYSCR, the IICS, IICD, IICX, IICE, and STAC bits in STCR, and the
RAMS and RAM0 bits in WSCR.
Note: 1. ZTAT is a trademark of Hitachi, Ltd.
4
Table 1-1 Features
Item Specification
CPU Two-way general register configuration
• Eight 16-bit registers, or
• Sixteen 8-bit registers
High-speed operation
• Maximum clock rate (φ clock): 10 MHz at 5 V
• 8- or 16-bit register-register add/subtract: 200 ns (10 MHz)
• 8 × 8-bit multiply: 1400 ns (10 MHz)
• 16 ÷ 8-bit divide: 1400 ns (10 MHz)
Streamlined, concise instruction set
• Instruction length: 2 or 4 bytes
• Register-register arithmetic and logic operations
• MOV instruction for data transfer between registers and memory
Instruction set features
• Multiply instruction (8 bits × 8 bits)
• Divide instruction (16 bits ÷ 8 bits)
• Bit-accumulator instructions
• Register-indirect specification of bit positions
Memory • H8/3534: 32-kbyte ROM; 1-kbyte RAM
• H8/3522: 16-kbyte ROM; 512-byte RAM
16-bit free-
running timer
(1 channel)
• One 16-bit free-running counter (can also count external events)
• Two output-compare lines
• Four input capture lines (can be buffered)
8-bit timer
(2 channels) Each channel has
• One 8-bit up-counter (can also count external events)
• Two time constant registers
PWM timer
(2 channels)
(H8/3534 only)
• Duty cycle can be set from 0 to 100%
• Resolution: 1/250
Watchdog timer
(WDT)
(1 channel)
• Overflow can generate a reset or NMI interrupt
• Also usable as interval timer
Serial communication
interface (SCI)
(H8/3534: 2 channels
H8/3522: 1 channel)
• Asynchronous or synchronous mode (selectable)
• Full duplex: can transmit and receive simultaneously
• On-chip baud rate generator
5
Table 1-1 Features (cont)
Item Specification
Keyboard
controller
(H8/3534 only)
• Controls a matrix-scan keyboard by providing a keyboard scan function with
wake-up interrupts and sense ports
A/D converter • 10-bit resolution
• Eight channels: single or scan mode (selectable)
• Start of A/D conversion can be externally triggered
• Sample-and-hold function
I/O ports
(H8/3534) • 58 input/output lines (16 of which can drive LEDs)
• 8 input-only lines
I/O ports
(H8/3522) • 43 input/output lines (16 of which can drive LEDs)
• 8 input-only lines
Interrupts
(H8/3534) • Nine external interrupt lines:
10,
,
,54
0 to
,54
7
• 26 on-chip interrupt sources
Interrupts
(H8/3522) • Four external interrupt lines:
10,
,
,54
0 to
,54
2
• 19 on-chip interrupt sources
Wait control • Three selectable wait modes
Operating
modes • Expanded mode with on-chip ROM disabled (mode 1)
• Expanded mode with on-chip ROM enabled (mode 2)
• Single-chip mode (mode 3)
Power-down
modes • Sleep mode
• Software standby mode
• Hardware standby mode
Other features • On-chip oscillator
Series lineup Product Name Part Number Package ROM
H8/3534 HD6433534F10 80-pin QFP (FP-80A) Mask ROM
H8/3522 HD6433522F10 64-pin QFP (FP-64A)
HD6433522P10 64-pin shrink DIP (DP-64S)
6
1.2 Block Diagram
Figure 1-1 shows a block diagram of the H8/3534. Figure 1-2 shows a block diagram of the
H8/3522.
P90/ADTRG/IRQ2
P91/IRQ1
P92/IRQ0
P93/RD
P94/WR
P95/AS
P96/ø
P97/WAIT
P30/D0
P31/D1
P32/D2
P33/D3
P34/D4
P35/D5
P36/D6
P37/D7
P80
P81
P82
P83
P84/TxD1/IRQ3
P85/RxD1/IRQ4
P86/SCK1/IRQ5
P10/A0
P11/A1
P12/A2
P13/A3
P14/A4
P15/A5
P16/A6
P17/A7
P20/A8
P21/A9
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
P60/FTCI/KEYIN0
P61/FTOA/KEYIN1
P62/FTIA/KEYIN2
P63/FTIB/KEYIN3
P64/FTIC/KEYIN4
P65/FTID/KEYIN5
P66/FTOB/IRQ6/KEYIN6
P67/IRQ7/KEYIN7
P40/TMCI0
P41/TMO0
P42/TMRI0
P43/TMCI1
P44/TMO1
P45/TMRI1
P46/PW0
P47/PW1
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
P50/TxD0
P51/RxD0
P52/SCK0
AVCC
AVSS
XTAL
EXTAL
Port 9Port 3Port 8
Port 6 Port 2 Port 1
Port 4 Port 5
Data bus (low)
10-bit
A/D converter
(8 channels)
16-bit
free-running
timer
8-bit timer
(2 channels)
PWM timer
(2 channels)
Clock pulse
generator
Watchdog
timer
Serial
communication
interface
(2 channels)
CPU
H8/300
Data bus (high)
Address bus
ROM
32 kbytes RAM
1 kbytes
RES
STBY
NMI
MD0
MD1
VCC
VCC
VSS
VSS
VSS
Port 7
Figure 1-1 Block Diagram for H8/3534
7
P40/IRQ2/ADTRG
P41/IRQ1
P42/IRQ0
P43/RD
P44/WR
P45/AS
P46/ø
P47/WAIT
P30/D0
P31/D1
P32/D2
P33/D3
P34/D4
P35/D5
P36/D6
P37/D7
P10/A0
P11/A1
P12/A2
P13/A3
P14/A4
P15/A5
P16/A6
P17/A7
P20/A8
P21/A9
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
P60/FTCI/TMCI0
P61/FTOA
P62/FTIA
P63/FTIB/TMRI0
P64/FTIC/TMO0
P65/FTID/TMCI1
P66/FTOB/TMRI1
P67/TMO1
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
P50/TxD
P51/RxD
P52/SCK
AVCC
AVSS
XTAL
EXTAL
Port 4Port 3
Port 2 Port 1
Port 6 Port 7 Port 5
Data bus (low)
10-bit
A/D converter
(8 channels)
16-bit
free-running
timer
8-bit timer
(2 channels)
Clock pulse
generator
Watchdog
timer
Serial
communication
interface
CPU
H8/300
Data bus (high)
Address bus
RAM
512 bytes
ROM
16 kbytes
RES
STBY
NMI
MD0
MD1
VCC
VCC
VSS
VSS
Figure 1-2 Block Diagram for H8/3522
8
1.3 Pin Assignments and Functions
1.3.1 Pin Arrangement
Figure 1-3 shows the pin arrangement of the FP-80A package for the H8/3534.
Figure 1-4 and 1-5 show the pin arrangement of the FP-64A and DP-64S packages for the
H8/3522.
P14/A4
P15/A5
P16/A6
P17/A7
VSS
P20/A8
P21/A9
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P27/A15
VCC
P47/PW1
P46/PW0
P45/TMRI1
P44/TMO1
P43/TMCI1
P42/TMRI0
RES
XTAL
EXTAL
MD1
MD0
NMI
STBY
VCC
P52/SCK0
P51/RxD0
P50/TxD0
VSS
P97/WAIT
P96/ø
P95/AS
P94/WR
P93/RD
P92/IRQ0
P91/IRQ1
P90/ADTRG/IRQ2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
37
38
39
40
P86/IRQ5/SCK1
P85/IRQ4/RxD1
P84/IRQ3/TxD1
P83
P82
P81
P80
VSS
P37/D7
P36/D6
P35/D5
P34/D4
P33/D3
P32/D2
P31/D1
P30/D0
P10/A0
P11/A1
P12/A2
P13/A3
P60/KEYIN0/FTCI
P61/KEYIN1/FTOA
P62/KEYIN2/FTIA
P63/KEYIN3/FTIB
P64/KEYIN4/FTIC
P65/KEYIN5/FTID
P66/FTOB/KEYIN6/IRQ6
P67/KEYIN7/IRQ7
AVCC
P70/AN0
P71/AN1
P72/AN2
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
AVSS
P40/TMCI0
P41/TMO0
FP-80A
(top view)
Figure 1-3 Pin Arrangement for H8/3534 (FP-80A, Top View)
9
P10/A0
P11/A1
P12/A2
P13/A3
P14/A4
P15/A5
P16/A6
P17/A7
VSS
P20/A8
P21/A9
P22/A10
P23/A11
P24/A12
P25/A13
P26/A14
P50/TxD
P51/RxD
P52/SCK
RES
NMI
VCC
STBY
VSS
XTAL
EXTAL
MD1
MD0
AVSS
P70/AN0
P71/AN1
P72/AN2
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
P73/AN3
P74/AN4
P75/AN5
P76/AN6
P77/AN7
AVCC
P60/FTCI/TMCI0
P61/FTOA
P62/FTIA
P63/FTIB/TMRI0
P64/FTIC/TMO0
P65/FTID/TMCI1
P66/FTOB/TMRI1
P67/TMO1
VCC
P27/A15
P47/WAIT
P46/ø
P45/AS
P44/WR
P43/RD
P42/IRQ0
P41/IRQ1
P40/ADTRG/IRQ2
P37/D7
P36/D6
P35/D5
P34/D4
P33/D3
P32/D2
P31/D1
P30/D0
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
FP-64A
(top view)
Figure 1-4 Pin Arrangement for H8/3522 (FP-64A, Top View)
10
P4
0
/ADTRG/IRQ
2
P4
1
/IRQ
1
P4
2
/IRQ
0
P4
3
/RD
P4
4
/WR
P4
5
/AS
P4
6
/ø
P4
7
/WAIT
P5
0
/TxD
P5
1
/RxD
P5
2
/SCK
RES
NMI
V
CC
STBY
V
SS
XTAL
EXTAL
MD
1
MD
0
AV
SS
P7
0
/AN
0
P7
1
/AN
1
P7
2
/AN
2
P7
3
/AN
3
P7
4
/AN
4
P7
5
/AN
5
P7
6
/AN
6
P7
7
/AN
7
AV
CC
P6
0
/FTCI/TMCI
0
P6
1
/FTOA
P3
7
/D
7
P3
6
/D
6
P3
5
/D
5
P3
4
/D
4
P3
3
/D
3
P3
2
/D
2
P3
1
/D
1
P3
0
/D
0
P1
0
/A
0
P1
1
/A
1
P1
2
/A
2
P1
3
/A
3
P1
4
/A
4
P1
5
/A
5
P1
6
/A
6
P1
7
/A
7
V
SS
P2
0
/A
8
P2
1
/A
9
P2
2
/A
10
P2
3
/A
11
P2
4
/A
12
P2
5
/A
13
P2
6
/A
14
P2
7
/A
15
V
CC
P6
7
/TMO
1
P6
6
/FTOB/TMRI
1
P6
5
/FTID/TMCI
1
P6
4
/FTIC/TMO
0
P6
3
/FTIB/TMRI
0
P6
2
/FTIA
DP-64S
(top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
64
63
62
61
60
59
58
57
56
55
54
53
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
Figure 1-5 Pin Arrangement for H8/3522 (DP-64S, Top View)
11
1.3.2 Pin Functions
(1) Pin Assignments in Each Operating Mode: Tables 1-2 and 1-3 list the assignments of the
pins of the H8/3534’s FP-80A package and the H8/3522’s FP-64A and DP-64S packages in
each operating mode.
Table 1-2 Pin Assignments for H8/3534 in Each Operating Mode
Pin No. Expanded Modes Single-Chip Mode
FP-80A Mode 1 Mode 2 Mode 3
1
5(6 5(6 5(6
2 XTAL XTAL XTAL
3 EXTAL EXTAL EXTAL
4MD
1MD1MD1
5MD
0MD0MD0
6
10, 10, 10,
7
67%< 67%< 67%<
8V
CC VCC VCC
9P5
2
/SCK0P52/SCK0P52/SCK0
10 P51/RxD0P51/RxD0P51/RxD0
11 P50/TxD0P50/TxD0P50/TxD0
12 VSS VSS VSS
13 P97/
:$,7
P97/
:$,7
P97
14 φφ P96/φ
15
$6 $6
P95
16
:5 :5
P94
17
5' 5'
P93
18 P92/
,54
0P92/IRQ0P92/
,54
0
19 P91/
,54
1P91/
,54
1P91/
,54
1
20 P90/
$'75*
/IRQ2P90/
$'75*
/IRQ2P90/
$'75*
/IRQ2
21 P60/
.(<,1
0/FTCI P60/
.(<,1
0/FTCI P60/
.(<,1
0/FTCI
22 P61/
.(<,1
1/FTOA P61/
.(<,1
1/FTOA P61/
.(<,1
1/FTOA
23 P62/
.(<,1
2/FTIA P62/
.(<,1
2/FTIA P62/
.(<,1
2/FTIA
24 P63/
.(<,1
3/FTIB P63/
.(<,1
3/FTIB P63/
.(<,1
3/FTIB
25 P64/
.(<,1
4/FTIC P64/
.(<,1
4/FTIC P64/
.(<,1
4/FTIC
12
Table 1-2 Pin Assignments for H8/3534 in Each Operating Mode (cont)
Pin No. Expanded Modes Single-Chip Mode
FP-80A Mode 1 Mode 2 Mode 3
26 P65/
.(<,1
5/FTID P65/
.(<,1
5/FTID P65/
.(<,1
5/FTID
27 P66/FTOB/
.(<,1
6/
,54
6
P66/FTOB/
.(<,1
6/
,54
6
P66/FTOB/
.(<,1
6/
,54
6
28 P67/
.(<,1
7/
,54
7P67/
.(<,1
7/
,54
7P67/
.(<,1
7/
,54
7
29 AVCC AVCC AVCC
30 P70/AN0P70/AN0P70/AN0
31 P71/AN1P71/AN1P71/AN1
32 P72/AN2P72/AN2P72/AN2
33 P73/AN3P73/AN3P73/AN3
34 P74/AN4P74/AN4P74/AN4
35 P75/AN5P75/AN5P75/AN5
36 P76/AN6P76/AN6P76/AN6
37 P77/AN7P77/AN7P77/AN7
38 AVSS AVSS AVSS
39 P40/TMCI0P40/TMCI0P40/TMCI0
40 P41/TMO0P41/TMO0P41/TMO0
41 P42/TMRI0P42/TMRI0P42/TMRI0
42 P43/TMCI1P43/TMCI1P43/TMCI1
43 P44/TMO1P44/TMO1P44/TMO1
44 P45/TMRI1P45/TMRI1P45/TMRI1
45 P46/PW0P46/PW0P46/PW0
46 P47/PW1P47/PW1P47/PW1
47 VCC VCC VCC
48 A15 P27/A15 P27
49 A14 P26/A14 P26
13
Table 1-2 Pin Assignments for H8/3534 in Each Operating Mode (cont)
Pin No. Expanded Modes Single-Chip Mode
FP-80A Mode 1 Mode 2 Mode 3
50 A13 P25/A13 P25
51 A12 P24/A12 P24
52 A11 P23/A11 P23
53 A10 P22/A10 P22
54 A9P21/A9P21
55 A8P20/A8P20
56 VSS VSS VSS
57 A7P17/A7P17
58 A6P16/A6P16
59 A5P15/A5P15
60 A4P14/A4P14
61 A3P13/A3P13
62 A2P12/A2P12
63 A1P11/A1P11
64 A0P10/A0P10
65 D0D0P30
66 D1D1P31
67 D2D2P32
68 D3D3P33
69 D4D4P34
70 D5D5P35
71 D6D6P36
72 D7D7P37
73 VSS VSS VSS
74 P80P80P80
14
Table 1-2 Pin Assignments for H8/3534 in Each Operating Mode (cont)
Pin No. Expanded Modes Single-Chip Mode
FP-80A Mode 1 Mode 2 Mode 3
75 P81P81P81
76 P82P82P82
77 P83P83P83
78 P84/
,54
3/TxD1P84/
,54
3/TxD1P84/
,54
3/TxD1
79 P85/
,54
4/RxD1P85/
,54
4/RxD1P85/
,54
4/RxD1
80 P86/
,54
5/SCK1P86/
,54
5/SCK1P86/
,54
5/SCK1
15
Table 1-3 Pin Assignments for H8/3522 in Each Operating Mode
Pin No. Expanded Modes Single-Chip Mode
DP-64S FP-64A Mode 1 Mode 2 Mode 3
157P4
0
/
$'75*
/
,54
2P40/
$'75*
/
,54
2P40/
$'75*
/
,54
2
258P4
1
/
,54
1P41/
,54
1P41/
,54
1
359P4
2
/
,54
0P42/
,54
0P42/
,54
0
460
5' 5'
P43
561
:5 :5
P44
662
$6 $6
P45
763φφ P46/φ
864P4
7
/
:$,7
P47/
:$,7
P47
91P5
0
/TxD P50/TxD P50/TxD
10 2 P51/RxD P51/RxD P51/RxD
11 3 P52/SCK P52/SCK P52/SCK
12 4
5(6 5(6 5(6
13 5
10, 10, 10,
14 6 VCC VCC VCC
15 7
67%< 67%< 67%<
16 8 VSS VSS VSS
17 9 XTAL XTAL XTAL
18 10 EXTAL EXTAL EXTAL
19 11 MD1MD1MD1
20 12 MD0MD0MD0
21 13 AVSS AVSS AVSS
22 14 P70/AN0P70/AN0P70/AN0
23 15 P71/AN1P71/AN1P71/AN1
24 16 P72/AN2P72/AN2P72/AN2
25 17 P73/AN3P73/AN3P73/AN3
26 18 P74/AN4P74/AN4P74/AN4
27 19 P75/AN5P75/AN5P75/AN5
28 20 P76/AN6P76/AN6P76/AN6
29 21 P77/AN7P77/AN7P77/AN7
30 22 AVCC AVCC AVCC
31 23 P60/FTCI/TMCI0P60/FTCI/TMCI0P60/FTCI/TMCI0
32 24 P61/FTOA P61/FTOA P61/FTOA
16
Table 1-3 Pin Assignments for H8/3522 in Each Operating Mode (cont)
Pin No. Expanded Modes Single-Chip Mode
DP-64S FP-64A Mode 1 Mode 2 Mode 3
33 25 P62/FTIA P62/FTIA P62/FTIA
34 26 P63/FTIB/TMRI0P63/FTIB/TMRI0P63/FTIB/TMRI0
35 27 P64/FTIC/TMO0P64/FTIC/TMO0P64/FTIC/TMO0
36 28 P65/FTID/TMCI1P65/FTID/TMCI1P65/FTID/TMCI1
37 29 P66/FTOB/TMRI1P66/FTOB/TMRI1P66/FTOB/TMRI1
38 30 P67/TMO1P67/TMO1P67/TMO1
39 31 VCC VCC VCC
40 32 A15 P27/A15 P27
41 33 A14 P26/A14 P26
42 34 A13 P25/A13 P25
43 35 A12 P24/A12 P24
44 36 A11 P23/A11 P23
45 37 A10 P22/A10 P22
46 38 A9P21/A9P21
47 39 A8P20/A8P20
48 40 VSS VSS VSS
49 41 A7P17/A7P17
50 42 A6P16/A6P16
51 43 A5P15/A5P15
52 44 A4P14/A4P14
53 45 A3P13/A3P13
54 46 A2P12/A2P12
55 47 A1P11/A1P11
56 48 A0P10/A0P10
57 49 D0D0P30
58 50 D1D1P31
59 51 D2D2P32
60 52 D3D3P33
61 53 D4D4P34
62 54 D5D5P35
63 55 D6D6P36
64 56 D7D7P37
17
Table 1-4 Pin Functions
Pin No.
H8/3534 H8/3522
Type Symbol FP-80A FP-64A DP-64S I/O Name and Function
Power VCC 8, 47 6, 31 14, 39 I Power: Connected to the power
supply. Connect both VCC pins to
the system power supply.
VSS 12, 56,
73 8, 40 16, 48 I Ground: Connected to ground
(0 V). Connect all VSS pins to
systemground (0 V).
Clock XTAL 2 9 17 I Crystal: Connected to a crystal
oscillator. The crystal frequency
should be the same as the
desired system clock frequency.
If an external clock is input at
the EXTAL pin, a reverse-phase
clock should be input at the
XTAL pin.
EXTAL 3 10 18 I External crystal: Connected to
a crystal oscillator or external
clock. The frequency of the
external clock should be the
same as the desired system
clock frequency. See section
6.2, Oscillator Circuit, for
examples of connections to a
crystal and external clock.
φ14 63 7 O System clock: Supplies the
system clock to peripheral
devices.
System
Control
5(6
1412IReset: A low input causes the
chip to reset.
67%<
7715IStandby: A transition to the
hardware standby mode occurs
when a low input is received at
the
67%<
pin.
Address bus A15 to A048 to 55,
57 to 64 32 to 39
41 to 48 40 to 47
49 to 56 OAddress bus: Address output
pins.
Data bus D7 to D072 to 65 56 to 49 64 to 57 I/ O Data bus: 8-bit bidirectional
data bus.
18
Table 1-4 Pin Functions (cont)
Pin No.
H8/3534 H8/3522
Type Symbol FP-80A FP-64A DP-64S I/O Name and Function
Bus
control
:$,7
13 64 8 I Wait: Requests the CPU to insert wait
states into the bus cycle when an
external address is accessed.
5'
17 60 4 O Read: Goes low to indicate that the
CPU is reading an external address.
:5
16 61 5 O Write: Goes low to indicate that the
CPU is writing to an external address.
$6
15 62 6 O Address strobe: Goes low to indicate
that there is a valid address on the
address bus.
Interrupt
signals
10,
6513INonmaskable interrupt: Highest-
priority interrupt request. The NMIEG
bit in the system control register
(SYSCR) determines whether the
interrupt is recognized at the rising or
falling edge of the NMI input.
,54
0 to
,54
7,
,54
0 to
,54
2
18 to 20,
78 to 80,
27, 28
57 to 59 1 to 3 I Interrupt request 0 to 7: [H8/3534]
Interrupt request 0 to 2: [H8/3522]
Maskable interrupt request pins.
Operating
control MD1
MD0
4,
511
12 19
20 IMode: Input pins for setting the MCU
mode operating mode according to the
table below.
MD1MD0Mode Description
0 1 Mode 1 Expanded mode
with on-chip
ROM disabled
1 0 Mode 2 Expanded mode
with on-chip
ROM enabled
1 1 Mode 3 Single-chip mode
19
Table 1-4 Pin Functions (cont)
Pin No.
H8/3534 H8/3522
Type Symbol FP-80A FP-64A DP-64S I/O Name and Function
16-bit free-
running timer
(FRT)
FTCI 21 23 31 I FRT counter clock input: Input pin for
an external clock signal for the
free-running timer.
FTOA 22 24 32 O FRT output compare A output:
Output compare A output pin.
FTOB 27 29 37 O FRT output compare B output:
Output compare B output pin.
FTIA 23 25 33 I FRT input capture A input: Input
capture A input pin.
FTIB 24 26 34 I FRT input capture B input: Input
capture B input pin.
FTIC 25 27 35 I FRT input capture C input: Input
capture C input pin.
FTID 26 28 36 I FRT input capture D input: Input
capture D input pin.
8-bit timer TMO0
TMO1
40
43 27
30 35
38 O8-bit timer output (channels 0 and 1):
Compare-match output pins for the 8-
bit timers.
TMCI0
TMCI1
39
42 23
28 31
36 I8-bit timer counter clock input
(channels 0 and 1): External clock
input pins for the 8-bit timer counters.
TMRI0
TMRI1
41
44 26
29 34
37 I8-bit timer counter reset input
(channels 0 and 1): A high input at
these pins resets the 8-bit timer
counters.
PWM timer
[H8/3534
only]
PW0
PW1
45
46 —— OPWM timer output (channels 0 and
1): Pulse-width modulation timer output
pins.
Serial
communi-
cation
interface(SCI)
TxD0
TxD1
11
78 1
—9
—OTransmit data (channels 0 and 1):
Data output pins for the serial
communication interface.
RxD0
RxD1
10
79 2
—10
—IReceive data (channels 0 and 1):
Data input pins for the serial
communication interface.
SCK0
SCK1
9
80 3
—11
—I/O Serial clock (channels 0 and 1):
Input/output pins for the serial clock.
20
Table 1-4 Pin Functions (cont)
Pin No.
H8/3534 H8/3522
Type Symbol FP-80A FP-64A DP-64S I/O Name and Function
Keyboard
[H8/3534
only]
.(<,1
0 to
.(<,1
7
21 to 28 — — I Keyboard input: Input pins from
a control matrix keyboard.
(Keyboard scan signals are
normally output from P10 to P17
and P20 to P27, allowing a
maximum 16 × 8 key matrix. The
number of keys can be further
increased by use of other output
ports.)
A/D
converter AN7 to
AN0
37 to 30 21 to 14 29 to 22 I Analog input: Analog signal input
pins for the A/D converter.
$'75*
20 57 1 I A/D trigger: External trigger input
for starting the A/D converter.
AVCC 29 22 30 I Analog reference voltage:
Reference voltage pin for the A/D
converter. If the A/D converter
are not used, connect AVCC to the
system power supply.
AVSS 38 13 21 I Analog ground: Ground pin for
the A/D converter. Connect to
system ground (0 V).
I/O ports P17 to P1057 to 64 41 to 48 49 to 56 I/O Port 1: An 8-bit input/output port
with programmable MOS input
pull-ups and LED driving
capability. The direction of each bit
can be selected in the port 1 data
direction register (P1DDR).
P27 to P2048 to 55 32 to 39 40 to 47 I/O Port 2: An 8-bit input/output port
with programmable MOS input
pull-ups and LED driving
capability. The direction of each bit
can be selected in the port 2 data
direction register (P2DDR).
P37 to P3072 to 65 56 to 49 64 to 57 I/O Port 3: An 8-bit input/output port
with programmable MOS input
pull-ups. The direction of each bit
can be selected in the port 3 data
direction register (P3DDR).
21
Table 1-4 Pin Functions (cont)
Pin No.
H8/3534 H8/3522
Type Symbol FP-80A FP-64A DP-64S I/O Name and Function
I/O ports P47 to P4046 to 39 — — I/O Port 4 [H8/3534]: An 8-bit input/output
port. The direction of each bit can be
selected in the port 4 data direction
register (P4DDR).
P52 to P509 to 11 3 to 1 11 to 9 I/O Port 5: A 3-bit input/output port. The
direction of each bit can be selected in
the port 5 data direction register
(P5DDR).
P67 to P6028 to 21 30 to 23 38 to 31 I/O Port 6: An 8-bit input/output port with
programmable MOS input pull-ups. The
direction of each bit can be selected in
the port 6 data direction register
(P6DDR).
P77 to P7037 to 30 21 to 14 29 to 22 I Port 7: An 8-bit input port.
P86 to P8080 to 74 — — I/O Port 8: A 7-bit input/output port. The
direction of each bit can be selected in
the port 8 data direction register
(P8DDR).
P97 to P90
[H8/3534]
P47 to P40
[H8/3522]
13 to 20 64 to 57 8 to 1 I/O Port 9 [H8/3534]: An 8-bit input/ output
port. The direction of each bit (except for
P96) can be selected in the port 9 data
direction register (P9DDR).
Port 4 [H8/3522]: An 8-bit input/output
port. The direction of each bit (except for
P46) can be selected in the port 4 data
direction register (P4DDR).
22
23
Section 2 CPU
2.1 Overview
The H8/300 CPU is a fast central processing unit with eight 16-bit general registers (also
configurable as 16 eight-bit registers) and a concise instruction set designed for high-speed
operation.
2.1.1 Features
The main features of the H8/300 CPU are listed below.
• Two-way register configuration
Sixteen 8-bit general registers, or
Eight 16-bit general registers
• Instruction set with 57 basic instructions, including:
Multiply and divide instructions
Powerful bit-manipulation instructions
• Eight addressing modes
Register direct (Rn)
Register indirect (@Rn)
Register indirect with displacement (@(d:16, Rn))
Register indirect with post-increment or pre-decrement (@Rn+ or @–Rn)
Absolute address (@aa:8 or @aa:16)
Immediate (#xx:8 or #xx:16)
PC-relative (@(d:8, PC))
Memory indirect (@@aa:8)
• Maximum 64-kbyte address space
• High-speed operation
All frequently-used instructions are executed in two to four states
• Maximum clock rate (φ clock): 10 MHz at 5 V
8- or 16-bit register-register add or subtract: 200 ns (10 MHz)
8 × 8-bit multiply: 1400 ns (10 MHz)
16 ÷ 8-bit divide: 1400 ns (10 MHz)
• Power-down mode
SLEEP instruction
24
2.1.2 Address Space
The H8/300 CPU supports an address space with a maximum size of 64 kbytes for program code
and data combined. The memory map differs depending on the mode (mode 1, 2, or 3). For
details, see section 3.4, Address Space Map in Each Operating Mode.
2.1.3 Register Configuration
Figure 2-1 shows the internal register structure of the H8/300 CPU. There are two groups of
registers: the general registers and control registers.
7070
15 0
PC
R0H
R1H
R2H
R3H
R4H
R5H
R6H
R7H
R0L
R1L
R2L
R3L
R4L
R5L
R6L
R7L
(SP) SP: Stack pointer
PC: Program counter
CCR: Condition code register
Carry flag
Overflow flag
Zero flag
Negative flag
Half-carry flag
Interrupt mask bit
User bit
User bit
CCR I U H U N Z V C
General registers (Rn)
Control registers
75321064
Figure 2-1 CPU Registers
25
2.2 Register Descriptions
2.2.1 General Registers
All the general registers can be used as both data registers and address registers. When used as
address registers, the general registers are accessed as 16-bit registers (R0 to R7). When used as
data registers, they can be accessed as 16-bit registers, or the high and low bytes can be accessed
separately as 8-bit registers (R0H to R7H and R0L to R7L).
R7 also functions as the stack pointer, used implicitly by hardware in processing interrupts and
subroutine calls. In assembly-language coding, R7 can also be denoted by the letters SP. As
indicated in figure 2-2, R7 (SP) points to the top of the stack.
Unused area
Stack area
SP (R7)
Figure 2-2 Stack Pointer
2.2.2 Control Registers
The CPU control registers include a 16-bit program counter (PC) and an 8-bit condition code
register (CCR).
(1) Program Counter (PC): This 16-bit register indicates the address of the next instruction the
CPU will execute. Each instruction is accessed in 16 bits (1 word), so the least significant bit
of the PC is ignored (always regarded as 0).
(2) Condition Code Register (CCR): This 8-bit register contains internal status information,
including carry (C), overflow (V), zero (Z), negative (N), and half-carry (H) flags and the
interrupt mask bit (I).
Bit 7—Interrupt Mask Bit (I): When this bit is set to 1, all interrupts except NMI are
masked. This bit is set to 1 automatically by a reset and at the start of interrupt handling.
26
Bit 6—User Bit (U): This bit can be written and read by software (using the LDC, STC,
ANDC, ORC, and XORC instructions).
Bit 5—Half-Carry Flag (H): This flag is set to 1 when the ADD.B, ADDX.B, SUB.B,
SUBX.B, NEG.B, or CMP.B instruction causes a carry or borrow out of bit 3, and is cleared
to 0 otherwise. Similarly, it is set to 1 when the ADD.W, SUB.W, or CMP.W instruction
causes a carry or borrow out of bit 11, and cleared to 0 otherwise. It is used implicitly in the
DAA and DAS instructions.
Bit 4—User Bit (U): This bit can be written and read by software (using the LDC, STC,
ANDC, ORC, and XORC instructions).
Bit 3—Negative Flag (N): This flag indicates the most significant bit (sign bit) of the result
of an instruction.
Bit 2—Zero Flag (Z): This flag is set to 1 to indicate a zero result and cleared to 0 to
indicate a nonzero result.
Bit 1—Overflow Flag (V): This flag is set to 1 when an arithmetic overflow occurs, and
cleared to 0 at other times.
Bit 0—Carry Flag (C): This flag is used by:
Add and subtract instructions, to indicate a carry or borrow at the most significant bit of
the result
Shift and rotate instructions, to store the value shifted out of the most significant or least
significant bit
Bit manipulation and bit load instructions, as a bit accumulator
The LDC, STC, ANDC, ORC, and XORC instructions enable the CPU to load and store the
CCR, and to set or clear selected bits by logic operations. The N, Z, V, and C flags are used in
conditional branching instructions (Bcc).
For the action of each instruction on the flag bits, see the H8/300 Series Programming Manual.
2.2.3 Initial Register Values
When the CPU is reset, the program counter (PC) is loaded from the vector table and the
interrupt mask bit (I) in the CCR is set to 1. The other CCR bits and the general registers are not
initialized. In particular, the stack pointer (R7) is not initialized. The stack pointer and CCR
should be initialized by software, by the first instruction executed after a reset.
27
2.3 Data Formats
The H8/300 CPU can process 1-bit data, 4-bit (BCD) data, 8-bit (byte) data, and 16-bit (word)
data.
• Bit manipulation instructions operate on 1-bit data specified as bit n (n = 0, 1, 2, ..., 7) in a
byte operand.
• All arithmetic and logic instructions except ADDS and SUBS can operate on byte data.
• The DAA and DAS instruction perform decimal arithmetic adjustments on byte data in
packed BCD form. Each nibble of the byte is treated as a decimal digit.
• The MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8 bits), and
DIVXU (16 bits ÷ 8 bits) instructions operate on word data.
28
2.3.1 Data Formats in General Registers
Data of all the sizes above can be stored in general registers as shown in figure 2-3.
76543210 Don’t care
Data Type Register No. Data Format
70
1-bit data RnH
76543210
Don’t care
70
1-bit data RnL
MSB LSB
Don’t care
70
Byte data RnH
Byte data RnL
Word data Rn
4-bit BCD data RnH
4-bit BCD data RnL
Legend
RnH:
RnL:
MSB:
LSB:
Upper digit of general register
Lower digit of general register
Most significant bit
Least significant bit
MSB LSB
Don’t care
70
MSB LSB
15 0
Upper digit Lower digit
Don’t care
7034
Don’t care
Upper digit Lower digit
70
34
Figure 2-3 Register Data Formats
29
2.3.2 Memory Data Formats
Figure 2-4 indicates the data formats in memory.
Word data stored in memory must always begin at an even address. In word access the least
significant bit of the address is regarded as 0. If an odd address is specified, no address error
occurs but the access is performed at the preceding even address. This rule affects MOV.W
instructions and branching instructions, and implies that only even addresses should be stored in
the vector table.
Data Format
76543210
AddressData Type
70
Address n
MSB LSB
MSB
LSB
Upper 8 bits
Lower 8 bits
MSB LSBCCR
CCR*
MSB
LSB
MSB LSB
Address n
Even address
Odd address
Even address
Odd address
Even address
Odd address
1-bit data
Byte data
Word data
Byte data (CCR) on stack
Word data on stack
Note: * Ignored on return
Legend
CCR: Condition code register
Figure 2-4 Memory Data Formats
When the stack is addressed by register R7, it must always be accessed a word at a time. When
the CCR is pushed on the stack, two identical copies of the CCR are pushed to make a complete
word. When they are restored, the lower byte is ignored.
30
2.4 Addressing Modes
2.4.1 Addressing Mode
The H8/300 CPU supports eight addressing modes. Each instruction uses a subset of these
addressing modes.
Table 2-1 Addressing Modes
No. Addressing Mode Symbol
(1) Register direct Rn
(2) Register indirect @Rn
(3) Register indirect with displacement @(d:16, Rn)
(4) Register indirect with post-increment
Register indirect with pre-decrement @Rn+
@–Rn
(5) Absolute address @aa:8 or @aa:16
(6) Immediate #xx:8 or #xx:16
(7) Program-counter-relative @(d:8, PC)
(8) Memory indirect @@aa:8
(1) Register Direct—Rn: The register field of the instruction specifies an 8- or 16-bit general
register containing the operand. In most cases the general register is accessed as an 8-bit
register. Only the MOV.W, ADD.W, SUB.W, CMP.W, ADDS, SUBS, MULXU (8 bits × 8
bits), and DIVXU (16 bits ÷ 8 bits) instructions have 16-bit operands.
(2) Register Indirect—@Rn: The register field of the instruction specifies a 16-bit general
register containing the address of the operand.
(3) Register Indirect with Displacement—@(d:16, Rn): This mode, which is used only in
MOV instructions, is similar to register indirect but the instruction has a second word (bytes
3 and 4) which is added to the contents of the specified general register to obtain the operand
address. For the MOV.W instruction, the resulting address must be even.
(4) Register Indirect with Post-Increment or Pre-Decrement—@Rn+ or @–Rn:
Register indirect with Post-Increment—@Rn+
The @Rn+ mode is used with MOV instructions that load registers from memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the
register field of the instruction is incremented after the operand is accessed. The size of
the increment is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for
MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.
31
Register Indirect with Pre-Decrement—@–Rn
The @–Rn mode is used with MOV instructions that store register contents to memory.
It is similar to the register indirect mode, but the 16-bit general register specified in the
register field of the instruction is decremented before the operand is accessed. The size of
the decrement is 1 or 2 depending on the size of the operand: 1 for MOV.B; 2 for
MOV.W. For MOV.W, the original contents of the 16-bit general register must be even.
(5) Absolute Address—@aa:8 or @aa:16: The instruction specifies the absolute address of the
operand in memory. The MOV.B instruction uses an 8-bit absolute address of the form
H'FFxx. The upper 8 bits are assumed to be 1, so the possible address range is H'FF00 to
H'FFFF (65280 to 65535). The MOV.B, MOV.W, JMP, and JSR instructions can use 16-bit
absolute addresses.
(6) Immediate—#xx:8 or #xx:16: The instruction contains an 8-bit operand in its second byte,
or a 16-bit operand in its third and fourth bytes. Only MOV.W instructions can contain 16-bit
immediate values.
The ADDS and SUBS instructions implicitly contain the value 1 or 2 as immediate data.
Some bit manipulation instructions contain 3-bit immediate data (#xx:3) in the second or
fourth byte of the instruction, specifying a bit number.
(7) Program-Counter-Relative—@(d:8, PC): This mode is used to generate branch addresses
in the Bcc and BSR instructions. An 8-bit value in byte 2 of the instruction code is added as a
sign-extended value to the program counter contents. The result must be an even number.
The possible branching range is –126 to +128 bytes (–63 to +64 words) from the current
address.
(8) Memory Indirect—@@aa:8: This mode can be used by the JMP and JSR instructions. The
second byte of the instruction code specifies an 8-bit absolute address from H'0000 to H'00FF
(0 to 255). The word located at this address contains the branch address. The upper 8 bits of
the absolute address are 0 (H'00), thus the branch address is limited to values from 0 to 255
(H'0000 to H'00FF). Note that some of the addresses in this range are also used in the vector
table. Refer to section 3.4, Address Space Map in Each Operating Mode.
If an odd address is specified as a branch destination or as the operand address of a MOV.W
instruction, the least significant bit is regarded as 0, causing word access to be performed at
the address preceding the specified address. See section 2.3.2, Memory Data Formats, for
further information.
32
2.4.2 Calculation of Effective Address
Table 2-2 shows how the H8/300 calculates effective addresses in each addressing mode.
Arithmetic, logic, and shift instructions use register direct addressing (1). The ADD.B,
ADDX.B, SUBX.B, CMP.B, AND.B, OR.B, and XOR.B instructions can also use immediate
addressing (6).
The MOV instruction uses all the addressing modes except program-counter relative (7) and
memory indirect (8).
Bit manipulation instructions use register direct (1), register indirect (2), or 8-bit absolute (5)
addressing to identify a byte operand, and 3-bit immediate addressing to identify a bit within the
byte. The BSET, BCLR, BNOT, and BTST instructions can also use register direct addressing
(1) to identify the bit.
33
Table 2-2 Effective Address Calculation
Addressing Mode and
Instruction Format
op reg
76 34015
No. Effective Address Calculation Effective Address
1 Register direct, Rn
Operands are contained in registers regm
and regn
Register indirect, @Rn 16-bit register contents
015
Register indirect with displacement,
@(d:16, Rn)
op regm regn
87 34015
op reg
76 34015
disp
op reg
76 34015
Register indirect with
post-increment, @Rn+
op reg
76 34015
Register indirect with pre-decrement,
@–Rn
2
3
4
1 for a byte operand, 2 for a word operand
015
disp
015
015
015
1 or 2
015
015
1 or 2
015
regm
30
regn
30
16-bit register contents
16-bit register contents
16-bit register contents
*
*
*Note:
Table 2-2 Effective Address Calculation
34
Table 2-2 Effective Address Calculation (cont)
Addressing Mode and
Instruction Format
No. Effective Address Calculation Effective address
5 Absolute address
@aa:8
Operand is 1- or 2-byte immediate data
@aa:16
op
87 015
op
015
IMM
op disp
7015
PC-relative
@(d:8, PC)
6
7
015
PC contents
015
015
abs
H'FF
87 015
015
abs
op
#xx:16
op
87 015
IMM
Immediate
#xx:8
8
Sign extension disp
Table 2-2 Effective Address Calculation (cont)
35
Table 2-2 Effective Address Calculation (cont)
Addressing Mode and
Instruction Format
No. Effective Address Calculation Effective Address
8 Memory indirect, @@aa:8
op
87 015
Memory contents (16 bits)
015
abs
H'00
87 015
Legend
reg, regm, regn:
op:
disp:
IMM:
abs:
Register field
Operation field
Displacement
Immediate data
Absolute address
Table 2-2 Effective Address Calculation (cont)
36
2.5 Instruction Set
The H8/300 CPU has 57 types of instructions, which are classified by function in table 2-3.
Table 2-3 Instruction Classification
Function Instructions Types
Data transfer MOV, MOVTPE*3, MOVFPE*3, PUSH*1, POP*1 3
Arithmetic
operations ADD, SUB, ADDX, SUBX, INC, DEC, ADDS,
SUBS, DAA, DAS, MULXU, DIVXU, CMP, NEG 14
Logic operations AND, OR, XOR, NOT 4
Shift SHAL, SHAR, SHLL, SHLR, ROTL, ROTR, ROTXL,
ROTXR 8
Bit manipulation BSET, BCLR, BNOT, BTST, BAND, BIAND, BOR,
BIOR, BXOR, BIXOR, BLD, BILD, BST, BIST 14
Branch Bcc*2, JMP, BSR, JSR, RTS 5
System control RTE, SLEEP, LDC, STC, ANDC, ORC, XORC,
NOP 8
Block data transfer EEPMOV 1
Total 57
Notes: 1. USH Rn is equivalent to MOV.W Rn, @–SP.
POP Rn is equivalent to MOV.W @SP+, Rn.
2. Bcc is a conditional branch instruction in which cc represents a condition code.
3. Not supported by the H8/3534 and H8/3522.
37
The following sections give a concise summary of the instructions in each category, and indicate
the bit patterns of their object code. The notation used is defined next.
Operation Notation
Rd General register (destination)
Rs General register (source)
Rn General register
(EAd) Destination operand
(EAs) Source operand
SP Stack pointer
PC Program counter
CCR Condition code register
N N (negative) flag of CCR
Z Z (zero) flag of CCR
V V (overflow) flag of CCR
C C (carry) flag of CCR
#imm Immediate data
#xx:3 3-bit immediate data
#xx:8 8-bit immediate data
#xx:16 16-bit immediate data
disp Displacement
+ Addition
– Subtraction
×Multiplication
÷Division
∧Logical AND
∨Logical OR
⊕Exclusive Logical OR
→Move
¬NOT (logical complement)
38
2.5.1 Data Transfer Instructions
Table 2-4 describes the data transfer instructions. Figure 2-5 shows their object code formats.
Table 2-4 Data Transfer Instructions
Instruction Size* Function
MOV B/W (EAs) → Rd, Rs → (EAd)
Moves data between two general registers or between a general register
and memory, or moves immediate data to a general register.
The Rn, @Rn, @(d:16, Rn), @aa:16, #xx:8 or #xx:16, @–Rn, and @Rn+
addressing modes are available for byte or word data. The @aa:8
addressing mode is available for byte data only.
The @–R7 and @R7+ modes require word operands. Do not specify byte
size for these two modes.
MOVTPE B Not supported by the H8/3534 and H8/3522.
MOVFPE B Not supported by the H8/3534 and H8/3522.
PUSH W Rn → @–SP
Pushes a 16-bit general register onto the stack. Equivalent to MOV.W Rn,
@–SP.
POP W @SP+ → Rn
Pops a 16-bit general register from the stack. Equivalent to MOV.W @SP+,
Rn.
Note: * Size: Operand size
B: Byte
W: Word
39
15 087
op rm rn MOV
Rm→Rn
15 087
op rm rn @Rm←→Rn
15 087
op rm rn @(d:16, Rm)←→Rn
disp
15 087
op rm rn @Rm+→Rn, or
Rn→@–Rm
15 087
op rn abs @aa:8←→Rn
15 087
op rn @aa:16←→Rn
abs
15 087
op rn IMM #xx:8→Rn
15 087
op rn #xx:16→Rn
IMM
15 087
op rn POP, PUSH
Legend
op:
rm, rn:
disp:
abs:
IMM:
Operation field
Register field
Displacement
Absolute address
Immediate data
15 087
op rn MOVFPE, MOVTPE
abs
Figure 2-5 Data Transfer Instruction Codes
40
2.5.2 Arithmetic Operations
Table 2-5 describes the arithmetic instructions. See figure 2-6 in section 2.5.4, Shift Operations,
for their object codes.
Table 2-5 Arithmetic Instructions
Instruction Size* Function
ADD
SUB B/W Rd ± Rs → Rd, Rd + #imm → Rd
Performs addition or subtraction on data in two general registers, or addition
on immediate data and data in a general register. Immediate data cannot be
subtracted from data in a general register. Word data can be added or
subtracted only when both words are in general registers.
ADDX
SUBX B Rd ± Rs ± C → Rd, Rd ± #imm ± C → Rd
Performs addition or subtraction with carry or borrow on byte data in two
general registers, or addition or subtraction on immediate data and data in a
general register.
INC
DEC B Rd ± #1 → Rd
Increments or decrements a general register.
ADDS
SUBS W Rd ± #imm → Rd
Adds or subtracts immediate data to or from data in a general register. The
immediate data must be 1 or 2.
DAA
DAS B Rd decimal adjust → Rd
Decimal-adjusts (adjusts to packed BCD) an addition or subtraction result in
a general register by referring to the CCR.
MULXU B Rd × Rs → Rd
Performs 8-bit × 8-bit unsigned multiplication on data in two general
registers, providing a 16-bit result.
DIVXU B Rd ÷ Rs → Rd
Performs 16-bit ÷ 8-bit unsigned division on data in two general registers,
providing an 8-bit quotient and 8-bit remainder.
CMP B/W Rd – Rs, Rd – #imm
Compares data in a general register with data in another general register or
with immediate data. Word data can be compared only between two general
registers.
NEG B 0 – Rd → Rd
Obtains the two’s complement (arithmetic complement) of data in a general
register.
Note: * Size: Operand size
B: Byte
W: Word
41
2.5.3 Logic Operations
Table 2-6 describes the four instructions that perform logic operations. See figure 2-6 in
section 2.5.4, Shift Operations, for their object codes.
Table 2-6 Logic Operation Instructions
Instruction Size* Function
AND B Rd ∧ Rs → Rd, Rd ∧ #imm → Rd
Performs a logical AND operation on a general register and another general
register or immediate data.
OR B Rd ∨ Rs → Rd, Rd ∨ #imm → Rd
Performs a logical OR operation on a general register and another general
register or immediate data.
XOR B Rd ⊕ Rs → Rd, Rd ⊕ #imm → Rd
Performs a logical exclusive OR operation on a general register and another
general register or immediate data.
NOT B ~ (Rd) → (Rd)
Obtains the one’s complement (logical complement) of general register
contents.
Note: * Size: Operand size
B: Byte
2.5.4 Shift Operations
Table 2-7 describes the eight shift instructions. Figure 2-6 shows the object code formats of the
arithmetic, logic, and shift instructions.
Table 2-7 Shift Instructions
Instruction Size* Function
SHAL
SHAR B Rd shift → Rd
Performs an arithmetic shift operation on general register
contents.
SHLL
SHLR B Rd shift → Rd
Performs a logical shift operation on general register contents.
ROTL
ROTR B Rd rotate → Rd
Rotates general register contents.
ROTXL
ROTXR B Rd rotate through carry → Rd
Rotates general register contents through the C (carry) bit.
Note: * Size: Operand size
B: Byte
42
15 087
op rm rn ADD, SUB, CMP,
ADDX, SUBX (Rm)
Legend
op:
rm, rn:
IMM:
Operation field
Register field
Immediate data
15 087
op rn ADDS, SUBS, INC, DEC,
DAA, DAS, NEG, NOT
15 087
op rn MULXU, DIVXU
rm
15 087
rn IMM ADD, ADDX, SUBX,
CMP (#xx:8)
op
15 087
op rn AND, OR, XOR (Rm)
rm
15 087
rn IMM AND, OR, XOR (#xx:8)
op
15 087
rn SHAL, SHAR, SHLL, SHLR,
ROTL, ROTR, ROTXL, ROTXR
op
Figure 2-6 Arithmetic, Logic, and Shift Instruction Codes
43
2.5.5 Bit Manipulations
Table 2-8 describes the bit-manipulation instructions. Figure 2-7 shows their object code
formats.
Table 2-8 Bit-Manipulation Instructions
Instruction Size* Function
BSET B 1 → (<bit no.> of <EAd>)
Sets a specified bit in a general register or memory to 1. The bit is specified
by a bit number, given in 3-bit immediate data or the lower three bits of a
general register.
BCLR B 0 → (<bit no.> of <EAd>)
Clears a specified bit in a general register or memory to 0. The bit is
specified by a bit number, given in 3-bit immediate data or the lower three
bits of a general register.
BNOT B ¬ (<bit no.> of <EAd>) → (<bit no.> of <EAd>)
Inverts a specified bit in a general register or memory. The bit is specified by
a bit number, given in 3-bit immediate data or the lower three bits of a
general register
BTST B ¬ (<bit no.> of <EAd>) →→ Z
Tests a specified bit in a general register or memory and sets or clears the Z
flag accordingly. The bit is specified by a bit number, given in
3-bit immediate data or the lower three bits of a general register.
BAND
BIAND
BC ∧ (<bit no.> of <EAd>) → C
ANDs the C flag with a specified bit in a general register or memory.
C ∧ [¬ (<bit no.> of <EAd>)] → C
ANDs the C flag with the inverse of a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.
BOR
BIOR
BC ∨ (<bit no.> of <EAd>) → C
ORs the C flag with a specified bit in a general register or memory.
C ∨ [¬ (<bit no.> of <EAd>)] → C
ORs the C flag with the inverse of a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.
BXOR B C ⊕ (<bit no.> of <EAd>) → C
XORs the C flag with a specified bit in a general register or memory.
Note: * Size: Operand size
B: Byte
44
Table 2-8 Bit-Manipulation Instructions (cont)
Instruction Size* Function
BIXOR B C ⊕ ¬ [(<bit no.> of <EAd>)] → C
XORs the C flag with the inverse of a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.
BLD
BILD
B (<bit no.> of <EAd>) → C
Copies a specified bit in a general register or memory to the C flag.
¬ (<bit no.> of <EAd>) → C
Copies the inverse of a specified bit in a general register or memory to the C
flag.
The bit number is specified by 3-bit immediate data.
BST
BIST
BC → (<bit no.> of <EAd>)
Copies the C flag to a specified bit in a general register or memory.
¬ C → (<bit no.> of <EAd>)
Copies the inverse of the C flag to a specified bit in a general register or
memory.
The bit number is specified by 3-bit immediate data.
Note: * Size: Operand size
B: Byte
Notes on Bit Manipulation Instructions: BSET, BCLR, BNOT, BST, and BIST are read-
modify-write instructions. They read a byte of data, modify one bit in the byte, then write the
byte back. Care is required when these instructions are applied to registers with write-only bits
and to the I/O port registers.
Step Description
1 Read Read one data byte at the specified address
2 Modify Modify one bit in the data byte
3 Write Write the modified data byte back to the specified address
Example 1: BCLR is executed to clear bit 0 in the port 4 data direction register (P4DDR) under
the following conditions.
P47: Input pin, low
P46: Input pin, high
P45 – P40: Output pins, low
The intended purpose of this BCLR instruction is to switch P40 from output to input.
45
Before Execution of BCLR Instruction
P47P46P45P44P43P42P41P40
Input/output Input Input Output Output Output Output Output Output
Pin state Low High Low Low Low Low Low Low
DDR 0 0 1 1 1 1 1 1
DR 1 0 0 0 0 0 0 0
Execution of BCLR Instruction
BCLR #0, @P4DDR ;Clear bit 0 in data direction register
After Execution of BCLR Instruction
P47P46P45P44P43P42P41P40
Input/output Output Output Output Output Output Output Output Input
Pin state Low High Low Low Low Low Low High
DDR 1 1 1 1 1 1 1 0
DR 1 0 0 0 0 0 0 0
Explanation: To execute the BCLR instruction, the CPU begins by reading P4DDR. Since
P4DDR is a write-only register, it is read as H'FF, even though its true value is H'3F.
Next the CPU clears bit 0 of the read data, changing the value to H'FE.
Finally, the CPU writes this value (H'FE) back to P4DDR to complete the BCLR instruction.
As a result, P40DDR is cleared to 0, making P40 an input pin. In addition, P47DDR and P46DDR
are set to 1, making P47 and P46 output pins.
46
15 087
op IMM rn Operand:
Bit no.:
Legend
op:
rm, rn:
abs:
IMM:
Operation field
Register field
Absolute address
Immediate data
15 087
op rn
BSET, BCLR, BNOT, BTST
register direct (Rn)
immediate (#xx:3)
Operand:
Bit no.: register direct (Rn)
register direct (Rm)
rm
15 087
op 0 Operand:
Bit no.:
register indirect (@Rn)
immediate (#xx:3)
rn
0
0
0
0
0
0
0IMM
15 087
op 0 Operand:
Bit no.:
register indirect (@Rn)
register direct (Rm)
rn
0
0
0
0
0
0
0rmop
15 087
op Operand:
Bit no.:
absolute (@aa:8)
immediate (#xx:3)
abs
0000IMM
op
op
15 087
op Operand:
Bit no.:
absolute (@aa:8)
register direct (Rm)
abs
0000rmop
15 087
op IMM rn Operand:
Bit no.: register direct (Rn)
immediate (#xx:3)
BAND, BOR, BXOR, BLD, BST
15 087
op 0 Operand:
Bit no.:
register indirect (@Rn)
immediate (#xx:3)
rn
0
0
0
0
0
0
0IMMop
15 087
op Operand:
Bit no.:
absolute (@aa:8)
immediate (#xx:3)
abs
0000IMMop
Figure 2-7 Bit Manipulation Instruction Codes (1)
47
Legend
op:
rm, rn:
abs:
IMM:
Operation field
Register field
Absolute address
Immediate data
15 087
op IMM rn Operand:
Bit no.: register direct (Rn)
immediate (#xx:3)
BIAND, BIOR, BIXOR, BILD, BIST
15 087
op 0 Operand:
Bit no.:
register indirect (@Rn)
immediate (#xx:3)
rn
0
0
0
0
0
0
0IMMop
15 087
op Operand:
Bit no.:
absolute (@aa:8)
immediate (#xx:3)
abs
0000IMMop
Figure 2-7 Bit Manipulation Instruction Codes (2)
48
2.5.6 Branching Instructions
Table 2-9 describes the branching instructions. Figure 2-8 shows their object code formats.
Table 2-9 Branching Instructions
Instruction Size Function
Bcc — Branches if condition cc is true.
Mnemonic cc field Description Condition
BRA (BT) 0 0 0 0 Always (true) Always
BRN (BF) 0 0 0 1 Never (false) Never
BHI 0 0 1 0 High C ∨ Z = 0
BLS 0 0 1 1 Low or same C ∨ Z = 1
BCC (BHS) 0 1 0 0 Carry clear (High or same) C = 0
BCS (BLO) 0 1 0 1 Carry set (low) C = 1
BNE 0 1 1 0 Not equal Z = 0
BEQ 0 1 1 1 Equal Z = 1
BVC 1 0 0 0 Overflow clear V = 0
BVS 1 0 0 1 Overflow set V = 1
BPL 1 0 1 0 Plus N = 0
BMI 1 0 1 1 Minus N = 1
BGE 1 1 0 0 Greater or equal N ⊕ V = 0
BLT 1 1 0 1 Less than N ⊕ V = 1
BGT 1 1 1 0 Greater than Z ∨ (N ⊕ V) = 0
BLE 1 1 1 1 Less or equal Z ∨ (N ⊕ V) = 1
JMP — Branches unconditionally to a specified address.
JSR — Branches to a subroutine at a specified address.
BSR — Branches to a subroutine at a specified displacement from the current
address.
RTS — Returns from a subroutine.
49
Legend
op:
cc:
rm:
disp:
abs:
Operation field
Condition field
Register field
Displacement
Absolute address
15 087
op cc disp Bcc
15 087
op rm 0 JMP (@Rm)
000
15 087
op JMP (@aa:16)
abs
15 087
op abs JMP (@@aa:8)
15 087
op disp BSR
15 087
op rm 0 JSR (@Rm)
000
15 087
op JSR (@aa:16)
abs
15 087
op abs JSR (@@aa:8)
15 087
op RTS
Figure 2-8 Branching Instruction Codes
50
2.5.7 System Control Instructions
Table 2-10 describes the system control instructions. Figure 2-9 shows their object code formats.
Table 2-10 System Control Instructions
Instruction Size Function
RTE — Returns from an exception-handling routine.
SLEEP — Causes a transition to the power-down state.
LDC B Rs → CCR, #imm → CCR
Moves immediate data or general register contents to the condition code
register.
STC B CCR → Rd
Copies the condition code register to a specified general register.
ANDC B CCR ∧ #imm → CCR
Logically ANDs the condition code register with immediate data.
ORC B CCR ∨ #imm → CCR
Logically ORs the condition code register with immediate data.
XORC B CCR ⊕ #imm → CCR
Logically exclusive-ORs the condition code register with immediate data.
NOP — PC + 2 → PC
Only increments the program counter.
Note: * Size: Operand size
B: Byte
Legend
op:
rn:
IMM:
Operation field
Register field
Immediate data
15 087
op RTE, SLEEP, NOP
15 087
op rn LDC, STC (Rn)
15 087
op IMM ANDC, ORC,
XORC, LDC (#xx:8)
Figure 2-9 System Control Instruction Codes
51
2.5.8 Block Data Transfer Instruction
Table 2-11 describes the EEPMOV instruction. Figure 2-10 shows its object code format.
Table 2-11 Block Data Transfer Instruction
Instruction Size Function
EEPMOV — if R4L ≠ 0 then
repeat @R5+ → @R6+
R4L – 1 → R4L
until R4L = 0
else next;
Moves a data block according to parameters set in
general registers R4L, R5, and R6.
R4L: size of block (bytes)
R5: starting source address
R6: starting destination address
Execution of the next instruction starts as soon as the
block transfer is completed.
Legend
op: Operation field
15 087
op
op
Figure 2-10 Block Data Transfer Instruction
52
Notes on EEPMOV Instruction
1. The EEPMOV instruction is a block data transfer instruction. It moves the number of bytes
specified by R4L from the address specified by R5 to the address specified by R6.
←R6
←R6 + R4L
R5 →
R5 + R4L →
2. When setting R4L and R6, make sure that the final destination address (R6 + R4L) does not
exceed H'FFFF. The value in R6 must not change from H'FFFF to H'0000 during execution
of the instruction
H'FFFF
Not allowed
←R6
←R6 + R4L
R5 →
R5 + R4L →
53
2.6 CPU States
2.6.1 Overview
The CPU has three states: the program execution state, exception-handling state, and power-
down state. The power-down state is further divided into three modes: sleep mode, software
standby mode, and hardware standby mode. Figure 2-11 summarizes these states, and figure 2-
12 shows a map of the state transitions.
State Program execution state
The CPU executes successive program instructions.
Exception-handling state
A transient state triggered by a reset or interrupt. The CPU executes
a hardware sequence that includes loading the program counter from
the vector table.
Power-down state
A state in which some or
all of the chip functions are
stopped to conserve power.
Sleep mode
Software standby mode
Hardware standby mode
Figure 2-11 Operating States
54
Reset state Hardware
standby mode
Interrupt request
RES = 1
Power-down state
Sleep mode
Exception-
handling state
Program
execution state
Exception
handling
request End of exception
handing
SLEEP instruction
with SSBY bit set
STBY = 1, RES = 0
SLEEP
instruction
Software
standby mode
NMI, IRQ0
to IRQ2 or IRQ6
Notes: 1.
2.
A transition to the reset state occurs when RES goes low, except when the chip
is in the hardware standby mode.
A transition from any state to the hardware standby mode occurs when STBY
goes low.
Figure 2-12 State Transitions
2.6.2 Program Execution State
In this state the CPU executes program instructions.
2.6.3 Exception-Handling State
The exception-handling state is a transient state that occurs when the CPU is reset or interrupted
and changes its normal processing flow. In interrupt exception handling, the CPU references the
stack pointer (R7) and saves the program counter and condition code register on the stack. For
further details see section 4, Exception Handling.
2.6.4 Power-Down State
The power-down state includes three modes: sleep mode, software standby mode, and hardware
standby mode.
55
(1) Sleep Mode: Is entered when a SLEEP instruction is executed. The CPU halts, but CPU
register contents remain unchanged and the on-chip supporting modules continue to function.
(2) Software Standby Mode: Is entered if the SLEEP instruction is executed while the SSBY
(Software Standby) bit in the system control register (SYSCR) is set. The CPU and all on-
chip supporting modules halt. The on-chip supporting modules are initialized, but the
contents of the on-chip RAM and CPU registers remain unchanged as long as a specified
voltage is supplied. I/O port outputs also remain unchanged.
(3) Hardware Standby Mode: Is entered when the input at the
67%<
pin goes low. All chip
functions halt, including I/O port output. The on-chip supporting modules are initialized, but
on-chip RAM contents are held.
See section 19, Power-Down State, for further information.
2.7 Access Timing and Bus Cycle
The CPU is driven by the system clock (φ). The period from one rising edge of the system clock
to the next is referred to as a “state.” Memory access is performed in a two- or three-state bus
cycle. On-chip memory, on-chip supporting modules, and external devices are accessed in
different bus cycles as described below.
2.7.1 Access to On-Chip Memory (RAM and ROM)
On-chip ROM and RAM are accessed in a cycle of two states designated T1 and T2. Either byte
or word data can be accessed, via a 16-bit data bus. Figure 2-13 shows the on-chip memory
access cycle. Figure 2-14 shows the associated pin states.
56
Bus cycle
Internal data bus (read)
Internal address bus
Internal read signal
Internal write signal
Internal data bus (write)
Address
T
1
state T
2
state
ø
Write data
Read data
Figure 2-13 On-Chip Memory Access Cycle
57
Bus cycle
T
1
state T
2
state
Address
ø
Address bus
AS: High
RD: High
WR: High
Data bus:
High impedance state
Figure 2-14 Pin States during On-Chip Memory Access Cycle
58
2.7.2 Access to On-Chip Supporting Modules and External Devices
The on-chip supporting module registers and external devices are accessed in a cycle consisting
of three states: T1, T2, and T3. Only one byte of data can be accessed per cycle, via an 8-bit data
bus. Access to word data or instruction codes requires two consecutive cycles (six states).
Figure 2-15 shows the access cycle for the on-chip supporting modules. Figure 2-16 shows the
associated pin states. Figures 2-17 (a) and (b) show the read and write access timing for external
devices.
Bus cycle
Internal data bus
(read)
Internal address
bus
Internal read
signal
Internal write
signal
Internal data bus
(write)
ø
Address
Write data
T
1
state T
2
state T
3
state
Read data
Figure 2-15 On-Chip Supporting Module Access Cycle
59
Address
Bus cycle
T
3
stateT
2
state
T
1
state
ø
Address bus
AS: High
RD: High
WR: High
Data bus:
High impedance state
Figure 2-16 Pin States during On-Chip Supporting Module Access Cycle
60
Read cycle
Address
Read data
T1 state T2 state T3 state
ø
Address bus
AS
WR: High
Data bus
RD
Figure 2-17 (a) External Device Access Timing (Read)
61
Write cycle
Address
Write data
T
1
state T
2
state T
3
state
ø
Address bus
AS
WR
Data bus
RD: High
Figure 2-17 (b) External Device Access Timing (Write)
62
63
Section 3 MCU Operating Modes and Address Space
3.1 Overview
3.1.1 Mode Selection
The H8/3534 and H8/3522 operate in three modes numbered 1, 2, and 3. The mode is selected
by the inputs at the mode pins (MD1 and MD0). See table 3-1.
Table 3-1 Operating Modes
Mode MD1MD0Address space On-chip ROM On-chip RAM
Mode 0 Low Low — — —
Mode 1 Low High Expanded Disabled Enabled*
Mode 2 High Low Expanded Enabled Enabled*
Mode 3 High High Single-chip Enabled Enabled
Note: *If the RAME bit in the system control register (SYSCR) is cleared to 0, off-chip memory
can be accessed instead.
Modes 1 and 2 are expanded modes that permit access to off-chip memory and peripheral
devices. The maximum address space supported by these externally expanded modes is 64
kbytes.
In mode 3 (single-chip mode), only on-chip ROM and RAM and the on-chip register field are
used. All ports are available for general-purpose input and output.
Mode 0 is inoperative in the H8/3534 and H8/3522. Avoid setting the mode pins to mode 0.
64
3.1.2 Mode and System Control Registers
Table 3-2 lists the registers related to the chip’s operating mode: the system control register
(SYSCR) and mode control register (MDCR). The mode control register indicates the inputs to
the mode pins MD1 and MD0.
Table 3-2 Mode and System Control Registers
Name Abbreviation Read/Write Address
System control register SYSCR R/W H'FFC4
Mode control register MDCR R H'FFC5
3.2 System Control Register (SYSCR)
Bit
[H8/3534]
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
(HIE)
0
R/W
Bit
[H8/3522]
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
—
1
—
The system control register (SYSCR) is an 8-bit register that controls the operation of the chip.
Bit 7—Software Standby (SSBY): Enables transition to the software standby mode. For details,
see section 16, Power-Down State.
On recovery from software standby mode by an external interrupt, the SSBY bit remains set to 1.
It can be cleared by writing 0.
Bit 7
SSBY Description
0 The SLEEP instruction causes a transition to sleep mode. (Initial value)
1 The SLEEP instruction causes a transition to software standby mode.
65
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling
time when the chip recovers from the software standby mode by an external interrupt. During
the selected time the CPU and on-chip supporting modules continue to stand by. These bits
should be set according to the clock frequency so that the settling time is at least 8 ms. For
specific settings, see section 16.3.3, Clock Settling Time for Exit from Software Standby Mode.
Bit 6
STS2 Bit 5
STS1 Bit 4
STS0 Description
0 0 0 Settling time = 8,192 states (Initial value)
0 0 1 Settling time = 16,384 states
0 1 0 Settling time = 32,768 states
0 1 1 Settling time = 65,536 states
1 0 — Settling time = 131,072 states
1 1 — Unused
Bit 3—External Reset (XRST): Indicates the source of a reset. A reset can be generated by
input of an external reset signal, or by a watchdog timer overflow when the watchdog timer is
used. XRST is a read-only bit. It is set to 1 by an external reset, and cleared to 0 by watchdog
timer overflow.
Bit 3
XRST Description
0 Reset was caused by watchdog timer overflow.
1 Reset was caused by external input. (Initial value)
Bit 2—NMI Edge (NMIEG): Selects the valid edge of the
10,
input.
Bit 2
NMIEG Description
0 An interrupt is requested on the falling edge of the
10,
input. (Initial value)
1 An interrupt is requested on the rising edge of the
10,
input.
Bit 1—Host Interface Enable (HIE): [H8/3534] Reserved. Do not set this bit to 1.
Bit 1—Reserved: [H8/3522] This bit cannot be modified and is always read as 1.
Bit 0—RAM Enable (RAME): Enables or disables the on-chip RAM. The RAME bit is
initialized by a reset, but is not initialized in the software standby mode.
66
Bit 0
RAME Description
0 The on-chip RAM is disabled.
1 The on-chip RAM is enabled. (Initial value)
3.3 Mode Control Register (MDCR)
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
0
—
3
—
0
—
0
MDS0
R
2
—
1
—
1
MDS1
R
—*
Note: Initialized according to MD1 and MD0 inputs.
*
—*
The mode control register (MDCR) is an 8-bit register that indicates the operating mode of the
chip.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 1.
Bits 4 and 3—Reserved: These bits cannot be modified and are always read as 0.
Bit 2—Reserved: This bit cannot be modified and is always read as 1.
Bits 1 and 0—Mode Select 1 and 0 (MDS1 and MDS0): These bits indicate the values of the
mode pins (MD1 and MD0), thereby indicating the current operating mode of the chip. MDS1
corresponds to MD1 and MDS0 to MD0. These bits can be read but not written. When the mode
control register is read, the levels at the mode pins (MD1 and MD0) are latched in these bits.
67
3.4 Address Space Map in Each Operating Mode
Figures 3-1, 3-2 show memory maps of the H8/3534, H8/3522 in modes 1, 2, and 3.
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'FB80
H'FB7F
H'F780
H'F77F
H'004C
H'004B
H'0000
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'FB80
H'FB7F
H'F780
H'F77F
H'FFFF
H'FF88
H'FF7F
H'EF80
H'EF7F
H'8000
H'7FFF H'8000
H'7FFF
H'004C
H'004B
H'0000
H'004C
H'004B
H'0000
Mode 1
Expanded Mode without
On-Chip ROM
Mode 2
Expanded Mode with
On-Chip ROM
Mode 3
Single-Chip Mode
Vector table
On-chip ROM,
32,768 bytes
Vector tableVector table
Reserved*1
Reserved*1, *2Reserved*1, *2
External address space
On-chip RAM*2,
1,024 bytes On-chip RAM,
1,024 bytes
External address space
External address space
External address space
On-chip RAM*2,
1,024 bytes
On-chip register field On-chip register field On-chip register field
Do not access reserved areas.
External memory can be accessed at these addresses when the RAME bit in
the system control register (SYSCR) is cleared to 0.
Notes: 1.
2.
On-chip ROM,
32,768 bytes
Reserved*1
Reserved*1
H'F780
H'F77F
H'FB80
H'FB7F
Figure 3-1 H8/3534 Address Space Map
68
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'FD80
H'FD7F
H'FB80
H'FB7F
H'004A
H'0049
H'0000
H'FFFF
H'FF88
H'FF87
H'FF80
H'FF7F
H'FD80
H'FD7F
H'FB80
H'FB7F
H'FFFF
H'FF88
H'FF7F
H'8000
H'7FFF H'7FFF
H'4000
H'3FFF H'4000
H'3FFF
H'004A
H'0049
H'0000
H'004A
H'0049
H'0000
Mode 1
Expanded Mode without
On-Chip ROM
Mode 2
Expanded Mode with
On-Chip ROM
Mode 3
Single-Chip Mode
Vector table
On-chip ROM,
16,384 bytes
Vector tableVector table
Reserved
*1
Reserved
*1,
*2
Reserved
*1,
*2
External address space
On-chip RAM
*2
,
512 bytes On-chip RAM,
512 bytes
External address space
External address space
External address space
On-chip RAM
*2
,
512 bytes
On-chip register field On-chip register field On-chip register field
Do not access reserved areas.
External memory can be accessed at these addresses when the RAME bit in
the system control register (SYSCR) is cleared to 0.
Notes: 1.
2.
On-chip ROM,
16,384 bytes
Reserved
*1
Reserved
*1
H'FB80
H'FD80
H'FD7F
Figure 3-2 H8/3522 Address Space Map
69
Section 4 Exception Handling
4.1 Overview
The H8/3534 and H8/3522 recognize two kinds of exceptions: interrupts and the reset. Table 4-1
indicates their priority and the timing of their hardware exception-handling sequence.
Table 4-1 Hardware Exception-Handling Sequences and Priority
Priority Type of
Exception Detection
Timing Timing of Exception-Handling Sequence
High Reset Synchronized
with clock The hardware exception-handling sequence begins as
soon as
5(6
changes from low to high.
↓
Low
Interrupt End of instruction
execution*When an interrupt is requested, the hardware
exception-handling sequence begins at the end of
the current instruction, or at the end of the current
hardware exception-handling sequence.
Note: *Not detected after ANDC, ORC, XORC, and LDC instructions.
4.2 Reset
4.2.1 Overview
A reset has the highest exception-handling priority. When the
5(6
pin goes low or when there is
a watchdog timer reset (when the reset option is selected for watchdog timer overflow), all
current processing stops and the chip enters the reset state. The internal state of the CPU and the
registers of the on-chip supporting modules are initialized. The reset exception-handling
sequence starts when
5(6
returns from low to high, or at the end of a watchdog reset pulse.
4.2.2 Reset Sequence
The reset state begins when
5(6
goes low or a watchdog reset is generated. To ensure correct
resetting, at power-on the
5(6
pin should be held low for at least 20 ms. In a reset during
operation, the
5(6
pin should be held low for at least 10 system clock cycles. The watchdog
reset pulse width is always 518 system clocks. For the pin states during a reset, see appendix D,
Port States in Each Mode.
The following sequence is carried out when reset exception handling begins.
(1) The internal state of the CPU and the registers of the on-chip supporting modules are
initialized, and the I bit in the condition code register (CCR) is set to 1.
(2) The CPU loads the program counter with the first word in the vector table (stored at
addresses H'0000 and H'0001) and starts program execution.
70
The
5(6
pin should be held low when power is switched off, as well as when power is switched
on.
Figure 4-1 indicates the timing of the reset sequence in modes 2 and 3. Figure 4-2 indicates the
timing in mode 1.
(1)
ø
RES/watchdog timer
reset (internal)
(2)
Internal address
bus
Internal read
signal
Internal write
signal
Internal data bus
(16 bits)
(1) Reset vector address (H'0000)
(2) Starting address of program
(3) First instruction of program
Vector
fetch Internal
processing Instruction
prefetch
(2) (3)
Figure 4-1 Reset Sequence (Mode 2 or 3, Program Stored in On-Chip ROM)
71
(1) (3) (5) (7)
(1), (3) Reset vector address: (1) = H'0000, (3) = H'0001
(2), (4) Starting address of program (contents of reset vector): (2) = upper byte, (4) = lower byte
(5), (7) Starting address of program: (5) = (2) (4), (7) = (2) (4) + 1
(6), (8) First instruction of program: (6) = first byte, (8) = second byte
Vector fetch
Internal
process-
ing Instruction prefetch
RES/watchdog timer
reset (internal)
D
7
to D
0
(8 bits)
A
15
to A
0
ø
RD
WR
(2) (4) (6) (8)
Figure 4-2 Reset Sequence (Mode 1)
72
4.2.3 Disabling of Interrupts after Reset
After a reset, if an interrupt were to be accepted before initialization of the stack pointer (SP:
R7), the program counter and condition code register might not be saved correctly, leading to a
program crash. To prevent this, all interrupts, including NMI, are disabled immediately after a
reset. The first program instruction is therefore always executed. This instruction should
initialize the stack pointer (example: MOV.W #xx:16, SP).
After reset exception handling, in order to initialize the contents of CCR, a CCR manipulation
instruction can be executed before an instruction to initialize the stack pointer. Immediately after
execution of a CCR manipulation instruction, all interrupts including NMI are disabled. Use the
next instruction to initialize the stack pointer.
4.3 Interrupts
4.3.1 Overview
The interrupt sources for the H8/3534 include nine external sources from 23 input pins (NMI,
IRQ0 to IRQ7, and KEYIN0 to KEYIN7), and 23 internal sources in the on-chip supporting
modules. The H8/3522 has four external sources (NMI, and IRQ0 to IRQ2) and 19 internal
sources in the on-chip supporting modules. Table 4-2 lists the interrupt sources in priority order
and gives their vector addresses. When two or more interrupts are requested, the interrupt with
highest priority is served first.
The features of these interrupts are:
• NMI has the highest priority and is always accepted. All internal and external interrupts
except NMI can be masked by the I bit in the CCR. When the I bit is set to 1, interrupts other
than NMI are not accepted.
• IRQ0 to IRQ7 [H8/3534]/IRQ0 to IRQ 2 [H8/3522] can be sensed on the falling edge of the
input signal, or level-sensed. The type of sensing can be selected for each interrupt
individually. NMI is edge-sensed, and either the rising or falling edge can be selected.
• All interrupts are individually vectored. The software interrupt-handling routine does not
have to determine what type of interrupt has occurred.
• IRQ6 [H8/3534] is multiplexed with 8 external sources (KEYIN0 to KEYIN7). KEYIN0 to
KEYIN7 can be masked individually by user software.
• The watchdog timer can generate either an NMI or overflow interrupt, depending on the
needs of the application. For details, see section 11, Watchdog Timer.
73
Table 4-2 (a) H8/3534 Interrupts
Interrupt source No. Vector Table Address Priority
NMI
IRQ0
IRQ1
IRQ2
IRQ3
IRQ4
IRQ5
IRQ6
IRQ7
3
4
5
6
7
8
9
10
11
H'0006 to H'0007
H'0008 to H'0009
H'000A to H'000B
H'000C to H'000D
H'000E to H'000F
H'0010 to H'0011
H'0012 to H'0013
H'0014 to H'0015
H'0016 to H'0017
High
16-bit free-
running timer ICIA (Input capture A)
ICIB (Input capture B)
ICIC (Input capture C)
ICID (Input capture D)
OCIA (Output compare A)
OCIB (Output compare B)
FOVI (Overflow)
12
13
14
15
16
17
18
H'0018 to H'0019
H'001A to H'001B
H'001C to H'001D
H'001E to H'001F
H'0020 to H'0021
H'0022 to H'0023
H'0024 to H'0025
8-bit timer 0 CMI0A (Compare-match A)
CMI0B (Compare-match B)
OVI0 (Overflow)
19
20
21
H'0026 to H'0027
H'0028 to H'0029
H'002A to H'002B
↓
8-bit timer 1 CMI1A (Compare-match A)
CMI1B (Compare-match B)
OVI1 (Overflow)
22
23
24
H'002C to H'002D
H'002E to H'002F
H'0030 to H'0031
Reserved 25
26 H'0032 to H'0033
H'0034 to H'0035
Serial
communication
interface 0
ERI0 (Receive error)
RXI0 (Receive end)
TXI0 (TDR empty)
TEI0 (TSR empty)
27
28
29
30
H'0036 to H'0037
H'0038 to H'0039
H'003A to H'003B
H'003C to H'003D
Serial
communication
interface 1
ERI1 (Receive error)
RXI1 (Receive end)
TXI1 (TDR empty)
TEI1 (TSR empty)
31
32
33
34
H'003E to H'003F
H'0040 to H'0041
H'0042 to H'0043
H'0044 to H'0045
A/D converter ADI (Conversion end) 35 H'0046 to H'0047
Watchdog timer WOVF (WDT overflow) 36 H'0048 to H'0049 Low
Notes: 1. H'0000 and H'0001 contain the reset vector.
2. H'0002 to H'0005 are reserved in the H8/3534 and are not available to the user.
74
Table 4-2 (b) H8/3522 Interrupts
Interrupt source No. Vector Table Address Priority
NMI
IRQ0
IRQ1
IRQ2
3
4
5
6
H'0006 to H'0007
H'0008 to H'0009
H'000A to H'000B
H'000C to H'000D
High
Reserved 7
8
9
10
11
H'000E to H'000F
H'0010 to H'0011
H'0012 to H'0013
H'0014 to H'0015
H'0016 to H'0017
16-bit free-
running timer ICIA (Input capture A)
ICIB (Input capture B)
ICIC (Input capture C)
ICID (Input capture D)
OCIA (Output compare A)
OCIB (Output compare B)
FOVI (Overflow)
12
13
14
15
16
17
18
H'0018 to H'0019
H'001A to H'001B
H'001C to H'001D
H'001E to H'001F
H'0020 to H'0021
H'0022 to H'0023
H'0024 to H'0025
8-bit timer 0 CMI0A (Compare-match A)
CMI0B (Compare-match B)
OVI0 (Overflow)
19
20
21
H'0026 to H'0027
H'0028 to H'0029
H'002A to H'002B
↓
8-bit timer 1 CMI1A (Compare-match A)
CMI1B (Compare-match B)
OVI1 (Overflow)
22
23
24
H'002C to H'002D
H'002E to H'002F
H'0030 to H'0031
Reserved 25
26 H'0032 to H'0033
H'0034 to H'0035
Serial
communication
interface
ERI (Receive error)
RXI (Receive end)
TXI (TDR empty)
TEI (TSR empty)
27
28
29
30
H'0036 to H'0037
H'0038 to H'0039
H'003A to H'003B
H'003C to H'003D
Reserved 31
32
33
34
H'003E to H'003F
H'0040 to H'0041
H'0042 to H'0043
H'0044 to H'0045
A/D converter ADI (Conversion end) 35 H'0046 to H'0047
Watchdog timer WOVF (WDT overflow) 36 H'0048 to H'0049 Low
Notes: 1. H'0000 and H'0001 contain the reset vector.
2. H'0002 to H'0005 are reserved in the H8/3522 and are not available to the user.
75
4.3.2 Interrupt-Related Registers
The interrupt-related registers are the system control register (SYSCR), IRQ sense control
register (ISCR), IRQ enable register (IER), and keyboard matrix interrupt mask register
(KMIMR).
Table 4-3 Registers Read by Interrupt Controller
Name Abbreviation Read/write Address
System control register SYSCR R/W H'FFC4
IRQ sense control register ISCR R/W H'FFC6
IRQ enable register IER R/W H'FFC7
Keyboard matrix interrupt mask register KMIMR R/W H'FFF1
System Control Register (SYSCR)
Bit
[H8/3534]
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
(HIE)
0
R/W
Bit
[H8/3522]
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
—
1
—
The valid edge on the
10,
line is controlled by bit 2 (NMIEG) in the system control register.
Bit 2—NMI Edge (NMIEG): Determines whether a nonmaskable interrupt is generated on the
falling or rising edge of the
10,
input signal.
Bit 2
NMIEG Description
0 An interrupt is generated on the falling edge of
10,
. (Initial value)
1 An interrupt is generated on the rising edge of
10,
.
See section 3.2, System Control Register, for information on the other SYSCR bits.
76
IRQ Sense Control Register (ISCR)
Bit
[H8/3534]
Initial value
Read/Write
7
IRQ7SC
0
R/W
6
IRQ6SC
0
R/W
5
IRQ5SC
0
R/W
4
IRQ4SC
0
R/W
3
IRQ3SC
0
R/W
0
IRQ0SC
0
R/W
2
IRQ2SC
0
R/W
1
IRQ1SC
0
R/W
Bit
[H8/3522]
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IRQ0SC
0
R/W
2
IRQ2SC
0
R/W
1
IRQ1SC
0
R/W
[H8/3534]
Bits 0 to 7—IRQ0 to IRQ7 Sense Control (IRQ0SC to IRQ7SC): These bits determine
whether
,54
to
,54
7 are level-sensed or sensed on the falling edge.
Bits 0 to 7
IRQ0SC to IRQ7SC Description
0 An interrupt is generated when
,54
0 to
,54
7 (Initial value)
inputs are low.
1 An interrupt is generated by the falling edge of the
,54
0 to
,54
7 inputs.
[H8/3522]
Bits 3 to 7—Reserved: These bits cannot be modified and are always read as 1.
Bits 0 to 2—IRQ0 to IRQ2 Sense Control (IRQ0SC to IRQ2SC): These bits determine
whether
,54
0 to
,54
2 are level-sensed or sensed on the falling edge.
Bits 0 to 2
IRQ0SC to IRQ2SC Description
0 An interrupt is generated when
,54
0 to
,54
2 inputs are low. (Initial value)
1 An interrupt is generated by the falling edge of the
,54
0 to
,54
2 inputs.
77
IRQ Enable Register (IER)
Bit
[H8/3534]
Initial value
Read/Write
7
IRQ7E
0
R/W
6
IRQ6E
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
0
IRQ0E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
Bit
[H8/3522]
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IRQ0E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
[H8/3534]
Bits 0 to 7—IRQ0 to IRQ7 Enable (IRQ0E to IRQ7E): These bits enable or disable the IRQ0
to IRQ7 interrupts individually.
Bits 0 to 7
IRQ0E to IRQ7E Description
0 IRQ0 to IRQ7 interrupt requests are disabled. (Initial value)
1 IRQ0 to IRQ7 interrupt requests are enabled.
[H8/3522]
Bits 3 to 7—Reserved: These bits cannot be modified and are always read as 1.
Bits 0 to 2—IRQ0 to IRQ2 Enable (IRQ0E to IRQ2E): These bits enable or disable the IRQ0
to IRQ2 interrupts individually.
Bits 0 to 2
IRQ0E to IRQ2E Description
0 IRQ0 to IRQ2 interrupt requests are disabled. (Initial value)
1 IRQ0 to IRQ2 interrupt requests are enabled.
When edge sensing is selected (by setting bits IRQ0SC to IRQ7SC* to 1), it is possible for an
interrupt-handling routine to be executed even though the corresponding enable bit (IRQ0E to
IRQ7E*) is cleared to 0 and the interrupt is disabled. If an interrupt is requested while the enable
bit (IRQ0E to IRQ7E) is set to 1, the request will be held pending until served. If the enable bit
is cleared to 0 while the request is still pending, the request will remain pending, although new
requests will not be recognized. If the interrupt mask bit (I) in the CCR is cleared to 0, the
interrupt-handling routine can be executed even though the enable bit is now 0.
78
If execution of interrupt-handling routines under these conditions is not desired, it can be
avoided by using the following procedure to disable and clear interrupt requests.
1. Set the I bit to 1 in the CCR, masking interrupts. Note that the I bit is set to 1 automatically
when execution jumps to an interrupt vector.
2. Clear the desired bits from IRQ0E to IRQ7E to 0 to disable new interrupt requests.
3. Clear the corresponding IRQ0SC to IRQ7SC bits to 0, then set them to 1 again. Pending
IRQn interrupt requests are cleared when I = 1 in the CCR, IRQnSC = 0, and IRQnE = 0.
Note: *For the H8/3522, read "IRQ0SC to IRQ2SC bits " and "IRQ0E to IRQ2E bits",
respectively.
Keyboard Matrix Interrupt Mask Register (KMIMR) [H8/3534 only]
KMIMR is provided as a register for keyboard matrix interrupt masking. This register controls
interrupts from the KEYIN0 to KEYIN7 key sense input pins for a 16 × 8 matrix keyboard.
Bits KMIMR0 to KMIMR7 of KMIMR correspond to key sense inputs KEYIN0 to KEYIN7.
In interrupt mask bit initialization, bit KMIMR6 corresponding to the IRQ6/KEYIN6 pin is set to
enable interrupt requests, while the other mask bits are set to disable interrupts.
KMIMR is an 8-bit readable/writable register used in keyboard matrix scan/sense. This register
initializes to a state in which only the input at the IRQ6 pin is enabled. To enable key sense input
interrupts from two or more pins in keyboard matrix scanning and sensing, clear the
corresponding mask bits to 0.
Bit
[H8/3534]
Initial value
Read/Write
7
KMIMR7
1
R/W
6
KMIMR6
0
R/W
5
KMIMR5
1
R/W
4
KMIMR4
1
R/W
3
KMIMR3
1
R/W
0
KMIMR0
1
R/W
2
KMIMR2
1
R/W
1
KMIMR1
1
R/W
Bits 0 to 7—Keyboard Matrix Interrupt Mask (KMIMR7 to KMIMR0): These bits control
key sense input interrupt requests KEYIN7 to KEYIN0.
Bits 0 to 7
KMIMR0 to KMIMR7 Description
0 Key sense input interrupt request is enabled.
1 Key sense input interrupt request is disabled. (Initial value)*
Note: * Except KMIMR6, which is initially 0.
79
Figure 4-3 shows the relationship between the IRQ6 interrupt and KMIMR.
IRQ
6
E
IRQ
6
SC
KMIMR0 ("1")
P6
0
/KEYIN
0
KMIMR7 ("1")
P6
7
/KEYIN
7
KMIMR6 ("0")
P6
6
/KEYIN
6
/IRQ
6
.
.
.
.
.
.
.
.
IRQ
6
internal signal
Edge/level select
and enable/
disable control
IRQ
6
interrupt
Initial values are given in parentheses
Figure 4-3 KMIMR and IRQ6 Interrupt
4.3.3 External Interrupts
NMI, IRQ0, IRQ1, IRQ2, and IRQ6 can be used to recover from software standby mode.
(1) NMI: A nonmaskable interrupt is generated on the rising or falling edge of the
10,
input
signal regardless of whether the I (interrupt mask) bit is set in the CCR. The valid edge is
selected by the NMIEG bit in the system control register. The NMI vector number is 3. In the
NMI hardware exception-handling sequence the I bit in the CCR is set to 1.
(2) IRQ0 to IRQ7*: These interrupt signals are level-sensed or sensed on the falling edge of the
input, as selected by ISCR bits IRQ0SC to IRQ7SC*. These interrupts can be masked
collectively by the I bit in the CCR, and can be enabled and disabled individually by setting
and clearing bits IRQ0E to IRQ7E* in the IRQ enable register.
In the H8/3534, the IRQ6 input signal can be logically ORed internally with the key sense
input signals.
When KEYIN0 to KEYIN7 pins (P60 to P67) are used for key sense input, the corresponding
KMIMR bits should be cleared to 0 to enable the corresponding key sense input interrupts.
KMIMR bits corresponding to unused key sense inputs should be set to 1 to disable the
interrupts. All 8 key sense input interrupts are combined into a single IRQ6 interrupt.
80
When one of these interrupts is accepted, the I bit is set to 1. IRQ0 to IRQ7 have interrupt
vector numbers 4 to 11. They are prioritized in order from IRQ7 (low) to IRQ0 (high). For
details, see table 4-2.
Interrupts IRQ0 to IRQ7 do not depend on whether pins IRQ0 to IRQ 7* are input or output
pins. When using external interrupts IRQ0 to IRQ7, clear the corresponding DDR bits to 0 to
set these pins to the input state, and do not use these pins as input or output pins for the
timers, serial communication interface, or A/D converter.
Note: *For the H8/3522, read “IRQ0 to IRQ2”, “bits IRQ0SC to IRQ2SC”, “ bits IRQ0E to
IRQ2E”, and “pins IRQ0 to IRQ2”, respectively.
4.3.4 Internal Interrupts
Twenty-three [H8/3534] or nineteen [H8/3522] internal interrupts can be requested by the on-
chip supporting modules. Each interrupt source has its own vector number, so the interrupt-
handling routine does not have to determine which interrupt has occurred. All internal interrupts
are masked when the I bit in the CCR is set to 1. When one of these interrupts is accepted, the I
bit is set to 1 to mask further interrupts (except NMI). The vector numbers are 12 to 36. For the
priority order, see table 4-2.
81
4.3.5 Interrupt Handling
Interrupts are controlled by an interrupt controller that arbitrates between simultaneous interrupt
requests, commands the CPU to start the hardware interrupt exception-handling sequence, and
furnishes the necessary vector number. Figure 4-4 shows a block diagram of the interrupt
controller.
IRQ
0
flag
IRQ0E
OVF
OVIE
CPU
I (CCR)
NMI interrupt Interrupt
controller
Priority
decision
IRQ
0
interrupt Interrupt request
Vector number
WOVF
interrupt
Note: *
*
For edge-sensed interrupts, these AND gates change to the circuit shown below.
IRQ0 edge
IRQ0E SQ
IRQ0 flag
IRQ0 interrupt
Figure 4-4 Block Diagram of Interrupt Controller
The IRQ interrupts and interrupts from the on-chip supporting modules (except for reset selected
for a watchdog timer overflow) all have corresponding enable bits. When the enable bit is
cleared to 0, the interrupt signal is not sent to the interrupt controller, so the interrupt is ignored.
These interrupts can also all be masked by setting the CPU’s interrupt mask bit (I) to 1.
Accordingly, these interrupts are accepted only when their enable bit is set to 1 and the I bit is
cleared to 0.
The nonmaskable interrupt (NMI) is always accepted, except in the reset state and hardware
standby mode.
82
When an NMI or another enabled interrupt is requested, the interrupt controller transfers the
interrupt request to the CPU and indicates the corresponding vector number. (When two or more
interrupts are requested, the interrupt controller selects the vector number of the interrupt with
the highest priority.) When notified of an interrupt request, at the end of the current instruction
or current hardware exception-handling sequence, the CPU starts the hardware exception-
handling sequence for the interrupt and latches the vector number.
Figure 4-5 shows the interrupt-handling sequence.
(1) An interrupt request is sent to the interrupt controller when an NMI interrupt occurs, and
when an interrupt occurs on an IRQ input line or in an on-chip supporting module provided
the enable bit of that interrupt is set to 1.
(2) The interrupt controller checks the I bit in CCR and accepts the interrupt request if the I bit is
cleared to 0. If the I bit is set to 1 only NMI requests are accepted; other interrupt requests
remain pending.
(3) Among all accepted interrupt requests, the interrupt controller selects the request with the
highest priority and passes it to the CPU. Other interrupt requests remain pending.
(4) When it receives the interrupt request, the CPU waits until completion of the current
instruction or hardware exception-handling sequence, then starts the hardware exception-
handling sequence for the interrupt and latches the interrupt vector number.
(5) In the hardware exception-handling sequence, the CPU first pushes the PC and CCR onto the
stack. See figure 4-6. The stacked PC indicates the address of the first instruction that will be
executed on return from the software interrupt-handling routine.
(6) Next the I bit in CCR is set to 1, masking all further interrupts except NMI.
(7) The vector address corresponding to the vector number is generated, the vector table entry at
this vector address is loaded into the program counter, and execution branches to the
software interrupt-handling routine at the address indicated by that entry.
Figure 4-7 shows the interrupt timing sequence for the case in which the software interrupt-
handling routine is in on-chip ROM and the stack is in on-chip RAM.
83
Program execution
No
No
No
Yes
No
Yes
Yes
Yes
No
Yes
NMI?
I = 0?
IRQ
0
?
IRQ
1
?
WOVF
Reset
I← 1
Interrupt
requested?
Pending
Latch vector no.
Save PC
Save CCR
Read vector address
Branch to software
interrupt-handling
routine
Yes
Figure 4-5 Hardware Interrupt-Handling Sequence
84
SP(R7)SP – 4
SP – 3
SP – 2
SP – 1
SP (R7)
SP + 1
SP + 2
SP + 3
SP + 4 Even address
CCR
CCR*
PCH
Before interrupt
is accepted After interrupt
is accepted
Pushed onto stack
Upper byte of progam counter
Lower byte of progam counter
Condition code register
Stack pointer
PCH:
PCL:
CCR:
SP: The PC contains the address of the first instruction
executed after return.
Registers must be saved and restored by word
access at an even address.
Notes: 1.
2.
* Ignored on return.
Stack area
PCL
Figure 4-6 Usage of Stack in Interrupt Handling
The CCR is comprised of one byte, but when it is saved to the stack, it is treated as one word of
data. During interrupt processing, two identical bytes of CCR data are saved to the stack to
create one word of data. When the RTE instruction is executed to restore the value from the
stack, the byte located at the even address is loaded into CCR, and the byte located at the odd
address is ignored.
85
(3) (5) (6) (8) (9)(1)
Interrupt priority
decision. Wait for
end of instruction.
Interrupt
accepted
Internal
process-
ing Stack
Vector
fetch Internal
process-
ing
Instruction prefetch
(first instruction of
interrupt-handling
routine)
Interrupt request
signal
Internal address
bus
Internal write
signal
Internal read
signal
Internal 16-bit
data bus
ø
(1)(2) (4) (7) (9) (10)
Instruction
prefetch
(1)
(2) (4)
(3)
(5)
(6)
(7)
(8)
(9)
(10)
Instruction prefetch address (Pushed on stack. Instruction is executed on return from interrupt-handling
routine.)
Instruction code (Not executed)
Instruction prefetch address (Not executed)
SP–2
SP–4
CCR
Address of vector table entry
Vector table entry (address of first instruction of interrupt-handling routine)
First instruction of interrupt-handling routine
Figure 4-7 Timing of Interrupt Sequence
86
4.3.6 Interrupt Response Time
Table 4-4 indicates the number of states that elapse from an interrupt request signal until the first
instruction of the software interrupt-handling routine is executed. Since on-chip memory is
accessed 16 bits at a time, very fast interrupt service can be obtained by placing interrupt-
handling routines in on-chip ROM and the stack in on-chip RAM.
Table 4-4 Number of States before Interrupt Service
Number of States
No. Reason for Wait On-Chip Memory External Memory
1 Interrupt priority decision 2*32*3
2 Wait for completion of
current instruction*11 to 13 5 to 17*2
3 Save PC and CCR 4 12*2
4 Fetch vector 2 6*2
5 Fetch instruction 4 12*2
6 Internal processing 4 4
Total 17 to 29 41 to 53 *2
Notes: 1. These values do not apply if the current instruction is EEPMOV.
2. If wait states are inserted in external memory access, add the number of wait states.
3. 1 for internal interrupts.
4.3.7 Precaution
Note that the following type of contention can occur in interrupt handling.
When software clears the enable bit of an interrupt to 0 to disable the interrupt, the interrupt
becomes disabled after execution of the clearing instruction. If an enable bit is cleared by a
BCLR or MOV instruction, for example, and the interrupt is requested during execution of that
instruction, at the instant when the instruction ends the interrupt is still enabled, so after
execution of the instruction, the hardware exception-handling sequence is executed for the
interrupt. If a higher-priority interrupt is requested at the same time, however, the hardware
exception-handling sequence is executed for the higher-priority interrupt and the interrupt that
was disabled is ignored.
Similar considerations apply when an interrupt request flag is cleared to 0.
87
Figure 4-8 shows an example in which the OCIAE bit is cleared to 0.
ø
Internal address bus
OCIAE
OCIA exception handling
OCIA interrupt signal
OCFA
CPU write
cycle to TIER
Internal write signal
TIER address
Figure 4-8 Contention between Interrupt and Disabling Instruction
The above contention does not occur if the enable bit or flag is cleared to 0 while the interrupt
mask bit (I) is set to 1.
4.4 Note on Stack Handling
In word access, the least significant bit of the address is always assumed to be 0. The stack is
always accessed by word access. Care should be taken to keep an even value in the stack pointer
(general register R7). Use the PUSH Rn and POP Rn (or MOV.W Rn, @–SP and MOV.W
@SP+, Rn) instructions to push and pop registers on the stack.
Setting the stack pointer to an odd value can cause programs to crash. Figure 4-9 shows an
example of damage caused when the stack pointer contains an odd address.
88
PC
H
SP PC
L
H'FECD
H'FECF
H'FECC
BSR instruction MOV.B R1L, @–R7
PC is improperly stored
beyond top of stack
H'FECF set in SP PC
H
is lost
PC
H
:
PC
L
:
R1L:
SP:
Upper byte of program counter
Lower byte of program counter
General register
Stack pointer
SP
R1L
SP
PC
L
Figure 4-9 Example of Damage Caused by Setting an Odd Address in SP
89
Section 5 Wait-State Controller
5.1 Overview
The H8/3534 and H8/3522 have an on-chip wait-state controller that enables insertion of wait
states into bus cycles for interfacing to low-speed external devices.
5.1.1 Features
Features of the wait-state controller are listed below.
• Three selectable wait modes: programmable wait mode, pin auto-wait mode, and pin wait
mode
• Automatic insertion of zero to three wait states
90
5.1.2 Block Diagram
Figure 5-1 shows a block diagram of the wait-state controller.
WAIT Wait-state controller
(WSC)
WSCR
Internal data bus
Wait request
signal
Legend
WSCR: Wait-state control register
Figure 5-1 Block Diagram of Wait-State Controller
91
5.1.3 Input/Output Pins
Table 5-1 summarizes the wait-state controller’s input pin.
Table 5-1 Wait-State Controller Pins
Name Abbreviation I/O Function
Wait
:$,7
Input Wait request signal for access to external addresses
5.1.4 Register Configuration
Table 5-2 summarizes the wait-state controller’s register.
Table 5-2 Register Configuration
Address Name Abbreviation R/W Initial Value
H'FFC2 Wait-state control register WSCR R/W H'08
5.2 Register Description
5.2.1 Wait-State Control Register (WSCR)
WSCR is an 8-bit readable/writable register that selects the wait mode for the wait-state
controller (WSC) and specifies the number of wait states. It also controls frequency division of
the clock signals supplied to the supporting modules.
Bit
[H8/3534]
Initial value
Read/Write
7
(RAMS)
0
R/W
6
(RAM0)
0
R/W
5
CKDBL
0
R/W
4
—
0
R/W
3
WMS1
1
R/W
0
WC0
0
R/W
2
WMS0
0
R/W
1
WC1
0
R/W
Bit
[H8/3522]
Initial value
Read/Write
7
—
0
R/W
6
—
0
R/W
5
CKDBL
0
R/W
4
—
0
R/W
3
WMS1
1
R/W
0
WC0
0
R/W
2
WMS0
0
R/W
1
WC1
0
R/W
WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
92
Bit 7—RAM Select (RAMS) [H8/3534]
Bit 6—RAM Area Select (RAM0) [H8/3534]
These bits are reserved. They should not be set to 1.
Bits 7 and 6—Reserved: [H8/3522] These bits are reserved, but they can be written and read.
Their initial value is 0.
Bit 5—Clock Double (CKDBL): Controls frequency division of clock signals supplied to
supporting modules. For details, see section 6, Clock Pulse Generator.
Bit 4—Reserved: This bit is reserved, but it can be written and read. Its initial value is 0.
Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1/0): These bits select the wait mode.
Bit 3
WMS1 Bit 2
WMS0 Description
0 0 Programmable wait mode
1 No wait states inserted by wait-state controller
1 0 Pin wait mode (Initial value)
1 Pin auto-wait mode
Bits 1 and 0—Wait Count 1 and 0 (WC1/0): These bits select the number of wait states
inserted in access to external address areas.
Bit 1
WC1 Bit 0
WC0 Description
0 0 No wait states inserted by wait-state controller (Initial value)
1 1 state inserted
1 0 2 states inserted
1 3 states inserted
93
5.3 Wait Modes
Programmable Wait Mode: The number of wait states (TW) selected by bits WC1 and WC0 are
inserted in all accesses to external addresses. Figure 5-2 shows the timing when the wait count is
1 (WC1 = 0, WC0 = 1).
T
1 T
2 T
W T
3
ø
Address bus
AS
RD
WR
Data bus
Data bus
External address
Read data
Write data
Read
access
Write
access
Figure 5-2 Programmable Wait Mode
94
Pin Wait Mode: In all accesses to external addresses, the number of wait states (TW) selected by
bits WC1 and WC0 are inserted. If the
:$,7
pin is low at the fall of the system clock (φ) in the
last of these wait states, an additional wait state is inserted. If the
:$,7
pin remains low, wait
states continue to be inserted until the
:$,7
signal goes high.
Pin wait mode is useful for inserting four or more wait states, or for inserting different numbers
of wait states for different external devices.
Figure 5-3 shows the timing when the wait count is 1 (WC1 = 0, WC0 = 1) and one additional
wait state is inserted by
:$,7
input.
Address bus
Data bus
AS
RD
WR
T
1
T
2
T
W
T
W
T
3
Write data
*
Read data
*
Read
access
Write
access
Note: Arrows indicate time of sampling of the pin.*WAIT
ø
pinWAIT
Data bus
External address
Write data
Inserted by
wait count Inserted by
signalWAIT
Figure 5-3 Pin Wait Mode
95
Pin Auto-Wait Mode: If the
:$,7
pin is low, the number of wait states (TW) selected by bits
WC1 and WC0 are inserted.
In pin auto-wait mode, if the
:$,7
pin is low at the fall of the system clock (φ) in the T2 state,
the number of wait states (TW) selected by bits WC1 and WC0 are inserted. No additional wait
states are inserted even if the
:$,7
pin remains low. Pin auto-wait mode can be used for an
easy interface to low-speed memory, simply by routing the chip select signal to the
:$,7
pin.
Figure 5-4 shows the timing when the wait count is 1.
ø
Address bus
Data bus
AS
RD
WR
Data bus
T
1
T
2
T
3
T
1
T
2
T
W
T
3
**
Read data Read data
Write data Write data
Read
access
Write
access
Note: Arrows indicate time of sampling of the pin.*WAIT
External address External address
WAIT
Figure 5-4 Pin Auto-Wait Mode
96
97
Section 6 Clock Pulse Generator
6.1 Overview
The H8/3534 and H8/3522 have a built-in clock pulse generator (CPG) consisting of an
oscillator circuit, a duty adjustment circuit, and a divider and a prescaler that generates clock
signals for the on-chip supporting modules.
6.1.1 Block Diagram
Figure 6-1 shows a block diagram of the clock pulse generator.
XTAL
EXTAL Oscillator
circuit
Duty
adjustment
circuit
Frequency
divider (1/2) CKDBL
ø
(system
clock)
øP
(for sup-
porting
modules) Prescaler
øP/2 to øP/4096
Figure 6-1 Block Diagram of Clock Pulse Generator
Input an external clock signal to the EXTAL pin, or connect a crystal resonator to the XTAL and
EXTAL pins. The system clock frequency (φ) will be the same as the input frequency. This same
system clock frequency (φP) can be supplied to timers and other supporting modules, or it can be
divided by two. The selection is made by software, by controlling the CKDBL bit.
98
6.1.2 Wait-State Control Register (WSCR)
WSCR is an 8-bit readable/writable register that controls frequency division of the clock signals
supplied to the supporting modules. It also controls wait-state insertion and emulation of flash
memory by RAM.
WSCR is initialized to H'08 by a reset and in hardware standby mode. It is not initialized in
software standby mode.
Bit
[H8/3534]
Initial value
Read/Write
7
(RAMS)
0
R/W
6
(RAM0)
0
R/W
5
CKDBL
0
R/W
4
—
0
R/W
3
WMS1
1
R/W
0
WC0
0
R/W
2
WMS0
0
R/W
1
WC1
0
R/W
Bit
[H8/3522]
Initial value
Read/Write
7
—
0
R/W
6
—
0
R/W
5
CKDBL
0
R/W
4
—
0
R/W
3
WMS1
1
R/W
0
WC0
0
R/W
2
WMS0
0
R/W
1
WC1
0
R/W
Bit 7—RAM Select (RAMS) [H8/3534]
Bit 6—RAM Area Select (RAM0) [H8/3534]
These bits are reserved. They should not be set to 1.
Bits 7 and 6—Reserved: [H8/3522] These bits are reserved, but they can be written and read.
Their initial value is 0.
Bit 5—Clock Double (CKDBL): Controls the frequency division of clock signals supplied to
supporting modules.
Bit 5
CKDBL Description
0 The undivided system clock (φ) is supplied as the clock (φP) for supporting modules.
(Initial value)
1 The system clock (φ) is divided by two and supplied as the clock (φP) for supporting
modules.
99
Bit 4—Reserved: This bit is reserved, but it can be written and read. Its initial value is 0.
Bits 3 and 2—Wait Mode Select 1 and 0 (WMS1/0)
Bits 1 and 0—Wait Count 1 and 0 (WC1/0)
These bits control wait-state insertion. For details, see section 5, Wait-State Controller.
6.2 Oscillator Circuit
If an external crystal is connected across the EXTAL and XTAL pins, the on-chip oscillator
circuit generates a system clock signal. Alternatively, an external clock signal can be applied to
the EXTAL pin.
1. Connecting an External Crystal
(1) Circuit Configuration: An external crystal can be connected as in the example in figure
6-2. Table 6-1 indicates the appropriate damping resistance Rd. An AT-cut parallel
resonance crystal should be used.
EXTAL
XTAL
C
L1
C
L2
C = C = 10 pF to 22 pF
L1 L2
Rd
Figure 6-2 Connection of Crystal Oscillator (Example)
Table 6-1 Damping Resistance
Frequency (MHz) 4 8 10
Rd (Ω) 500 200 0
100
(2) Crystal Oscillator: Figure 6-3 shows an equivalent circuit of the crystal resonator. The
crystal resonator should have the characteristics listed in table 6-2.
XTAL
LRs
C
L
C
0
EXTAL
AT-cut parallel resonating crystal
Figure 6-3 Equivalent Circuit of External Crystal
Table 6-2 External Crystal Parameters
Frequency (MHz) 4 8 10
Rs max (Ω) 120 80 70
C0 (pF) 7 pF max
Use a crystal with the same frequency as the desired system clock frequency (φ).
101
(3) Note on Board Design: When an external crystal is connected, other signal lines
should be kept away from the crystal circuit to prevent induction from interfering with
correct oscillation. See figure 6-4. The crystal and its load capacitors should be placed as
close as possible to the XTAL and EXTAL pins.
XTAL
EXTAL
C
L2
C
L1
Not allowed Signal A Signal B
Figure 6-4 Board Design around External Crystal
102
2. Input of External Clock Signal
(1) Circuit Configuration: An external clock signal can be input as shown in the examples
in figure 6-5. In example (b) in figure 6-5, the external clock signal should be kept high
during standby.
If the XTAL pin is left open, make sure the stray capacitance does not exceed 10 pF.
EXTAL
XTAL
EXTAL
XTAL
74HC04
External clock input
Open
External clock input
(a) Connections with XTAL pin left open
(b) Connections with inverted clock input at XTAL pin
Figure 6-5 External Clock Input (Example)
103
(2) External Clock Input
The external clock signal should have the same frequency as the desired system clock (φ).
Clock timing parameters are given in table 6-3 and figure 6-6.
Table 6-3 Clock Timing
VCC =
5.0 V ±±10%
Item Symbol Min Max Unit Test Conditions
Low pulse width of external
clock input tEXL 40 — ns Figure 6-6
High pulse width of external
clock input tEXH 40 — ns
External clock rise time tEXr —10 ns
External clock fall time tEXf —10 ns
Clock pulse width low tCL 0.3 0.7 tcyc φ ≥ 5 MHz Figure 17-4
0.4 0.6 tcyc φ < 5 MHz
Clock pulse width high tCH 0.3 0.7 tcyc φ ≥ 5 MHz
0.4 0.6 tcyc φ < 5 MHz
t
EXH
t
EXL
t
EXf
t
EXr
V
CC
× 0.5
EXTAL
Figure 6-6 External Clock Input Timing
104
Table 6- 4 shows the external clo ck o utp u t s ettlin g d elay time. Figure 6- 7 s h o w s the timing fo r the
extern al clock o u tpu t settling delay time. Th e o s cillato r and d u ty co r r ection cir cuit h av e th e fu n ctio n o f
regulating the waveform of the external clock input to the EXTAL pin. When the specified clock
signal is input to the EXTAL pin, internal clock signal output is confirmed after the elapse of the
extern al clock o u tpu t settling delay time ( t DEXT). As clock signal output is not confirmed during the tDEXT
period, the reset signal s hould be driven low and the res et state maintained during this time.
Table 6-4 External Clock Output Settling Delay Time
Conditions: VCC = 4.5 to 5.5 V, AVCC = 4.5 to 5.5 V, VSS = AVSS = 0 V
Item Symbol Min Max Unit Notes
External clock output settling
delay time tDEXT*500 — µs Figure 6-7
Note: *tDEXT includes a 10 tcyc
5(6
pulse width (tRESW).
V
CC
STBY
EXTAL
ø (internal or
external)
RES
t
DEXT
*
Note: * t
DEXT
includes a 10 t
cyc
RES pulse width (t
RESW
).
4.5 V
V
IH
Figure 6-7 External Clock Output Settling Delay Time
6.3 Duty Adjustment Circuit
When the clock frequency is 5 MHz or above, the duty adjustment circuit adjusts the duty cycle
of the signal from the oscillator circuit to generate the system clock (φ).
6.4 Prescaler
The clock for the on-chip supporting modules (φP) has either the same frequency as the system
clock (φ) or this frequency divided by two, depending on the CKDBL bit. The prescaler divides
the frequency of φP to generate internal clock signals with frequencies from φP/2 to φP/4096.
105
Section 7 I/O Ports
7.1 Overview
The H8/3534 has six 8-bit input/output ports, one 7-bit input/output port, one 3-bit input/output
port, and one 8-bit dedicated input port. The H8/3522 has five 8-bit input/output ports, one 3-bit
input/output port, and one 8-bit dedicated input port.
Table 7-1 lists the functions of each port in each operating mode. As table 7-1 indicates, the port
pins are multiplexed, and the pin functions differ depending on the operating mode.
Each port has a data direction register (DDR) that selects input or output, and a data register
(DR) that stores output data. If bit manipulation instructions will be executed on the port data
direction registers, see “Notes on Bit Manipulation Instructions” in section 2.5.5, Bit
Manipulation Instructions.
Ports 1, 2, 3, 4, 6, and 9 can drive one TTL load and a 90-pF capacitive load. Ports 5 and 8 can
drive one TTL load and a 30-pF capacitive load. Ports 1 and 2 can drive LEDs (with 10-mA
current sink). Ports 1 to 6, 8, and 9 can drive a darlington pair. Ports 1 to 3, and 6 have built-in
MOS pull-up transistors.
For block diagrams of the ports, see appendix C, I/O Port Block Diagrams.
106
Table 7-1 (a) Port Functions for H8/3534
Expanded Modes Single-Chip
Mode
Port Description Pins Mode 1 Mode 2 Mode 3
Master Mode
Port 1 • 8-bit I/O port
• Can drive
LEDs
• Built-in input
pull-ups
P17 to P10/A7 to A0Lower address
output (A7 to A0)Lower address
output (A7 to A0) or
general input
General
input/output
(Can also be
used as Key
scan output
port)
Port 2 • 8-bit I/O port
• Can drive
LEDs
• Built-in input
pull-ups
P27 to P20/A15 to A8Upper address
output (A15 to A8)Upper address
output (A15 to A8)
or general input
General
input/output
(Can also be
used as Key-
scan output
port)
Port 3 • 8-bit I/O port
• Built-in input
pull-ups
P37 to P30 /
D7 to D0
Data bus (D7 to D0) General
input/ output
Port 4 • 8-bit I/O port P47/PW1
P46/PW0
PWM timer 0/1 output (PW0, PW1), or general
input/output
P45/TMRI1
P44/TMO1
P43/TMCI1
8-bit timer 1 input/output (TMCI1, TMO1, TMRI1), or
general input/output
P42/TMRI0
P41/TMO0
P40/TMCI0
8-bit timer 0 input/output (TMCI0, TMO0, TMRI0) or
general input/output
Port 5 • 3-bit I/O port P52/SCK0
P51/RxD0
P50/TxD0
Serial communication interface 0 input/output (TxD0,
RxD0, SCK0) or general input/output
Port 6 • 8-bit I/Oport
• Built-in input
pull-ups
P67/
,54
7/
.(<,1
7
P66/FTOB/
,54
6/
.(<,1
6
P65/FTID/
.(<,1
5
P64/FTIC/
.(<,1
4
P63/FTIB/
.(<,1
3
P62/FTIA/
.(<,1
2
P61/FTOA/
.(<,1
1
P60/FTCI/KEYIN0
16-bit free-running timer input/output (FTCI, FTOA, FTIA,
FTIB, FTIC, FTID, FTOB), key sense interrupt
input(
.(<,1
7 to
.(<,1
0), external interrupt input (
,54
7,
,54
6), or general input/output
Port 7 • 8-bit input
port
P77~P70/AN7~AN0A/D converter analog input (AN7 to AN0) or general input
107
Table 7-1 (a) Port Functions for H8/3534 (cont)
Expanded
Modes Single-Chip
Mode
Port Description Pins Mode 1 Mode 2 Mode 3
Port 8 • 7-bit I/O
port
P86/
,54
5/SCK1
P85/
,54
4/RxD1
P84/
,54
3/TxD1
Serial communication interface 1 input/output (TxD1, RxD1,
SCK1), external interrupt input (
,54
5,
,54
4,
,54
3), or general
input/output
P83
P82
P81
P80
General input/output
Port 9 • 8-bit I/O
port
P97/
:$,7
Expanded data bus control input(
:$,7
), or
general input/output General input/
output
P96/φSystem clock (φ) output φ output or
general input
P95/
$6
P94/
:5
P93/
5'
Expanded data bus control output(
5'
,
:5
,
$6
)General input/
output
P92/
,54
0
P91/
,54
1
External interrupt (
,54
0,
,54
1) or general input/output
P90/
$'75*
/
,54
2A/D converter external trigger input (
$'75*
), external
interrupt input (
,54
2), or general input/output
108
Table 7-1 (b) Port Functions for H8/3522
Expanded
Modes Single-Chip
Mode
Port Description Pins Mode 1 Mode 2 Mode 3
Master Mode
Port 1 • 8-bit I/O
port
• Can drive
LEDs
• Built-in
input pull-
ups
P17 to P10/A7 to A0Lower address output
(A7 to A0)When DDR = 0(after
reset): general input
When DDR = 1:
lower address output
(A7 to A0)
General
input/output
Port 2 • 8-bit I/O
port
• Can drive
LEDs
• Built-in
input pull-
ups
P27 to P20/A15 to A8Upper address output
(A15 to A8)When DDR = 0
(after reset):
general input
When DDR = 1:
upper address
output (A15 to A8)
General
input/output
Port 3 • 8-bit I/O
port
• Built-in
input pull-
ups
P37 to P30/
D7 to D0
Data bus (D7 to D0) General input/
output
Port 4 • 8-bit I/O
port P47/
:$,7
Expanded data bus control input (
:$,7
) or
general input/output General input/
output
P46/φSystem clock (φ) output When DDR=0:
(after reset): When
DDR=1:general
input φ output
P45/
$6
P44/
:5
P43/
5'
Expanded data bus control output(
5'
,
:5
,
$6
)General input/
output
P42/IRQ0
P41/IRQ1
External interrupt (
,54
0,
,54
1) or general input/output
P40/IRQ2/
$'75*
A/D converter external trigger input (
$'75*
), external interrupt
(
,54
2), or general input/output
Port 5 • 3-bit I/O
port P52/SCK
P51/RxD
P50/TxD
Serial communication interface input/output (TxD, RxD, SCK) or
general input/output
Port 6 • 8-bit I/O
port P67/TMO1
P66/FTOB/TMRI1
P65/FTID/TMCI1
P64/FTIC/TMO0
P63/FTIB/TMRI0
P62/FTIA
P61/FTOA
P60/FTCI/TMCI0
16-bit free-running timer input/output (FTCI, FTOA, FTIA, FTIB,
FTIC, FTID, FTOB), 8-bit timer 0 and 1 input/ output (TMCI0,
TMRI0, TMO0, TMCI1, TMRI1, TMO1), or general input/output
Port 7 • 8-bit input
port P77 to P70/AN7 to AN0A/D converter analog input (AN7 to AN0) or general input
109
7.2 Port 1
7.2.1 Overview
Port 1 is an 8-bit input/output port with the pin configuration shown in figure 7-1. The pin
functions differ depending on the operating mode.
Port 1 has built-in, software-controllable MOS input pull-up transistors that can be used in
modes 2 and 3.
Pins in port 1 can drive one TTL load and a 90-pF capacitive load. They can also drive LEDs
and darlington transistors.
P1
7
/A
7
P1
6
/A
6
P1
5
/A
5
P1
4
/A
4
P1
3
/A
3
P1
2
/A
2
P1
1
/A
1
P1
0
/A
0
Port 1
Port 1 pins
A
7
(output)
A
6
(output)
A
5
(output)
A
4
(output)
A
3
(output)
A
2
(output)
A
1
(output)
A
0
(output)
Pin configuration
in mode 1
(expanded mode
with on-chip ROM
disabled)
A
7
(output)/P1
7
(input)
A
6
(output)/P1
6
(input)
A
5
(output)/P1
5
(input)
A
4
(output)/P1
4
(input)
A
3
(output)/P1
3
(input)
A
2
(output)/P1
2
(input)
A
1
(output)/P1
1
(input)
A
0
(output)/P1
0
(input)
Pin configuration
in mode 2
(expanded mode
with on-chip ROM
enabled)
P1
7
(input/output)
P1
6
(input/output)
P1
5
(input/output)
P1
4
(input/output)
P1
3
(input/output)
P1
2
(input/output)
P1
1
(input/output)
P1
0
(input/output)
Pin configuration in mode 3
(single-chip mode)
Figure 7-1 Port 1 Pin Configuration
110
7.2.2 Register Configuration and Descriptions
Table 7-2 summarizes the port 1 registers.
Table 7-2 Port 1 Registers
Name Abbreviation Read/Write Initial Value Address
Port 1 data direction register P1DDR W H'FF (mode 1)
H'00 (modes 2 and 3) H'FFB0
Port 1 data register P1DR R/W H'00 H'FFB2
Port 1 input pull-up control
register P1PCR R/W H'00 H'FFAC
Port 1 Data Direction Register (P1DDR)
Bit
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
7
P1
7
DDR
1
—
0
W
6
P1
6
DDR
1
—
0
W
5
P1
5
DDR
1
—
0
W
4
P1
4
DDR
1
—
0
W
3
P1
3
DDR
1
—
0
W
0
P1
0
DDR
1
—
0
W
2
P1
2
DDR
1
—
0
W
1
P1
1
DDR
1
—
0
W
P1DDR controls the input/output direction of each pin in port 1.
Mode 1: The P1DDR values are fixed at 1. Port 1 consists of lower address output pins. P1DDR
values cannot be modified and are always read as 1.
In hardware standby mode, the address bus is in the high-impedance state.
Mode 2: A pin in port 1 is used for address output if the corresponding P1DDR bit is set to 1,
and for general input if this bit is cleared to 0.
Mode 3: A pin in port 1 is used for general output if the corresponding P1DDR bit is set to 1,
and for general input if this bit is cleared to 0.
In modes 2 and 3, P1DDR is a write-only register. Read data is invalid. If read, all bits always
read 1. P1DDR is initialized to H'00 by a reset and in hardware standby mode. In software
standby mode it retains its existing values, so if a transition to software standby mode occurs
while a P1DDR bit is set to 1, the corresponding pin remains in the output state.
111
Port 1 Data Register (P1DR)
Bit
Initial value
Read/Write
7
P1
0
R/W
7
6
P1
0
R/W
6
5
P1
0
R/W
5
4
P1
0
R/W
4
3
P1
0
R/W
3
2
P1
0
R/W
2
1
P1
0
R/W
1
0
P1
0
R/W
0
P1DR is an 8-bit register that stores data for pins P17 to P10. When a P1DDR bit is set to 1, if
port 1 is read, the value in P1DR is obtained directly, regardless of the actual pin state. When a
P1DDR bit is cleared to 0, if port 1 is read the pin state is obtained.
P1DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values.
Port 1 Input Pull-Up Control Register (P1PCR)
Bit
Initial value
Read/Write
7
P1
7
PCR
0
R/W
6
P1
6
PCR
0
R/W
5
P1
5
PCR
0
R/W
4
P1
4
PCR
0
R/W
3
P1
3
PCR
0
R/W
0
P1
0
PCR
0
R/W
2
P1
2
PCR
0
R/W
1
P1
1
PCR
0
R/W
P1PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 1.
If a P1DDR bit is cleared to 0 (designating input) and the corresponding P1PCR bit is set to 1,
the input pull-up transistor is turned on.
P1PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values.
112
7.2.3 Pin Functions in Each Mode
Port 1 has different pin functions in different modes. A separate description for each mode is
given below.
Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 1 is
automatically used for lower address output (A7 to A0). Figure 7-2 shows the pin functions in
mode 1.
A
7
(output)
A
6
(output)
A
5
(output)
A
4
(output)
A
3
(output)
A
2
(output)
A
1
(output)
A
0
(output)
Port 1
Figure 7-2 Pin Functions in Mode 1 (Port 1)
113
Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 1 can provide lower
address output pins and general input pins. Each pin becomes a lower address output pin if its
P1DDR bit is set to 1, and a general input pin if this bit is cleared to 0. Following a reset, all pins
are input pins. To be used for address output, their P1DDR bits must be set to 1. Figure 7-3
shows the pin functions in mode 2.
A
7
(output)
A
6
(output)
A
5
(output)
A
4
(output)
A
3
(output)
A
2
(output)
A
1
(output)
A
0
(output)
When P1DDR = 1
P1
7
(input)
P1
6
(input)
P1
5
(input)
P1
4
(input)
P1
3
(input)
P1
2
(input)
P1
1
(input)
P1
0
(input)
When P1DDR = 0
Port 1
Figure 7-3 Pin Functions in Mode 2 (Port 1)
114
Mode 3: In mode 3 (single-chip mode), the input or output direction of each pin can be selected
individually. A pin becomes a general input pin when its P1DDR bit is cleared to 0 and a general
output pin when this bit is set to 1. Figure 7-4 shows the pin functions in mode 3.
P1
7
(input/output)
P1
6
(input/output)
P1
5
(input/output)
P1
4
(input/output)
P1
3
(input/output)
P1
2
(input/output)
P1
1
(input/output)
P1
0
(input/output)
Port 1
Figure 7-4 Pin Functions in Mode 3 (Port 1)
115
7.2.4 Input Pull-Up Transistors
Port 1 has built-in programmable input pull-up transistors that are available in modes 2 and 3.
The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in
mode 2 or 3, set the corresponding P1PCR bit to 1 and clear the corresponding P1DDR bit to 0.
P1PCR is cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups
off. In software standby mode, the previous state is maintained.
Table 7-3 indicates the states of the input pull-up transistors in each operating mode.
Table 7-3 States of Input Pull-Up Transistors (Port 1)
Mode Reset Hardware Standby Software Standby Other Operating Modes
1 Off Off Off Off
2 Off Off On/off On/off
3 Off Off On/off On/off
Notes: Off: The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P1PCR = 1 and P1DDR = 0, but
offotherwise.
116
7.3 Port 2
7.3.1 Overview
Port 2 is an 8-bit input/output port with the pin configuration shown in figure 7-5. The pin
functions differ depending on the operating mode.
Port 2 has built-in, software-controllable MOS input pull-up transistors that can be used in
modes 2 and 3.
Pins in port 2 can drive one TTL load and a 90-pF capacitive load. They can also drive LEDs
and darlington transistors.
117
P2
7
/A
15
P2
6
/A
14
P2
5
/A
13
P2
4
/A
12
P2
3
/A
11
P2
2
/A
10
P2
1
/A
9
P2
0
/A
8
Port 2
Port 2 pins
A
15
(output)
A
14
(output)
A
13
(output)
A
12
(output)
A
11
(output)
A
10
(output)
A
9
(output)
A
8
(output)
Pin configuration
in mode 1
(expanded mode
with on-chip ROM
disabled)
A
15
(output)/P2
7
(input)
A
14
(output)/P2
6
(input)
A
13
(output)/P2
5
(input)
A
12
(output)/P2
4
(input)
A
11
(output)/P2
3
(input)
A
10
(output)/P2
2
(input)
A
9
(output)/P2
1
(input)
A
8
(output)/P2
0
(input)
Pin configuration
in mode 2
(expanded mode
with on-chip ROM
enabled)
P2
7
(input/output)
P2
6
(input/output)
P2
5
(input/output)
P2
4
(input/output)
P2
3
(input/output)
P2
2
(input/output)
P2
1
(input/output)
P2
0
(input/output)
Pin configuration in mode 3
(single-chip mode)
Figure 7-5 Port 2 Pin Configuration
118
7.3.2 Register Configuration and Descriptions
Table 7-4 summarizes the port 2 registers.
Table 7-4 Port 2 Registers
Name Abbreviation Read/Write Initial Value Address
Port 2 data direction register P2DDR W H'FF (mode 1)
H'00 (modes 2 and 3) H'FFB1
Port 2 data register P2DR R/W H'00 H'FFB3
Port 2 input pull-up control
register P2PCR R/W H'00 H'FFAD
Port 2 Data Direction Register (P2DDR)
Bit
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
7
P2
7
DDR
1
—
0
W
6
P2
6
DDR
1
—
0
W
5
P2
5
DDR
1
—
0
W
4
P2
4
DDR
1
—
0
W
3
P2
3
DDR
1
—
0
W
0
P2
0
DDR
1
—
0
W
2
P2
2
DDR
1
—
0
W
1
P2
1
DDR
1
—
0
W
P2DDR controls the input/output direction of each pin in port 2.
Mode 1: The P2DDR values are fixed at 1. Port 2 consists of upper address output pins. P2DDR
values cannot be modified and are always read as 1.
In hardware standby mode, the address bus is in the high-impedance state.
Mode 2: A pin in port 2 is used for address output if the corresponding P2DDR bit is set to 1,
and for general input if this bit is cleared to 0.
Mode 3: A pin in port 2 is used for general output if the corresponding P2DDR bit is set to 1,
and for general input if this bit is cleared to 0.
In modes 2 and 3, P2DDR is a write-only register. Read data is invalid. If read, all bits always
read 1. P2DDR is initialized to H'00 by a reset and in hardware standby mode. In software
standby mode it retains its existing values, so if a transition to software standby mode occurs
while a P2DDR bit is set to 1, the corresponding pin remains in the output state.
119
Port 2 Data Register (P2DR)
Bit
Initial value
Read/Write
7
P2
0
R/W
7
6
P2
0
R/W
6
5
P2
0
R/W
5
4
P2
0
R/W
4
3
P2
0
R/W
3
2
P2
0
R/W
2
1
P2
0
R/W
1
0
P2
0
R/W
0
P2DR is an 8-bit register that stores data for pins P27 to P20. When a P2DDR bit is set to 1, if
port 2 is read, the value in P2DR is obtained directly, regardless of the actual pin state. When a
P2DDR bit is cleared to 0, if port 2 is read the pin state is obtained.
P2DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values.
Port 2 Input Pull-Up Control Register (P2PCR)
Bit
Initial value
Read/Write
7
P2
7
PCR
0
R/W
6
P2
6
PCR
0
R/W
5
P2
5
PCR
0
R/W
4
P2
4
PCR
0
R/W
3
P2
3
PCR
0
R/W
0
P2
0
PCR
0
R/W
2
P2
2
PCR
0
R/W
1
P2
1
PCR
0
R/W
P2PCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 2.
If a P2DDR bit is cleared to 0 (designating input) and the corresponding P2PCR bit is set to 1,
the input pull-up transistor is turned on.
P2PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values.
120
7.3.3 Pin Functions in Each Mode
Port 2 has different pin functions in different modes. A separate description for each mode is
given below.
Pin Functions in Mode 1: In mode 1 (expanded mode with on-chip ROM disabled), port 2 is
automatically used for upper address output (A15 to A8). Figure 7-6 shows the pin functions in
mode 1.
A
15
(output)
A
14
(output)
A
13
(output)
A
12
(output)
A
11
(output)
A
10
(output)
A
9
(output)
A
8
(output)
Port 2
Figure 7-6 Pin Functions in Mode 1 (Port 2)
121
Mode 2: In mode 2 (expanded mode with on-chip ROM enabled), port 2 can provide upper
address output pins and general input pins. Each pin becomes an upper address output pin if its
P2DDR bit is set to 1, and a general input pin if this bit is cleared to 0. Following a reset, all pins
are input pins. To be used for address output, their P2DDR bits must be set to 1. Figure 7-7
shows the pin functions in mode 2.
A
15
(output)
A
14
(output)
A
13
(output)
A
12
(output)
A
11
(output)
A
10
(output)
A
9
(output)
A
8
(output)
When P2DDR = 1
P2
7
(input)
P2
6
(input)
P2
5
(input)
P2
4
(input)
P2
3
(input)
P2
2
(input)
P2
1
(input)
P2
0
(input)
When P2DDR = 0
Port 2
Figure 7-7 Pin Functions in Mode 2 (Port 2)
122
Mode 3: In mode 3 (single-chip mode), the input or output direction of each pin can be selected
individually. A pin becomes a general input pin when its P2DDR bit is cleared to 0, and a
general output pin when this bit is set to 1. Figure 7-8 shows the pin functions in mode 3.
P2
7
(input/output)
P2
6
(input/output)
P2
5
(input/output)
P2
4
(input/output)
P2
3
(input/output)
P2
2
(input/output)
P2
1
(input/output)
P2
0
(input/output)
Port 2
Figure 7-8 Pin Functions in Mode 3 (Port 2)
123
7.3.4 Input Pull-Up Transistors
Port 2 has built-in programmable input pull-up transistors that are available in modes 2 and 3.
The pull-up for each bit can be turned on and off individually. To turn on an input pull-up in
mode 2 or 3, set the corresponding P2PCR bit to 1 and clear the corresponding P2DDR bit to 0.
P2PCR is cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups
off. In software standby mode, the previous state is maintained.
Table 7-5 indicates the states of the input pull-up transistors in each operating mode.
Table 7-5 States of Input Pull-Up Transistors (Port 2)
Mode Reset Hardware Standby Software Standby Other Operating Modes
1 Off Off Off Off
2 Off Off On/off On/off
3 Off Off On/off On/off
Notes: Off: The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P2PCR = 1 and P2DDR = 0, but off
otherwise.
124
7.4 Port 3
7.4.1 Overview
Port 3 is an 8-bit input/output port that is multiplexed with the data bus. Figure 7-9 shows the pin
configuration of port 3. The pin functions differ depending on the operating mode.
Port 3 has built-in, software-controllable MOS input pull-up transistors that can be used in mode
3.
Pins in port 3 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington pair.
125
P3
7
/D
7
(input/output)
P3
6
/D
6
(input/output)
P3
5
/D
5
(input/output)
P3
4
/D
4
(input/output)
P3
3
/D
3
(input/output)
P3
2
/D
2
(input/output)
P3
1
/D
1
(input/output)
P3
0
/D
0
(input/output)
Port 3
Port 3 pins
D
7
(input/output)
D
6
(input/output)
D
5
(input/output)
D
4
(input/output)
D
3
(input/output)
D
2
(input/output)
D
1
(input/output)
D
0
(input/output)
Pin configuration in mode 1
(expanded mode with on-chip
ROM disabled) and mode 2
(expanded mode with on-chip
ROM enabled)
P3
7
(input/output)
P3
6
(input/output)
P3
5
(input/output)
P3
4
(input/output)
P3
3
(input/output)
P3
2
(input/output)
P3
1
(input/output)
P3
0
(input/output)
Pin configuration in mode 3 (single-chip mode)
Figure 7-9 Port 3 Pin Configuration
126
7.4.2 Register Configuration and Descriptions
Table 7-6 summarizes the port 3 registers.
Table 7-6 Port 3 Registers
Name Abbreviation Read/Write Initial Value Address
Port 3 data direction register P3DDR W H'00 H'FFB4
Port 3 data register P3DR R/W H'00 H'FFB6
Port 3 input pull-up control
register P3PCR R/W H'00 H'FFAE
Port 3 Data Direction Register (P3DDR)
Bit
Initial value
Read/Write
7
P3 DDR
0
W
7
6
P3 DDR
0
W
6
5
P3 DDR
0
W
5
4
P3 DDR
0
W
4
3
P3 DDR
0
W
3
2
P3 DDR
0
W
2
1
P3 DDR
0
W
1
0
P3 DDR
0
W
0
P3DDR is an 8-bit readable/writable register that controls the input/output direction of each pin
in port 3. P3DDR is a write-only register. Read data is invalid. If read, all bits always read 1.
Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and mode 2 (expanded
mode with on-chip ROM enabled), the input/output directions designated by P3DDR are
ignored. Port 3 automatically consists of the input/output pins of the 8-bit data bus (D7 to D0).
The data bus is in the high-impedance state during reset, and during hardware and software
standby.
Mode 3: A pin in port 3 is used for general output if the corresponding P3DDR bit is set to 1,
and for general input if this bit is cleared to 0. P3DDR is initialized to H'00 by a reset and in
hardware standby mode. In software standby mode it retains its existing values, so if a transition
to software standby mode occurs while a P3DDR bit is set to 1, the corresponding pin remains in
the output state.
127
Port 3 Data Register (P3DR)
Bit
Initial value
Read/Write
7
P3
0
R/W
7
6
P3
0
R/W
6
5
P3
0
R/W
5
4
P3
0
R/W
4
3
P3
0
R/W
3
2
P3
0
R/W
2
1
P3
0
R/W
1
0
P3
0
R/W
0
P3DR is an 8-bit register that stores data for pins P37 to P30. When a P3DDR bit is set to 1, if
port 3 is read, the value in P3DR is obtained directly, regardless of the actual pin state. When a
P3DDR bit is cleared to 0, if port 3 is read the pin state is obtained.
P3DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values.
Port 3 Input Pull-Up Control Register (P3PCR)
Bit
Initial value
Read/Write
7
P3
7
PCR
0
R/W
6
P3
6
PCR
0
R/W
5
P3
5
PCR
0
R/W
4
P3
4
PCR
0
R/W
3
P3
3
PCR
0
R/W
0
P3
0
PCR
0
R/W
2
P3
2
PCR
0
R/W
1
P3
1
PCR
0
R/W
P3PCR is an 8-bit readable/writable register that controls the input pull-up MOStransistors in
port 3. If a P3DDR bit is cleared to 0 (designating input) and the corresponding P3PCR bit is set
to 1, the input pull-up transistor is turned on.
P3PCR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values.
128
7.4.3 Pin Functions in Each Mode
Port 3 has different pin functions in different modes. A separate description for each mode is
given below.
Pin Functions in Modes 1 and 2: In mode 1 (expanded mode with on-chip ROM disabled) and
mode 2 (expanded mode with on-chip ROM enabled), port 3 is automatically used for the
input/output pins of the 8-bit data bus (D7 to D0). Figure 7-10 shows the pin functions in modes 1
and 2.
D
7
(input/output)
D
6
(input/output)
D
5
(input/output)
D
4
(input/output)
D
3
(input/output)
D
2
(input/output)
D
1
(input/output)
D
0
(input/output)
Port 3
Modes 1 and 2
Figure 7-10 Pin Functions in Modes 1 and 2 (Port 3)
129
Mode 3: In mode 3 (single-chip mode), port 3 is a general-purpose input/output port. A pin
becomes an output pin when its P3DDR bit is set to 1, and an input pin when this bit is cleared
to 0.
Figure 7-11 shows the pin functions in mode 3.
P3
7
(input/output)
P3
6
(input/output)
P3
5
(input/output)
P3
4
(input/output)
P3
3
(input/output)
P3
2
(input/output)
P3
1
(input/output)
P3
0
(input/output)
Port 3
Figure 7-11 Pin Functions in Mode 3 (Port 3)
130
7.4.4 Input Pull-Up Transistors
Port 3 has built-in programmable input pull-up transistors that are available in mode 3. The
pull-up for each bit can be turned on and off individually. To turn on an input pull-up in mode 3,
set the corresponding P3PCR bit to 1 and clear the corresponding P3DDR bit to 0. P3PCR is
cleared to H'00 by a reset and in hardware standby mode, turning all input pull-ups off. In
software standby mode, the previous state is maintained.
Table 7-7 indicates the states of the input pull-up transistors in each operating mode.
Table 7-7 States of Input Pull-Up Transistors (Port 3)
Mode Reset Hardware Standby Software Standby Other Operating Modes
1 Off Off Off Off
2 Off Off Off Off
3 Off Off On/off On/off
Notes: Off: The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if P3PCR = 1 and P3DDR = 0, but off
otherwise.
131
7.5 Port 4
7.5.1 Overview
Port 4 is an 8-bit input/output port that is multiplexed with input/output pins (TMRI0, TMRI1,
TMCI0, TMCI1, TMO0, TMO1) of 8-bit timers 0 and 1 and output pins (PW0, PW1) of PWM
timers 0 and 1. Port 4 pin functions are the same in all modes.
Figure 7-12 shows the pin configuration of port 4.
Pins in port 4 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington pair.
Port 4 in the H8/3522 has the same functions as port 9 in the H8/3534. For details, see section
7.10, Port 9 (H8/3534)/Port 4 (H8/3522).
P4
7
(input/output)/PW
1
(output)
P4
6
(input/output)/PW
0
(output)
P4
5
(input/output)/TMRI
1
(input)
P4
4
(input/output)/TMO
1
(output)
P4
3
(input/output)/TMCI
1
(input)
P4
2
(input/output)/TMRI
0
(input)
P4
1
(input/output)/TMO
0
(output)
P4
0
(input/output)/TMCI
0
(input)
Port 4
Port 4 pins
Figure 7-12 Port 4 Pin Configuration
132
7.5.2 Register Configuration and Descriptions
Table 7-8 summarizes the port 4 registers.
Table 7-8 Port 4 Registers
Name Abbreviation Read/Write Initial Value Address
Port 4 data direction register P4DDR W H'00 H'FFB5
Port 4 data register P4DR R/W H'00 H'FFB7
Port 4 Data Direction Register (P4DDR)
Bit
Initial value
Read/Write
7
P4 DDR
0
W
7
6
P4 DDR
0
W
6
5
P4 DDR
0
W
5
4
P4 DDR
0
W
4
3
P4 DDR
0
W
3
2
P4 DDR
0
W
2
1
P4 DDR
0
W
1
0
P4 DDR
0
W
0
P4DDR is an 8-bit readable/writable register that controls the input/output direction of each pin
in port 4. A pin functions as an output pin if the corresponding P4DDR bit is set to 1, and as an
input pin if this bit is cleared to 0.
P4DDR is a write-only register. Read data is invalid. If read, all bits always read 1.
P4DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby
mode it retains its existing values, so if a transition to software standby mode occurs while a
P4DDR bit is set to 1, the corresponding pin remains in the output state.
If a transition to software standby mode occurs while port 4 is being used by an on-chip
supporting module (for example, for 8-bit timer output), the on-chip supporting module will be
initialized, so the pin will revert to general-purpose input/output, controlled by P4DDR and
P4DR.
133
Port 4 Data Register (P4DR)
Bit
Initial value
Read/Write
7
P4
0
R/W
7
6
P4
0
R/W
6
5
P4
0
R/W
5
4
P4
0
R/W
4
3
P4
0
R/W
3
2
P4
0
R/W
2
1
P4
0
R/W
1
0
P4
0
R/W
0
P4DR is an 8-bit register that stores data for pins P47 to P40. When a P4DDR bit is set to 1, if
port 4 is read, the value in P4DR is obtained directly, regardless of the actual pin state. When a
P4DDR bit is cleared to 0, if port 4 is read the pin state is obtained. This also applies to pins
used by on-chip supporting modules.
P4DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values.
134
7.5.3 Pin Functions
Port 4 has different pin functions depending on whether the chip is or is not operating in slave
mode. Table 7-9 indicates the pin functions of port 4.
Table 7-9 Port 4 Pin Functions
Pin Pin Functions and Selection Method
P47/PW1Bit OE in TCR of PWM timer 1 and bit P47DDR select the pin function as follows
OE 0 1
P47DDR 0 1 0 1
Pin function P47 input P47 output PW1 output
P46/PW0Bit OE in TCR of PWM timer 0 and bit P46DDR select the pin function as follows
OE 0 1
P46DDR 0 1 0 1
Pin function P46 input P46 output PW0 output
P45/TMRI1
P45DDR 0 1
Pin function P45 input P45 output
TMRI1 input
TMRI1 input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of 8-bit
timer 1
P44/TMO1Bits OS3 to OS0 in TCSR of 8-bit timer 1, bit P44DDR, and the operating mode select
the pin function as follows
OS3 to 0 All 0 Not all 0
P44DDR 0 1 —
Pin function P44 input P44 output TMO1 output
135
Table 7-9 Port 4 Pin Functions (cont)
Pin Pin Functions and Selection Method
P43/TMCI1
P43DDR 0 1
Pin function P43 input P43 output
TMCI1 input
TMCI1 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 1 select an
external clock source
P42/TMRI0
P42DDR 0 1
Pin function P42 input P42 output
TMRI0 input
TMRI0 input is usable when bits CCLR1 and CCLR0 are both set to 1 in TCR of 8-bit
timer 0
P41/TMO0Bits OS3 to OS0 in TCSR of 8-bit timer 0 and bit P41DDR select the pin function as
follows
OS3 to 0 All 0 Not all 0
P41DDR 0 1 —
Pin function P41 input P41 output TMO0 output
P40/TMCI0
P40DDR 0 1
Pin function P40 input P40 output
TMCI0 input
TMCI0 input is usable when bits CKS2 to CKS0 in TCR of 8-bit timer 0 select an
external clock source
136
7.6 Port 5
7.6.1 Overview
Port 5 is a 3-bit input/output port that is multiplexed with serial communication interface 0
input/output pins (TxD0, RxD0, SCK0 in the H8/3534; TxD, RxD, SCK in the H8/3522). The
port 5 pin functions are the same in all operating modes.
Pins in port 5 can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington pair.
P52 (input/output)/SCK0 (input/output)
P51 (input/output)/RxD0 (input)
P50 (input/output)/TxD0 (output)
P52 (input/output)/SCK (input/output)
P51 (input/output)/RxD (input)
P50 (input/output)/TxD (output)
or
Port 5 pins
Port 5
Figure 7-13 Port 5 Pin Configuration
7.6.2 Register Configuration and Descriptions
Table 7-10 summarizes the port 5 registers.
Table 7-10 Port 5 Registers
Name Abbreviation Read/Write Initial Value Address
Port 5 data direction register P5DDR W H'F8 H'FFB8
Port 5 data register P5DR R/W H'F8 H'FFBA
137
Port 5 Data Direction Register (P5DDR)
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
2
P5 DDR
0
W
2
1
P5 DDR
0
W
1
0
P5 DDR
0
W
0
P5DDR is an 8-bit register that controls the input/output direction of each pin in port 5. A pin
functions as an output pin if the corresponding P5DDR bit is set to 1, and as an input pin if this
bit is cleared to 0.
P5DDR is a write-only register. Read data is invalid. Bits 7 to 3 are reserved. If read, these bits
always read 1.
P5DDR is initialized to H'F8 by a reset and in hardware standby mode. In software standby
mode it retains its existing values, so if a transition to software standby mode occurs while a
P5DDR bit is set to 1, the corresponding pin remains in the output state.
If a transition to software standby mode occurs while port 5 is being used by the SCI, the SCI
will be initialized, so the pin will revert to general-purpose input/output, controlled by P5DDR
and P5DR.
Port 5 Data Register (P5DR)
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
2
P5
0
R/W
2
1
P5
0
R/W
1
0
P5
0
R/W
0
P5DR is an 8-bit register that stores data for pins P52 to P50. Bits 7 to 3 are reserved. They
cannot be modified, and are always read as 1.
When a P5DDR bit is set to 1, if port 5 is read, the value in P5DR is obtained directly, regardless
of the actual pin state. When a P5DDR bit is cleared to 0, if port 5 is read the pin state is
obtained. This also applies to pins used as SCI pins.
P5DR is initialized to H'F8 by a reset and in hardware standby mode. In software standby mode
it retains its existing values.
138
7.6.3 Pin Functions
Port 5 has the same pin functions in each operating mode. All pins can also be used as SCI
input/output pins. Table 7-11 indicates the pin functions of port 5.
Table 7-11 Port 5 Pin Functions
Pin Pin Functions and Selection Method
P52/SCK0
or P52/SCK Bit C/
$
in SMR of SCI0, bits CKE0 and CKE1 in SCR of SCI0, and bit P52DDR select
the pin function as follows
CKE1 0 1
C/
$
01—
CKE0 0 1 — —
P52DDR 0 1 — — —
Pin function P52
input P52
output SCK0 (SCK)
output SCK0
(SCK)
output
SCK0 (SCK)
input
P51/RxD0 or
P51/RxD Bit RE in SCR of SCI0 and bit P51DDR select the pin function as follows
RE 0 1
P51DDR 0 1 —
Pin function P51 input P51 output RxD0 (RxD) input
P50/TxD0 or
P50/TxD Bit TE in SCR of SCI0 and bit P50DDR select the pin function as follows
TE 0 1
P50DDR 0 1 —
Pin function P50 input P50 output TxD0 (TxD) output
139
7.7 Port 6
7.7.1 Overview
Port 6 is an 8-bit input/output port that is multiplexed with input/output pins (FTOA, FTOB,
FTIA to FTID, FTCI) of the 16-bit free-running timer (FRT), with key-sense input pins (
.(<,1
0
to
.(<,1
7) [H8/3534], with
,54
6 and
,54
7 input pins [H8/3534], and input/output pins (TMCI0,
TMRI0, TMO0, TMCI1, TMRI1, TMO1) of 8-bit timer 0 and timer 1 [H8/3522]. The port 6 pin
functions are the same in all operating modes. Figure 7-14 shows the pin configuration of port 6.
Port 6 has built-in, software-controllable MOS input pull-up transistors. [H8/3534]
Pins in port 6 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington pair.
P6
7
(input/output)/IRQ
7
(input)/KEYIN
7
(input)
P6
6
(input/output)/FTOB (output)/IRQ
6
(input)/KEYIN
6
(input)
P6
5
(input/output)/FTID (input)/KEYIN
5
(input)
P6
4
(input/output)/FTIC (input)/KEYIN
4
(input)
P6
3
(input/output)/FTIB (input)/KEYIN
3
(input)
P6
2
(input/output)/FTIA (input)/KEYIN
2
(input)
P6
1
(input/output)/FTOA (output)/KEYIN
1
(input)
P6
0
(input/output)/FTCI (input)/KEYIN
0
(input)
Port 6
Port 6 pins
Figure 7-14 (a) H8/3534 Port 6 Pin Configuration
140
P6
7
(input/output)/TMO
1
(output)
P6
6
(input/output)/FTOB (output)/TMRI
1
(input)
P6
5
(input/output)/FTID (input)/TMCI
1
(input)
P6
4
(input/output)/FTIC (input)/TMO
0
(output)
P6
3
(input/output)/FTIB (input)/TMRI
0
(input)
P6
2
(input/output)/FTIA (input)
P6
1
(input/output)/FTOA (output)
P6
0
(input/output)/FTCI (input)/TMCI
0
(input)
Port 6
Port 6 pins
Figure 7-14 (b) H8/3522 Port 6 Pin Configuration
141
7.7.2 Register Configuration and Descriptions
Table 7-12 summarizes the port 6 registers.
Table 7-12 (a) H8/3534 Port 6 Registers
Name Abbreviation Read/Write Initial Value Address
Port 6 data direction register P6DDR W H'00 H'FFB9
Port 6 data register P6DR R/W H'00 H'FFBB
Port 6 input pull-up control
register KMPCR R/W H'00 H'FFF2
Table 7-12 (b) H8/3522 Port 6 Registers
Name Abbreviation Read/Write Initial Value Address
Port 6 data direction register P6DDR W H'00 H'FFB9
Port 6 data register P6DR R/W H'00 H'FFBB
Port 6 Data Direction Register (P6DDR)
Bit
Initial value
Read/Write
7
P6
7
DDR
0
W
6
P6
6
DDR
0
W
5
P6
5
DDR
0
W
4
P6
4
DDR
0
W
3
P6
3
DDR
0
W
2
P6
2
DDR
0
W
1
P6
1
DDR
0
W
0
P6
0
DDR
0
W
P6DDR is an 8-bit readable/writable register that controls the input/output direction of each pin
in port 6. A pin functions as an output pin if the corresponding P6DDR bit is set to 1, and as an
input pin if this bit is cleared to 0.
P6DDR is a write-only register. Read data is invalid. If read, all bits always read 1.
P6DDR is initialized to H'00 by a reset and in hardware standby mode. In software standby
mode it retains its existing values, so if a transition to software standby mode occurs while a
P6DDR bit is set to 1, the corresponding pin remains in the output state.
If a transition to software standby mode occurs while port 6 is being used by the free-running
timer, or other timer the timer will be initialized, so the pin will revert to general-purpose
input/output, controlled by P6DDR and P6DR.
142
Port 6 Data Register (P6DR)
Bit
Initial value
Read/Write
7
P6
7
0
R/W
6
P6
6
0
R/W
5
P6
5
0
R/W
4
P6
4
0
R/W
3
P6
3
0
R/W
2
P6
2
0
R/W
1
P6
1
0
R/W
0
P6
0
0
R/W
P6DR is an 8-bit register that stores data for pins P67 to P60. When a P6DDR bit is set to 1, if
port 6 is read, the value in P6DR is obtained directly, regardless of the actual pin state. When a
P6DDR bit is cleared to 0, if port 6 is read the pin state is obtained. This also applies to pins
used as FRT and timer pins.
P6DR is initialized to H'00 by a reset and in hardware standby mode. In software standby mode
it retains its existing values.
Port 6 Input Pull-Up Control Register (KMPCR) [H8/3534]
Bit
Initial value
Read/Write
7
KM
7
PCR
0
R/W
6
KM
6
PCR
0
R/W
5
KM
5
PCR
0
R/W
4
KM
4
PCR
0
R/W
3
KM
3
PCR
0
R/W
0
KM
0
PCR
0
R/W
2
KM
2
PCR
0
R/W
1
KM
1
PCR
0
R/W
KMPCR is an 8-bit readable/writable register that controls the input pull-up transistors in port 6.
If a P6DDR bit is cleared to 0 (designating input) and the corresponding KMPCR bit is set to 1,
the input pull-up transistor is turned on.
KMPCR is initialized to H'00 by a reset and in hardware standby mode. In software standby
mode it retains its existing values.
143
7.7.3 Pin Functions
Port 6 has the same pin functions in all operating modes. The pins are multiplexed with FRT
input/output,
,54
6 and
,54
7 input [H8/3534], key-sense input, and input/output of 8-bit timer 0
and timer 1 [H8/3522]. Table 7-13 indicates the pin functions of port 6.
Table 7-13 (a) H8/ 3534 Port 6 Pin Functions
Pin Pin Functions and Selection Method
P67/
,54
7/
.(<,1
7
P67DDR 0 1
Pin function P67 input P67 output
,54
7 input or
.(<,1
7 input
,54
7 input is usable when bit IRQ7E is set to 1 in IER
P66/FTOB/
,54
6/
.(<,1
6Bit OEB in TOCR of the FRT and bit P66DDR select the pin function as follows
OEB 0 1
P66DDR 0 1 0 1
Pin function P66 input P66
output FTOB output
,54
6 input or
.(<,1
6 input
,54
6 input is usable when bit IRQ6E is set to 1 in IER
P65/FTID/
.(<,1
5P65DDR 0 1
Pin function P65 input P65 output
FTID input or
.(<,1
5 input
P64/FTIC/
.(<,1
4P64DDR 0 1
Pin function P64 input P64 output
FTIC input or
.(<,1
4 input
144
Table 7-13 (a) H8/ 3534 Port 6 Pin Functions (cont)
Pin Pin Functions and Selection Method
P63/FTIB/
.(<,1
3P63DDR 0 1
Pin function P63 input P63 output
FTIB input or
.(<,1
3 input
P62/FTIA/
.(<,1
2P62DDR 0 1
Pin function P62 input P62 output
FTIA input or
.(<,1
2 input
P61/FTOA/
.(<,1
1
Bit OEA in TOCR of the FRT and bit P61DDR select the pin function as follows
OEA 0 1
P61DDR 0 1 0 1
Pin function P61 input P61 output FTOA output
.(<,1
1 input
P60/FTCI/
.(<,1
0P60DDR 0 1
Pin function P60 input P60 output
FTCI input or
.(<,1
0 input
FTCI input is usable when bits CKS1 and CKS0 in TCR of the FRT select an
external clock source
145
Table 7-13 (b) H8/3522 Port 6 Pin Functions
Pin Pin Functions and Selection Method
P67/TMO1Bits OS3 to OS0 in TCSR of 8-bit timer 1 and bit P67DDR select the pin function
as follows
OS3 to OS0 All 0 Not all 1
P67DDR 0 1 —
Pin function P67 input P67 output TMO1 output
P66/FTOB/
TMRI1
Bit OEB in TOCR of the FRT and bit P66DDR select the pin function as follows
OEB 0 1
P66DDR 0 1 —
Pin function P66 input P66 output FTOB output
TMRI1 input
TMRI1 input is usable when bit CCLR1 or CCLR0 is set to 1 in TCR of 8-bit timer
1
P65/FTID/TMCI1
P65DDR 0 1
Pin function P65 input P65 output
FTID input, TMCI1 input
TMCI1 input is usable when an external clock is selected by bits CKS2 to CKS0
in TCSR of 8-bit timer 1
P64/FTIC/ TMO0Bits OS3 to OS0 in TCSR of 8-bit timer 0 and bit P64DDR select the pin function
as follows
OS3 to OS0 All 0 Not all 1
P64DDR 0 1 —
Pin function P64 input P64 output TMO0 output
FTIC input
146
Table 7-13 (b) H8/3522 Port 6 Pin Functions (cont)
Pin Pin Functions and Selection Method
P63/FTIB/TMRI0
P63DDR 0 1
Pin function P63 input P63 output
FTIB input, TMRI0 input
TMRI0 input is usable when bit CCLR1 or CCLR0 is set to 1 in TCR of 8-bit
timer 0
P62/FTIA
P62DDR 0 1
Pin function P62 input P62 output
FTIA input
P61/FTOA Bit OEA in TOCR of the free-running timer and bit P61DDR select the pin
function as follows
OEA 0 1
P61DDR 0 1 —
Pin function P61 input P61 output FTOA output
P60/FTCI/TMRI0
P60DDR 0 1
Pin function P60 input P60 output
FTCI input, TMCI0 input
FTCI input is usable when an external clock is selected by bits CKS1 and CKS0
in TCR of the free-running timer
TMCI0 input is usable when an external clock is selected by bits CKS2 to CKS0
in TCR of 8-bit timer 0
147
7.7.4 Input Pull-Up Transistors [H8/3534]
Port 6 has built-in programmable input pull-up transistors. The pull-up for each bit can be turned
on and off individually. To turn on an input pull-up, set the corresponding KMPCR bit to 1 and
clear the corresponding P6DDR bit to 0. KMPCR is cleared to H'00 by a reset and in hardware
standby mode, turning all input pull-ups off. In software standby mode, the previous state is
maintained.
Table 7-14 indicates the states of the input pull-up transistors in each operating mode.
Table 7-14 States of Input Pull-Up Transistors (Port 6)
Mode Reset Hardware Standby Software Standby Other Operating Modes
1 Off Off On/off On/off
2 Off Off On/off On/off
3 Off Off On/off On/off
Notes: Off: The input pull-up transistor is always off.
On/off: The input pull-up transistor is on if KMPCR = 1 and P6DDR = 0, but off otherwise.
148
7.8 Port 7
7.8.1 Overview
Port 7 is an 8-bit input port that also provides the analog input pins for the A/D converter. The
pin functions are the same in all modes. Figure 7-15 shows the pin configuration of port 7.
P7
7
(input)/AN
7
(input)
P7
6
(input)/AN
6
(input)
P7
5
(input)/AN
5
(input)
P7
4
(input)/AN
4
(input)
P7
3
(input)/AN
3
(input)
P7
2
(input)/AN
2
(input)
P7
1
(input)/AN
1
(input)
P7
0
(input)/AN
0
(input)
Port 7
Port 7 pins
Figure 7-15 Port 7 Pin Configuration
7.8.2 Register Configuration and Descriptions
Table 7-15 summarizes the port 7 registers. Port 7 is a dedicated input port, and has no data
direction register.
Table 7-15 Port 7 Register
Name Abbreviation Read/Write Initial Value Address
Port 7 input data register P7PIN R Undetermined H'FFBE
149
Port 7 Input Data Register (P7PIN)
Bit
Initial value
Read/Write
0
P7
0
—*
R
Note: *
1
P7
1
—*
R
2
P7
2
—*
R
3
P7
3
—*
R
4
P7
4
—*
R
5
P7
5
—*
R
6
P7
6
—*
R
7
P7
7
—*
R
Depends on the levels of pins P7
7
to P7
0
.
When P7PIN is read, the pin states are always read.
P7PIN is a read-only register and cannot be modified.
7.9 Port 8 [H8/3534]
7.9.1 Overview
Port 8 is a 7-bit input/output port that is multiplexed with input/output pins (TxD1, RxD1, SCK1)
of serial communication interface 1, and with interrupt input pins (IRQ5 to IRQ 3).
Port 8 pin functions are the same in all operating modes.
Figure 7-16 shows the pin configuration of port 8.
Pins in port 8 can drive one TTL load and a 30-pF capacitive load. They can also drive a
darlington pair.
Port 8
Port 8 pins
P8
6
(input/output)/IRQ
5
(input)/SCK
1
(input/output)
P8
5
(input/output)/IRQ
4
(input)/RxD
1
(input)
P8
4
(input/output)/IRQ
3
(input)/TxD
1
(output)
P8
3
(input/output)
P8
2
(input/output)
P8
1
(input/output)
P8
0
(input/output)
Figure 7-16 Port 8 Pin Configuration
150
7.9.2 Register Configuration and Descriptions
Table 7-16 summarizes the port 8 registers.
Table 7-16 Port 8 Registers
Name Abbreviation Read/Write Initial Value Address
Port 8 data direction register P8DDR W H'80 H'FFBD
Port 8 data register P8DR R/W H'80 H'FFBF
Port 8 Data Direction Register (P8DDR)
7
—
1
—
6
P8
6
DDR
0
W
5
P8
5
DDR
0
W
4
P8
4
DDR
0
W
3
P8
3
DDR
0
W
2
P8
2
DDR
0
W
1
P8
1
DDR
0
W
0
P8
0
DDR
0
W
Bit
Initial value
Read/Write
P8DDR is an 8-bit readable/writable register that controls the input/output direction of each pin
in port 8. A pin functions as an output pin if the corresponding P8DDR bit is set to 1, and as an
input pin if this bit is cleared to 0. P8DDR is a write-only register. Read data is invalid. If read,
all bits always read 1. Bit 7 is a reserved bit that always reads 1.
P8DDR is initialized to H'80 by a reset and in hardware standby mode. In software standby
mode P8DDR retains its existing values, so if a transition to software standby mode occurs while
a P8DDR bit is set to 1, the corresponding pin remains in the output state.
Port 8 Data Register (P8DR)
Bit
Initial value
Read/Write
7
—
1
—
6
P8
6
0
R/W
5
P8
5
0
R/W
4
P8
4
0
R/W
3
P8
3
0
R/W
2
P8
2
0
R/W
1
P8
1
0
R/W
0
P8
0
0
R/W
P8DR is an 8-bit register that stores data for pins P86 to P80. Bit 7 is a reserved bit that always
reads 1.
When a P8DDR bit is set to 1, if port 8 is read, the value in P8DR is obtained directly, regardless
of the actual pin state. When a P8DDR bit is cleared to 0, if port 8 is read the pin state is
obtained. This also applies to pins used by on-chip supporting modules.
151
P8DR is initialized to H'80 by a reset and in hardware standby mode. In software standby mode
it retains its existing values.
7.9.3 Pin Functions
Pins P86 to P84 are multiplexed with SCI1 input/output and IRQ5 to IRQ3 input. Table 7-17
indicates the functions of pins P86 to P84.
Table 7-17 Pin Functions of Port 8 Pins P86 to P84
Pin Pin Functions and Selection Method
P86/
,54
5/
SCK1
Bit C/
$
in SMR of SCI1, bits CKE0 and CKE1 in SCR of SCI1, and bit P86DDR select
the pin function as follows
CKE1 0 1
C/
$
01—
CKE0 0 1 — —
P86DDR 0 1 — — —
Pin function P86
input P86
output SCK1
output SCK1
output SCK1
intput
,54
5 input
,54
5 input is usable when bit IRQ5E is set to 1 in IER
P85/
,54
4/
RxD1
Bit RE in SCR of SCI1, and bit P85DDR select the pin function as follows
RE 0 1
P85DDR 0 1 —
Pin function P85
input P85
output RxD1
input
,54
4 input
,54
4 input is usable when bit IRQ4E is set to 1 in IER
P84/
,54
3/
TxD1
Bit TE in SCR of SCI1, and bit P84DDR select the pin function as follows
TE 0 1
P84DDR 0 1 —
Pin function P84
input P84
output TxD1
output
,54
3 input
,54
3 input is usable when bit IRQ3E is set to 1 in IER
152
7.10 Port 9 [H8/3534] · Port 4 [H8/3522]
7.10.1 Overview
Port 9 in the H8/3534 and port 4 in the H8/3522 have the same functions except that the DR and
DDR addresses are different. Port 9 in the H8/3534 is described below.
Port 9 is an 8-bit input/output port that is multiplexed with interrupt input pins (
,54
0 to
,54
2),
input/output pins for bus control signals (
5'
,
:5
,
$6
,
:$,7
), an input pin (
$'75*
) for the
A/D converter, and an output pin (φ) for the system clock. The function of pins P92 to P90 is the
same in all operating modes, while the function of pins P97 to P93 depends on the operating
mode. Figure 7-17 shows the pin configuration of port 9.
Pins in port 9 can drive one TTL load and a 90-pF capacitive load. They can also drive a
darlington pair.
P9
7
/WAIT
P9
6
/ø
P9
5
/AS
P9
4
/WR
P9
3
/RD
P9
2
/IRQ
0
Port 9
Port 9 pins
P9
7
(input/output)/WAIT (input)
ø (output)
AS (output)
WR (output)
RD (output)
P9
2
(input/output)/IRQ
0
(input)
Pin configuration in mode 1
(expanded mode with on-chip ROM disabled)
mode 2 (expanded mode with on-chip ROM enabled)
P9
7
(input/output)
P9
6
(input)/ø (output)
P9
5
(input/output)
P9
4
(input/output)
P9
3
(input/output)
P9
2
(input/output)/IRQ
0
(input)
Pin configuration in mode 3 (single-chip mode)
P9
1
(input/output)/IRQ
1
(input)
(input)
P9
0
(input/output)/IRQ
2
P9
11 1
/IRQ
P9
02
/IRQ
/ADTRG P9
02
(input/output)/IRQ (input) /ADTRG (input)
/ADTRG (input)
P9
1
(input/output)/IRQ (input)
Figure 7-17 Port 9 Pin Configuration
153
7.10.2 Register Configuration and Descriptions
Table 7-18 summarizes the port 9 registers.
Table 7-18 (a) H8/3534 Port 9 Registers
Name Abbreviation Read/Write Initial Value Address
Port 9 data direction register P9DDR W H'40 (modes 1 and 2)
H'00 (mode 3) H'FFC0
Port 9 data register P9DR R/W*1Undetermined*2H'FFC1
Table 7-18 (b) H8/3522 Port 4 Registers
Name Abbreviation Read/Write Initial Value Address
Port 4 data direction register P4DDR W H'40 (modes 1 and 2)
H'00 (mode 3) H'FFB5
Port 4 data register P4DR R/W*1Undetermined*2H'FFB7
Notes: 1. Bit 6 is read-only.
2. Bit 6 is undetermined. Other bits are initially 0.
154
Port 9 Data Direction Register (P9DDR)
7
P9
7
DDR
0
W
0
W
6
P9
6
DDR
1
—
0
W
5
P9
5
DDR
0
W
0
W
4
P9
4
DDR
0
W
0
W
3
P9
3
DDR
0
W
0
W
2
P9
2
DDR
0
W
0
W
1
P9
1
DDR
0
W
0
W
0
P9
0
DDR
0
W
0
W
Bit
Modes 1, 2
Initial value
Read/Write
Mode 3
Initial value
Read/Write
P9DDR is an 8-bit readable/writable register that controls the input/output direction of each pin
in port 9. A pin functions as an output pin if the corresponding P9DDR bit is set to 1, and as an
input pin if this bit is cleared to 0. In modes 1 and 2, P96DDR is fixed at 1 and cannot be
modified.
P9DDR is a write-only register. Read data is invalid. If read, all bits always read 1.
P9DDR is initialized by a reset and in hardware standby mode. The initial value is H'40 in
modes 1 and 2, and H'00 in mode 3. In software standby mode P9DDR retains its existing
values, so if a transition to software standby mode occurs while a P9DDR bit is set to 1, the
corresponding pin remains in the output state.
Port 9 Data Register (P9DR)
Bit
Initial value
Read/Write
7
P9
7
0
R/W
6
P9
6
—*
R
5
P9
5
0
R/W
4
P9
4
0
R/W
3
P9
3
0
R/W
2
P9
2
0
R/W
1
P9
1
0
R/W
0
P9
0
0
R/W
Note: * Determined by the level at pin P9
6
.
P9DR is an 8-bit register that stores data for pins P97 to P90. When a P9DDR bit is set to 1, if
port 9 is read, the value in P9DR is obtained directly, regardless of the actual pin state, except
for P96. When a P9DDR bit is cleared to 0, if port 9 is read the pin state is obtained. This also
applies to pins used by on-chip supporting modules and for bus control signals. P96 always
returns the pin state.
Except for bit P96, P9DR bits are initialized to 0 by a reset and in hardware standby mode. In
software standby mode it retains its existing values.
155
7.10.3 Pin Functions
Port 9 has one set of pin functions in modes 1 and 2, and a different set of pin functions in mode
3. The pins are multiplexed with IRQ0 to IRQ2 input, bus control signal input/output, A/D
converter input and system clock (φ) output. Table 7-19 indicates the pin functions of port 9.
Table 7-19 Port 9 Pin Functions
Pin Pin Functions and Selection Method
P97/
:$,7
Bit P97DDR, the wait mode as determined by WSCR, and the operating mode select
the pin function as follows
Operating mode Modes 1 and 2 Mode 3
Wait mode
:$,7
used
:$,7
not used —
P97DDR — 0 1 0 1
Pin function
:$,7
input
pin
P97
input
pin
P97
output
pin
P97
input
pin
P97
output pin
P96/φBit P96DDR and the operating mode select the pin function as follows
Operating mode Modes 1 and 2 Mode 3
P96DDR Always 1 0 1
Pin function φ output P96 input φ output
P95/
$6
Bit P95DDR and the operating mode select the pin function as follows
Operating mode Modes 1 and 2 Mode 3
P95DDR — 0 1
Pin function
$6
output P95 input P95 output
P94/
:5
Bit P94DDR and the operating mode select the pin function as follows
Operating mode Modes 1 and 2 Mode 3
P94DDR — 0 1
Pin function
:5
output P94 input P94 output
156
Table 7-19 Port 9 Pin Functions (cont)
Pin Pin Functions and Selection Method
P93/
5'
Bit P93DDR and the operating mode select the pin function as follows
Operating mode Modes 1 and 2 Mode 3
P93DDR — 0 1
Pin function
5'
output P93 input P93 output
P92/
,54
0P92DDR 0 1
Pin function P92 input P92 output
,54
0 input
,54
0 input can be used when bit IRQ0E is set to 1 in IER
P91/
,54
1
P91DDR 0 1
Pin function P91 input P91 output
,54
1 input
,54
1 input can be used when bit IRQ1E is set to 1 in IER
P90/
,54
2/
$'75*
P90DDR 0 1
Pin function P90 input P90 output
,54
2 input and
$'75*
input
,54
2 input can be used when bit IRQ2E is set to 1 in IER
$'75*
input can be used when bit TRGE is set to 1 in ADCR
157
Section 8 16-Bit Free-Running Timer
8.1 Overview
The H8/3534 and H8/3522 have an on-chip 16-bit free-running timer (FRT) module that uses a
16-bit free-running counter as a time base. Applications of the FRT module include rectangular-
wave output (up to two independent waveforms), input pulse width measurement, and
measurement of external clock periods.
8.1.1 Features
The features of the free-running timer module are listed below.
• Selection of four clock sources
The free-running counter can be driven by an internal clock source (φP/2, φP/8, or φP/32), or an
external clock input (enabling use as an external event counter).
• Two independent comparators
Each comparator can generate an independent waveform.
• Four input capture channels
The current count can be captured on the rising or falling edge (selectable) of an input signal.
The four input capture registers can be used separately, or in a buffer mode.
• Counter can be cleared under program control
The free-running counters can be cleared on compare-match A.
• Seven independent interrupts
Compare-match A and B, input capture A to D, and overflow interrupts are requested
independently.
158
8.1.2 Block Diagram
Figure 8-1 shows a block diagram of the free-running timer.
External
clock source
Internal
clock sources
Clock select
Comparator A
OCRA (H/L)
Comparator B
OCRB (H/L)
Bus interface
Internal
data bus
ø
P
/2
ø
P
/8
ø
P
/32
FTCI
Compare-
match A
Clear
Clock
FTOA
FTOB
Overflow
ICRA (H/L)
Compare-
match B
Capture
FRC (H/L)
TCSR
FTIA
FTIB
FTIC
FTID
Control
logic
Module data bus
TIER
TCR
TOCR
Interrupt signals
ICIA
ICIB
ICIC
ICID
OCIA
OCIB
FOVI
Legend
FRC:
OCRA, B:
ICRA, B, C, D:
TCSR:
Free-running counter (16 bits)
Output compare register A, B (16 bits)
Input capture register A, B, C, D (16 bits)
Timer control/status register (8 bits)
TIER:
TCR:
TOCR:
Timer interrupt enable register (8 bits)
Timer control register (8 bits)
Timer output compare control
register (8 bits)
ICRB (H/L)
ICRC (H/L)
ICRD (H/L)
Figure 8-1 Block Diagram of 16-Bit Free-Running Timer
159
8.1.3 Input and Output Pins
Table 8-1 lists the input and output pins of the free-running timer module.
Table 8-1 Input and Output Pins of Free-Running Timer Module
Name Abbreviation I/O Function
Counter clock input FTCI Input Input of external free-running counter clock
signal
Output compare A FTOA Output Output controlled by comparator A
Output compare B FTOB Output Output controlled by comparator B
Input capture A FTIA Input Trigger for capturing current count into input
capture register A
Input capture B FTIB Input Trigger for capturing current count into input
capture register B
Input capture C FTIC Input Trigger for capturing current count into input
capture register C
Input capture D FTID Input Trigger for capturing current count into input
capture register D
160
8.1.4 Register Configuration
Table 8-2 lists the registers of the free-running timer module.
Table 8-2 Register Configuration
Name Abbreviation R/W Initial
Value Address
Timer interrupt enable register TIER R/W H'01 H'FF90
Timer control/status register TCSR R/(W)*1 H'00 H'FF91
Free-running counter (high) FRC (H) R/W H'00 H'FF92
Free-running counter (low) FRC (L) R/W H'00 H'FF93
Output compare register A/B
(high)*2 OCRA/B (H) R/W H'FF H'FF94*2
Output compare register A/B (low)*2 OCRA/B (L) R/W H'FF H'FF95*2
Timer control register TCR R/W H'00 H'FF96
Timer output compare control
register TOCR R/W H'E0 H'FF97
Input capture register A (high) ICRA (H) R H'00 H'FF98
Input capture register A (low) ICRA (L) R H'00 H'FF99
Notes: 1. Software can write a 0 to clear bits 7 to 1, but cannot write a 1 in these bits. Bit 0 can
be read and written to.
2. OCRA and OCRB share the same addresses. Access is controlled by the OCRS bit in
TOCR.
161
Table 8-2 Register Configuration (cont.)
Name Abbreviation R/W Initial
Value Address
Input capture register B (high) ICRB (H) R H'00 H'FF9A
Input capture register B (low) ICRB (L) R H'00 H'FF9B
Input capture register C (high) ICRC (H) R H'00 H'FF9C
Input capture register C (low) ICRC (L) R H'00 H'FF9D
Input capture register D (high) ICRD (H) R H'00 H'FF9E
Input capture register D (low) ICRD (L) R H'00 H'FF9F
8.2 Register Descriptions
8.2.1 Free-Running Counter (FRC)
Bit
Initial
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
value
WriteRead/
FRC is a 16-bit readable/writable up-counter that increments on an internal pulse generated from
a clock source. The clock source is selected by the clock select 1 and 0 bits (CKS1 and CKS0) of
the timer control register (TCR).
When FRC overflows from H'FFFF to H'0000, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to 1.
Because FRC is a 16-bit register, a temporary register (TEMP) is used when FRC is written or
read. See section 8.3, CPU Interface, for details.
FRC is initialized to H'0000 by a reset and in the standby modes.
162
8.2.2 Output Compare Registers A and B (OCRA and OCRB)
Bit
Initial
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
value
WriteRead/
OCRA and OCRB are 16-bit readable/writable registers, the contents of which are continually
compared with the value in the FRC. When a match is detected, the corresponding output
compare flag (OCFA or OCFB) is set in the timer control/status register (TCSR).
In addition, if the output enable bit (OEA or OEB) in the timer output compare control register
(TOCR) is set to 1, when the output compare register and FRC values match, the logic level
selected by the output level bit (OLVLA or OLVLB) in TOCR is output at the output compare
pin (FTOA or FTOB). Following a reset, the FTOA and FTOB output levels are 0 until the first
compare-match.
OCRA and OCRB share the same address. They are differentiated by the OCRS bit in TOCR. A
temporary register (TEMP) is used for write access, as explained in section 8.3, CPU Interface.
OCRA and OCRB are initialized to H'FFFF by a reset and in the standby modes.
8.2.3 Input Capture Registers A to D (ICRA to ICRD)
Bit
Initial
15
0
R
14
0
R
13
0
R
12
0
R
11
0
R
10
0
R
9
0
R
8
0
R
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
2
0
R
1
0
R
0
0
R
value
WriteRead/
There are four input capture registers A to D, each of which is a 16-bit read-only register.
When the rising or falling edge of the signal at an input capture pin (FTIA to FTID) is detected,
the current FRC value is copied to the corresponding input capture register (ICRA to ICRD).* At
the same time, the corresponding input capture flag (ICFA to ICFD) in the timer control/status
register (TCSR) is set to 1. The input capture edge is selected by the input edge select bits
(IEDGA to IEDGD) in the timer control register (TCR).
Note: *The FRC contents are transferred to the input capture register regardless of the value of
the input capture flag (ICFA/B/C/D).
Input capture can be buffered by using the input capture registers in pairs. When the BUFEA bit
in TCR is set to 1, ICRC is used as a buffer register for ICRA as shown in figure 8-2. When an
FTIA input is received, the old ICRA contents are moved into ICRC, and the new FRC count is
copied into ICRA.
163
BUFEA:
IEDGA:
IEDGC:
ICRC:
ICRA:
FRC:
Buffer enable A
Input edge select A
Input edge select C
Input capture register C
Input capture register A
Free-running counter
BUFEA
IEDGA IEDGC
FTIA Edge detect and
capture signal
generating circuit
FRCICRC ICRA
Figure 8-2 Input Capture Buffering (Example)
Similarly, when the BUFEB bit in TCR is set to 1, ICRD is used as a buffer register for ICRB.
When input capture is buffered, if the two input edge bits are set to different values (IEDGA ≠
IEDGC or IEDGB ≠ IEDGD), then input capture is triggered on both the rising and falling edges
of the FTIA or FTIB input signal. If the two input edge bits are set to the same value (IEDGA =
IEDGC or IEDGB = IEDGD), then input capture is triggered on only one edge. See table 8-3.
Table 8-3 Buffered Input Capture Edge Selection (Example)
IEDGA IEDGC Input Capture Edge
0 0 Captured on falling edge of input capture A (FTIA) (Initial value)
1 Captured on both rising and falling edges of input capture A (FTIA)
10
1 1 Captured on rising edge of input capture A (FTIA)
Because the input capture registers are 16-bit registers, a temporary register (TEMP) is used
when they are read. See section 8.3, CPU Interface, for details.
To ensure input capture, the width of the input capture pulse should be at least 1.5 system clock
(φ) periods. When triggering is enabled on both edges, the input capture pulse width should be at
least 2.5 system clock periods.
The input capture registers are initialized to H'0000 by a reset and in the standby modes.
164
8.2.4 Timer Interrupt Enable Register (TIER)
Bit
Initial value
Read/Write
7
ICIAE
0
R/W
6
ICIBE
0
R/W
5
ICICE
0
R/W
4
ICIDE
0
3
OCIAE
0
R/W
0
—
1
—
2
OCIBE
0
R/W
1
OVIE
0
R/W
R/W
TIER is an 8-bit readable/writable register that enables and disables interrupts.
TIER is initialized to H'01 by a reset and in the standby modes.
Bit 7—Input Capture Interrupt A Enable (ICIAE): This bit selects whether to request input
capture interrupt A (ICIA) when input capture flag A (ICFA) in the timer status/control register
(TCSR) is set to 1.
Bit 7
ICIAE Description
0 Input capture interrupt request A (ICIA) is disabled. (Initial value)
1 Input capture interrupt request A (ICIA) is enabled.
Bit 6—Input Capture Interrupt B Enable (ICIBE): This bit selects whether to request input
capture interrupt B (ICIB) when input capture flag B (ICFB) in TCSR is set to 1.
Bit 6
ICIBE Description
0 Input capture interrupt request B (ICIB) is disabled. (Initial value)
1 Input capture interrupt request B (ICIB) is enabled.
Bit 5—Input Capture Interrupt C Enable (ICICE): This bit selects whether to request input
capture interrupt C (ICIC) when input capture flag C (ICFC) in TCSR is set to 1.
Bit 5
ICICE Description
0 Input capture interrupt request C (ICIC) is disabled. (Initial value)
1 Input capture interrupt request C (ICIC) is enabled.
165
Bit 4—Input Capture Interrupt D Enable (ICIDE): This bit selects whether to request input
capture interrupt D (ICID) when input capture flag D (ICFD) in TCSR is set to 1.
Bit 4
ICIDE Description
0 Input capture interrupt request D (ICID) is disabled. (Initial value)
1 Input capture interrupt request D (ICID) is enabled.
Bit 3—Output Compare Interrupt A Enable (OCIAE): This bit selects whether to request
output compare interrupt A (OCIA) when output compare flag A (OCFA) in TCSR is set to 1.
Bit 3
OCIAE Description
0 Output compare interrupt request A (OCIA) is disabled. (Initial value)
1 Output compare interrupt request A (OCIA) is enabled.
Bit 2—Output Compare Interrupt B Enable (OCIBE): This bit selects whether to request
output compare interrupt B (OCIB) when output compare flag B (OCFB) in TCSR is set to 1.
Bit 2
OCIBE Description
0 Output compare interrupt request B (OCIB) is disabled. (Initial value)
1 Output compare interrupt request B (OCIB) is enabled.
Bit 1—Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a free-
running timer overflow interrupt (FOVI) when the timer overflow flag (OVF) in TCSR is set to
1.
Bit 1
OVIE Description
0 Timer overflow interrupt request (FOVI) is disabled. (Initial value)
1 Timer overflow interrupt request (FOVI) is enabled.
Bit 0—Reserved: This bit cannot be modified and is always read as 1.
166
8.2.5 Timer Control/Status Register (TCSR)
Bit
Initial value
Read/Write
7
ICFA
0
R/(W)*
6
ICFB
0
R/(W)*
5
ICFC
0
4
ICFD
0
3
OCFA
0
0
CCLRA
0
R/W
2
OCFB
0
R/(W)*
1
OVF
0
R/(W)*
R/(W)*
R/(W)* R/(W)*
Note: * Software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits.
TCSR is an 8-bit readable and partially writable register that contains the seven interrupt flags
and specifies whether to clear the counter on compare-match A (when the FRC and OCRA
values match).
TCSR is initialized to H'00 by a reset and in the standby modes.
Timing is described in section 8.4, Operation.
Bit 7—Input Capture Flag A (ICFA): This status bit is set to 1 to flag an input capture A
event. If BUFEA = 0, ICFA indicates that the FRC value has been copied to ICRA. If BUFEA =
1, ICFA indicates that the old ICRA value has been moved into ICRC and the new FRC value
has been copied to ICRA.
ICFA must be cleared by software. It is set by hardware, however, and cannot be set by
software.
Bit 7
ICFA Description
0 To clear ICFA, the CPU must read ICFA after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when an FTIA input signal causes the FRC value to be copied to
ICRA.
Bit 6—Input Capture Flag B (ICFB): This status bit is set to 1 to flag an input capture B
event. If BUFEB = 0, ICFB indicates that the FRC value has been copied to ICRB. If BUFEB =
1, ICFB indicates that the old ICRB value has been moved into ICRD and the new FRC value
has been copied to ICRB.
ICFB must be cleared by software. It is set by hardware, however, and cannot be set by software.
167
Bit 6
ICFB Description
0 To clear ICFB, the CPU must read ICFB after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when an FTIB input signal causes the FRC value to be copied to
ICRB.
Bit 5—Input Capture Flag C (ICFC): This status bit is set to 1 to flag input of a rising or
falling edge of FTIC as selected by the IEDGC bit. When BUFEA = 0, this indicates capture of
the FRC count in ICRC. When BUFEA = 1, however, the FRC count is not captured, so ICFC
becomes simply an external interrupt flag. In other words, the buffer mode frees FTIC for use as
a general-purpose interrupt signal (which can be enabled or disabled by the ICICE bit).
ICFC must be cleared by software. It is set by hardware, however, and cannot be set by software.
Bit 5
ICFC Description
0 To clear ICFC, the CPU must read ICFC after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when an FTIC input signal is received.
Bit 4—Input Capture Flag D (ICFD): This status bit is set to 1 to flag input of a rising or
falling edge of FTID as selected by the IEDGD bit. When BUFEB = 0, this indicates capture of
the FRC count in ICRD. When BUFEB = 1, however, the FRC count is not captured, so ICFD
becomes simply an external interrupt flag. In other words, the buffer mode frees FTID for use as
a general-purpose interrupt signal (which can be enabled or disabled by the ICIDE bit).
ICFD must be cleared by software. It is set by hardware, however, and cannot be set by
software.
Bit 4
ICFD Description
0 To clear ICFD, the CPU must read ICFD after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when an FTID input signal is received
168
Bit 3—Output Compare Flag A (OCFA): This status flag is set to 1 when the FRC value
matches the OCRA value. This flag must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 3
OCFA Description
0 To clear OCFA, the CPU must read OCFA after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when FRC = OCRA.
Bit 2—Output Compare Flag B (OCFB): This status flag is set to 1 when the FRC value
matches the OCRB value. This flag must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 2
OCFB Description
0 To clear OCFB, the CPU must read OCFB after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when FRC = OCRB.
Bit 1—Timer Overflow Flag (OVF): This status flag is set to 1 when FRC overflows (changes
from H'FFFF to H'0000). This flag must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 1
OVF Description
0 To clear OVF, the CPU must read OVF after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when FRC changes from H'FFFF to H'0000.
Bit 0—Counter Clear A (CCLRA): This bit selects whether to clear FRC at compare-match A
(when the FRC and OCRA values match).
Bit 0
CCLRA Description
0 The FRC is not cleared. (Initial value)
1 The FRC is cleared at compare-match A.
169
8.2.6 Timer Control Register (TCR)
Bit
Initial value
Read/Write
7
IEDGA
0
R/W
6
IEDGB
0
R/W
5
IEDGC
0
4
IEDGD
0
3
BUFEA
0
0
CKS0
0
R/W
2
BUFEB
0
R/W
1
CKS1
0
R/W
R/W
R/W R/W
TCR is an 8-bit readable/writable register that selects the rising or falling edge of the input
capture signals, enables the input capture buffer mode, and selects the FRC clock source.
TCR is initialized to H'00 by a reset and in the standby modes.
Bit 7—Input Edge Select A (IEDGA): This bit selects the rising or falling edge of the input
capture A signal (FTIA).
Bit 7
IEDGA Description
0 Input capture A events are recognized on the falling edge of FTIA. (Initial value)
1 Input capture A events are recognized on the rising edge of FTIA.
Bit 6—Input Edge Select B (IEDGB): This bit selects the rising or falling edge of the input
capture B signal (FTIB).
Bit 6
IEDGB Description
0 Input capture B events are recognized on the falling edge of FTIB. (Initial value)
1 Input capture B events are recognized on the rising edge of FTIB.
Bit 5—Input Edge Select C (IEDGC): This bit selects the rising or falling edge of the input
capture C signal (FTIC).
Bit 5
IEDGC Description
0 Input capture C events are recognized on the falling edge of FTIC. (Initial value)
1 Input capture C events are recognized on the rising edge of FTIC.
170
Bit 4—Input Edge Select D (IEDGD): This bit selects the rising or falling edge of the input
capture D signal (FTID).
Bit 4
IEDGD Description
0 Input capture D events are recognized on the falling edge of FTID. (Initial value)
1 Input capture D events are recognized on the rising edge of FTID.
Bit 3—Buffer Enable A (BUFEA): This bit selects whether to use ICRC as a buffer register for
ICRA.
Bit 3
BUFEA Description
0 ICRC is not used as a buffer register for ICRA. (Initial value)
1 ICRC is used as a buffer register for ICRA.
Bit 2—Buffer Enable B (BUFEB): This bit selects whether to use ICRD as a buffer register for
ICRB.
Bit 2
BUFEB Description
0 ICRD is not used as a buffer register for ICRB. (Initial value)
1 ICRD is used as a buffer register for ICRB.
Bits 1 and 0—Clock Select (CKS1 and CKS0): These bits select external clock input or one of
three internal clock sources for FRC. External clock pulses are counted on the rising edge of
signals input to pin FTCI.
Bit 1
CKS1 Bit 0
CKS0 Description
00φ
P
/2 internal clock source (Initial value)
01φ
P
/8 internal clock source
10φ
P
/32 internal clock source
1 1 External clock source (rising edge)
171
8.2.7 Timer Output Compare Control Register (TOCR)
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
4
OCRS
0
3
OEA
0
0
OLVLB
0
R/W
2
OEB
0
R/W
1
OLVLA
0
R/W
R/W
—R/W
TOCR is an 8-bit readable/writable register that enables output from the output compare pins,
selects the output levels, and switches access between output compare registers A and B.
TOCR is initialized to H'E0 by a reset and in the standby modes.
Bits 7 to 5—Reserved: These bits cannot be modified and are always read as 1.
Bit 4—Output Compare Register Select (OCRS): OCRA and OCRB share the same address.
When this address is accessed, the OCRS bit selects which register is accessed. This bit does not
affect the operation of OCRA or OCRB.
Bit 4
OCRS Description
0 OCRA is selected. (Initial value)
1 OCRB is selected.
Bit 3—Output Enable A (OEA): This bit enables or disables output of the output compare A
signal (FTOA).
Bit 3
OEA Description
0 Output compare A output is disabled. (Initial value)
1 Output compare A output is enabled.
Bit 2—Output Enable B (OEB): This bit enables or disables output of the output compare B
signal (FTOB).
Bit 2
OEB Description
0 Output compare B output is disabled. (Initial value)
1 Output compare B output is enabled.
172
Bit 1—Output Level A (OLVLA): This bit selects the logic level to be output at the FTOA pin
when the FRC and OCRA values match.
Bit 1
OLVLA Description
0 A 0 logic level is output for compare-match A. (Initial value)
1 A 1 logic level is output for compare-match A.
Bit 0—Output Level B (OLVLB): This bit selects the logic level to be output at the FTOB pin
when the FRC and OCRB values match.
Bit 0
OLVLB Description
0 A 0 logic level is output for compare-match B. (Initial value)
1 A 1 logic level is output for compare-match B.
8.3 CPU Interface
The free-running counter (FRC), output compare registers (OCRA and OCRB), and input
capture registers (ICRA to ICRD) are 16-bit registers, but they are connected to an 8-bit data
bus. When the CPU accesses these registers, to ensure that both bytes are written or read
simultaneously, the access is performed using an 8-bit temporary register (TEMP).
These registers are written and read as follows:
• Register Write
When the CPU writes to the upper byte, the byte of write data is placed in TEMP. Next,
when the CPU writes to the lower byte, this byte of data is combined with the byte in TEMP
and all 16 bits are written in the register simultaneously.
• Register Read
When the CPU reads the upper byte, the upper byte of data is sent to the CPU and the lower
byte is placed in TEMP. When the CPU reads the lower byte, it receives the value in TEMP.
Programs that access these registers should normally use word access. Equivalently, they may
access first the upper byte, then the lower byte by two consecutive byte accesses. Data will not
be transferred correctly if the bytes are accessed in reverse order, or if only one byte is accessed.
Figure 8-3 shows the data flow when FRC is accessed. The other registers are accessed in the
same way. As an exception, when the CPU reads OCRA or OCRB, it reads both the upper and
lower bytes directly, without using TEMP.
173
Coding Examples
To write the contents of general register R0 to OCRA:
MOV.W R0, @OCRA
To transfer the contents of ICRA to general register R0:
MOV.W @ICRA, R0
CPU writes
data H'AA
(1) Upper byte write
(2) Lower byte write
CPU writes
data H'55
Bus
interface
Bus
interface
Module data bus
Module data bus
TEMP
[H'AA]
FRCH
[ ] FRCL
[ ]
TEMP
[H'AA]
FRCH
[H'AA] FRCL
[H'55]
Figure 8-3 (a) Write Access to FRC (when CPU Writes H'AA55)
174
CPU reads
data H'AA
(1) Upper byte read
(2) Lower byte read
CPU reads
data H'55
Bus
interface
Bus
interface
Module data bus
Module data bus
TEMP
[H'55]
FRCH
[H'AA] FRCL
[H'55]
TEMP
[H'55]
FRCH
[ ] FRCL
[ ]
Figure 8-3 (b) Read Access to FRC (when FRC Contains H'AA55)
175
8.4 Operation
8.4.1 FRC Increment Timing
FRC increments on a pulse generated once for each period of the selected (internal or external)
clock source. The clock source is selected by bits CKS0 and CKS1 in TCR.
Internal Clock: The internal clock sources (φP/2, φP/8, φP/32) are created from the system clock
(φ) by a prescaler. FRC increments on a pulse generated from the falling edge of the prescaler
output. See figure 8-4.
N – 1
FRC clock
pulse
ø
FRC
Internal
clock
N N + 1
Figure 8-4 Increment Timing for Internal Clock Source
176
External Clock: If external clock input is selected, FRC increments on the rising edge of the
FTCI clock signal. Figure 8-5 shows the increment timing.
The pulse width of the external clock signal must be at least 1.5 system clock (φ) periods. The
counter will not increment correctly if the pulse width is shorter than 1.5 system clock periods.
N + 1N
FRC clock
pulse
ø
FRC
FTCI
Figure 8-5 Increment Timing for External Clock Source
177
8.4.2 Output Compare Timing
When a compare-match occurs, the logic level selected by the output level bit (OLVLA or
OLVLB) in TOCR is output at the output compare pin (FTOA or FTOB). Figure 8-6 shows the
timing of this operation for compare-match A.
N + 1NN + 1N
N
OCRA
ø
Internal compare-
match A signal
FRC
OLVLA
FTOA
Clear*
Note: * Cleared by software
N
Figure 8-6 Timing of Output Compare A
178
8.4.3 FRC Clear Timing
If the CCLRA bit in TCSR is set to 1, the FRC is cleared when compare-match A occurs. Figure
8-7 shows the timing of this operation.
N H'0000
FRC
ø
Internal compare-
match A signal
Figure 8-7 Clearing of FRC by Compare-Match A
179
8.4.4 Input Capture Timing
(1) Input Capture Timing: An internal input capture signal is generated from the rising or
falling edge of the signal at the input capture pin FTIx (x = A, B, C, D), as selected by the
corresponding IEDGx bit in TCR. Figure 8-8 shows the usual input capture timing when the
rising edge is selected (IEDGx = 1).
Internal input
capture signal
ø
Input data
FTI pin
Figure 8-8 Input Capture Timing (Usual Case)
If the upper byte of ICRA/B/C/D is being read when the corresponding input capture signal
arrives, the internal input capture signal is delayed by one state. Figure 8-9 shows the timing
for this case.
Internal input
capture signal
ø
Input at FTI pin
T
1
T
2
T
3
ICR upper byte read cycle
Figure 8-9 Input Capture Timing (1-State Delay Due to ICRA/B/C/D Read)
180
(2) Buffered Input Capture Timing: ICRC and ICRD can operate as buffers for ICRA and
ICRB.
Figure 8-10 shows how input capture operates when ICRA and ICRC are used in buffer mode
and IEDGA and IEDGC are set to different values (IEDGA = 0 and IEDGC = 1, or IEDG A
= 1 and IEDGC = 0), so that input capture is performed on both the rising and falling edges
of FTIA.
nn + 1 N N + 1
MnnN
mM Mn
ø
FTIA
Internal input
capture signal
FRC
ICRA
ICRC
Figure 8-10 Buffered Input Capture with Both Edges Selected
181
When ICRC or ICRD is used as a buffer register, its input capture flag is set by the selected
transition of its input capture signal. For example, if ICRC is used to buffer ICRA, when the
edge transition selected by the IEDGC bit occurs on the FTIC input capture line, ICFC will
be set, and if the ICIEC bit is set, an interrupt will be requested. The FRC value will not be
transferred to ICRC, however.
In buffered input capture, if the upper byte of either of the two registers to which data will be
transferred (ICRA and ICRC, or ICRB and ICRD) is being read when the input signal
arrives, input capture is delayed by one system clock (φ). Figure 8-11 shows the timing when
BUFEA = 1.
Internal input
capture signal
ø
Input at
FTIA pin
T
1
T
2
T
3
Read cycle:
CPU reads upper byte of ICRA or ICRC
Figure 8-11 Input Capture Timing (1-State Delay, Buffer Mode)
182
8.4.5 Timing of Input Capture Flag (ICF) Setting
The input capture flag ICFx (x = A, B, C, D) is set to 1 by the internal input capture signal.
Figure 8-12 shows the timing of this operation.
ICF
ø
FRC
Internal input
capture signal
N
NICR
Figure 8-12 Setting of Input Capture Flag
183
8.4.6 Setting of Output Compare Flags A and B (OCFA and OCFB)
The output compare flags are set to 1 by an internal compare-match signal generated when the
FRC value matches the OCRA or OCRB value. This compare-match signal is generated at the
last state in which the two values match, just before FRC increments to a new value.
Accordingly, when the FRC and OCR values match, the compare-match signal is not generated
until the next period of the clock source. Figure 8-13 shows the timing of the setting of the
output compare flags.
OCRA or OCRB
ø
Internal compare-
match signal
FRC N N + 1
N
OCFA or OCFB
Figure 8-13 Setting of Output Compare Flags
184
8.4.7 Setting of Timer Overflow Flag (OVF)
The timer overflow flag (OVF) is set to 1 when FRC overflows (changes from H'FFFF to
H'0000). Figure 8-14 shows the timing of this operation.
H'FFFF H'0000
Internal overflow
signal
ø
FRC
OVF
Figure 8-14 Setting of Timer Overflow Flag (OVF)
8.5 Interrupts
The free-running timer can request seven interrupts (three types): input capture A to D (ICIA,
ICIB, ICIC, ICID), output compare A and B (OCIA and OCIB), and overflow (FOVI). Each
interrupt can be enabled or disabled by an enable bit in TIER. Independent signals are sent to the
interrupt controller for each interrupt. Table 8-4 lists information about these interrupts.
Table 8-4 Free-Running Timer Interrupts
Interrupt Description Priority
ICIA Requested by ICFA High
ICIB Requested by ICFB
ICIC Requested by ICFC
ICID Requested by ICFD ↓
OCIA Requested by OCFA
OCIB Requested by OCFB
FOVI Requested by OVF Low
185
8.6 Sample Application
In the example below, the free-running timer is used to generate two square-wave outputs with a
50% duty cycle and arbitrary phase relationship. The programming is as follows:
(1) The CCLRA bit in TCSR is set to 1.
(2) Each time a compare-match interrupt occurs, software inverts the corresponding output level
bit in TOCR (OLVLA or OLVLB).
FRC
Clear counter
H'FFFF
OCRA
OCRB
H'0000
FTOA
FTOB
Figure 8-15 Square-Wave Output (Example)
186
8.7 Application Notes
Application programmers should note that the following types of contention can occur in the
free-running timer.
(1) Contention between FRC Write and Clear: If an internal counter clear signal is generated
during the T3 state of a write cycle to the lower byte of the free-running counter, the clear
signal takes priority and the write is not performed.
Figure 8-16 shows this type of contention.
T
1
T
2
T
3
Write cycle:
CPU write to lower byte of FRC
Internal address
bus FRC address
Internal write
signal
ø
FRC clear signal
FRC N H'0000
Figure 8-16 FRC Write-Clear Contention
187
(2) Contention between FRC Write and Increment: If an FRC increment pulse is generated
during the T3 state of a write cycle to the lower byte of the free-running counter, the write
takes priority and FRC is not incremented.
Figure 8-17 shows this type of contention.
T
1
T
2
T
3
Write cycle:
CPU write to lower byte of FRC
Internal address bus
Internal write signal
ø
FRC clock pulse
FRC N M
Write data
FRC address
Figure 8-17 FRC Write-Increment Contention
188
(3) Contention between OCR Write and Compare-Match: If a compare-match occurs
during the T3 state of a write cycle to the lower byte of OCRA or OCRB, the write takes
priority and the compare-match signal is inhibited.
Figure 8-18 shows this type of contention.
T
1
T
2
T
3
Write cycle:
CPU write to lower byte of OCRA or OCRB
Internal address bus
Internal write signal
ø
FRC
OCRA or OCRB N M
Write data
OCR address
N N + 1
Compare-match
A or B signal Inhibited
Figure 8-18 Contention between OCR Write and Compare-Match
189
(4) Increment Caused by Changing of Internal Clock Source: When an internal clock source
is changed, the changeover may cause FRC to increment. This depends on the time at which
the clock select bits (CKS1 and CKS0) are rewritten, as shown in table 8-5.
The pulse that increments FRC is generated at the falling edge of the internal clock source. If
clock sources are changed when the old source is high and the new source is low, as in case
no. 3 in table 8-5, the changeover generates a falling edge that triggers the FRC increment
clock pulse.
Switching between an internal and external clock source can also cause FRC to increment.
Table 8-5 Effect of Changing Internal Clock Sources
No. Description Timing
1 Low → low:
CKS1 and CKS0 are
rewritten while both
clock sources are low.
N + 1
Old clock
source
New clock
source
FRC clock
pulse
FRC
CKS rewrite
N
2 Low → high:
CKS1 and CKS0 are
rewritten while old
clock source is low and
new clock source is high.
N + 1 N + 2
Old clock
source
New clock
source
FRC clock
pulse
FRC
CKS rewrite
N
190
Table 8-5 Effect of Changing Internal Clock Sources (cont)
No. Description Timing
3 High → low:
CKS1 and CKS0 are
rewritten while old
clock source is high and
new clock source is low.
N + 1N N + 2
*
Old clock
source
New clock
source
FRC clock
pulse
FRC
CKS rewrite
4 High → high:
CKS1 and CKS0 are
rewritten while both
clock sources are high.
N + 1 N + 2N
Old clock
source
New clock
source
FRC clock
pulse
CKS rewrite
FRC
Note: * The switching of clock sources is regarded as a falling edge that increments FRC.
191
Section 9 8-Bit Timers
9.1 Overview
The H8/3534 and H8/3522 include an 8-bit timer module with two channels (numbered 0 and 1).
Each channel has an 8-bit counter (TCNT) and two time constant registers (TCORA and
TCORB) that are constantly compared with the TCNT value to detect compare-match events.
One of the many applications of the 8-bit timer module is to generate a rectangular-wave output
with an arbitrary duty cycle.
9.1.1 Features
The features of the 8-bit timer module are listed below.
• Selection of seven clock sources
The counters can be driven by one of six internal clock signals or an external clock input
(enabling use as an external event counter).
• Selection of three ways to clear the counters
The counters can be cleared on compare-match A or B, or by an external reset signal.
• Timer output controlled by two compare-match signals
The timer output signal in each channel is controlled by two independent compare-match
signals, enabling the timer to generate output waveforms with an arbitrary duty cycle, or
PWM waveforms.
• Three independent interrupts
Compare-match A and B and overflow interrupts can be requested independently.
192
9.1.2 Block Diagram
Figure 9-1 shows a block diagram of one channel in the 8-bit timer module.
External
clock source
TMCI
TMO
TMRI
Internal
clock sources Channel 0 Channel 1
ø
P
/2
ø
P
/8
ø
P
/32
ø
P
/64
ø
P
/256
ø
P
/1024
ø
P
/2
ø
P
/8
ø
P
/64
ø
P
/128
ø
P
/1024
ø
P
/2048
Clock
Overflow
Clear
Compare-match B
Control
logic
Clock select TCORA
Comparator A
TCNT
Comparator B
TCORB
TCSR
TCR
Module data bus
Bus interface
Internal
data bus
CMIA
CMIB
OVI
Interrupt signals
TCR:
TCSR:
TCORA:
TCORB:
TCNT:
Timer control register (8 bits)
Timer control status register (8 bits)
Time constant register A (8 bits)
Time constant register B (8 bits)
Timer counter
Compare-match A
Figure 9-1 Block Diagram of 8-Bit Timer (1 Channel)
193
9.1.3 Input and Output Pins
Table 9-1 lists the input and output pins of the 8-bit timer.
Table 9-1 Input and Output Pins of 8-Bit Timer
Abbreviation*
Name Channel 0 Channel 1 I/O Function
Timer output TMO0TMO1Output Output controlled by compare-match
Timer clock input TMCI0TMCI1Input External clock source for the counter
Timer reset input TMRI0TMRI1Input External reset signal for the counter
Note: * In this manual, the channel subscript has been deleted, and only TMO, TMCI, and TMRI
are used.
9.1.4 Register Configuration
Table 9-2 lists the registers of the 8-bit timer module.
Table 9-2 8-Bit Timer Registers
Channel Name Abbreviation R/W Initial Value Address
0 Timer control register TCR R/W H'00 H'FFC8
Timer control/status register TCSR R/(W)* H'10 H'FFC9
Time constant register A TCORA R/W H'FF H'FFCA
Time constant register B TCORB R/W H'FF H'FFCB
Timer counter TCNT R/W H'00 H'FFCC
1 Timer control register TCR R/W H'00 H'FFD0
Timer control/status register TCSR R/(W)* H'10 H'FFD1
Time constant register A TCORA R/W H'FF H'FFD2
Time constant register B TCORB R/W H'FF H'FFD3
Timer counter TCNT R/W H'00 H'FFD4
0, 1 Serial/timer control register STCR R/W H'00 H'FFC3
Note: * Software can write a 0 to clear bits 7 to 5, but cannot write a 1 in these bits.
194
9.2 Register Descriptions
9.2.1 Timer Counter (TCNT)
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Each timer counter (TCNT) is an 8-bit up-counter that increments on a pulse generated from an
internal or external clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) of the timer
control register (TCR). The CPU can always read or write the timer counter.
The timer counter can be cleared by an external reset input or by an internal compare-match
signal generated at a compare-match event. Clock clear bits 1 and 0 (CCLR1 and CCLR0) of the
timer control register select the method of clearing.
When a timer counter overflows from H'FF to H'00, the overflow flag (OVF) in the timer
control/status register (TCSR) is set to 1.
The timer counters are initialized to H'00 by a reset and in the standby modes.
9.2.2 Time Constant Registers A and B (TCORA and TCORB)
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
TCORA and TCORB are 8-bit readable/writable registers. The timer count is continually
compared with the constants written in these registers (except during the T3 state of a write cycle
to TCORA or TCORB). When a match is detected, the corresponding compare-match flag
(CMFA or CMFB) is set in the timer control/status register (TCSR).
The timer output signal is controlled by these compare-match signals as specified by output
select bits 3 to 0 (OS3 to OS0) in the timer control/status register (TCSR).
TCORA and TCORB are initialized to H'FF by a reset and in the standby modes.
195
9.2.3 Timer Control Register (TCR)
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0
TCR is an 8-bit readable/writable register that selects the clock source and the time at which the
timer counter is cleared, and enables interrupts.
TCR is initialized to H'00 by a reset and in the standby modes.
For timing diagrams, see section 9.3, Operation.
Bit 7—Compare-Match Interrupt Enable B (CMIEB): This bit selects whether to request
compare-match interrupt B (CMIB) when compare-match flag B (CMFB) in the timer
control/status register (TCSR) is set to 1.
Bit 7
CMIEB Description
0 Compare-match interrupt request B (CMIB) is disabled. (Initial value)
1 Compare-match interrupt request B (CMIB) is enabled.
Bit 6—Compare-Match Interrupt Enable A (CMIEA): This bit selects whether to request
compare-match interrupt A (CMIA) when compare-match flag A (CMFA) in TCSR is set to 1.
Bit 6
CMIEA Description
0 Compare-match interrupt request A (CMIA) is disabled. (Initial value)
1 Compare-match interrupt request A (CMIA) is enabled.
196
Bit 5—Timer Overflow Interrupt Enable (OVIE): This bit selects whether to request a timer
overflow interrupt (OVI) when the overflow flag (OVF) in TCSR is set to 1.
Bit 5
OVIE Description
0 The timer overflow interrupt request (OVI) is disabled. Initial value)
1 The timer overflow interrupt request (OVI) is enabled.
Bits 4 and 3—Counter Clear 1 and 0 (CCLR1 and CCLR0): These bits select how the timer
counter is cleared: by compare-match A or B or by an external reset input (TMRI).
Bit 4
CCLR1 Bit 3
CCLR0 Description
0 0 Not cleared. (Initial value)
0 1 Cleared on compare-match A.
1 0 Cleared on compare-match B.
1 1 Cleared on rising edge of external reset input signal.
197
Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits and bits ICKS1 and
ICKS0 in the serial/timer control register (STCR) select the internal or external clock source for
the timer counter. Six internal clock sources, derived by prescaling the system clock, are
available for each timer channel. For internal clock sources the counter is incremented on the
falling edge of the internal clock. For an external clock source, these bits can select whether to
increment the counter on the rising or falling edge of the clock input (TMCI), or on both edges.
TCR STCR
Bit 2 Bit 1 Bit 0 Bit 1 Bit 0
Channel CKS2 CKS1 CKS0 ICKS1 ICKS0 Description
0 0 0 0 — — No clock source (timer stopped) (Initial value)
001—0φ
P
/8 internal clock, counted on falling edge
001—1φ
P
/2 internal clock, counted on falling edge
010—0φ
P
/64 internal clock, counted on falling edge
010—1φ
P
/32 internal clock, counted on falling edge
011—0φ
P
/1024 internal clock, counted on falling edge
011—1φ
P
/256 internal clock, counted on falling edge
1 0 0 — — No clock source (timer stopped)
1 0 1 — — External clock source, counted on rising edge
1 1 0 — — External clock source, counted on falling edge
1 1 1 — — External clock source, counted on both rising
and falling edges
1 0 0 0 — — No clock source (timer stopped) (Initial value)
0010 —φ
P
/8 internal clock, counted on falling edge
0011 —φ
P
/2 internal clock, counted on falling edge
0100 —φ
P
/64 internal clock, counted on falling edge
0101 —φ
P
/128 internal clock, counted on falling edge
0110 —φ
P
/1024 internal clock, counted on falling edge
0111 —φ
P
/2048 internal clock, counted on falling edge
1 0 0 — — No clock source (timer stopped)
1 0 1 — — External clock source, counted on rising edge
1 1 0 — — External clock source, counted on falling edge
1 1 1 — — External clock source, counted on both rising
and falling edges
198
9.2.4 Timer Control/Status Register (TCSR)
Bit
Initial value
Read/Write
7
CMFB
0
R/(W)*
6
CMFA
0
R/(W)*
5
OVF
0
R/(W)*
4
—
1
—
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Note: * Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits.
TCSR is an 8-bit readable and partially writable register that indicates compare-match and
overflow status and selects the effect of compare-match events on the timer output signal.
TCSR is initialized to H'10 by a reset and in the standby modes.
Bit 7—Compare-Match Flag B (CMFB): This status flag is set to 1 when the timer count
matches the time constant set in TCORB. CMFB must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Bit 7
CMFB Description
0 To clear CMFB, the CPU must read CMFB after it has been set to 1 (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when TCNT = TCORB.
Bit 6—Compare-Match Flag A (CMFA): This status flag is set to 1 when the timer count
matches the time constant set in TCORA. CMFA must be cleared by software. It is set by
hardware, however, and cannot be set by software.
Bit 6
CMFA Description
0 To clear CMFA, the CPU must read CMFA after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when TCNT = TCORA.
199
Bit 5—Timer Overflow Flag (OVF): This status flag is set to 1 when the timer count overflows
(changes from H'FF to H'00). OVF must be cleared by software. It is set by hardware, however,
and cannot be set by software.
Bit 5
OVF Description
0 To clear OVF, the CPU must read OVF after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when TCNT changes from H'FF to H'00.
Bit 4—Reserved: This bit is always read as 1. It cannot be written.
Bits 3 to 0—Output Select 3 to 0 (OS3 to OS0): These bits specify the effect of TCOR–TCNT
compare-match events on the timer output signal (TMO). Bits OS3 and OS2 control the effect of
compare-match B on the output level. Bits OS1 and OS0 control the effect of compare-match A
on the output level.
If compare-match A and B occur simultaneously, any conflict is resolved according to the
following priority order: toggle > 1 output > 0 output.
When all four output select bits are cleared to 0 the timer output signal is disabled.
After a reset, the timer output is 0 until the first compare-match event.
Bit 3
OS3 Bit 2
OS2 Description
0 0 No change when compare-match B occurs. (Initial value)
0 1 Output changes to 0 when compare-match B occurs.
1 0 Output changes to 1 when compare-match B occurs.
1 1 Output inverts (toggles) when compare-match B occurs
. Bit 1
OS1 Bit 0
OS0 Description
0 0 No change when compare-match A occurs. (Initial value)
0 1 Output changes to 0 when compare-match A occurs.
1 0 Output changes to 1 when compare-match A occurs.
1 1 Output inverts (toggles) when compare-match A occurs.
200
9.2.5 Serial/Timer Control Register (STCR)
Bit
[H8/3534]
Initial value
Read/Write
7
(IICS)
0
R/W
6
(IICD)
0
R/W
5
(IICX)
0
R/W
4
(IICE)
0
R/W
3
(STAC)
0
R/W
0
ICKS0
0
R/W
2
MPE
0
R/W
1
ICKS1
0
R/W
Bit
[H8/3522]
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
ICKS0
0
R/W
2
MPE
0
R/W
1
ICKS1
0
R/W
STCR is an 8-bit readable/writable register that controls the operating mode of the serial
communication interface and selects internal clock sources for the timer counters.
STCR is initialized to H'00 [H8/3534]/H'F8 [H8/3522] by a reset.
Bits 7 to 4—I2C Control (IICS, IICD, IICX, IICE) [H8/3534]: These bits are reserved. They
should not be set to 1.
Bit 3—Slave Input Switch (STAC) [H8/3534]: This bit is reserved. It should not be set to 1.
Bits 7 to 3—Reserved [H8/3522]: These bits cannot be modified and are always read as 1.
Bit 2—Multiprocessor Enable (MPE): Controls the operating mode of serial communication
interfaces 0 and 1. For details, see section 12, Serial Communication Interface.
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1 and ICKS0): These bits and bits
CKS2 to CKS0 in TCR select clock sources for the timer counters. For details, see section 9.2.3,
Timer Control Register.
201
9.3 Operation
9.3.1 TCNT Increment Timing
The timer counter increments on a pulse generated once for each period of the selected (internal
or external) clock source.
Internal Clock: Internal clock sources are created from the system clock by a prescaler. The
counter increments on an internal TCNT clock pulse generated from the falling edge of the
prescaler output, as shown in figure 9-2. Bits CKS2 to CKS0 of TCR and bits ICKS1 and ICKS0
of STCR can select one of the six internal clocks.
N – 1
TCNT clock
pulse
ø
TCNT
Internal
clock
N N + 1
Figure 9-2 Increment Timing for Internal Clock Input
202
External Clock: If external clock input (TMCI) is selected, the timer counter can increment on
the rising edge, the falling edge, or both edges of the external clock signal. Figure 9-3 shows
incrementation on both edges of the external clock signal.
The external clock pulse width must be at least 1.5 system clock (φ) periods for incrementation
on a single edge, and at least 2.5 system clock periods for incrementation on both edges. The
counter will not increment correctly if the pulse width is shorter than these values.
N – 1 NN + 1
TCNT clock
pulse
ø
TCNT
External clock
source (TMCI)
Figure 9-3 Increment Timing for External Clock Input
203
9.3.2 Compare-Match Timing
1. Setting of Compare-Match Flags A and B (CMFA and CMFB): The compare-match flags
are set to 1 by an internal compare-match signal generated when the timer count matches the
time constant in TCORA or TCORB. The compare-match signal is generated at the last state
in which the match is true, just before the timer counter increments to a new value.
Accordingly, when the timer count matches one of the time constants, the compare-match
signal is not generated until the next period of the clock source. Figure 9-4 shows the timing
of the setting of the compare-match flags.
TCOR
ø
Internal compare-
match signal
TCNT N
N
N + 1
CMF
Figure 9-4 Setting of Compare-Match Flags
204
2. Output Timing: When a compare-match event occurs, the timer output changes as specified
by the output select bits (OS3 to OS0) in the TCSR. Depending on these bits, the output can
remain the same, change to 0, change to 1, or toggle.
Figure 9-5 shows the timing when the output is set to toggle on compare-match A.
Timer output
(TMO)
ø
Internal compare-
match A signal
Figure 9-5 Timing of Timer Output
3. Timing of Compare-Match Clear: Depending on the CCLR1 and CCLR0 bits in TCR, the
timer counter can be cleared when compare-match A or B occurs. Figure 9-6 shows the
timing of this operation.
TCNT
ø
Internal compare-
match signal
N H'00
Figure 9-6 Timing of Compare-Match Clear
205
9.3.3 External Reset of TCNT
When the CCLR1 and CCLR0 bits in TCR are both set to 1, the timer counter is cleared on the
rising edge of an external reset input. Figure 9-7 shows the timing of this operation. The timer
reset pulse width must be at least 1.5 system clock (φ) periods.
Internal clear
pulse
ø
TCNT
External reset
input (TMRI)
N – 1 N H'00
Figure 9-7 Timing of External Reset
9.3.4 Setting of Overflow Flag (OVF)
The overflow flag (OVF) in TCSR is set to 1 when the timer count overflows (changes from
H'FF to H'00). Figure 9-8 shows the timing of this operation.
H'FF H'00
Internal overflow
signal
ø
TCNT
OVF
Figure 9-8 Setting of Overflow Flag (OVF)
206
9.4 Interrupts
Each channel in the 8-bit timer can generate three types of interrupts: compare-match A and B
(CMIA and CMIB), and overflow (OVI). Each interrupt can be enabled or disabled by an enable
bit in TCR. Independent signals are sent to the interrupt controller for each interrupt. Table 9-3
lists information about these interrupts.
Table 9-3 8-Bit Timer Interrupts
Interrupt Description Priority
CMIA Requested by CMFA High
CMIB Requested by CMFB ↓
OVI Requested by OVF Low
9.5 Sample Application
In the example below, the 8-bit timer is used to generate a pulse output with a selected duty
cycle. The control bits are set as follows:
(1) In TCR, CCLR1 is cleared to 0 and CCLR0 is set to 1 so that the timer counter is cleared
when its value matches the constant in TCORA.
(2) In TCSR, bits OS3 to OS0 are set to 0110, causing the output to change to 1 on compare-
match A and to 0 on compare-match B.
With these settings, the 8-bit timer provides output of pulses at a rate determined by TCORA
with a pulse width determined by TCORB. No software intervention is required.
TCNT
Clear counter
H'FF
TCORA
TCORB
H'00
TMO
Figure 9-9 Example of Pulse Output
207
9.6 Application Notes
Application programmers should note that the following types of contention can occur in the 8-
bit timer.
9.6.1 Contention between TCNT Write and Clear
If an internal counter clear signal is generated during the T3 state of a write cycle to the timer
counter, the clear signal takes priority and the write is not performed.
Figure 9-10 shows this type of contention.
T
1
T
2
T
3
Write cycle: CPU writes to TCNT
Internal address
bus TCNT address
Internal write
signal
ø
Counter clear
signal
TCNT N H'00
Figure 9-10 TCNT Write-Clear Contention
208
9.6.2 Contention between TCNT Write and Increment
If a timer counter increment pulse is generated during the T3 state of a write cycle to the timer
counter, the write takes priority and the timer counter is not incremented.
Figure 9-11 shows this type of contention.
T
1
T
2
T
3
Write cycle: CPU writes to TCNT
Internal address bus
Internal write signal
ø
TCNT clock pulse
TNCT N M
Write data
TCNT address
Figure 9-11 TCNT Write-Increment Contention
209
9.6.3 Contention between TCOR Write and Compare-Match
If a compare-match occurs during the T3 state of a write cycle to TCOR, the write takes priority
and the compare-match signal is inhibited.
Figure 9-12 shows this type of contention.
T
1
T
2
T
3
Write cycle: CPU writes to TCOR
Internal address bus
Internal write signal
ø
TCNT
TCOR N M
TCOR write data
TCOR address
N N + 1
Compare-match
A or B signal
Inhibited
Figure 9-12 Contention between TCOR Write and Compare-Match
210
9.6.4 Contention between Compare-Match A and Compare-Match B
If identical time constants are written in TCORA and TCORB, causing compare-match A and B
to occur simultaneously, any conflict between the output selections for compare-match A and B
is resolved by following the priority order in table 9-4.
Table 9-4 Priority of Timer Output
Output Selection Priority
Toggle High
1 output ↓
0 output
No change Low
9.6.5 Increment Caused by Changing of Internal Clock Source
When an internal clock source is changed, the changeover may cause the timer counter to
increment. This depends on the time at which the clock select bits (CKS1, CKS0) are rewritten,
as shown in table 9-5.
The pulse that increments the timer counter is generated at the falling edge of the internal clock
source signal. If clock sources are changed when the old source is high and the new source is
low, as in case no. 3 in table 9-5, the changeover generates a falling edge that triggers the TCNT
clock pulse and increments the timer counter.
Switching between an internal and external clock source can also cause the timer counter to
increment.
211
Table 9-5 Effect of Changing Internal Clock Sources
No. Description Timing
1 Low → low*1
N + 1
Old clock
source
New clock
source
TCNT clock
pulse
TCNT
CKS rewrite
N
2 Low → high*2
N + 1 N + 2
Old clock
source
New clock
source
TCNT clock
pulse
TCNT
CKS rewrite
N
Notes: 1. Including a transition from low to the stopped state (CKS1 = 0, CKS0 = 0), or a
transition from the stopped state to low.
2. Including a transition from the stopped state to high.
212
Table 9-5 Effect of Changing Internal Clock Sources (cont)
No. Description Timing chart
3 High → low*1
N + 1N N + 2
*2
Old clock
source
New clock
source
TCNT clock
pulse
TCNT
CKS rewrite
4 High → high
N + 1 N + 2N
Old clock
source
New clock
source
TCNT clock
pulse
CKS rewrite
TCNT
Notes: 1. Including a transition from high to the stopped state.
2. The switching of clock sources is regarded as a falling edge that increments TCNT.
213
Section 10 PWM Timers (H8/3534 Only)
10.1 Overview
The H8/3534 has an on-chip pulse-width modulation (PWM) timer module with two
independent channels (PWM0 and PWM1). Both channels are functionally identical. Each PWM
channel generates a rectangular output pulse with a duty cycle of 0 to 100%. The duty cycle is
specified in an 8-bit duty register (DTR).
10.1.1 Features
The PWM timer module has the following features:
• Selection of eight clock sources
• Duty cycles from 0 to 100% with 1/250 resolution
• Direct or inverted PWM output, and software enable/disable control
214
10.1.2 Block Diagram
Figure 10-1 shows a block diagram of one PWM timer channel.
Comparator
DTR
Bus interface
Internal
data bus
Pulse
TCR
TCNT
Compare-match
ø
P
/2
ø
P
/8
ø
P
/32
ø
P
/128
ø
P
/256
ø
P
/1024
ø
P
/2048
ø
P
/4096
Output
control
Clock Clock
select
Internal clock sources
TCR:
DTR:
TCNT:
Timer control register (8 bits)
Duty register (8 bits)
Timer counter (8 bits)
Module data bus
Figure 10-1 Block Diagram of PWM Timer (One Channel)
215
10.1.3 Input and Output Pins
Table 10-1 lists the output pins of the PWM timer module. There are no input pins.
Table 10-1 Output Pins of PWM Timer Module
Name Abbreviation I/O Function
PWM0 output PW0Output Pulse output from PWM timer channel 0.
PWM1 output PW1Output Pulse output from PWM timer channel 1.
10.1.4 Register Configuration
The PWM timer module has three registers for each channel as listed in table 10-2.
Table 10-2 PWM Timer Registers
Initial Address
Name Abbreviation R/W Value PWM0 PWM1
Timer control register TCR R/W H'38 H'FFA0 H'FFA4
Duty register DTR R/W H'FF H'FFA1 H'FFA5
Timer counter TCNT R/W H'00 H'FFA2 H'FFA6
216
10.2 Register Descriptions
10.2.1 Timer Counter (TCNT)
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
R/W
TCNT is an 8-bit readable/writable up-counter. When the output enable bit (OE) is set to 1 in
TCR, TCNT starts counting pulses of an internal clock source selected by clock select bits 2 to 0
(CKS2 to CKS0). After counting from H'00 to H'F9, the count repeats from H'00. When TCNT
changes from H'00 to to H'01, the PWM output is placed in the 1 state, unless the DTR value is
H'00, in which case the duty cycle is 0% and the PWM output remains in the 0 state.
TCNT is initialized to H'00 at a reset and in the standby modes, and when the OE bit is cleared
to 0.
10.2.2 Duty Register (DTR)
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
R/W
DTR is an 8-bit readable/writable register that specifies the duty cycle of the output pulse. Any
duty cycle from 0% to 100% can be output by setting the corresponding value in DTR. The
resolution is 1/250. Writing 0 (H'00) in DTR gives a 0% duty cycle. Writing 125 (H'7D) gives a
50% duty cycle. Writing 250 (H'FA) gives a 100% duty cycle.
The DTR and TCNT values are always compared. When the values match, the PWM output is
placed in the 0 state.
DTR is double-buffered. A new value written in DTR does not become valid until after the timer
count changes from H'F9 to H'00. While the OE bit is cleared to 0 in TCR, however, new values
written in DTR become valid immediately. When DTR is read, the value read is the currently
valid value.
DTR is initialized to H'FF by a reset and in the standby modes.
217
10.2.3 Timer Control Register (TCR)
Bit
Initial value
Read/Write
7
0
R/W
6
OS
0
R/W
5
—
1
—
4
—
1
3
—
1
—
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
—
OE
TCR is an 8-bit readable/writable register that selects the clock input to TCNT and controls
PWM output.
TCR is initialized to H'38 by a reset and in standby mode.
Bit 7—Output Enable (OE): This bit enables the timer counter and the PWM output.
Bit 7
OE Description
0 PWM output is disabled. TCNT is cleared to H'00 and stopped. (Initial value)
1 PWM output is enabled. TCNT runs.
Bit 6—Output Select (OS): This bit selects positive or negative logic for the PWM output.
Bit 6
OS Description
0 Positive logic; positive-going PWM pulse, 1 = high (Initial value)
1 Negative logic; negative-going PWM pulse, 1 = low
Bits 5 to 3—Reserved: These bits cannot be modified and are always read as 1.
218
Bits 2, 1, and 0—Clock Select (CKS2, CKS1, and CKS0): These bits select one of eight
internal clock sources obtained by dividing the supporting-module clock (φP).
Bit 2
CKS2 Bit 1
CKS1 Bit 0
CKS0 Description
00 0 φ
P
/2 (Initial value)
00 1 φ
P
/8
01 0 φ
P
/32
01 1 φ
P
/128
10 0 φ
P
/256
10 1 φ
P
/1024
11 0 φ
P
/2048
11 1 φ
P
/4096
From the clock source frequency, the resolution, period, and frequency of the PWM output can
be calculated as follows.
Resolution = 1/clock source frequency
PWM period = resolution × 250
PWM frequency = 1/PWM period
If the φP clock frequency is 10 MHz, then the resolution, period, and frequency of the PWM
output for each clock source are as shown in table 10-3.
Table 10-3 PWM Timer Parameters for 10 MHz System Clock
Internal Clock Frequency Resolution PWM Period PWM Frequency
φP/2 200 ns 50 µs 20 kHz
φP/8 800 ns 200 µs 5 kHz
φP/32 3.2 µs 800 µs 1.25 kHz
φP/128 12.8 µs 3.2 ms 312.5 Hz
φP/256 25.6 µs 6.4 ms 156.3 Hz
φP/1024 102.4 µs 25.6 ms 39.1 Hz
φP/2048 204.8 µs 51.2 ms 19.5 Hz
φP/4096 409.6 µs 102.4 ms 9.8 Hz
219
10.3 Operation
10.3.1 Timer Increment
The PWM clock source is created by dividing the system clock (φ). The timer counter
increments on a TCNT clock pulse generated from the falling edge of the prescaler output as
shown in figure 10-2.
N – 1
TCNT clock
pulse
ø
TCNT
Prescaler
output
N N + 1
Figure 10-2 TCNT Increment Timing
220
10.3.2 PWM Operation
Figure 10-3 is a timing chart of the PWM operation.
N – 1 N + 1
(a) H'00 (b) H'01 H'02 NH'F9 (d) H'00 H'01
N(d) M
H'FF
(c)
(a)*
(e)*
(b) (c)
N written in DTR M written in DTR
ø
TCNT clock
pulses
OE
TCNT
DTR
(OS = 0)
PWM output
(OS = 1)
One PWM cycle
Note: * State depends on values in data register and data direction register.
Figure 10-3 PWM Timing
221
1. Direct Output (OS = 0)
(1) When (OE = 0)—(a) in Figure 10-3: The timer count is held at H'00 and PWM output
is inhibited. [Pin 46 (for PW0) or pin 47 (for PW1) is used for port 4 input/output, and its
state depends on the corresponding port 4 data register and data direction register.] Any
value (such as N in figure 10-3) written in the DTR becomes valid immediately.
(2) When (OE = 1)
i) The timer counter begins incrementing. The PWM output goes high when TCNT
changes from H'00 to H'01, unless DTR = H'00. [(b) in figure 10-3]
ii) When the count passes the DTR value, the PWM output goes low. [(c) in figure 10-3]
iii) If the DTR value is changed (by writing the data “M” in figure 10-3), the new value
becomes valid after the timer count changes from H'F9 to H'00. [(d) in figure 10-3]
2. Inverted Output (OS = 1)—(e) in Figure 10-3: The operation is the same except that high
and low are reversed in the PWM output. [(e) in figure 10-3]
10.4 Application Notes
Some notes on the use of the PWM timer module are given below.
(1) Any necessary changes to the clock select bits (CKS2 to CKS0) and output select bit (OS)
should be made before the output enable bit (OE) is set to 1.
(2) If the DTR value is H'00, the duty cycle is 0% and PWM output remains constant at 0.
If the DTR value is H'FA to H'FF, the duty cycle is 100% and PWM output remains constant
at 1.
(For direct output, 0 is low and 1 is high. For inverted output, 0 is high and 1 is low.)
222
223
Section 11 Watchdog Timer
11.1 Overview
The H8/3534 and H8/3522 have an on-chip watchdog timer (WDT) that can monitor system
operation by resetting the CPU or generating a nonmaskable interrupt if a system crash allows
the timer count to overflow.
When this watchdog function is not needed, the watchdog timer module can be used as an
interval timer. In interval timer mode, it requests an OVF interrupt at each counter overflow.
11.1.1 Features
• Selection of eight clock sources
• Selection of two modes:
Watchdog timer mode
Interval timer mode
• Counter overflow generates an interrupt request or reset:
Reset or NMI request in watchdog timer mode
OVF interrupt request in interval timer mode
224
11.1.2 Block Diagram
Figure 11-1 is a block diagram of the watchdog timer.
Interrupt
control
Reset or NMI
(Watchdog timer mode)
OVF (Interval
timer mode)
Interrupt
signals
Internal reset
Overflow TCNT
TCSR
Read/write
control
Internal
data bus
Clock
select
ø
P
/2
ø
P
/32
ø
P
/64
ø
P
/128
ø
P
/256
ø
P
/512
ø
P
/2048
ø
P
/4096
Internal clock source
Clock
TCNT:
TCSR: Timer counter
Timer control/status register
Figure 11-1 Block Diagram of Watchdog Timer
11.1.3 Register Configuration
Table 11-1 lists information on the watchdog timer registers.
Table 11-1 Register Configuration
Addresses
Name Abbreviation R/W Initial Value Write Read
Timer control/status register TCSR R/(W)*H'18 H'FFA8 H'FFA8
Timer counter TCNT R/W H'00 H'FFA8 H'FFA9
Note: *Software can write a 0 to clear the status flag bits, but cannot write 1.
225
11.2 Register Descriptions
11.2.1 Timer Counter (TCNT)
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
TCNT is an 8-bit readable/writable up-counter. When the timer enable bit (TME) in the timer
control/status register (TCSR) is set to 1, the timer counter starts counting pulses of an internal
clock source selected by clock select bits 2 to 0 (CKS2 to CKS0) in TCSR. When the count
overflows (changes from H'FF to H'00), an overflow flag (OVF) in TCSR is set to 1.
TCNT is initialized to H'00 by a reset and when the TME bit is cleared to 0.
Note: TCNT is write-protected by a password. See Section 11.2.3, Register Access, for details.
11.2.2 Timer Control/Status Register (TCSR)
Bit
Initial value
Read/Write
7
OVF
0
R/(W*)
6
WT/IT
0
R/W
5
TME
0
R/W
4
—
1
—
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Note: *Software can write a 0 in bit 7 to clear the flag, but cannot write a 1 in this bit.
TCSR is an 8-bit readable/writable register that selects the timer mode and clock source and
performs other functions.
Bits 7 to 5 and bit 3 are initialized to 0 by a reset and in the standby modes. Bits 2 to 0 are
initialized to 0 by a reset, but retain their values in the standby modes.
Note: TCSR is write-protected by a password. See section 11.2.3, Register Access, for details.
226
Bit 7—Overflow Flag (OVF): Indicates that the watchdog timer count has overflowed from
H’FF to H’00.
Bit 7
OVF Description
0 To clear OVF, the CPU must read OVF after it has been set to 1, (Initial value)
then write a 0 in this bit
1 Set to 1 when TCNT changes from H'FF to H'00
Bit 6—Timer Mode Select (WT/
,7
,7
): Selects whether to operate in watchdog timer mode or
interval timer mode. When TCNT overflows, an OVF interrupt request is sent to the CPU in
interval timer mode. For watchdog timer mode, a reset or NMI interrupt is requested.
Bit 6
WT/
,7
,7
Description
0 Interval timer mode (OVF request) (Initial value)
1 Watchdog timer mode (reset or NMI request)
Bit 5—Timer Enable (TME): Enables or disables the timer.
Bit 5
TME Description
0 TCNT is initialized to H'00 and stopped (Initial value)
1 TCNT runs and requests a reset or an interrupt when it overflows
Bit 4—Reserved: This bit cannot be modified and is always read as 1.
Bit 3: Reset or NMI Select (RST/
10,
10,
): Selects either an internal reset or the NMI function at
watchdog timer overflow.
Bit 3
RST/
10,
10,
Description
0 NMI function enabled (Initial value)
1 Reset function enabled
227
Bits 2 to 0— Clock Select (CKS2–CKS0): These bits select one of eight clock sources obtained
by dividing the system clock (φ).
The overflow interval is the time from when the watchdog timer counter begins counting from
H'00 until an overflow occurs. In interval timer mode, OVF interrupts are requested at this
interval.
Bit 2
CKS2 Bit 1
CKS1 Bit 0
CKS0 Clock Source Overflow Interval (φφP = 10 MHz)
000φ
P
/2 51.2 µs (Initial value)
001φ
P
/32 819.2 µs
010φ
P
/64 1.6 ms
011φ
P
/128 3.3 ms
100φ
P
/256 6.6 ms
101φ
P
/512 13.1 ms
110φ
P
/2048 52.4 ms
111φ
P
/4096 104.9 ms
11.2.3 Register Access
The watchdog timer’s TCNT and TCSR registers are more difficult to write to than other
registers. The procedures for writing and reading these registers are given below.
Writing to TCNT and TCSR: Word access is required. Byte data transfer instructions cannot
be used for write access.
The TCNT and TCSR registers have the same write address. The write data must be contained in
the lower byte of a word written at this address. The upper byte must contain H'5A (password for
TCNT) or H'A5 (password for TCSR). See figure 11-2. The result of the access depicted in
figure 11-2 is to transfer the write data from the lower byte to TCNT or TCSR.
228
Write dataH'5A
15 8 7 0
Write dataH'A5
15 8 7 0
H'FFA8
H'FFA8
Writing to TCNT
Writing to TCSR
Address
Address
Figure 11-2 Writing to TCNT and TCSR
Reading TCNT and TCSR: The read addresses are H'FFA8 for TCSR and H'FFA9 for TCNT, as
indicated in table 11-2.
These two registers are read like other registers. Byte access instructions can be used.
Table 11-2 Read Addresses of TCNT and TCSR
Read Address Register
H'FFA8 TCSR
H'FFA9 TCNT
229
11.3 Operation
11.3.1 Watchdog Timer Mode
The watchdog timer function begins operating when software sets the WT/
,7
and TME bits to 1
in TCSR. Thereafter, software should periodically rewrite the contents of the timer counter
(normally by writing H'00) to prevent the count from overflowing. If a program crash allows the
timer count to overflow, the entire chip is reset for 518 system clocks (518 φ), or an NMI
interrupt is requested. Figure 11-3 shows the operation.
NMI requests from the watchdog timer have the same vector as NMI requests from the
10,
pin.
Avoid simultaneous handling of watchdog timer NMI requests and NMI requests from pin
10,
.
A reset from the watchdog timer has the same vector as an external reset from the
5(6
pin. The
reset source can be determined by the XRST bit in SYSCR.
H'FF
H'00
TCNT count
WDT overflow
WT/IT = 1
TME = 1 H'00 written
to TCNT
OVF = 1
Reset
518 ø
H'00 written
to TCNT
WT/IT = 1
TME = 1
Time t
Figure 11-3 Operation in Watchdog Timer Mode
230
11.3.2 Interval Timer Mode
Interval timer operation begins when the WT/
,7
bit is cleared to 0 and the TME bit is set to 1.
In interval timer mode, an OVF request is generated each time the timer count overflows. This
function can be used to generate OVF requests at regular intervals. See figure 11-4.
H'FF
H'00
WT/IT = 0
TME = 1
Time t
OVF
request OVF
request OVF
request OVF
request OVF
request
TCNT count
Figure 11-4 Operation in Interval Timer Mode
11.3.3 Setting the Overflow Flag
The OVF bit is set to 1 when the timer count overflows. Simultaneously, the WDT module
requests an internal reset, NMI, or OVF interrupt. The timing is shown in figure 11-5.
H'FF H'00
ø
TCNT
Internal overflow
signal
OVF
Figure 11-5 Setting the OVF Bit
231
11.4 Application Notes
11.4.1 Contention between TCNT Write and Increment
If a timer counter clock pulse is generated during the T3 state of a write cycle to the timer
counter, the write takes priority and the timer counter is not incremented. See figure 11-6.
TCNT address
NM
Counter write data
Internal address bus
Internal write signal
TCNT clock pulse
TCNT
ø
T
3
T
2
T
1
Write cycle (CPU writes to TCNT)
Figure 11-6 TCNT Write-Increment Contention
11.4.2 Changing the Clock Select Bits (CKS2 to CKS0)
Software should stop the watchdog timer (by clearing the TME bit to 0) before changing the
value of the clock select bits. If the clock select bits are modified while the watchdog timer is
running, the timer count may be incremented incorrectly.
11.4.3 Recovery from Software Standby Mode
TCSR bits, except bits 0 to 2, and the TCNT counter are reset when the chip recovers from
software standby mode. Re-initialize the watchdog timer as necessary to resume normal
operation.
232
233
Section 12 Serial Communication Interface
12.1 Overview
The H8/3534 includes two serial communication interface channels (SCI0 and SCI1), and the
H8/3522 one channel, for transferring serial data to and from other chips. Either synchronous or
asynchronous communication can be selected.
12.1.1 Features
The features of the on-chip serial communication interface are:
• Asynchronous mode
The H8/3534 and H8/3522 can communicate with a UART (Universal Asynchronous
Receiver/Transmitter), ACIA (Asynchronous Communication Interface Adapter), or other
chip that employs standard asynchronous serial communication. A multiprocessor
communication function is also provided for communication with other processors. Twelve
data formats are available.
Data length: 7 or 8 bits
Stop bit length: 1 or 2 bits
Parity: Even, odd, or none
Multiprocessor bit: 1 or 0
Error detection: Parity, overrun, and framing errors
Break detection: When a framing error occurs, the break condition can be detected by
reading the level of the RxD line directly.
• Synchronous mode
The SCI can communicate with chips able to perform clocked synchronous data transfer.
Data length: 8 bits
Error detection: Overrun errors
• Full duplex communication
The transmitting and receiving sections are independent, so each channel can transmit and
receive simultaneously. Both the transmit and receive sections use double buffering, so
continuous data transfer is possible in either direction.
• Built-in baud rate generator
Any specified bit rate can be generated.
234
• Internal or external clock source
The SCI can operate on an internal clock signal from the baud rate generator, or an external
clock signal input at the SCK0 or SCK1 pin.
• Four interrupts
TDR-empty, TSR-empty, receive-end, and receive-error interrupts are requested
independently.
235
12.1.2 Block Diagram
Figure 12-1 shows a block diagram of one serial communication interface channel.
TDR
Bus interface
Internal
data bus
Parity
generate Clock
Parity check
TSR ø
ø
P
/4
ø
P
/16
ø
P
/64
RxD
TxD
TXI
RXI
ERI
Interrupt signals
External clock source
Internal
clock
RDR
RSR
SCK
BRR
Communi-
cation
control
SSR
SCR
SMR Baud rate
generator
RSR:
RDR:
TSR:
TDR:
SMR:
SCR:
SSR:
BRR:
Receive shift register (8 bits)
Receive data register (8 bits)
Transmit shift register (8 bits)
Transmit data register (8 bits)
Serial mode register (8 bits)
Serial control register (8 bits)
Serial status register (8 bits)
Bit rate register (8 bits)
TEI
Module data bus
Figure 12-1 Block Diagram of Serial Communication Interface
236
12.1.3 Input and Output Pins
Table 12-1 lists the input and output pins used by the SCI module.
Table 12-1 SCI Input/Output Pins
Channel Name Abbr. I/O Function
0 Serial clock input/output SCK0 (SCK) Input/output SCI0 clock input and output
Receive data input RxD0 (RxD) Input SCI0 receive data input
Transmit data output TxD0 (TxD) Output SCI0 transmit data output
1 Serial clock input/output SCK1Input/output SCI1 clock input and output
[H8/3534 Receive data input RxD1Input SCI1 receive data input
only] Transmit data output TxD1Output SCI1 transmit data output
Note: In this manual, the channel subscript has been deleted, and only SCK, RxD, and TxD are
used.
237
12.1.4 Register Configuration
Table 12-2 lists the SCI registers. These registers specify the operating mode (synchronous or
asynchronous), data format and bit rate, and control the transmit and receive sections.
Table 12-2 SCI Registers
Channel Name Abbr. R/W Value Address
0 Receive shift register RSR —*1——
Receive data register RDR R H'00 H'FFDD
Transmit shift register TSR —*1——
Transmit data register TDR R/W H'FF H'FFDB
Serial mode register SMR R/W H'00 H'FFD8
Serial control register SCR R/W H'00 H'FFDA
Serial status register SSR R/(W)*2H'84 H'FFDC
Bit rate register BRR R/W H'FF H'FFD9
1 Receive shift register RSR —*1——
[H8/3534 Receive data register RDR R H'00 H'FF8D
only] Transmit shift register TSR —*1——
Transmit data register TDR R/W H'FF H'FF8B
Serial mode register SMR R/W H'00 H'FF88
Serial control register SCR R/W H'00 H'FF8A
Serial status register SSR R/(W)*2H'84 H'FF8C
Bit rate register BRR R/W H'FF H'FF89
0 and 1 Serial/timer control register STCR R/W H'00 H'FFC3
Note: 1. Cannot be read or written to.
2. Software can write a 0 to clear the flags in bits 7 to 3, but cannot write 1 in these bits.
238
12.2 Register Descriptions
12.2.1 Receive Shift Register (RSR)
Bit
Read/Write
7
—
6
—
5
—
4
—
3
—
0
—
2
—
1
—
RSR is a shift register that converts incoming serial data to parallel data. When one data
character has been received, it is transferred to the receive data register (RDR).
The CPU cannot read or write RSR directly.
12.2.2 Receive Data Register (RDR)
Bit
Initial value
Read/Write
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
RDR stores received data. As each character is received, it is transferred from RSR to RDR,
enabling RSR to receive the next character. This double-buffering allows the SCI to receive data
continuously.
RDR is a read-only register. RDR is initialized to H'00 by a reset and in the standby modes.
12.2.3 Transmit Shift Register (TSR)
Bit
Read/Write
7
—
6
—
5
—
4
—
3
—
0
—
2
—
1
—
TSR is a shift register that converts parallel data to serial transmit data. When transmission of
one character is completed, the next character is moved from the transmit data register (TDR) to
TSR and transmission of that character begins. If the TDRE bit is still set to 1, however, nothing
is transferred to TSR.
The CPU cannot read or write TSR directly.
239
12.2.4 Transmit Data Register (TDR)
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
TDR is an 8-bit readable/writable register that holds the next data to be transmitted. When TSR
becomes empty, the data written in TDR is transferred to TSR. Continuous data transmission is
possible by writing the next data in TDR while the current data is being transmitted from TSR.
TDR is initialized to H'FF by a reset and in the standby modes.
12.2.5 Serial Mode Register (SMR)
Bit
Initial value
Read/Write
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
SMR is an 8-bit readable/writable register that controls the communication format and selects
the clock source of the on-chip baud rate generator. It is initialized to H'00 by a reset and in the
standby modes. For further information on the SMR settings and communication formats, see
tables 12-5 and 12-7 in section 12.3, Operation.
Bit 7—Communication Mode (C/
$
$
): This bit selects asynchronous or synchronous
communication mode.
Bit 7
C/
$
$
Description
0 Asynchronous communication (Initial value)
1 Synchronous communication
240
Bit 6—Character Length (CHR): This bit selects the character length in asynchronous mode.
It is ignored in synchronous mode.
Bit 6
CHR Description
0 8 bits per character (Initial value)
1 7 bits per character (Bits 0 to 6 of TDR and RDR are used for transmitting and
receiving, respectively.)
Bit 5—Parity Enable (PE): This bit selects whether to add a parity bit in asynchronous mode.
It is ignored in synchronous mode, and when a multiprocessor format is used.
Bit 5
PE Description
0 Transmit: No parity bit is added. (Initial value)
Receive: Parity is not checked.
1 Transmit: A parity bit is added.
Receive: Parity is checked.
Bit 4—Parity Mode (O/
(
(
): In asynchronous mode, when parity is enabled (PE = 1), this bit
selects even or odd parity.
Even parity means that a parity bit is added to the data bits for each character to make the total
number of 1’s even. Odd parity means that the total number of 1’s is made odd.
This bit is ignored when PE = 0, or when a multiprocessor format is used. It is also ignored in
synchronous mode.
Bit 4
O/
(
(
Description
0 Even parity (Initial value)
1 Odd parity
241
Bit 3—Stop Bit Length (STOP): This bit selects the number of stop bits. It is ignored in
synchronous mode.
Bit 3
STOP Description
0 One stop bit (Initial value)
Transmit: One stop bit is added.
Receive: One stop bit is checked to detect framing errors.
1 Two stop bits
Transmit: Two stop bits are added.
Receive: The first stop bit is checked to detect framing errors. If the second stop bit is
a space (0), it is regarded as the next start bit.
Bit 2—Multiprocessor Mode (MP): This bit selects the multiprocessor format in asynchronous
communication. When multiprocessor format is selected, the parity settings of the parity enable
bit (PE) and parity mode bit (O/
(
) are ignored. The MP bit is ignored in synchronous
communication.
The MP bit is valid only when the MPE bit in the serial/timer control register (STCR) is set to 1.
When the MPE bit is cleared to 0, the multiprocessor communication function is disabled
regardless of the setting of the MP bit.
Bit 2
MP Description
0 Multiprocessor communication function is disabled. (Initial value)
1 Multiprocessor communication function is enabled.
Bits 1 and 0—Clock Select 1 and 0 (CKS1 and CKS0): These bits select the clock source of
the on-chip baud rate generator.
Bit 1
CKS1 Bit 0
CKS0 Description
00φ clock (Initial value)
01φ
P
/4 clock
10φ
P
/16 clock
11φ
P
/64 clock
242
12.2.6 Serial Control Register (SCR)
Bit
Initial value
Read/Write
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
SCR is an 8-bit readable/writable register that enables or disables various SCI functions.
It is initialized to H'00 by a reset and in the standby modes.
Bit 7—Transmit Interrupt Enable (TIE): This bit enables or disables the TDR-empty
interrupt (TXI) requested when the transmit data register empty (TDRE) bit in the serial status
register (SSR) is set to 1.
Bit 7
TIE Description
0 The TDR-empty interrupt request (TXI) is disabled. (Initial value)
1 The TDR-empty interrupt request (TXI) is enabled.
Bit 6—Receive Interrupt Enable (RIE): This bit enables or disables the receive-end interrupt
(RXI) requested when the receive data register full (RDRF) bit in the serial status register (SSR)
is set to 1, and the receive error interrupt (ERI) requested when the overrun error (ORER),
framing error (FER), or parity error (PER) bit in the serial status register (SSR) is set to 1.
Bit 6
RIE Description
0 The receive-end interrupt (RXI) and receive-error (ERI) requests are (Initial value)
disabled.
1 The receive-end interrupt (RXI) and receive-error (ERI) requests are enabled.
Bit 5—Transmit Enable (TE): This bit enables or disables the transmit function. When the
transmit function is enabled, the TxD pin is automatically used for output. When the transmit
function is disabled, the TxD pin can be used as a general-purpose I/O port.
Bit 5
TE Description
0 The transmit function is disabled. (Initial value)
The TxD pin can be used for general-purpose I/O.
1 The transmit function is enabled. The TxD pin is used for output.
243
Bit 4—Receive Enable (RE): This bit enables or disables the receive function. When the
receive function is enabled, the RxD pin is automatically used for input. When the receive
function is disabled, the RxD pin is available as a general-purpose I/O port.
Bit 4
RE Description
0 The receive function is disabled. The RxD pin can be (Initial value)
used for general-purpose I/O.
1 The receive function is enabled. The RxD pin is used for input.
Bit 3—Multiprocessor Interrupt Enable (MPIE): When serial data is received in a
multiprocessor format, this bit enables or disables the receive-end interrupt (RXI) and receive-
error interrupt (ERI) until data with the multiprocessor bit set to 1 is received. It also enables or
disables the transfer of received data from RSR to RDR, and enables or disables setting of the
RDRF, FER, PER, and ORER bits in the serial status register (SSR).
The MPIE bit is ignored when the MP bit is cleared to 0, and in synchronous mode.
Clearing the MPIE bit to 0 disables the multiprocessor receive interrupt function. In this
condition data is received regardless of the value of the multiprocessor bit in the receive data.
Setting the MPIE bit to 1 enables the multiprocessor receive interrupt function. In this condition,
if the multiprocessor bit in the receive data is 0, the receive-end interrupt (RXI) and receive-
error interrupt (ERI) are disabled, the receive data is not transferred from RSR to RDR, and the
RDRF, FER, PER, and ORER bits in the serial status register (SSR) are not set. If the
multiprocessor bit is 1, however, the MPB bit in SSR is set to 1, the MPIE bit is cleared to 0, the
receive data is transferred from RSR to RDR, the FER, PER, and ORER bits can be set, and the
receive-end and receive-error interrupts are enabled.
Bit 3
MPIE Description
0 The multiprocessor receive interrupt function is disabled. (Initial value)
(Normal receive operation)
1 The multiprocessor receive interrupt function is enabled. During the interval before
data with the multiprocessor bit set to 1 is received, the receive interrupt request (RXI)
and receive-error interrupt request (ERI) are disabled, the RDRF, FER, PER, and
ORER bits are not set in the serial status register (SSR), and no data is transferred
from the RSR to the RDR. The MPIE bit is cleared at the following times:
(1) When 0 is written in MPIE.
(2) When data with the multiprocessor bit set to 1 is received
244
Bit 2—Transmit-End Interrupt Enable (TEIE): This bit enables or disables the TSR-empty
interrupt (TEI) requested when the transmit-end bit (TEND) in the serial status register (SSR) is
set to 1.
Bit 2
TEIE Description
0 The TSR-empty interrupt request (TEI) is disabled. (Initial value)
1 The TSR-empty interrupt request (TEI) is enabled.
Bit 1—Clock Enable 1 (CKE1): This bit selects the internal or external clock source for the
baud rate generator. When the external clock source is selected, the SCK pin is automatically
used for input of the external clock signal.
Bit 1
CKE1 Description
0 Internal clock source (Initial value)
When C/
$
= 1, the serial clock signal is output at the SCK pin.
When C/
$
= 0, output depends on the CKE0 bit.
1 External clock source. The SCK pin is used for input.
Bit 0—Clock Enable 0 (CKE0): When an internal clock source is used in asynchronous mode,
this bit enables or disables serial clock output at the SCK pin.
This bit is ignored when the external clock is selected, or when synchronous mode is selected.
For further information on the communication format and clock source selection, see table 12-6
in section 12.3, Operation.
Bit 0
CKE0 Description
0 The SCK pin is not used by the SCI (and is available as (Initial value)
a general-purpose I/O port).
1 The SCK pin is used for serial clock output.
245
12.2.7 Serial Status Register (SSR)
Bit
Initial value
Read/Write
7
TDRE
1
R/(W)*
6
RDRF
0
R/(W)*
5
ORER
0
R/(W)*
4
FER
0
R/(W)*
3
PER
0
R/(W)*
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Note: * Software can write a 0 to clear the flags, but cannot write a 1 in these bits.
SSR is an 8-bit register that indicates transmit and receive status. It is initialized to H'84 by a
reset and in the standby modes.
Bit 7—Transmit Data Register Empty (TDRE): This bit indicates when transmit data can
safely be written in TDR.
Bit 7
TDRE Description
0 To clear TDRE, the CPU must read TDRE after it has been set to 1, then write a 0 in
this bit.
1 This bit is set to 1 at the following times: (Initial value)
(1) When TDR contents are transferred to TSR.
(2) When the TE bit in SCR is cleared to 0.
Bit 6—Receive Data Register Full (RDRF): This bit indicates when one character has been
received and transferred to RDR.
Bit 6
RDRF Description
0 To clear RDRF, the CPU must read RDRF after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when one character is received without error and transferred from
RSR to RDR.
246
Bit 5—Overrun Error (ORER): This bit indicates an overrun error during reception.
Bit 5
ORER Description
0 To clear ORER, the CPU must read ORER after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 if reception of the next character ends while the receive data
register is still full (RDRF = 1).
Bit 4—Framing Error (FER): This bit indicates a framing error during data reception in
asynchronous mode. It has no meaning in synchronous mode.
Bit 4
FER Description
0 To clear FER, the CPU must read FER after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 if a framing error occurs (stop bit = 0).
Bit 3—Parity Error (PER): This bit indicates a parity error during data reception in the
asynchronous mode, when a communication format with parity bits is used.
This bit has no meaning in the synchronous mode, or when a communication format without
parity bits is used.
Bit 3
PER Description
0 To clear PER, the CPU must read PER after it has been set to 1, (Initial value)
then write a 0 in this bit.
1 This bit is set to 1 when a parity error occurs (the parity of the received data does not
match the parity selected by the O/
(
bit in SMR).
247
Bit 2—Transmit End (TEND): This bit indicates that the serial communication interface has
stopped transmitting because there was no valid data in TDR when the last bit of the current
character was transmitted. The TEND bit is also set to 1 when the TE bit in the serial control
register (SCR) is cleared to 0.
The TEND bit is a read-only bit and cannot be modified directly. To use the TEI interrupt, first
start transmitting data, which clears TEND to 0, then set TEIE to 1.
Bit 2
TEND Description
0 To clear TEND, the CPU must read TDRE after TDRE has been set to 1, then write a
0 in TDRE
1 This bit is set to 1 when: (Initial value)
(1) TE = 0
(2) TDRE = 1 at the end of transmission of a character
Bit 1—Multiprocessor Bit (MPB): Stores the value of the multiprocessor bit in data received
in a multiprocessor format in asynchronous communication mode. This bit retains its previous
value in synchronous mode, when a multiprocessor format is not used, or when the RE bit is
cleared to 0 even if a multiprocessor format is used.
MPB can be read but not written.
Bit 1
MPB Description
0 Multiprocessor bit = 0 in receive data. (Initial value)
1 Multiprocessor bit = 1 in receive data.
Bit 0—Multiprocessor Bit Transfer (MPBT): Stores the value of the multiprocessor bit
inserted in transmit data when a multiprocessor format is used in asynchronous communication
mode. The MPBT bit is double-buffered in the same way as TSR and TDR. The MPBT bit has
no effect in synchronous mode, or when a multiprocessor format is not used.
Bit 0
MPBT Description
0 Multiprocessor bit = 0 in transmit data. (Initial value)
1 Multiprocessor bit = 1 in transmit data.
248
12.2.8 Bit Rate Register (BRR)
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
BRR is an 8-bit register that, together with the CKS1 and CKS0 bits in SMR, determines the bit
rate output by the baud rate generator.
BRR is initialized to H'FF by a reset and in the standby modes.
Tables 12-3 and 12-4 show examples of BRR settings.
Table 12-3 Examples of BRR Settings in Asynchronous Mode (When φφP = φφ)
φ Frequency (MHz)
2 2.097152
Bit Rate
(bit/s) n N Error
(%) n N Error
(%)
110 1 141 +0.03 1 148 –0.04
150 1 103 +0.16 1 108 +0.21
300 0 207 +0.16 0 217 +0.21
600 0 103 +0.16 0 108 +0.21
1200 0 51 +0.16 0 54 –0.70
2400 0 25 +0.16 0 26 +1.14
4800 0 12 +0.16 0 13 –2.48
9600 — — — 0 6 –2.48
19200 — — — — — —
31250 0 1 0 — — —
38400 — — — — — —
Note: If possible, the error should be within 1%.
In the shaded section, if φP = φ/2, the bit rate is cut in half. In this case, BRR settings for
the desired bit rate should be referenced from the column of one-half the actual system
clock frequency (φ).
249
Table 12-3 Examples of BRR Settings in Asynchronous Mode (When φφP = φφ) (cont)
φ Frequency (MHz)
2.4576 3 3.6864 4
Bit Rate Error Error Error Error
(bit/s) n N (%) n N (%) n N (%) n N (%)
110 1 174 –0.26 2 52 +0.50 2 64 +0.70 2 70 +0.03
150 1 127 0 1 155 +0.16 1 191 0 1 207 +0.16
300 0 255 0 1 77 +0.16 1 95 0 1 103 +0.16
600 0 127 0 0 155 +0.16 0 191 0 0 207 +0.16
1200 0 63 0 0 77 +0.16 0 95 0 0 103 +0.16
2400 0 31 0 0 38 +0.16 0 47 0 0 51 +0.16
4800 0 15 0 0 19 –2.34 0 23 0 0 25 +0.16
9600 0 7 0 0 9 –2.34 0 11 0 0 12 +0.16
19200 0 3 0 0 4 –2.34 0 5 0 — — —
31250 — — — 0 2 0 — — — 0 3 0
38400 0 1 0 — — — 0 2 0 — — —
250
Table 12-3 Examples of BRR Settings in Asynchronous Mode (When φφP = φφ) (cont)
φ Frequency (MHz)
4.9152 5 6 6.144
Bit Rate Error Error Error Error
(bit/s) n N (%) n N (%) n N (%) n N (%)
110 2 86 +0.31 2 88 –0.25 2 106 –0.44 2 108 +0.08
150 1 255 0 2 64 +0.16 2 77 +0.16 2 79 0
300 1 127 0 1 129 +0.16 1 155 +0.16 1 159 0
600 0 255 0 1 64 +0.16 1 77 +0.16 1 79 0
1200 0 127 0 0 129 +0.16 0 155 +0.16 0 159 0
2400 0 63 0 0 64 +0.16 0 77 +0.16 0 79 0
4800 0 31 0 0 32 –1.36 0 38 +0.16 0 39 0
9600 0 15 0 0 15 +1.73 0 19 –2.34 0 19 0
19200 0 7 0 0 7 +1.73 0 9 –2.34 0 9 0
31250 0 4 –1.70 0 4 0 0 5 0 0 5 +2.40
38400 0 3 0 0 3 +1.73 0 4 –2.34 0 4 0
Note: If possible, the error should be within 1%.
In the shaded section, if φP = φ/2, the bit rate is cut in half. In this case, BRR settings for
the desired bit rate should be referenced from the column of one-half the actual system
clock frequency (φ).
251
Table 12-3 Examples of BRR Settings in Asynchronous Mode (When φφP = φφ) (cont)
φ Frequency (MHz)
7.3728 8 9.8304 10
Bit Rate Error Error Error Error
(bit/s) n N (%) n N (%) n N (%) n N (%)
110 2 130 –0.07 2 141 +0.03 2 174 –0.26 2 177 –0.25
150 2 95 0 2 103 +0.16 2 127 0 2 129 +0.16
300 1 191 0 1 207 +0.16 1 255 0 2 64 +0.16
600 1 95 0 1 103 +0.16 1 127 0 1 129 +0.16
1200 0 191 0 0 207 +0.16 0 255 0 1 64 +0.16
2400 0 95 0 0 103 +0.16 0 127 0 0 129 +0.16
4800 0 47 0 0 51 +0.16 0 63 0 0 64 +0.16
9600 0 23 0 0 25 +0.16 0 31 0 0 32 –1.36
19200 0 11 0 0 12 +0.16 0 15 0 0 15 +1.73
31250 — — — 0 7 0 0 9 –1.70 0 9 0
38400 0 5 0 — — — 0 7 0 0 7 +1.73
B = F × 106/[64 × 22n–1 × (N + 1)] → N = F × 106/[64 × 22n–1 × B] – 1
B: Bit rate (bits/second)
N: BRR value (0 ≤ N ≤ 255)
F: φP (MHz) when n ≠ 0, or φ (MHz) when n = 0
n: Internal clock source (0, 1, 2, or 3)
The meaning of n is given by the table below:
n CKS1 CKS0 Clock
00 0 φ
10 1 φ
P
/4
21 0 φ
P
/16
31 1 φ
P
/64
Bit rate error can be calculated with the formula below.
Error (%) = {[(F × 106)/ {(N + 1) × B × 64 × 22n–1}]– 1} × 100
252
Table 12-4 Examples of BRR Settings in Synchronous Mode (When φφP = φφ)
φφ Frequency (MHz)
Bit Rate 2 4 5 8 10
(bit/s) n N n N n N n N n N
100 — — — — — — — — — —
250 2 124 2 249 — — 3 124 — —
500 1 249 2 124 — — 2 249 — —
1 k 1 124 1 249 — — 2 124 — —
2.5 k 0 199 1 99 1 124 1 199 1 249
5 k 0 99 0 199 0 249 1 99 1 124
10 k 0 49 0 99 0 124 0 199 0 249
25 k 0 19 0 39 0 49 0 79 0 99
50 k09019024039049
100 k 0 4 0 9 — — 0 19 0 24
250 k 0 1 0 3 0 4 0 7 0 9
500 k 0 0*01 ——0304
1 M 0 0*——01——
2.5 M 00
*
4 M
Notes: In the shaded section, if φP = φ/2, the bit rate is cut in half. In this case, BRR settings for
the desired bit rate should be referenced from the column of one-half the actual system
clock frequency (φ).
Blank: No setting is available.
—: A setting is available, but the bit rate is inaccurate.
*: Continuous transfer is not possible.
B = F × 106/[8 × 22n–1 × (N + 1)] → N = F × 106/[8 × 22n–1 × B] – 1
B: Bit rate (bits per second)
N: BRR value (0 ≤ N ≤ 255)
F: φP (MHz) when n ≠ 0, or φ (MHz) when n = 0
n: Internal clock source (0, 1, 2, or 3)
253
The meaning of n is given by the table below:
n CKS1 CKS0 Clock
00 0 φ
10 1 φ
P
/4
21 0 φ
P
/16
31 1 φ
P
/64
12.2.9 Serial/Timer Control Register (STCR)
Bit
[H8/3534]
Initial value
Read/Write
7
(IICS)
0
R/W
6
(IICD)
0
R/W
5
(IICX)
0
R/W
4
(IICE)
0
R/W
3
(STAC)
0
R/W
0
ICKS0
0
R/W
2
MPE
0
R/W
1
ICKS1
0
R/W
Bit
[H8/3522]
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
ICKS0
0
R/W
2
MPE
0
R/W
1
ICKS1
0
R/W
STCR is an 8-bit readable/writable register that controls the SCI operating mode and selects the
TCNT clock source in the 8-bit timers. STCR is initialized to H'00 [H8/3534]/H'F8 [H8/3522]
by a reset.
Bits 7 to 4—I2C Control (IICS, IICD, IICX, IICE) [H8/3534]: These bits are reserved. They
should not be set to 1.
Bit 3—Slave Input Switch (STAC) [H8/3534]: This bit is reserved. It should not be set to 1.
Bits 7 to 3—Reserved [H8/3522]: These bits cannot be modified and are always read as 1.
Bit 2—Multiprocessor Enable (MPE): Enables or disables the multiprocessor communication
function on channels SCI0 and SCI1.
Bit 2
MPE Description
0 The multiprocessor communication function is disabled, (Initial value)
regardless of the setting of the MP bit in SMR.
1 The multiprocessor communication function is enabled. The multiprocessor format can
be selected by setting the MP bit in SMR to 1.
254
Bits 1 and 0—Internal Clock Source Select 1 and 0 (ICKS1, ICKS0): These bits select the
clock input to the timer counters (TCNT) in the 8-bit timers. For details, see section 9, 8-Bit
Timers.
12.3 Operation
12.3.1 Overview
The SCI supports serial data transfer in two modes. In asynchronous mode each character is
synchronized individually. In synchronous mode communication is synchronized with a clock
signal.
The selection of asynchronous or synchronous mode and the communication format depend on
SMR settings as indicated in table 12-5. The clock source depends on the settings of the C/
$
bit
in SMR and the CKE1 and CKE0 bits in SCR as indicated in table 12-6.
Asynchronous Mode
• Data length: 7 or 8 bits can be selected.
• A parity bit or multiprocessor bit can be added, and stop bit lengths of 1 or 2 bits can be
selected. (These selections determine the communication format and character length.)
• Framing errors (FER), parity errors (PER), and overrun errors (ORER) can be detected in
receive data, and the line-break condition can be detected.
• SCI clock source: An internal or external clock source can be selected.
Internal clock: The SCI is clocked by the on-chip baud rate generator and can output a clock
signal at the bit-rate frequency.
External clock: The external clock frequency must be 16 times the bit rate. (The on-chip
baud rate generator is not used.)
Synchronous Mode
• Communication format: The data length is 8 bits.
• Overrun errors (ORER) can be detected in receive data.
• SCI clock source: An internal or external clock source can be selected.
Internal clock: The SCI is clocked by the on-chip baud rate generator and outputs a serial
clock signal to external devices.
External clock: The on-chip baud rate generator is not used. The SCI operates on the input
serial clock.
255
Table 12-5 Communication Formats Used by SCI
SMR Settings Communication Format
Bit 7
C/
$
$
Bit 6
CHR Bit 2
MP Bit 5
PE Bit 3
STOP Mode Data
Length
Multi-
processor
Bit Parity
Bit
Stop-
Bit
Length
0 0 0 0 0 Asynchronous
mode 8 bits None None 1 bit
1 2 bits
1 0 Present 1 bit
1 2 bits
1 0 0 7 bits None 1 bit
1 2 bits
1 0 Present 1 bit
1 2 bits
0 1 — 0 Asynchronous
mode (multi-
processor
format)
8 bits Present None 1 bit
1 2 bits
1 0 7 bits 1 bit
1 2 bits
1 — — — — Synchronous
mode 8 bits None None
Table 12-6 SCI Clock Source Selection
SMR SCR
Bit 7 Bit 1 Bit 0 Serial Transmit/Receive Clock
C/
$
$
CKE1 CKE0 Mode Clock Source SCK Pin Function
0 0 0 Async Internal Input/output port (not used by SCI)
1 Serial clock output at bit rate
1 0 External Serial clock input at 16 × bit rate
1
1 0 0 Sync Internal Serial clock output
1
1 0 External Serial clock input
1
256
12.3.2 Asynchronous Mode
In asynchronous mode, each transmitted or received character is individually synchronized by
framing it with a start bit and stop bit.
Full duplex data transfer is possible because the SCI has independent transmit and receive
sections. Double buffering in both sections enables the SCI to be programmed for continuous
data transfer.
Figure 12-2 shows the general format of one character sent or received in asynchronous mode.
The communication channel is normally held in the mark state (high). Character transmission or
reception starts with a transition to the space state (low).
The first bit transmitted or received is the start bit (low). It is followed by the data bits, in which
the least significant bit (LSB) comes first. The data bits are followed by the parity or
multiprocessor bit, if present, then the stop bit or bits (high) confirming the end of the frame.
In receiving, the SCI synchronizes on the falling edge of the start bit, and samples each bit at the
center of the bit (at the 8th cycle of the internal serial clock, which runs at 16 times the bit rate).
D0 D1 DnStart bit
1 bit 7 or 8 bits
One unit of data (one character or frame)
Parity or
multipro-
cessor bit Stop bit
0 or 1 bit 1 or 2 bits
Idle state
(mark)
Figure 12-2 Data Format in Asynchronous Mode
(Example of 8-Bit Data with Parity Bit and Two Stop Bits)
257
1. Data Format: Table 12-7 lists the data formats that can be sent and received in
asynchronous mode. Twelve formats can be selected by bits in the serial mode register
(SMR).
Table 12-7 Data Formats in Asynchronous Mode
CHR
0
0
0
0
1
1
1
1
0
0
1
1
PE
0
0
1
1
0
0
1
1
—
—
—
—
MP
0
0
0
0
0
0
0
0
1
1
1
1
STOP
0
1
0
1
0
1
0
1
0
1
0
1
SMR Bits
1 2 3 4 5 6 7 8 9 10 11 12
S
S
S
S
S
S
S
S
S
S
S
S
8-bit data STOP
8-bit data STOP STOP
8-bit data PSTOP
8-bit data PSTOP STOP
7-bit data STOP
7-bit data STOP STOP
7-bit data PSTOP
7-bit data PSTOP STOP
8-bit data MPB STOP
8-bit data MPB STOP STOP
7-bit data MPB STOP
7-bit data MPB STOP STOP
Notes: SMR: Serial mode register
S: Start bit
STOP: Stop bit
P: Parity bit
MPB: Multiprocessor bit
2. Clock: In asynchronous mode it is possible to select either an internal clock created by the
on-chip baud rate generator, or an external clock input at the SCK pin. The selection is made
by the C/
$
bit in the serial mode register (SMR) and the CKE1 and CKE0 bits in the serial
control register (SCR). Refer to table 12-6.
If an external clock is input at the SCK pin, its frequency should be 16 times the desired bit
rate.
If the internal clock provided by the on-chip baud rate generator is selected and the SCK pin
is used for clock output, the output clock frequency is equal to the bit rate, and the clock
pulse rises at the center of the transmit data bits. Figure 12-3 shows the phase relationship
between the output clock and transmit data.
258
0 D0D1D2D3D4
One frame
D5 D6 D7 0/1 1 1
Figure 12-3 Phase Relationship between Clock Output and Transmit Data
(Asynchronous Mode)
3. Transmitting and Receiving Data
SCI Initialization: Before transmitting or receiving, software must clear the TE and RE
bits to 0 in the serial control register (SCR), then initialize the SCI following the
procedure in figure 12-4.
Note: When changing the communication mode or format, always clear the TE and
RE bits to 0 before following the procedure given below. Clearing TE to 0 sets TDRE to
1 and initializes the transmit shift register (TSR). Clearing RE to 0, however, does not
initialize the RDRF, PER, FER, and ORER flags and receive data register (RDR), which
retain their previous contents.
When an external clock is used, the clock should not be stopped during initialization or
subsequent operation. SCI operation becomes unreliable if the clock is stopped.
259
Clear TE and RE bits to
0 in SCR
1 bit interval
elapsed?
Start transmitting or receiving
No
Yes
1.
2.
3.
4.
Select interrupts and the clock source in the
serial control register (SCR). Leave TE and RE
cleared to 0. If clock output is selected, in
asynchronous mode, clock output starts
immediately after the setting is made in SCR.
Select the communication format in the serial
mode register (SMR).
Write the value corresponding to the bit rate in
the bit rate register (BRR). This step is not
necessary when an external clock is used.
Wait for at least the interval required to transmit
or receive one bit, then set TE or RE in the serial
control register (SCR). Setting TE or RE enables
the SCI to use the TxD or RxD pin.
Also set the RIE, TIE, TEIE, and MPIE bits as
necessary to enable interrupts. The initial states
are the mark transmit state, and the idle receive
state (waiting for a start bit).
1
2
Set CKE1 and CKE0 bits in
SCR (leaving TE and RE
cleared to 0)
3
Set TE or RE to 1 in SCR,
and set RIE, TIE, TEIE, and
MPIE as necessary
4
Initialization
Set value in BRR
Select communication
format in SMR
Figure 12-4 Sample Flowchart for SCI Initialization
260
Transmitting Serial Data: Follow the procedure in figure 12-5 for transmitting serial
data.
Start transmitting
Read TDRE bit in SSR
TDRE = 1?
Write transmit data in TDR
End of
transmission?
End
1
2
3
No
Yes
No
Yes
SCI initialization: the transmit data output function
of the TxD pin is selected automatically.
SCI status check and transmit data write: read
the serial status register (SSR), check that the
TDRE bit is 1, then write transmit data in the
transmit data register (TDR) and clear TDRE to 0.
If a multiprocessor format is selected, after
writing the transmit data write 0 or 1 in the
multiprocessor bit transfer (MPBT) in SSR.
Transition of the TDRE bit from 0 to 1 can be
reported by an interrupt.
To continue transmitting serial data: read the
TDRE bit to check whether it is safe to write; if
TDRE = 1, write data in TDR, then clear TDRE
to 0.
To end serial transmission: end of transmission
can be confirmed by checking transition of the
TEND bit from 0 to 1. This can be reported by
a TEI interrupt.
To output a break signal at the end of serial
transmission: set the DDR bit to 1 and clear the
DR bit to 0 (DDR and DR are I/O port registers),
then clear TE to 0 in SCR.
(a)
(b)
If using multiprocessor format,
select MPBT value in SSR
Clear TDRE bit to 0
Read TEND bit in SSR
TEND = 1? No
Yes
Output break
signal? No
Yes
Clear TE bit in SCR to 0
4
1.
2.
3.
4.
Initialize
Set DR = 0, DDR = 1
Serial transmission
Figure 12-5 Sample Flowchart for Transmitting Serial Data
261
In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI
recognizes that the transmit data register (TDR) contains new data, and loads this data
from TDR into the transmit shift register (TSR).
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts
transmitting. If the TIE bit (TDR-empty interrupt enable) is set to 1 in SCR, the SCI
requests a TXI interrupt (TDR-empty interrupt) at this time.
Serial transmit data are transmitted in the following order from the TxD pin:
(a) Start bit: One 0 bit is output.
(b) Transmit data: Seven or eight bits are output, LSB first.
(c) Parity bit or multiprocessor bit: One parity bit (even or odd parity) or one
multiprocessor bit is output. Formats in which neither a parity bit nor a multiprocessor
bit is output can also be selected.
(d) Stop bit: One or two 1 bits (stop bits) are output.
(e) Mark state: Output of 1 bits continues until the start bit of the next transmit
data.
3. The SCI checks the TDRE bit when it outputs the stop bit. If TDRE is 0, after loading
new data from TDR into TSR and transmitting the stop bit, the SCI begins serial
transmission of the next frame. If TDRE is 1, after setting the TEND bit to 1 in SSR
and transmitting the stop bit, the SCI continues 1-level output in the mark state, and if
the TEIE bit (TSR-empty interrupt enable) in SCR is set to 1, the SCI generates a TEI
interrupt request (TSR-empty interrupt).
262
Figure 12-6 shows an example of SCI transmit operation in asynchronous mode.
1Start
bit
0 D0 D1 D7 0/1
Stop
bit
1
Data Parity
bit Start
bit
0 D0 D1 D7 0/1
Stop
bit
1
Data Parity
bit 1
Idle state
(mark)
TDRE
TEND
TXI
request TXI interrupt handler
writes data in TDR and
clears TDRE to 0
TXI
request
1 frame
TEI request
Figure 12-6 Example of SCI Transmit Operation
(8-Bit Data with Parity and One Stop Bit)
263
Receiving Serial Data: Follow the procedure in figure 12-7 for receiving serial data.
Start receiving
RDRF = 1?
Read receive data from RDR,
and clear RDRF bit to 0
in SSR
PER ∨ RER ∨
ORER = 1?
Clear RE to 0 in SCR
Finished
receiving?
End
Error handling
Start error handling
FER = 1?
Discriminate and
process error, and
clear flags
Return
Break?
Clear RE to 0
in SCR
End
1
2
No
Yes
Yes
No
No
Yes
4
1.
2.
3.
4.
SCI initialization: the receive data function of the RxD
pin is selected automatically.
To continue receiving serial data: read RDR and
clear RDRF to 0 before the stop bit of the current
frame is received.
SCI status check and receive data read: read the
serial status register (SSR), check that RDRF is set
to 1, then read receive data from the receive data
register (RDR) and clear RDRF to 0. Transition of
the RDRF bit from 0 to 1 can be reported by an RXI
interrupt.
Receive error handling and break detection: if a
receive error occurs, read the ORER, PER, and
FER bits in SSR to identify the error. After executing
the necessary error handling, clear ORER, PER, and
FER all to 0. Transmitting and receiving cannot
resume if ORER, PER, or FER remains set to 1.
When a framing error occurs, the RxD pin can be
read to detect the break state.
Yes
No
Yes
No
3
Initialize
Read ORER, PER, and
FER in SSR
Read RDRF bit in SSR
Figure 12-7 Sample Flowchart for Receiving Serial Data
264
In receiving, the SCI operates as follows.
1. The SCI monitors the receive data line and synchronizes internally when it detects a
start bit.
2. Receive data is shifted into RSR in order from LSB to MSB.
3. The parity bit and stop bit are received.
After receiving these bits, the SCI makes the following checks:
(a) Parity check: The number of 1s in the receive data must match the even or odd
parity setting of the O/
(
bit in SMR.
(b) Stop bit check: The stop bit value must be 1. If there are two stop bits, only the
first stop bit is checked.
(c) Status check: RDRF must be 0 so that receive data can be loaded from RSR
into RDR.
If these checks all pass, the SCI sets RDRF to 1 and stores the received data in RDR.
If one of the checks fails (receive error), the SCI operates as indicated in table 12-8.
Note: When a receive error flag is set, further receiving is disabled. The RDRF bit is
not set to 1. Be sure to clear the error flags.
4. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in
SCR, the SCI requests an RXI (receive-end) interrupt. If one of the error flags
(ORER, PER, or FER) is set to 1 and the RIE bit in SCR is also set to 1, the SCI
requests an ERI (receive-error) interrupt.
Figure 12-8 shows an example of SCI receive operation in asynchronous mode.
265
Table 12-8 Receive Error Conditions and SCI Operation
Receive error Abbreviation Condition Data Transfer
Overrun error ORER Receiving of next data ends
while RDRF is still set to 1
in SSR
Receive data not loaded from
RSR into RDR
Framing error FER Stop bit is 0 Receive data loaded from
RSR into RDR
Parity error PER Parity of receive data differs
from even/odd parity setting
in SMR
Receive data loaded from RSR
into RDR
1 Start
bit
0 D0 D1 D7 0/1
Stop
bit
1
Data Parity
bit Start
bit
0 D0 D1 D7 0/1
Stop
bit
0
Data Parity
bit 1
Idle state
(mark)
RDRF
FER
1 frame
Framing error,
ERI request
RXI interrupt handler
reads data in RDR and
clears RDRF to 0
RXI
request
Figure 12-8 Example of SCI Receive Operation (8-Bit Data with Parity and One Stop Bit)
266
4. Multiprocessor Communication
The multiprocessor communication function enables several processors to share a single
serial communication line. The processors communicate in asynchronous mode using a
format with an additional multiprocessor bit (multiprocessor format).
In multiprocessor communication, each receiving processor is addressed by an ID.
A serial communication cycle consists of two cycles: an ID-sending cycle that identifies the
receiving processor, and a data-sending cycle. The multiprocessor bit distinguishes ID-
sending cycles from data-sending cycles.
The transmitting processor starts by sending the ID of the receiving processor with which it
wants to communicate as data with the multiprocessor bit set to 1. Next the transmitting
processor sends transmit data with the multiprocessor bit cleared to 0.
Receiving processors skip incoming data until they receive data with the multiprocessor bit
set to 1.
After receiving data with the multiprocessor bit set to 1, the receiving processor with an ID
matching the received data continues to receive further incoming data. Multiple processors
can send and receive data in this way.
Four formats are available. Parity-bit settings are ignored when a multiprocessor format is
selected. For details see table 12-7.
267
Transmitting
processor
Receiving
processor A
Serial communication line
Receiving
processor B Receiving
processor C Receiving
processor D
(ID = 01) (ID = 02) (ID = 03) (ID = 04)
Serial data H'01 H'AA
(MPB = 1) (MPB = 0)
ID-sending cycle:
receiving processor address Data-sending cycle:
data sent to receiving
processor specified by ID
MPB: Multiprocessor bit
Figure 12-9 Example of Communication among Processors using Multiprocessor Format
(Sending Data H'AA to Receiving Processor A)
268
Transmitting Multiprocessor Serial Data: See figures 12-5 and 12-6.
Receiving Multiprocessor Serial Data: Follow the procedure in figure 12-10 for
receiving multiprocessor serial data.
Start receiving
Set MPIE bit to 1 in SCR
FER ∨
ORER = 1?
FER +
ORER = 1?
Finished
receiving?
Clear RE to 0 in SCR
End
Error handling FER = 1?
Discriminate and
process error, and
clear flags
Return
Break?
Clear RE bit to
0 in SCR
End
1
2
3
4
No
Yes
Yes
No
Yes
No
No
Yes
No
Yes
5
1. SCI initialization: the receive data function of the RxD pin is
selected automatically.
2. ID receive cycle: Set the MPIE bit in the serial control register
(SCR) to 1.
3. SCI status check and ID check: read the serial status register
(SSR), check that RDRF is set to 1, then read receive data
from the receive data register (RDR) and compare with the
processor’s own ID. Transition of the RDRF bit from 0 to
1 can be reported by an RXI interrupt. If the ID does not match
the receive data, set MPIE to 1 again and clear RDRF to 0.
If the ID matches the receive data, clear RDRF to 0.
4. SCI status check and data receiving: read SSR, check that
RDRF is set to 1, then read data from the receive data register
(RDR) and write 0 in the RDRF bit. Transition of the RDRF bit
from 0 to 1 can be reported by an RXI interrupt.
5. Receive error handling and break detection: if a receive error
occurs, read the ORER and FER bits in SSR to identify the error.
After executing the necessary error handling, clear both ORER
and FER to 0. Receiving cannot resume while ORER or FER
remains set to 1. When a framing error occurs, the RxD pin
can be read to detect the break state.
Yes
No
Yes
No
Initialize
Start error handling
Read RDRF bit in SSR
RDRF = 1?
Read ORER and FER
bits in SSR
Own ID? No
Yes
Read RDRF bit in SSR
RDRF = 1?
Read ORER and FER
bits in SSR
Read receive data from RDR
Read receive data from RDR
Figure 12-10 Sample Flowchart for Receiving Multiprocessor Serial Data
269
Figure 12-11 shows an example of an SCI receive operation using a multiprocessor
format (8-bit data with multiprocessor bit and one stop bit).
1Start
bit
0D0D1 D71
Stop
bit
1
Data (ID1) MPB Start
bit
0D0D1 D70
Stop
bit
1
Data (Data1) MPB 1
Idle state
(mark)
MPIE
RDRF
RDR value ID1
RXI requestMPB detection
MPIE = 0 RXI handler reads
RDR data and clears
RDRF to 0
Not own ID, so
MPIE is set to
1 again
No RXI request,
RDR not updated
(Multiprocessor interrupt)
(a) Own ID does not match data
1Start
bit
0D0D1 D71
Stop
bit
1
Data (ID2) MPB Start
bit
0D0D1 D70
Stop
bit
1
Data (Data2) MPB 1
Idle state
(mark)
MPIE
RDRF
RDR value ID2
RXI requestMPB detection
MPIE = 0 RXI handler reads
RDR data and clears
RDRF to 0
Own ID, so receiving
continues, with data
received at each RXI
MPIE set to
1 again
(Multiprocessor interrupt)
(b) Own ID matches data
Data 2
Figure 12-11 Example of SCI Receive Operation
(8-Bit Data with Multiprocessor Bit and One Stop Bit)
270
12.3.3 Synchronous Mode
(1) Overview: In synchronous mode, the SCI transmits and receives data in synchronization
with clock pulses. This mode is suitable for high-speed serial communication.
The SCI transmitter and receiver share the same clock but are otherwise independent, so full
duplex communication is possible. The transmitter and receiver are also double buffered, so
continuous transmitting or receiving is possible by reading or writing data while transmitting
or receiving is in progress.
Figure 12-12 shows the general format in synchronous serial communication.
Serial clock
Serial data Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7
LSB MSB
Don’t care Don’t care
One unit (character or frame) of serial data
**
Note: High except in continuous transmitting or receiving*
Figure 12-12 Data Format in Synchronous Communication
In synchronous serial communication, each data bit is sent on the communication line from
one falling edge of the serial clock to the next. Data is received in synchronization with the
rising edge of the serial clock.
In each character, the serial data bits are transmitted in order from LSB (first) to MSB (last).
After output of the MSB, the communication line remains in the state of the MSB.
271
Communication Format: The data length is fixed at eight bits. No parity bit or
multiprocessor bit can be added.
Clock: An internal clock generated by the on-chip baud rate generator or an external
clock input from the SCK pin can be selected by clearing or setting the C/
$
bit in the
serial mode register (SMR) and the CKE1 and CKE0 bits in the serial control register
(SCR). See table 12-6.
When the SCI operates on an internal clock, it outputs the clock signal at the SCK pin.
Eight clock pulses are output per transmitted or received character. When the SCI is not
transmitting or receiving, the clock signal remains at the high level.
(2) Transmitting and Receiving Data
SCI Initialization: The SCI must be initialized in the same way as in asynchronous
mode. See figure 12-4. When switching from asynchronous mode to synchronous mode,
check that the ORER, FER, and PER bits are cleared to 0. Transmitting and receiving
cannot begin if ORER, FER, or PER is set to 1.
272
Transmitting Serial Data: Follow the procedure in figure 12-13 for transmitting serial
data.
Start transmitting
Read TDRE bit in SSR
TDRE = 1?
Write transmit data in
TDR and clear TDRE bit to
0 in SSR
End of
transmission?
End
1
2
3
No
Yes
No
Yes
SCI initialization: the transmit data output function
of the TxD pin is selected automatically.
SCI status check and transmit data write: read
the serial status register (SSR), check that the
TDRE bit is 1, then write transmit data in the
transmit data register (TDR) and clear TDRE to 0.
Transition of the TDRE bit from 0 to 1 can be
reported by a TXI interrupt.
To continue transmitting serial data: read the
TDRE bit to check whether it is safe to write; if
TDRE = 1, write data in TDR, then clear TDRE
to 0.
To end serial transmission: end of transmission
can be confirmed by checking transition of the
TEND bit from 0 to 1. This can be reported by
a TEI interrupt.
(a)
(b)
Read TEND bit in SSR
TEND = 1? No
Yes
1.
2.
3.
Initialize
Clear TE bit to 0 in SCR
Serial transmission
Figure 12-13 Sample Flowchart for Serial Transmitting
273
In transmitting serial data, the SCI operates as follows.
1. The SCI monitors the TDRE bit in SSR. When TDRE is cleared to 0 the SCI
recognizes that the transmit data register (TDR) contains new data, and loads this data
from TDR into the transmit shift register (TSR).
2. After loading the data from TDR into TSR, the SCI sets the TDRE bit to 1 and starts
transmitting. If the TIE bit (TDR-empty interrupt enable) in SCR is set to 1, the SCI
requests a TXI interrupt (TDR-empty interrupt) at this time.
If clock output is selected the SCI outputs eight serial clock pulses, triggered by the
clearing of the TDRE bit to 0. If an external clock source is selected, the SCI outputs
data in synchronization with the input clock.
Data is output from the TxD pin in order from LSB (bit 0) to MSB (bit 7).
3. The SCI checks the TDRE bit when it outputs the MSB (bit 7). If TDRE is 0, the SCI
loads data from TDR into TSR, then begins serial transmission of the next frame. If
TDRE is 1, the SCI sets the TEND bit in SSR to 1, transmits the MSB, then holds the
output in the MSB state. If the TEIE bit (transmit-end interrupt enable) in SCR is set
to 1, a TEI interrupt (TSR-empty interrupt) is requested at this time.
4. After the end of serial transmission, the SCK pin is held at the high level.
274
Figure 12-14 shows an example of SCI transmit operation.
Serial clock
Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
TXI
request
TDRE
TEND
TXI interrupt
handler writes
data in TDR and
clears TDRE to 0
TXI
request TEI
request
1 frame
Figure 12-14 Example of SCI Transmit Operation
275
Receiving Serial Data: Follow the procedure in figure 12-15 for receiving serial data.
When switching from asynchronous mode to synchronous mode, be sure to check that
PER and FER are cleared to 0. If PER or FER is set to 1 the RDRF bit will not be set and
both transmitting and receiving will be disabled.
Start receiving
Read ORER bit in SSR
ORER = 1?
RDRF = 1?
Read RDRF in SSR
Finished
receiving?
Clear RE to 0 in SCR
End
Error handling
1
2
3
Yes
No
No
Yes
No
Yes
4
1.
2.
3.
4.
SCI initialization: the receive data function of the
RxD pin is selected automatically.
Receive error handling: if a receive error occurs,
read the ORER bit in SSR then, after executing
the necessary error handling, clear ORER to 0.
Neither transmitting nor receiving can resume
while ORER remains set to 1. When clock
output mode is selected, receiving can be halted
temporarily by receiving one dummy byte and
causing an overrun error. When preparations
to receive the next data are completed, clear
the ORER bit to 0. This causes receiving to
resume, so return to the step marked 2 in the
flowchart.
SCI status check and receive data read: read
the serial status register (SSR), check that
RDRF is set to 1, then read receive data from
the receive data register (RDR) and clear RDRF
to 0. Transition of the RDRF bit from 0 to 1
can be reported by an RXI interrupt.
To continue receiving serial data: read RDR and
clear RDRF to 0 before the MSB (bit 7) of the
current frame is received.
Clear ORER to 0 in SSR
Return
Overrun error handling
Start error handling
Initialize
Read receive data
from RDR, and clear
RDRF bit to 0 in SSR
Figure 12-15 Sample Flowchart for Serial Receiving
276
In receiving, the SCI operates as follows.
1. If an external clock is selected, data is input in synchronization with the input clock.
If clock output is selected, as soon as the RE bit is set to 1 the SCI begins outputting
the serial clock and inputting data. If clock output is stopped because the ORER bit is
set to 1, output of the serial clock and input of data resume as soon as the ORER bit is
cleared to 0.
2. Receive data is shifted into RSR in order from LSB to MSB.
After receiving the data, the SCI checks that RDRF is 0 so that receive data can be
loaded from RSR into RDR. If this check passes, the SCI sets RDRF to 1 and stores
the received data in RDR. If the check does not pass (receive error), the SCI operates
as indicated in
table 12-8.
Note: Both transmitting and receiving are disabled while a receive error flag is set.
The RDRF bit is not set to 1. Be sure to clear the error flag.
3. After setting RDRF to 1, if the RIE bit (receive-end interrupt enable) is set to 1 in
SCR, the SCI requests an RXI (receive-end) interrupt. If the ORER bit is set to 1 and
the RIE bit in SCR is set to 1, the SCI requests an ERI (receive-error) interrupt.
When clock output mode is selected, clock output stops when the RE bit is cleared to
0 or the ORER bit is set to 1. To prevent clock count errors, it is safest to receive one
dummy byte and generate an overrun error.
Figure 12-16 shows an example of SCI receive operation.
Serial clock
Serial data Bit 0 Bit 1 Bit 7 Bit 0 Bit 1 Bit 6 Bit 7
RXI
request
RDRF
ORER
RXI interrupt
handler reads
data in RDR and
clears RDRF to 0
RXI
request Overrun error,
ERI request
1 frame
Figure 12-16 Example of SCI Receive Operation
277
Transmitting and Receiving Serial Data Simultaneously: Follow the procedure in
figure
12-17 for transmitting and receiving serial data simultaneously. If clock output mode is
selected, output of the serial clock begins simultaneously with serial transmission.
Start
Read TDRE bit in SSR
TDRE = 1?
Write transmit data
in TDR and clear TDRE
bit to 0 in SSR
RDRF = 1?
Read ORER bit in SSR
End of
transmitting and receiv-
ing?
Clear TE and RE bits
to 0 in SCR
End
Error handling
1
2
3
No
Yes
Yes
Yes
No
Yes
4
1.
2.
3.
4.
5.
SCI initialization: the transmit data output function of
the TxD pin and receive data input function of the
RxD pin are selected, enabling simultaneous
transmitting and receiving.
SCI status check and transmit data write: read the
serial status register (SSR), check that the TDRE bit
is 1, then write transmit data in the transmit data
register (TDR) and clear TDRE to 0. Transition of the
TDRE bit from 0 to 1 can be reported by a TXI interrupt.
SCI status check and receive data read: read the
serial status register (SSR), check that the RDRF
bit is 1, then read receive data from the receive data
register (RDR) and clear RDRF to 0. Transition of
the RDRF bit from 0 to 1 can be reported by an RXI
interrupt.
Receive error handling: if a receive error occurs, read
the ORER bit in SSR then, after executing the
necessary error handling, clear ORER to 0. Neither
transmitting nor receiving can resume while ORER
remains set to 1.
To continue transmitting and receiving serial data:
read RDR and clear RDRF to 0 before the MSB
(bit 7) of the current frame is received. Also read the
TDRE bit and check that it is set to 1, indicating that
it is safe to write; then write data in TDR and clear
TDRE to 0 before the MSB (bit 7) of the current frame
is transmitted.
ORER = 1?
Read RDRF bit in SSR
5
No
No
Initialize
Read receive data
from RDR and clear
RDRF bit to 0 in SSR
Figure 12-17 Sample Flowchart for Serial Transmitting and Receiving
Note: In switching from transmitting or receiving to simultaneous transmitting and receiving,
clear both TE and RE to 0, then set both TE and RE to 1.
278
12.4 Interrupts
The SCI can request four types of interrupts: ERI, RXI, TXI, and TEI. Table 12-9 indicates the
source and priority of these interrupts. The interrupt sources can be enabled or disabled by the
TIE, RIE, and TEIE bits in the SCR. Independent signals are sent to the interrupt controller for
each interrupt source, except that the receive-error interrupt (ERI) is the logical OR of three
sources: overrun error, framing error, and parity error.
The TXI interrupt indicates that the next transmit data can be written. The TEI interrupt
indicates that the SCI has stopped transmitting data.
Table 12-9 SCI Interrupt Sources
Interrupt Description Priority
ERI Receive-error interrupt (ORER, FER, or PER) High
RXI Receive-end interrupt (RDRF)
TXI TDR-empty interrupt (TDRE)
TEI TSR-empty interrupt (TEND) Low
12.5 Application Notes
Application programmers should note the following features of the SCI.
(1) TDR Write: The TDRE bit in SSR is simply a flag that indicates that the TDR contents
have been transferred to TSR. The TDR contents can be rewritten regardless of the TDRE
value. If a new byte is written in TDR while the TDRE bit is 0, before the old TDR contents
have been moved into TSR, the old byte will be lost. Software should check that the TDRE
bit is set to 1 before writing to TDR.
(2) Multiple Receive Errors: Table 12-10 lists the values of flag bits in the SSR when
multiple receive errors occur, and indicates whether the RSR contents are transferred to
RDR.
279
Table 12-10 SSR Bit States and Data Transfer when Multiple Receive Errors Occur
SSR Bits RSR →→
Receive error RDRF ORER FER PER RDR*2
Overrun error 1*1100No
Framing error 0 0 1 0 Yes
Parity error 0 0 0 1 Yes
Overrun and framing errors 1*1110No
Overrun and parity errors 1*1101No
Framing and parity errors 0 0 1 1 Yes
Overrun, framing, and parity errors 1*1111No
Notes: 1. Set to 1 before the overrun error occurs.
2. Yes: The RSR contents are transferred to RDR.
No: The RSR contents are not transferred to RDR.
(3) Line Break Detection: When the RxD pin receives a continuous stream of 0’s in
asynchronous mode (line-break state), a framing error occurs because the SCI detects a 0
stop bit. The value H'00 is transferred from RSR to RDR. Software can detect the line-break
state as a framing error accompanied by H'00 data in RDR.
The SCI continues to receive data, so if the FER bit is cleared to 0 another framing error will
occur.
(4) Sampling Timing and Receive Margin in Asynchronous Mode: The serial clock used by
the SCI in asynchronous mode runs at 16 times the bit rate. The falling edge of the start bit is
detected by sampling the RxD input on the falling edge of this clock. After the start bit is
detected, each bit of receive data in the frame (including the start bit, parity bit, and stop bit
or bits) is sampled on the rising edge of the serial clock pulse at the center of the bit. See
figure 12-18.
It follows that the receive margin can be calculated as in equation (1).
When the absolute frequency deviation of the clock signal is 0 and the clock duty cycle is
0.5, data can theoretically be received with distortion up to the margin given by equation (2).
This is a theoretical limit, however. In practice, system designers should allow a margin of
20% to 30%.
280
12 4
0567893 2123456789 111 12 1314 15 1610 13 14 1516 1210 11 3 4 5
Basic
clock
Sync
sampling
Data
sampling
D0 D1
Receive
data Start bit
–7.5 pulses +7.5 pulses
Figure 12-18 Sampling Timing (Asynchronous Mode)
M = { (0.5 – 1/2N) – (D – 0.5)/N – (L – 0.5)F} × 100 [%] (1)
M: Receive margin
N: Ratio of basic clock to bit rate (N=16)
D: Duty factor of clock—ratio of high pulse width to low width (0.5 to 1.0)
L: Frame length (9 to 12)
F: Absolute clock frequency deviation
When D = 0.5 and F = 0
M = (0.5 –1/2 × 16) × 100 [%] = 46.875% (2)
281
Section 13 A/D Converter
13.1 Overview
The H8/3534 and H8/3522 include a 10-bit successive-approximations A/D converter with a
selection of up to eight analog input channels.
13.1.1 Features
A/D converter features are listed below.
• 10-bit resolution
• Eight input channels
• High-speed conversion
Conversion time: minimum 13.4 µs per channel (with 10-MHz system clock)
• Two conversion modes
Single mode: A/D conversion of one channel
Scan mode: continuous conversion on one to four channels
• Four 16-bit data registers
A/D conversion results are transferred for storage into data registers corresponding to the
channels.
• Sample-and-hold function
• A/D conversion can be externally triggered
• A/D interrupt requested at end of conversion
At the end of A/D conversion, an A/D end interrupt (ADI) can be requested.
282
13.1.2 Block Diagram
Figure 13-1 shows a block diagram of the A/D converter.
Module data bus
Bus interface
Internal
data bus
ADDRA
ADDRB
ADDRC
ADDRD
ADCSR
ADCR
Successive-
approximations register
10-bit D/A
AV
CC
Analog
multi-
plexer
AN
AN
AN
AN
AN
AN
AN
AN
0
1
2
3
4
5
6
7
Sample-and-
hold circuit
Comparator
+
–
Control circuit
ADTRG
øp/8
øp/16
ADI
interrupt
signal
Legend
ADCR:
ADCSR:
ADDRA:
ADDRB:
ADDRC:
ADDRD:
A/D control register
A/D control/status register
A/D data register A
A/D data register B
A/D data register C
A/D data register D
AV
SS
Figure 13-1 A/D Converter Block Diagram
283
13.1.3 Input Pins
Table 13-1 lists the A/D converter’s input pins. The eight analog input pins are divided into two
groups: group 0 (AN0 to AN3), and group 1 (AN4 to AN7). AVCC and AVSS are the power supply
for the analog circuits in the A/D converter.
Table 13-1 A/D Converter Pins
Pin Name Abbreviation I/O Function
Analog power supply pin AVCC Input Analog power supply
Analog ground pin AVSS Input Analog ground and reference voltage
Analog input pin 0 AN0Input Group 0 analog inputs
Analog input pin 1 AN1Input
Analog input pin 2 AN2Input
Analog input pin 3 AN3Input
Analog input pin 4 AN4Input Group 1 analog inputs
Analog input pin 5 AN5Input
Analog input pin 6 AN6Input
Analog input pin 7 AN7Input
A/D external trigger input pin
$'75*
Input External trigger input for starting A/D
conversion
284
13.1.4 Register Configuration
Table 13-2 summarizes the A/D converter’s registers.
Table 13-2 A/D Converter Registers
Name Abbreviation R/W Initial Value Address
A/D data register A (high) ADDRAH R H'00 H'FFE0
A/D data register A (low) ADDRAL R H'00 H'FFE1
A/D data register B (high) ADDRBH R H'00 H'FFE2
A/D data register B (low) ADDRBL R H'00 H'FFE3
A/D data register C (high) ADDRCH R H'00 H'FFE4
A/D data register C (low) ADDRCL R H'00 H'FFE5
A/D data register D (high) ADDRDH R H'00 H'FFE6
A/D data register D (low) ADDRDL R H'00 H'FFE7
A/D control/status register ADCSR R/W* H'00 H'FFE8
A/D control register ADCR R/W H'7F H'FFE9
Note: * Only 0 can be written in bit 7, to clear the flag.
285
13.2 Register Descriptions
13.2.1 A/D Data Registers A to D (ADDRA to ADDRD)
Bit
ADDRn
Initial value
Read/Write
(n = A~D)
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
The four A/D data registers (ADDRA to ADDRD) are 16-bit read-only registers that store the
results of A/D conversion.
An A/D conversion produces 10-bit data, which is transferred for storage into the A/D data
register corresponding to the selected channel. The upper 8 bits of the result are stored in the
upper byte of the A/D data register. The lower 2 bits are stored in the lower byte. Bits 5 to 0 of
an A/D data register are reserved bits that always read 0. Table 13-3 indicates the pairings of
analog input channels and A/D data registers.
The CPU can always read and write the A/D data registers. The upper byte can be read directly,
but the lower byte is read through a temporary register (TEMP). For details see section 13.3,
CPU Interface.
The A/D data registers are initialized to H'0000 by a reset and in standby mode.
Table 13-3 Analog Input Channels and A/D Data Registers
Analog Input Channel
Group 0 Group 1 A/D Data Register
AN0AN4ADDRA
AN1AN5ADDRB
AN2AN6ADDRC
AN3AN7ADDRD
286
13.2.2 A/D Control/Status Register (ADCSR)
Bit
Initial value
Read/Write
7
ADF
0
R/(W)
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
0
CH0
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
*
Note: Only 0 can be written, to clear the flag.
*
ADCSR is an 8-bit readable/writable register that selects the mode and controls the A/D
converter. ADCSR is initialized to H'00 by a reset and in standby mode.
Bit 7—A/D End Flag (ADF): Indicates the end of A/D conversion.
Bit 7
ADF Description
0 [Clearing condition] (Initial value)
Cleared by reading ADF while ADF = 1, then writing 0 in ADF
1[Setting conditions]
1.Single mode: A/D conversion ends
2.Scan mode: A/D conversion ends in all selected channels
Bit 6—A/D Interrupt Enable (ADIE): Enables or disables the interrupt (ADI) requested at the
end of A/D conversion.
Bit 6
ADIE Description
0 A/D end interrupt request (ADI) is disabled (Initial value)
1 A/D end interrupt request (ADI) is enabled
287
Bit 5—A/D Start (ADST): Starts or stops A/D conversion. The ADST bit remains set to 1
during A/D conversion. It can also be set to 1 by external trigger input at the
$'75*
pin.
Bit 5
ADST Description
0 A/D conversion is stopped (Initial value)
11. Single mode: A/D conversion starts; ADST is automatically cleared to 0 when
conversion ends
2. Scan mode: A/D conversion starts and continues, cycling among the selected
channels, until ADST is cleared to 0 by software, by a reset, or by a transition to
standby mode
Bit 4—Scan Mode (SCAN): Selects single mode or scan mode. For further information on
operation in these modes, see section 13.4, Operation. Clear the ADST bit to 0 before switching
the conversion mode.
Bit 4
SCAN Description
0 Single mode (Initial value)
1 Scan mode
Bit 3—Clock Select (CKS): Selects the A/D conversion time. When φP = φ/2, the conversion
time doubles. Clear the ADST bit to 0 before switching the conversion time.
Bit 3
CKS Description
0 Conversion time = 266 states (maximum) (when φP = φ) (Initial value)
1 Conversion time = 134 states (maximum) (when φP = φ)
288
Bits 2 to 0—Channel Select 2 to 0 (CH2 to CH0): These bits and the SCAN bit select the
analog input channels. Clear the ADST bit to 0 before changing the channel selection.
Group Selection Channel Selection Description
CH2 CH1 CH0 Single Mode Scan Mode
000 AN
0
(initial value) AN0
01 AN
1AN0, AN1
10 AN
2AN0 to AN2
11 AN
3AN0 to AN3
100 AN
4AN4
01 AN
5AN4, AN5
10 AN
6AN4 to AN6
11 AN
7AN4 to AN7
289
13.2.3 A/D Control Register (ADCR)
Bit
Initial value
Read/Write
7
TRGE
0
R/W
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
ADCR is an 8-bit readable/writable register that enables or disables external triggering of A/D
conversion. ADCR is initialized to H'7F by a reset and in standby mode.
Bit 7—Trigger Enable (TRGE): Enables or disables external triggering of A/D conversion.
Bit 7
TRGE Description
0 A/D conversion cannot be externally triggered (Initial value)
1 A/D conversion is enabled by the external trigger signal (
$'75*
) (A/D conversion
can also be enabled by software)
Bits 6 to 0—Reserved: These bits cannot be modified, and are always read as 1.
290
13.3 CPU Interface
ADDRA to ADDRD are 16-bit registers, but they are connected to the CPU by an 8-bit data bus.
Therefore, although the upper byte can be be accessed directly by the CPU, the lower byte is
read through an 8-bit temporary register (TEMP).
An A/D data register is read as follows. When the upper byte is read, the upper-byte value is
transferred directly to the CPU and the lower-byte value is transferred into TEMP. Next, when
the lower byte is read, the TEMP contents are transferred to the CPU.
When reading an A/D data register, always read the upper byte before the lower byte. It is
possible to read only the upper byte, but if only the lower byte is read, incorrect data may be
obtained.
291
Figure 13-2 shows the data flow for access to an A/D data register.
Upper-byte read
Bus interface Module data bus
CPU
(H'AA)
ADDRnH
(H'AA) ADDRnL
(H'40)
Lower-byte read
Bus interface Module data bus
CPU
(H'40)
ADDRnH
(H'AA) ADDRnL
(H'40)
TEMP
(H'40)
TEMP
(H'40)
(n = A to D)
(n = A to D)
Figure 13-2 A/D Data Register Access Operation (Reading H'AA40)
292
13.4 Operation
The A/D converter operates by successive approximations with 10-bit resolution. It has two
operating modes: single mode and scan mode.
13.4.1 Single Mode (SCAN = 0)
Single mode should be selected when only one A/D conversion on one channel is required. A/D
conversion starts when the ADST bit is set to 1 by software, or by external trigger input. The
ADST bit remains set to 1 during A/D conversion and is automatically cleared to 0 when
conversion ends.
When conversion ends the ADF bit is set to 1. If the ADIE bit is also set to 1, an ADI interrupt is
requested at this time. To clear the ADF flag to 0, first read ADCSR, then write 0 in ADF.
When the mode or analog input channel must be switched during analog conversion, to prevent
incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion. After
making the necessary changes, set the ADST bit to 1 to start A/D conversion again. The ADST
bit can be set at the same time as the mode or channel is changed.
Typical operations when channel 1 (AN1) is selected in single mode are described next. Figure
13-3 shows a timing diagram for this example.
1. Single mode is selected (SCAN = 0), input channel AN1 is selected (CH2 = CH1 = 0, CH0 =
1), the A/D interrupt is enabled (ADIE = 1), and A/D conversion is started (ADST = 1).
2. When A/D conversion is completed, the result is transferred into ADDRB. At the same time
the ADF flag is set to 1, the ADST bit is cleared to 0, and the A/D converter becomes idle.
3. Since ADF = 1 and ADIE = 1, an ADI interrupt is requested.
4. The A/D interrupt handling routine starts.
5. The routine reads ADCSR, then writes 0 in the ADF flag.
6. The routine reads and processes the conversion result (ADDRB).
7. Execution of the A/D interrupt handling routine ends. After that, if the ADST bit is set to 1,
A/D conversion starts again and steps 2 to 7 are repeated.
293
ADIE
ADST
ADF
State of channel 0
(AN )
Set
Set Set
Clear Clear
Idle
Idle
Idle
Idle
A/D conversion A/D conversion
Idle
Read conversion result
A/D conversion result Read conversion result
A/D conversion result
(2)
Note: Vertical arrows ( ) indicate instructions executed by software.
0
1
2
3
A/D conversion
starts
*
*
*
*
*
(2)
(1)
(1)
*
ADDRA
ADDRB
ADDRC
ADDRD
State of channel 1
(AN )
State of channel 2
(AN )
State of channel 3
(AN )
Idle
Figure 13-3 Example of A/D Converter Operation (Single Mode, Channel 1 Selected)
294
13.4.2 Scan Mode (SCAN = 1)
Scan mode is useful for monitoring analog inputs in a group of one or more channels. When the
ADST bit is set to 1 by software or external trigger input, A/D conversion starts on the first
channel in the group (AN0 when CH2 = 0, AN4 when CH2 = 1). When two or more channels are
selected, after conversion of the first channel ends, conversion of the second channel (AN1 or
AN5) starts immediately. A/D conversion continues cyclically on the selected channels until the
ADST bit is cleared to 0. The conversion results are transferred for storage into the A/D data
registers corresponding to the channels.
When the mode or analog input channel selection must be changed during analog conversion, to
prevent incorrect operation, first clear the ADST bit to 0 in ADCSR to halt A/D conversion.
After making the necessary changes, set the ADST bit to 1. A/D conversion will start again from
the first channel in the group. The ADST bit can be set at the same time as the mode or channel
selection is changed.
Typical operations when three channels in group 0 (AN0 to AN2) are selected in scan mode are
described next. Figure 13-4 shows a timing diagram for this example.
1. Scan mode is selected (SCAN = 1), scan group 0 is selected (CH2 = 0), analog input
channels AN0 to AN2 are selected (CH1 = 1, CH0 = 0), and A/D conversion is started (ADST
= 1).
2. When A/D conversion of the first channel (AN0) is completed, the result is transferred into
ADDRA. Next, conversion of the second channel (AN1) starts automatically.
3. Conversion proceeds in the same way through the third channel (AN2).
4. When conversion of all selected channels (AN0 to AN2) is completed, the ADF flag is set to 1
and conversion of the first channel (AN0) starts again. If the ADIE bit is set to 1, an ADI
interrupt is requested at this time.
5. Steps 2 to 4 are repeated as long as the ADST bit remains set to 1. When the ADST bit is
cleared to 0, A/D conversion stops. After that, if the ADST bit is set to 1, A/D conversion
starts again from the first channel (AN0).
295
ADST
ADF
State of channel 0
(AN )
0
1
2
3
Continuous A/D conversion
Set Clear
*1
Clear
*1
Idle
A/D conversion
Idle
Idle
Idle
A/D conversion Idle
A/D conversion Idle A/D conversion Idle
A/D conversion Idle
Idle
Transfer A/D conversion result A/D conversion result
A/D conversion result
A/D conversion result
1.
2.
A/D conversion time
Notes:
*2
(1)
(2)
(4)
(5)
*1
(3)
(1) (4)
(2)
(3)
ADDRA
ADDRB
ADDRC
ADDRD
State of channel 1
(AN )
State of channel 2
(AN )
State of channel 3
(AN )
Vertical arrows ( ) indicate instructions executed by software.
Data currently being converted is ignored.
Figure 13-4 Example of A/D Converter Operation (Scan Mode, Channels AN0 to AN2
Selected)
296
13.4.3 Input Sampling and A/D Conversion Time
The A/D converter has a built-in sample-and-hold circuit. The A/D converter samples the analog
input at a time tD after the ADST bit is set to 1, then starts conversion. Figure 13-5 shows the
A/D conversion timing. Table 13-4 indicates the A/D conversion time.
As indicated in figure 13-5, the A/D conversion time includes t D and the input sampling time.
The length of tD varies depending on the timing of the write access to ADCSR. The total
conversion time therefore varies within the ranges indicated in table 13-4.
In scan mode, the values given in table 13-4 apply to the first conversion. In the second and
subsequent conversions the conversion time is fixed at 256 states when CKS = 0 or 128 states
when CKS = 1. (when φP = φ)
297
ø
Address bus
Write signal
Input sampling
timing
ADF
(1)
(2)
t
D
t
SPL
t
CONV
Legend
(1):
(2):
t :
t :
t :
D
SPL
CONV
ADCSR write cycle
ADCSR address
Synchronization delay
Input sampling time
A/D conversion time
Figure 13-5 A/D Conversion Timing
Table 13-4 A/D Conversion Time (Single Mode)
CKS = 0 CKS = 1
Symbol Min Typ Max Min Typ Max
Synchronization delay tD10 — 17 6 — 9
Input sampling time* tSPL —80——40—
A/D conversion time* tCONV 259 — 266 131 — 134
Note: * Values in the table are numbers of states. Values are for φP = φ. When φ
P
= φ/2, the values
are doubled.
298
13.4.4 External Trigger Input Timing
A/D conversion can be externally triggered. When the TRGE bit is set to 1 in ADCR, external
trigger input is enabled at the
$'75*
pin. A high-to-low transition at the
$'75*
pin sets the
ADST bit to 1 in ADCSR, starting A/D conversion. Other operations, in both single and scan
modes, are the same as if the ADST bit had been set to 1 by software. Figure 13-6 shows the
timing.
ø
ADTRG
Internal trigger
signal
ADST
A/D conversion
Figure 13-6 External Trigger Input Timing
13.5 Interrupts
The A/D converter generates an interrupt (ADI) at the end of A/D conversion. The ADI interrupt
request can be enabled or disabled by the ADIE bit in ADCSR.
13.6 Usage Notes
When using the A/D converter, note the following points:
Analog Input Voltage Range: During A/D conversion, the voltages input to the analog input
pins ANn should be in the range AVSS ≤ ANn ≤ AVCC. (n = 0 to 7)
AVCC and AVSS Input Voltage: AVSS should have the following value: AVSS = VSS. If the A/D
converter is not used, the values should be AVCC = VCC and AVSS = VSS.
299
Section 14 RAM
14.1 Overview
The H8/3534 has 1 kbyte of on-chip static RAM, and the H8/3522 has 512 bytes. The RAM is
connected to the CPU by a 16-bit data bus. Both byte and word access to the on-chip RAM are
performed in two states, enabling rapid data transfer and instruction execution.
The on-chip RAM is assigned to addresses H'FB80 to H'FF7F in the address space of the
H8/3534 and addresses H'FD80 to H'FF7F in the address space of the H8/3522. The RAME bit
in the system control register (SYSCR) can enable or disable the on-chip RAM.
14.1.1 Block Diagram
Figure 14-1 is a block diagram of the on-chip RAM.
H'FF7E
Internal data bus (upper 8 bits)
H'FF7F
H'FB82
H'FB80
H'FB83
H'FB81
Even address Odd address
On-chip RAM
Internal data bus (lower 8 bits)
Figure 14-1 Block Diagram of On-Chip RAM (H8/3534)
300
14.1.2 RAM Enable Bit (RAME) in System Control Register (SYSCR)
Bit
[H8/3534]
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
2
NMIEG
0
R/W
1
(HIE)
0
R/W
0
RAME
1
R/W
Bit
[H8/3522]
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
2
NMIEG
0
R/W
1
—
1
—
0
RAME
1
R/W
The on-chip RAM is enabled or disabled by the RAME bit in SYSCR. See section 3.2, System
Control Register, for the other SYSCR bits.
Bit 0—RAM Enable (RAME): This bit enables or disables the on-chip RAM. The RAME bit
is initialized to 1 on the rising edge of the
5(6
signal. The RAME bit is not initialized in
software standby mode.
Bit 0
RAME Description
0 On-chip RAM is disabled.
1 On-chip RAM is enabled. (Initial value)
14.2 Operation
14.2.1 Expanded Modes (Modes 1 and 2)
If the RAME bit is set to 1, accesses to addresses H'FB80 to H'FF7F in the H8/3534 and
addresses H'FD80 to H'FF7F in the H8/3522 are directed to the on-chip RAM.
If the RAME bit is cleared to 0, accesses to these addresses are directed to the external data bus.
14.2.2 Single-Chip Mode (Mode 3)
If the RAME bit is set to 1, accesses to addresses H'FB80 to H'FF7F in the H8/3534 and
addresses H'FD80 to H'FF7F in the H8/3522 are directed to the on-chip RAM.
If the RAME bit is cleared to 0, the on-chip RAM data cannot be accessed. Attempted write
access has no effect. Attempted read access always results in H'FF data being read.
301
Section 15 ROM
15.1 Overview
The size of the on-chip ROM is 32 kbytes in the H8/3534, and 16 kbytes in the H8/3522. The
on-chip ROM is connected to the CPU via a 16-bit data bus. Both byte data and word data are
accessed in two states, enabling rapid data transfer.
The on-chip ROM is enabled or disabled depending on the inputs at the mode pins (MD1 and
MD0). See table 15-1.
Table 15-1 On-Chip ROM Usage in Each MCU Operating Mode
Mode Pins
Mode MD1MD0On-chip ROM
Mode 1 (expanded mode) 0 1 Disabled (external addresses)
Mode 2 (expanded mode) 1 0 Enabled
Mode 3 (single-chip mode) 1 1 Enabled
302
15.1.1 Block Diagram
Figure 15-1 is a block diagram of the on-chip ROM.
H'7FFE
Internal data bus (upper 8 bits)
H'7FFF
H'0002
H'0000
H'0003
H'0001
Even address Odd address
On-chip ROM
Internal data bus (lower 8 bits)
Figure 15-1 Block Diagram of On-Chip ROM (H8/3534 Single-Chip Mode)
303
Section 16 Power-Down State
16.1 Overview
The H8/3534 and H8/3522 have a sleep mode that greatly reduces power consumption by
stopping CPU functions. The following two standby modes can also be set in addition to sleep
mode, but since a guaranteed value is not set for power consumption in the standby modes, use
of these modes is not recommended.
(1) Sleep mode
(2) Software standby mode
(3) Hardware standby mode
Table 16-1 lists the conditions for entering and leaving the power-down modes. It also indicates
the status of the CPU, on-chip supporting modules, etc. in each power-down mode.
Table 16-1 Power-Down State
State
Mode Entering
Procedure Clock CPU CPU
Reg’s. Sup.
Mod. RAM I/O
Ports Exiting Methods
Sleep mode Execute SLEEP
instruction Active Halted Held Active Held Held • Interrupt
•
5(6
•
67%<
Software
standby
mode
Set SSBY bit in
SYSCR 1, then
execute SLEEP
instruction
Halted Halted Held Halted
and
initialized
Held Held • NMI IRQ0 to
IRQ2 IRQ6
(include.
KEYIN0 to
KEYIN7)
• RES
• STBY
Hardware
standby
mode
Set
67%<
pin to low
level Halted Halted Undeter-
mined Halted
and
initialized
Held High
impe-
dance
state
•
67%<
and
5(6
Notes: 1 . SYSCR: System control register
2. SSBY: Software standby bit
304
16.1.1 System Control Register (SYSCR)
Four of the eight bits in the system control register (SYSCR) control the power-down state.
These are bit 7 (SSBY) and bits 6 to 4 (STS2 to STS0). See table 16-2.
Table 16-2 System Control Register
Name Abbreviation R/W Address
System control register SYSCR R/W H'FFC4
Bit
[H8/3534]
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
(HIE)
0
R/W
Bit
[H8/3522]
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
—
1
—
Bit 7—Software Standby (SSBY): This bit enables or disables the transition to software
standby mode.
On recovery from the software standby mode by an external interrupt, SSBY remains set to 1.
To clear this bit, software must write a 0.
Bit 7
SSBY Description
0 The SLEEP instruction causes a transition to sleep mode. (Initial value)
1 The SLEEP instruction causes a transition to software standby mode.
305
Bits 6 to 4—Standby Timer Select 2 to 0 (STS2 to STS0): These bits select the clock settling
time when the chip recovers from software standby mode by an external interrupt. During the
selected time, the clock oscillator runs but the CPU and on-chip supporting modules remain in
standby. Set bits STS2 to STS0 according to the clock frequency to obtain a settling time of at
least 8 ms. See table 16-3.
Bit 6
STS2 Bit 5
STS1 Bit 4
STS0 Description
0 0 0 Settling time = 8,192 states (Initial value)
0 0 1 Settling time = 16,384 states
0 1 0 Settling time = 32,768 states
0 1 1 Settling time = 65,536 states
1 0 — Settling time = 131,072 states
1 1 — Unused
306
16.2 Sleep Mode
16.2.1 Transition to Sleep Mode
When the SSBY bit in the system control register is cleared to 0, execution of the SLEEP
instruction causes a transition from the program execution state to sleep mode. After executing
the SLEEP instruction, the CPU halts, but the contents of its internal registers remain
unchanged. The on-chip supporting modules continue to operate normally.
16.2.2 Exit from Sleep Mode
The chip exits sleep mode when it receives an internal or external interrupt request, or a low
input at the
5(6
or
67%<
pin.
(1) Exit by Interrupt: An interrupt releases sleep mode and starts the CPU’s interrupt-handling
sequence.
If an interrupt from an on-chip supporting module is disabled by the corresponding
enable/disable bit in the module’s control register, the interrupt cannot be requested, so it
cannot wake the chip up. Similarly, the CPU cannot be awakened by an interrupt other than
NMI if the I (interrupt mask) bit is set when the SLEEP instruction is executed.
(2) Exit by
5(6
5(6
pin: When the
5(6
pin goes low, the chip exits from sleep mode to the reset
state.
(3) Exit by
67%<
67%<
pin: When the
67%<
pin goes low, the chip exits from sleep mode to
hardware standby mode.
16.3 Software Standby Mode
16.3.1 Transition to Software Standby Mode
To enter software standby mode, set the standby bit (SSBY) in the system control register
(SYSCR) to 1, then execute the SLEEP instruction.
In software standby mode, the system clock stops and chip functions halt, including both CPU
functions and the functions of the on-chip supporting modules. The on-chip supporting modules
and their registers are reset to their initial states, but as long as a minimum necessary voltage
supply is maintained, the contents of the CPU registers and on-chip RAM remain unchanged.
I/O ports retain their states.
307
16.3.2 Exit from Software Standby Mode
The chip can be brought out of software standby mode by an
5(6
input,
67%<
input, or external
interrupt input at the
10,
pin,
,54
0 to
,54
2 pins, or
,54
6 pin* (including
.(<,1
0 to
.(<,1
7).
(1) Exit by Interrupt: When an NMI, IRQ0, IRQ1, IRQ2, or IRQ6* interrupt request signal is
input, the clock oscillator begins operating. After the waiting time set in bits STS2 to STS0
of SYSCR, a stable clock is supplied to the entire chip, software standby mode is released,
and interrupt exception-handling begins. IRQ3, IRQ4, IRQ5, and IRQ7 interrupts should be
disabled before the transition to software standby (clear IRQ3E, IRQ4E, IRQ5E, and IRQ7E
to 0)*.
Note: * Applies to the H8/3534 only.
(2) Exit by
5(6
5(6
Pin: When the
5(6
input goes low, the clock oscillator begins operating.
When
5(6
is brought to the high level (after allowing time for the clock oscillator to settle),
the CPU starts reset exception handling. Be sure to hold
5(6
low long enough for clock
oscillation to stabilize.
(3) Exit by
67%<
67%<
Pin: When the
67%<
input goes low, the chip exits from software standby
mode to hardware standby mode.
16.3.3 Clock Settling Time for Exit from Software Standby Mode
Set bits STS2 to STS0 in SYSCR as follows:
• Crystal oscillator
Set STS2 to STS0 for a settling time of at least 8 ms. Table 16-3 lists the settling times
selected by these bits at several clock frequencies.
• External clock
The STS bits can be set to any value.
Table 16-3 Times Set by Standby Timer Select Bits (Unit: ms)
System Clock Frequency (MHz)
STS2 STS1 STS0 Settling
Time(States) 10 8 6 4
0 0 0 8,192 0.8 1.0 1.3 2.0
0 0 1 16,384 1.6 2.0 2.7 4.1
0 1 0 32,768 3.3 4.1 5.5 8.2
0 1 1 65,536 6.6 8.2 10.9 16.4
1 0 — 131,072 13.1 16.4 21.8 32.8
Note: Recommended values are printed in boldface.
308
16.3.4 Sample Application of Software Standby Mode
In this example the chip enters the software standby mode when
10,
goes low and exits when
10,
goes high, as shown in figure 16-1.
The NMI edge bit (NMIEG) in the system control register is originally cleared to 0, selecting the
falling edge. When
10,
goes low, the
10,
interrupt handling routine sets NMIEG to 1, sets
SSBY to 1 (selecting the rising edge), then executes the SLEEP instruction. The chip enters
software standby mode. It recovers from software standby mode on the next rising edge of
10,
.
ø
NMI
NMIEG
SSBY
NMI interrupt
handler
NMIEG = 1
SSBY = 1
Software standby
mode (power-
down state)
Settling time
SLEEP instruction
NMI interrupt
handler
Clock
oscillator
Figure 16-1 NMI Timing in Software Standby Mode (Application Example)
16.3.5 Application Notes
The I/O ports retain their present states in software standby mode. Thus, current dissipation
caused by the output current is not reduced.
309
16.4 Hardware Standby Mode
16.4.1 Transition to Hardware Standby Mode
Regardless of its current state, the chip enters hardware standby mode whenever the
67%<
pin
goes low.
Hardware standby mode halts the CPU, stopping all the functions of the on-chip supporting
modules, and placing I/O ports in the high-impedance state. The registers of the on-chip
supporting modules are reset to their initial values. Only the on-chip RAM is held unchanged,
provided the minimum necessary voltage supply is maintained.
Notes: 1. The RAME bit in the system control register should be cleared to 0 before the
67%<
pin goes low.
2. Do not change the inputs at the mode pins (MD1, MD0) during hardware standby
mode.
16.4.2 Recovery from Hardware Standby Mode
Recovery from the hardware standby mode requires inputs at both the
67%<
and
5(6
pins.
When the
67%<
pin goes high, the clock oscillator begins running. The
5(6
pin should be low
at this time and should be held low long enough for the clock to stabilize. When the
5(6
pin
changes from low to high, the reset sequence is executed and the chip returns to the program
execution state.
310
16.4.3 Timing Relationships in Hardware Standby Mode
Figure 16-2 shows the timing relationships in hardware standby mode.
In the sequence shown, first
5(6
goes low, then
67%<
goes low, at which point the chip enters
hardware standby mode. To recover, first
67%<
goes high, then after the clock settling time,
5(6
goes high.
RES
STBY
Clock pulse
generator
Clock settling
time
Restart
Figure 16-2 Hardware Standby Mode Timing
311
Section 17 Electrical Specifications
17.1 Absolute Maximum Ratings
Table 17-1 lists the absolute maximum ratings.
Table 17-1 Absolute Maximum Ratings
Item Symbol Rating Unit
Supply voltage VCC –0.3 to +7.0 V
Input voltage Pins other than Ports7 Vin –0.3 to VCC + 0.3 V
Port 7 Vin –0.3 to AVCC + 0.3 V
Analog supply voltage AVCC –0.3 to +7.0 V
Analog input voltage VAN –0.3 to AVCC + 0.3 V
Operating temperature Topr –20 to +75 °C
Storage temperature Tstg –55 to +125 °C
Note: Exceeding the absolute maximum ratings shown in table 17-1 can permanently destroy
the chip.
312
17.2 Electrical Characteristics
17.2.1 DC Characteristics
Table 17-2 lists the DC characteristics and Table 17-3 gives the allowable current output values.
Table 17-2 (a) H8/3534 DC Characteristics – Preliminary –
Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%*1, VSS = AVSS = 0 V, Ta = –20°C to +75°C
Item Symbol Min Typ Max Unit Test
Conditions
Schmitt
trigger input
voltage
P67 to P60*3, (1) VT–1.0 — — V
,54
2 to
,54
0*4, VT+ — — VCC × 0.7
,54
7 to
,54
3VT+ – VT– 0.4 — —
Input high
voltage
5(667%<
, (2)
MD1, MD0,VIH VCC – 0.7 — VCC + 0.3 V
EXTAL,
10,
P77 to P702.0 — AVCC + 0.3
All input pins other
than (1) and (2)
above
2.0 — VCC + 0.3
Input low
voltage
5(6
,
67%<
, (3)
MD1, MD0
VIL –0.3 — 0.5 V
All input pins other
than (1) and (3)
above
–0.3 — 0.8
Output high
voltage All output pins VOH VCC – 0.5 — — V IOH = –200 µA
3.5 — — IOH = –1.0mA
313
Table 17-2 (a) H8/3534 DC Characteristics (cont) – Preliminary –
Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%*1, VSS = AVSS = 0 V, Ta = –20°C to +75°C
Item Symbol Min Typ Max Unit Test Conditions
Output low
voltage All output pins VOL — — 0.4 V IOL = 1.6 mA
P17 to P10, — — 1.0 IOL = 10.0 mA
P27 to P20
Input leakage
current
5(6
,
67%<
| Iin | — — 10.0 µA Vin = 0.5 V to
10,
, MD1, MD0— — 1.0 VCC – 0.5 V
P77 to P70— — 1.0 Vin = 0.5 V to
AVCC – 0.5 V
Leakage
current in
three-state
(off state)
Ports 1 to 6, 8, 9, | I TSI | — — 1.0 µA Vin = 0.5 V to
VCC – 0.5 V
Input pull-up
MOS current Ports 1 to 3 –IP30 — 250 µA Vin = 0 V
Port 6 60 — 500
Input capaci-
tance
5(6
,
67%<
(4) Cin — — 60 pF Vin = 0 V,
10,
, MD1— — 50 f = 1 MHz,
P97, P86— — 20 Ta = 25°C
All input pins other
than (4) ——15
Current
dissipation*2 Normal operation ICC — 23 40 mA f = 10 MHz
Sleep mode — 15 25
314
Table 17-2 (a) H8/3534 DC Characteristics (cont) – Preliminary –
Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%*1, VSS = AVSS = 0 V, Ta = –20°C to +75°C
Item Symbol Min Typ Max Unit Test
Conditions
Analog supply
current During A/D
conversion AICC — 2.0 5.0 mA
Analog supply voltage*1 AVCC 4.5 — 5.5 V During
operation
2.0 — 5.5 While idle or
when not in
use
Notes: 1. Even when the A/D converter is not used, connect AVCC to power supply VCC and keep
the applied voltage between 2.0 V and 5.5 V.
2. Current dissipation values assume that VIH min = VCC – 0.5 V, VIL max = 0.5 V, all output pins
are in the no-load state, and all input pull-up transistors are off.
3. P67 to P60 include supporting module inputs multiplexed with them.
4. IRQ2 includes
$'75*
multiplexed with it.
315
Table 17-2 (b) H8/3522 DC Characteristics – Preliminary –
Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%*1, VSS = AVSS = 0 V, Ta = –20°C to +75°C
Item Symbol Min Typ Max Unit Test
Conditions
Schmitt
trigger
input
voltage
P67 to P60*3, (1) VT–1.0 — — V
,54
2 to
,54
0*4, VT+ — — VCC × 0.7
VT+ – VT– 0.4 — —
Input
high
voltage
5(6
,
67%<
, (2)
MD1, MD0,
EXTAL,
10,
VIH VCC – 0.7 — VCC + 0.3 V
P77 to P702.0 — AVCC + 0.3
All input pins other
than (1) and (2)
above
2.0 — VCC + 0.3
Input low
voltage
5(6
,
67%<
, (3)
MD1, MD0
VIL –0.3 — 0.5 V
All input pins other
than (1) and (3)
above
–0.3 — 0.8
Output
high
voltage
All output pins VOH VCC – 0.5 — — V IOH = –200 µA
3.5 — — IOH = –1.0mA
316
Table 17-2 (b) H8/3522 DC Characteristics (cont) – Preliminary –
Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%*1, VSS = AVSS = 0 V, Ta = –20°C to +75°C
Item Symbol Min Typ Max Unit Test
Conditions
Output low voltage All output pins VOL — — 0.4 V IOL = 1.6 mA
P17 to P10, — — 1.0 IOL = 10.0 mA
P27 to P20
Input leakage
current
5(6
,
67%<
| Iin | — — 10.0 µA Vin = 0.5 V to
10,
, MD1, MD0— — 1.0 VCC – 0.5 V
P77 to P70— — 1.0 Vin = 0.5 V to
AVCC – 0.5 V
Leakage current in
three-state (off
state)
Ports 1 to 6 | ITSI | — — 1.0 µA Vin = 0.5 V to
VCC – 0.5 V
Input pull-up MOS
current Ports 1 to 3 –IP30 — 250 µA Vin = 0 V
Input capacitance
5(6
,
67%<
(4) Cin — — 60 pF Vin = 0 V,
f = 1 MHz,
10,
, MD1— — 30 Ta = 25°C
All input pins other
than (4) ——15
Current
dissipation*2 Normal operation ICC — 23 40 mA f = 10 MHz
Sleep mode — 15 25
Analog supply
current During A/D
conversion AICC — 2.0 5.0 mA
Analog supply
voltage*1 AVCC 4.5 — 5.5 V During
operation
2.0 — 5.5 While idle or
when not in
use
Notes: 1. Even when the A/D converter is not used, connect AVCC to power supply VCC and keep
the applied voltage between 2.0 V and 5.5 V.
2. Current dissipation values assume that VIH min = VCC – 0.5 V, VIL max = 0.5 V, all output pins
are in the no-load state, and all input pull-up transistors are off.
3. P67 to P60 include supporting module inputs multiplexed with them.
4.
,54
2 includes
$'75*
multiplexed with it.
317
Table 17-3 Allowable Output Current Values – Preliminary –
Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0 V, Ta = –20°C to +75°C
Item Symbol Min Typ Max Unit
Allowable output low Ports 1 and 2 IOL —— 10 mA
current (per pin) Other output pins — — 2
Allowable output low Ports 1 and 2, total ΣIOL —— 80
current (total) Total of all output — — 120
Allowable output high
current (per pin) All output pins –IOH —— 2
Allowable output high
current (total) Total of all output Σ–IOH —— 40
Note: To avoid degrading the reliability of the chip, be careful not to exceed the output current
values in tables 17-3. In particular, when driving a darlington transistor pair or LED directly,
be sure to insert a current-limiting resistor in the output path. See figures 17-1 and 17-2.
318
H8/3534 or
H8/3522
Port 2 kΩ
Darlington
transistor
Figure 17-1 Example of Circuit for Driving a Darlington Transistor
H8/3534 or
H8/3522
Ports 1 or 2
LED
600Ω
V
CC
Figure 17-2 Example of Circuit for Driving an LED
319
17.2.2 AC Characteristics
The AC characteristics are listed in following tables. Bus timing parameters are given in table
17-4, control signal timing parameters in table 17-5, timing parameters of the on-chip supporting
modules in table 17-6, and external clock output delay timing parameters in table 17-7.
Table 17-4 Bus Timing – Preliminary –
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, φ = 4.0 MHz to maximum operating frequency,
Ta = –20°C to +75°C
10 MHz
Item Symbol Min Max Unit Test
Conditions
Clock cycle time tcyc 100 250 ns Fig. 17-4
Clock pulse width low tCL 35 –
Clock pulse width high tCH 35 –
Clock rise time tCr –15
Clock fall time tCf –15
Address delay time tAD –50
Address hold time tAH 20 –
Address strobe delay time tASD –40
Write strobe delay time tWSD –50
Strobe delay time tSD –50
Write strobe pulse width* tWSW 120 –
Address setup time 1* tAS1 15 –
Address setup time 2* tAS2 65 –
Read data setup time tRDS 35 –
Read data hold time* tRDH 0–
Read data access time* tACC – 170
Write data delay time tWDD –75
Write data setup time tWDS 5–
Write data hold time tWDH 20 –
Wait setup time tWTS 40 – Fig. 17-5
Wait hold time tWTH 10 –
Note: * Values at maximum operating frequency
320
Table 17-5 Control Signal Timing – Preliminary –
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, φ = 4.0 MHz to maximum operating frequency,
Ta = –20°C to +75°C
10 MHz
Item Symbol Min Max Unit Test
Conditions
5(6
setup time tRESS 200 – ns Fig. 17-6
5(6
pulse width tRESW 10 – tcyc
10,
setup time
(
10,
,
,54
0 to
,54
7)tNMIS 150 – ns Fig. 17-7
10,
hold time
(
10,
,
,54
0 to
,54
7)tNMIH 10 –
Interrupt pulse width for
recovery from software
standby mode
(
10,
,
,54
0 to
,54
2,
,54
6)
tNMIW 200 –
Crystal oscillator settling
time (reset) tOSC1 20 – ms Fig. 17-8
Crystal oscillator settling
time (software standby) tOSC2 8 – Fig. 17-9
• Measurement Conditions for AC Characteristics
C R
H
5 V
R
L
LSI
output pin C =
Input/output timing measurement levels
Low: 0.8 V
High: 2.0 V
R
L
=
R
H
=
90 pF: Ports 1–4, 6, 9
30 pF: Ports 5, 8
2.4 kΩ
12 kΩ
Figure 17-3 Output Load Circuit
321
Table 17-6 Timing Conditions of On-Chip Supporting Modules – Preliminary –
Conditions: VCC = 5.0 V ±10%, VSS = 0 V, φ = 4.0 MHz to maximum operating frequency,
Ta = –20°C to +75°C
10 MHz
Item Symbol Min Max Unit Test
Conditions
FRT Timer output delay time tFTOD – 100 ns Fig. 17-10
Timer input setup time tFTIS 50 –
Timer clock input setup time tFTCS 50 – Fig. 17-11
Timer clock pulse width tFTCWH
tFTCWL
1.5 – tcyc
TMR Timer output delay time tTMOD – 100 ns Fig. 17-12
Timer reset input setup time tTMRS 50 – Fig. 17-14
Timer clock input setup time tTMCS 50 – Fig. 17-13
Timer clock pulse width
(single edge) tTMCWH 1.5 – tcyc
Timer clock pulse width
(both edges) tTMCWL 2.5 –
PWM Timer output delay time
[H8/3534] tPWOD – 100 ns Fig. 17-15
SCI Input clock cycle (Async) tScyc 4–t
cyc Fig. 17-16
(Sync) tScyc 6–
Transmit data delay time
(Sync) tTXD – 100 ns Fig. 17-16
Receive data setup time
(Sync) tRXS 100 –
Receive data hold time
(Sync) tRXH 100 –
Input clock pulse width tSCKW 0.4 0.6 tScyc Fig. 17-17
Ports Output data delay time tPWD – 100 ns Fig. 17-18
Input data setup time tPRS 50 –
Input data hold time tPRH 50 –
322
Table 17-7 External clock output delay Timing – Preliminary –
Conditions: VCC = 4.5 V to 5.5 V, AVCC = 4.5 V to 5.5 V, VSS = AVSS = 0V,
Ta = –20°C to +75°C
Item Symbol Min Max Unit Notes
External clock output delay time tDEXT* 500 — µs Fig. 17-19
Note: * tDEXT includes to
5(6
pulse width tRESW (10 tcyc).
17.2.3 A/D Converter Characteristics
Table 17-8 lists the characteristics of the on-chip A/D converter.
Table 17-8 A/D Converter Characteristics – Preliminary –
Conditions: VCC = 5.0 V ±10%, AVCC = 5.0 V ±10%, VSS = AVSS = 0 V, φ = 4.0 MHz to
maximum operating frequency, Ta = –20°C to +75°C
10 MHz
Item Min Typ Max Unit
Resolution 10 10 10 Bits
Conversion (single mode)* — — 13.4 µs
Analog input capacitance — — 20 pF
Allowable signal source impedance — — 10 kΩ
Nonlinearity error — — ±3.0 LSB
Offset error — — ±3.5
Full-scale error — — ±3.5
Quantizing error — — ±0.5
Absolute accuracy — — ±4.0
Note: * Values at maximum operating frequency
323
17.3 MCU Operational Timing
This section provides the following timing charts:
17.3.1 Bus Timing Figures 17-4 and 17-5
17.3.2 Control Signal Timing Figures 17-6 to 17-9
17.3.3 16-Bit Free-Running Timer Timing Figures 17-10 and 17-11
17.3.4 8-Bit Timer Timing Figures 17-12 to 17-14
17.3.5 PWM Timer Timing Figure 17-15
17.3.6 SCI Timing Figures 17-16 and 17-17
17.3.7 I/O Port Timing Figure 17-18
17.3.8 External Clock Output Timing Figure 17-19
324
17.3.1 Bus Timing
(1) Basic Bus Cycle (without Wait States) in Expanded Modes
T
2
T
1
t
cyc
T
3
t
CH
t
CL
t
AD
t
Cr
t
ASD
t
ACC
t
RDS
t
WSD
t
AS2
t
WDD
t
WDS
t
WDH
t
AH
t
WSW
t
RDH
t
AH
t
SD
ø
A
15
to A
0
WR
D
7
to D
0
(read)
D
7
to D
0
(write)
AS, RD
t
Cf
t
AS1
t
SD
Figure 17-4 Basic Bus Cycle (without Wait States) in Expanded Modes
325
(2) Basic Bus Cycle (with 1 Wait State) in Expanded Modes
ø
AS, RD
WR
WAIT
D
7
to D
0
(read)
A
15
to A
0
D
7
to D
0
(write)
T
1
T
2
T
W
T
3
t
WTS
t
WTH
t
WTS
t
WTH
Figure 17-5 Basic Bus Cycle (with 1 Wait State) in Expanded Modes (Modes 1 and 2)
17.3.2 Control Signal Timing
(1) Reset Input Timing
ø
RES
t
RESS
t
RESS
t
RESW
Figure 17-6 Reset Input Timing
326
(2) Interrupt Input Timing
ø
IRQ
L
NMI
IRQ
i
t
NMIS
t
NMIH
t
NMIS
NMI
IRQ
E
t
NMIW
Note: i = 0 to 7; IRQ
E
: IRQ
i
when edge-sensed; IRQ
L
: IRQ
i
when level-sensed
Figure 17-7 Interrupt Input Timing
(3) Clock Settling Timing
ø
V
CC
RES
STBY t
OSC1
t
OSC1
Figure 17-8 Clock Settling Timing
327
(4) Clock Settling Timing for Recovery from Software Standby Mode
ø
NMI
IRQ
i
(i = 0, 1, 2, 6) t
OSC2
Figure 17-9 Clock Settling Timing for Recovery from Software Standby Mode
17.3.3 16-Bit Free-Running Timer Timing
(1) Free-Running Timer Input/Output Timing
ø
Compare-match
FTIA, FTIB,
FTIC, FTID
FTOA , FTOB
Free-running
timer counter t
FTOD
t
FTIS
Figure 17-10 Free-Running Timer Input/Output Timing
328
(2) External Clock Input Timing for Free-Running Timer
ø
FTCI
t
FTCS
t
FTCWL
t
FTCWH
Figure 17-11 External Clock Input Timing for Free-Running Timer
17.3.4 8-Bit Timer Timing
(1) 8-Bit Timer Output Timing
ø
Timer
counter Compare-match
TMO
0
,
TMO
1
t
TMOD
Figure 17-12 8-Bit Timer Output Timing
(2) 8-Bit Timer Clock Input Timing
ø
t
TMCS
t
TMCS
t
TMCWL
t
TMCWH
TMCI
0
,
TMCI
1
Figure 17-13 8-Bit Timer Clock Input Timing
329
(3) 8-Bit Timer Reset Input Timing
NH'00
ø
Timer
counter
tTMRS
TMRI0,
TMRI1
Figure 17-14 8-Bit Timer Reset Input Timing
17.3.5 Pulse Width Modulation Timer Timing [H8/3534]
Compare-match
tPWOD
ø
Timer
counter
PW0, PW1
Figure 17-15 PWM Timer Output Timing
330
17.3.6 Serial Communication Interface Timing
(1) SCI Input/Output Timing
tScyc
tTXD
tRXS tRXH
Serial clock
(SCK0, SCK1)
Transmit
data
(TxD0, TxD1)
Receive
data
(RxD0, RxD1)
Figure 17-16 SCI Input/Output Timing (Synchronous Mode)
(2) SCI Input Clock Timing
t
SCKW
t
Scyc
SCK
0
, SCK
1
Figure 17-17 SCI Input Clock Timing
331
17.3.7 I/O Port Timing
Note: * Except P9
6
and P7
7
to P7
0
[H8/3534]; except P7
7
to P7
0
and P4
6
[H8/3522].
t
PRS
t
PRH
t
PWD
Port 1 to
port 9 (input)
ø
Port 1* to
port 9 (output)
T
1
T
2
T
3
Figure 17-18 I/O Port Input/Output Timing
17.3.8 External Clock Output Timing
V
cc
STBY
4.5V
V
IH
EXTAL
RES
ø
t
DEXT
*
(internal or external)
Note: * t
DEXT
includes an RES pulse width (t
RESW
) of 10 t
cyc
.
Figure 17-19 External clock output delay Timing
332
333
Appendix A CPU Instruction Set
A.1 Instruction Set List
Operation Notation
Rd8/16 General register (destination) (8 or 16 bits)
Rs8/16 General register (source) (8 or 16 bits)
Rn8/16 General register (8 or 16 bits)
CCR Condition code register
N N (negative) flag in CCR
Z Z (zero) flag in CCR
V V (overflow) flag in CCR
C C (carry) flag in CCR
PC Program counter
SP Stack pointer
#xx:3/8/16 Immediate data (3, 8, or 16 bits)
d:8/16 Displacement (8 or 16 bits)
@aa:8/16 Absolute address (8 or 16 bits)
+ Addition
– Subtraction
×Multiplication
÷Division
∧Logical AND
∨Logical OR
⊕Exclusive logical OR
→Move
¬NOT (logical complement)
Condition Code Notation
∆Modified according to the instruction result
* Undetermined (unpredictable)
0 Always cleared to 0
— Not affected by the instruction result
334
Table A-1 Instruction Set
Addressing Mode/
Instruction Length
Mnemonic
Operand Size
Operation
#xx: 8/16
Rn
@Rn
@(d:16,Rn)
@–Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
Implied
Condition Code
No. of States
I HNZVC
MOV.B #xx:8, Rd B #xx:8 → Rd8 2 — — ∆∆0—2
MOV.B Rs, Rd B Rs8 → Rd8 2 — — ∆∆0—2
MOV.B @Rs, Rd B @Rs16 → Rd8 2 — — ∆∆0—4
MOV.B @(d:16, Rs), Rd B @(d:16, Rs16)→ Rd8 4 — — ∆∆0—6
MOV.B @Rs+, Rd B @Rs16 → Rd8
Rs16+1 → Rs16
2 ——∆∆0—6
MOV.B @aa:8, Rd B @aa:8 → Rd8 2 — — ∆∆0—4
MOV.B @aa:16, Rd B @aa:16 → Rd8 4 — — ∆∆0—6
MOV.B Rs, @Rd B Rs8 → @Rd16 2 — — ∆∆0—4
MOV.B Rs, @(d:16, Rd) B Rs8 → @(d:16, Rd16) 4 — — ∆∆0—6
MOV.B Rs, @–Rd B Rd16–1 → Rd16
Rs8 → @Rd16
2 ——∆∆0—6
MOV.B Rs, @aa:8 B Rs8 → @aa:8 2 — — ∆∆0—4
MOV.B Rs, @aa:16 B Rs8 → @aa:16 4 — — ∆∆0—6
MOV.W #xx:16, Rd W #xx:16 → Rd16 4 — — ∆∆0—4
MOV.W Rs, Rd W Rs16 → Rd16 2 — — ∆∆0—2
MOV.W @Rs, Rd W @Rs16 → Rd16 2 — — ∆∆0—4
MOV.W @(d:16, Rs), Rd W @(d:16, Rs16) → Rd16 4 — — ∆∆0—6
MOV.W @Rs+, Rd W @Rs16 → Rd16
Rs16+2 → Rs16
2 ——∆∆0—6
MOV.W @aa:16, Rd W @aa:16 → Rd16 4 — — ∆∆0—6
MOV.W Rs, @Rd W Rs16 → @Rd16 2 — — ∆∆0—4
MOV.W Rs, @(d:16, Rd) W Rs16 → @(d:16, Rd16) 4 — — ∆∆0—6
MOV.W Rs, @–Rd W Rd16–2 → Rd16
Rs16 → @Rd16
2 ——∆∆0—6
MOV.W Rs, @aa:16 W Rs16 → @aa:16 4 — — ∆∆0—6
POP Rd W @SP → Rd16
SP+2 → SP
2 ——∆∆0—6
PUSH Rs W SP–2 → SP
Rs16 → @SP
2 ——∆∆0—6
335
Table A-1 Instruction Set (cont)
Addressing Mode/
Instruction Length
Mnemonic
Operand Size
Operation
#xx: 8/16
Rn
@Rn
@(d:16,Rn)
@–Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
Implied
Condition Code
No. of States
I HNZVC
MOVFPE @aa:16, Rd B Not supported (5)
MOVTPE Rs, @aa:16 B Not supported (5)
EEPMOV — if R4L≠0 then
Repeat @R5 → @R6
R5+1 → R5
R6+1 → R6
R4L–1 → R4L
Until R4L=0
else next
4 ——————(4)
ADD.B #xx:8, Rd B Rd8+#xx:8 → Rd8 2 — ∆∆∆∆∆2
ADD.B Rs, Rd B Rd8+Rs8 → Rd8 2 — ∆∆∆∆∆2
ADD.W Rs, Rd W Rd16+Rs16 → Rd16 2 — (1) ∆∆∆∆2
ADDX.B #xx:8, Rd B Rd8+#xx:8 +C → Rd8 2 — ∆∆(2) ∆∆2
ADDX.B Rs, Rd B Rd8+Rs8 +C → Rd8 2 — ∆∆(2) ∆∆2
ADDS.W #1, Rd W Rd16+1 → Rd16 2 ——————2
ADDS.W #2, Rd W Rd16+2 → Rd16 2 ——————2
INC.B Rd B Rd8+1 → Rd8 2 — — ∆∆∆—2
DAA.B Rd B Rd8 decimal adjust →
Rd8
2—
*
∆∆*(3) 2
SUB.B Rs, Rd B Rd8–Rs8 → Rd8 2 — ∆∆∆∆∆2
SUB.W Rs, Rd W Rd16–Rs16 → Rd16 2 — (1) ∆∆∆∆2
SUBX.B #xx:8, Rd B Rd8–#xx:8 –C → Rd8 2 — ∆∆(2) ∆∆2
SUBX.B Rs, Rd B Rd8–Rs8 –C → Rd8 2 — ∆∆(2) ∆∆2
SUBS.W #1, Rd W Rd16–1 → Rd16 2 ——————2
SUBS.W #2, Rd W Rd16–2 → Rd16 2 ——————2
DEC.B Rd B Rd8–1 → Rd8 2 — — ∆∆∆—2
DAS.B Rd B Rd8 decimal adjust →
Rd8
2—
*
∆∆*—2
NEG.B Rd B 0–Rd8 → Rd8 2 — ∆∆∆∆∆2
CMP.B #xx:8, Rd B Rd8–#xx:8 2 — ∆∆∆∆∆2
CMP.B Rs, Rd B Rd8–Rs8 2 — ∆∆∆∆∆2
CMP.W Rs, Rd W Rd16–Rs16 2 — (1) ∆∆∆∆2
336
Table A-1 Instruction Set (cont)
Addressing Mode/
Instruction Length
Mnemonic
Operand Size
Operation
#xx: 8/16
Rn
@Rn
@(d:16,Rn)
@–Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
Implied
Condition Code
No. of States
IHNZVC
MULXU.B Rs, Rd B Rd8 × Rs8→Rd16 2 — — — — — — 14
DIVXU.B Rs, Rd B Rd16÷Rs8→Rd16
(RdH:remainder,
RdL:quotient)
2 — — (6) (7) — — 14
AND.B#xx:8,Rd B Rd8∧#xx:8→ Rd8 2 — — ∆∆0—2
AND.B Rs, Rd B Rd8∧Rs8 → Rd8 2 — — ∆∆0—2
OR.B #xx:8, Rd B Rd8∨#xx:8 → Rd8 2 — — ∆∆0—2
OR.B Rs, Rd B Rd8∨Rs8 → Rd8 2 — — ∆∆0—2
XOR.B #xx:8, Rd B Rd8⊕#xx:8 → Rd8 2 — — ∆∆0—2
XOR.B Rs, Rd B Rd8⊕Rs8 → Rd8 2 — — ∆∆0—2
NOT.B Rd B
5G
→ Rd8 2 — — ∆∆0—2
SHAL.B Rd B
b7b0
0C
2——
∆∆∆ ∆ 2
SHAR.B Rd B
C
b
7
b
0
2——
∆∆0∆2
SHLL.B Rd B
b7b0
0C
2——0
∆
0
∆
2
SHLR.B Rd B
b
7
b
0
0C
2——0
∆
0
∆
2
ROTXL.B Rd B
C
b7b0
2——
∆∆0∆2
ROTXR.B Rd B
C
b7b0
2——
∆∆0∆2
337
Table A-1 Instruction Set (cont)
Addressing Mode/
Instruction Length
Mnemonic
Operand Size
Operation
#xx: 8/16
Rn
@Rn
@(d:16,Rn)
@–Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
Implied
Condition Code
No. of States
I HNZVC
ROTL.BRd B
C
b7b0
2 ——∆∆0∆2
ROTR.BRd B
C
b7b0
2 ——∆∆0∆2
BSET #xx:3,Rd B (#xx:3 of Rd8) ← 1 2 ——————2
BSET #xx:3, @Rd B (#xx:3 of @Rd16) ← 1 4 ——————8
BSET #xx:3, @aa:8 B (#xx:3 of @aa:8) ← 1 4 ——————8
BSET Rn, Rd B (Rn8 of Rd8) ← 1 2 ——————2
BSET Rn, @Rd B (Rn8 of @Rd16) ← 1 4 ——————8
BSET Rn, @aa:8 B (Rn8 of @aa:8) ← 1 4 ——————8
BCLR #xx:3, Rd B (#xx:3 of Rd8) ← 0 2 ——————2
BCLR #xx:3, @Rd B (#xx:3 of @Rd16) ← 0 4 ——————8
BCLR #xx:3, @aa:8 B (#xx:3 of @aa:8) ← 0 4 ——————8
BCLR Rn, Rd B (Rn8 of Rd8) ← 0 2 ——————2
BCLR Rn, @Rd B (Rn8 of @Rd16) ← 0 4 ——————8
BCLR Rn, @aa:8 B (Rn8 of @aa:8) ← 0 4 ——————8
BNOT #xx:3, Rd B (#xx:3 of Rd8) ←
(
[[RI5G
)
2 ——————2
BNOT #xx:3, @Rd B (#xx:3 of @Rd16) ←
(
[[RI#5G
)
4 ——————8
BNOT #xx:3, @aa:8 B (#xx:3 of @aa:8) ←
(
[[RI#DD
)
4 ——————8
BNOT Rn, Rd B (Rn8 of Rd8) ←
(
5QRI5G
)
2 ——————2
BNOT Rn, @Rd B (Rn8 of @Rd16) ←
(
5QRI#5G
)
4 ——————8
BNOT Rn, @aa:8 B (Rn8 of @aa:8) ←
(
5QRI#DD
)
4 ——————8
338
Table A-1 Instruction Set (cont)
Addressing Mode/
Instruction Length
Mnemonic
Operand Size
Operation
#xx: 8/16
Rn
@Rn
@(d:16,Rn)
@–Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
Implied
Condition Code
No. of States
IHNZVC
BTST #xx:3, Rd B (
[[RI5G
) → Z 2 ———
∆——2
BTST #xx:3, @Rd B (
[[RI#5G
) → Z 4 ———
∆——6
BTST #xx:3, @aa:8 B (
[[RI#DD
) → Z 4 ———
∆——6
BTST Rn, Rd B (
5QRI5G
) → Z 2 ———
∆——2
BTST Rn, @Rd B (
5QRI#5G
) → Z 4 ———
∆——6
BTST Rn, @aa:8 B (
5QRI#DD
) → Z 4 ———
∆——6
BLD #xx:3, Rd B (#xx:3 of Rd8) → C 2 —————∆2
BLD #xx:3, @Rd B (#xx:3 of @Rd16) → C 4 —————∆6
BLD #xx:3, @aa:8 B (#xx:3 of @aa:8) → C 4 —————∆6
BILD #xx:3, Rd B (
[[RI5G
) → C 2 —————∆2
BILD #xx:3, @Rd B (
[[RI#5G
) → C 4 —————∆6
BILD #xx:3, @aa:8 B (
[[RI#DD
) → C 4 —————∆6
BST #xx:3, Rd B C → (#xx:3 of Rd8) 2 — — — — — — 2
BST #xx:3, @Rd B C → (#xx:3 of @Rd16) 4 — — — — — — 8
BST #xx:3, @aa:8 B C → (#xx:3 of @aa:8) 4 — — — — — — 8
BIST #xx:3, Rd B
&
→ (#xx:3 of Rd8) 2 — — — — — — 2
BIST #xx:3, @Rd B
&
→ (#xx:3 of @Rd16) 4 — — — — — — 8
BIST #xx:3, @aa:8 B
&
→ (#xx:3 of @aa:8) 4 — — — — — — 8
BAND #xx:3, Rd B C∧(#xx:3 of Rd8) → C 2 —————∆2
BAND #xx:3, @Rd B C∧(#xx:3 of @Rd16) → C 4 —————∆6
BAND #xx:3, @aa:8 B C∧(#xx:3 of @aa:8) → C 4 —————∆6
BIAND #xx:3, Rd B C∧(
[[RI5G
) → C 2 —————∆2
BIAND #xx:3, @Rd B C∧(
[[RI#5G
) → C 4 —————∆6
BIAND #xx:3, @aa:8 B C∧(
[[RI#DD
) → C 4 —————∆6
BOR #xx:3, Rd B C∨(#xx:3 of Rd8) → C 2 —————∆2
BOR #xx:3, @Rd B C∨(#xx:3 of @Rd16) → C 4 —————∆6
BOR #xx:3, @aa:8 B C∨(#xx:3 of @aa:8) → C 4 —————∆6
BIOR #xx:3, Rd B C∨(
[[RI5G
) → C 2 —————∆2
BIOR #xx:3, @Rd B C∨(
[[RI#5G
) → C 4 —————∆6
339
Table A-1 Instruction Set (cont)
Addressing Mode/
Instruction Length
Mnemonic
Operand Size
Operation
Branching
Condition
#xx: 8/16
Rn
@Rn
@(d:16,Rn)
@–Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
Implied
Condition Code
No. of States
IHNZVC
BIOR #xx:3, @aa:8 B C∨(
[[RI#DD
) → C 4 —————∆6
BXOR #xx:3, Rd B C⊕(#xx:3 of Rd8) → C 2 —————∆2
BXOR #xx:3, @Rd B C⊕(#xx:3 of @Rd16) → C 4 —————∆6
BXOR #xx:3, @aa:8 B C⊕(#xx:3 of @aa:8) → C 4 —————∆6
BIXOR #xx:3, Rd B C⊕(
[[RI5G
) → C 2 —————∆2
BIXOR #xx:3, @Rd B C⊕(
[[RI#5G
) → C 4 —————∆6
BIXOR #xx:3, @aa:8 B C⊕(
[[RI#DD
) → C 4 —————∆6
BRA d:8 (BT d:8) — PC ← PC+d:8 2 — —————4
BRN d:8 (BF d:8) — PC ← PC+2 2 — —————4
BHI d:8 — If condition C ∨ Z = 0 2 ——————4
BLS d:8 — is true then C ∨ Z = 1 2 ——————4
BCC d:8 (BHS d:8) — PC ←C = 0 2 ——————4
BCS d:8 (BLO d:8) — PC + d:8 C = 1 2 ——————4
BNE d:8 — else next; Z = 0 2 — —————4
BEQ d:8 — Z = 1 2 — —————4
BVC d:8 — V = 0 2 — —————4
BVS d:8 — V = 1 2 — —————4
BPL d:8 — N = 0 2 — —————4
BMI d:8 — N = 1 2 — —————4
BGE d:8 — N⊕V = 0 2 ——————4
BLT d:8 — N⊕V = 1 2 ——————4
BGT d:8 — Z ∨ (N⊕V) = 0 2 ——————4
BLE d:8 — Z ∨ (N⊕V) = 1 2 ——————4
JMP @Rn — PC ← Rn16 2 — —————4
JMP @aa:16 — PC ← aa:16 4 — —————6
JMP @@aa:8 — PC ← @aa:8 2 — —————8
BSR d:8 — SP –2 → SP
PC → @SP
PC ← PC+d:8
2 ——————6
340
Table A-1 Instruction Set (cont)
Addressing Mode/
Instruction Length
Mnemonic
Operand Size
Operation
#xx: 8/16
Rn
@Rn
@(d:16,Rn)
@–Rn/@Rn+
@aa:8/16
@(d:8, PC)
@@aa
Implied
Condition Code
No. of States
I HNZVC
JSR @Rn — SP–2 → SP
PC → @SP
PC ← Rn16
2 ——————6
JSR @aa:16 — SP–2 → SP
PC → @SP
PC ← aa:16
4 ——————8
JSR @@aa:8 — SP–2 → SP
PC → @SP
PC ← @aa:8
2 ——————8
RTS — PC ← @SP
SP+2 → SP 2 ——————8
RTE — CCR ← @SP
SP+2 → SP
PC ← @SP
SP+2 → SP
2∆∆∆∆∆∆10
SLEEP — Transition to power-
down state. 2 ——————2
LDC #xx:8, CCR B #xx:8 → CCR 2 ∆∆∆∆∆∆2
LDC Rs, CCR B Rs8 → CCR 2 ∆∆∆∆∆∆2
STC CCR, Rd B CCR → Rd8 2 ——————2
ANDC #xx:8, CCR B CCR∧#xx:8 → CCR 2 ∆∆∆∆∆∆2
ORC #xx:8, CCR B CCR∨#xx:8 → CCR 2 ∆∆∆∆∆∆2
XORC #xx:8, CCR B CCR⊕#xx:8 → CCR 2 ∆∆∆∆∆∆2
NOP — PC ← PC+2 2 ——————2
Notes: The number of states is the number of states required for execution when the instruction
and its operands are located in on-chip memory.
(1) Set to 1 when there is a carry or borrow from bit 11; otherwise cleared to 0.
(2) If the result is zero, the previous value of the flag is retained; otherwise the flag is
cleared to 0.
(3) Set to 1 if decimal adjustment produces a carry; otherwise retains its previous value.
(4) The number of states required for execution is 4n+8 (n = value of R4L).
(5) These instructions are not supported by the H8/3534 and H8/3522.
(6) Set to 1 if the divisor is negative; otherwise cleared to 0.
(7) Set to 1 if the divisor is 0; otherwise cleared to 0.
341
A.2 Operation Code Map
Table A-2 is a map of the operation codes contained in the first byte of the instruction code (bits
15 to 8 of the first instruction word).
Some pairs of instructions have identical first bytes. These instructions are differentiated by the
first bit of the second byte (bit 7 of the first instruction word).
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 0.
Instruction when first bit of byte 2 (bit 7 of first instruction word) is 1.
342
Table A-2 Operation Code Map
High Low 0123456789ABCDEF
0
1
2
3
4
5
6
7
8
9
A
B
C
D
E
F
NOP
BRA
*2
MULXU
BSET
SHLL
SHAL
SLEEP
BRN
*2
DIVXU
BNOT
SHLR
SHAR
STC
BHI
BCLR
ROTXL
ROTL
LDC
BLS
BTS
ROTXR
ROTR
ORC
OR
BCC
*2
RTS
XORC
XOR
BCS
*2
BSR
BOR
BIOR
BXOR
BIXOR
BAND
BIAND
ANDC
AND
BNE
RTE
LDC
BEQ
NOT
NEG
BLD
BILD
BST
BIST
ADD
SUB
BVC BVS
MOV
INC
DEC
BPL
JMP
ADDS
SUBS
BMI
EEPMOV
MOV
CMP
BGE BLT
ADDX
SUBX
BGT
JSR
DAA
DAS
BLE
MOV
ADD
ADDX
CMP
SUBX
OR
XOR
AND
MOV
MOV
*1
Notes: 1.
2.
Bit manipulation instructions
The MOVFPE and MOVTPE instructions are identical to MOV instructions in the first byte and first bit of the second byte (bits 15 to 7 of the instruction word).
The PUSH and POP instructions are identical in machine language to MOV instructions.
The BT, BF, BHS, and BLO instructions are identical in machine language to BRA, BRN, BCC, and BCS, respectively.
343
A.3 Number of States Required for Execution
The tables below can be used to calculate the number of states required for instruction
execution. Table A-3 indicates the number of states required for each cycle (instruction fetch,
branch address read, stack operation, byte data access, word data access, internal operation).
Table A-4 indicates the number of cycles of each type occurring in each instruction. The total
number of states required for execution of an instruction can be calculated from these two tables
as follows:
Execution states = I × SI + J × SJ + K × SK + L × SL + M × SM + N × SN
Examples: Mode 1 (on-chip ROM disabled), stack located in external memory, 1 wait state
inserted in external memory access.
1. BSET #0, @FFC7
From table A-4: I = L = 2, J = K = M = N= 0
From table A-3: SI = 8, SL = 3
Number of states required for execution: 2 × 8 + 2 × 3 =22
2. JSR @@30
From table A-4: I = 2, J = K = 1, L = M = N = 0
From table A-3: SI = SJ = SK = 8
Number of states required for execution: 2 × 8 + 1 × 8 + 1 × 8 = 32
Table A-3. Number of States Taken by Each Cycle in Instruction Execution
Access Location
Execution Status
(Instruction Cycle) On-Chip Memory On-Chip Supporting
Module External Device
Instruction fetch SI2 6 6 + 2m
Branch address read SJ
Stack operation SK
Byte data access SL3 3 + m
Word data access SM6 6 + 2m
Internal operation SN11 1
Notes: m: Number of wait states inserted in access to external device.
344
Table A-4 Number of Cycles in Each Instruction
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr.
Read
J
Stack
Operation
K
Byte
Data
Access
L
Word
Data
Access
M
Internal
Operation
N
ADD ADD.B #xx:8, Rd
ADD.B Rs, Rd
ADD.W Rs, Rd
1
1
1
ADDS ADDS.W #1/2, Rd 1
ADDX ADDX.B #xx:8, Rd
ADDX.B Rs, Rd 1
1
AND AND.B #xx:8, Rd
AND.B Rs, Rd 1
1
ANDC ANDC #xx:8, CCR 1
BAND BAND #xx:3, Rd
BAND #xx:3, @Rd
BAND #xx:3, @aa:8
1
2
21
1
Bcc BRA d:8 (BT d:8)
BRN d:8 (BF d:8)
BHI d:8
BLS d:8
BCC d:8 (BHS d:8)
BCS d:8 (BLO d:8)
BNE d:8
BEQ d:8
BVC d:8
BVS d:8
BPL d:8
BMI d:8
BGE d:8
BLT d:8
BGT d:8
BLE d:8
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
BCLR BCLR #xx:3, Rd
BCLR #xx:3, @Rd
BCLR #xx:3, @aa:8
BCLR Rn, Rd
BCLR Rn, @Rd
BCLR Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
Note: All values left blank are zero.
345
Table A-4 Number of Cycles in Each Instruction (cont)
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
BIAND BIAND #xx:3, Rd
BIAND #xx:3, @Rd
BIAND #xx:3, @aa:8
1
2
21
1
BILD BILD #xx:3, Rd
BILD #xx:3, @Rd
BILD #xx:3, @aa:8
1
2
21
1
BIOR BIOR #xx:3, Rd
BIOR #xx:3, @Rd
BIOR #xx:3, @aa:8
1
2
21
1
BIST BIST #xx:3, Rd
BIST #xx:3, @Rd
BIST #xx:3, @aa:8
1
2
22
2
BIXOR BIXOR #xx:3, Rd
BIXOR #xx:3, @Rd
BIXOR #xx:3, @aa:8
1
2
21
1
BLD BLD #xx:3, Rd
BLD #xx:3, @Rd
BLD #xx:3, @aa:8
1
2
21
1
BNOT BNOT #xx:3, Rd
BNOT #xx:3, @Rd
BNOT #xx:3, @aa:8
BNOT Rn, Rd
BNOT Rn, @Rd
BNOT Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
BOR BOR #xx:3, Rd
BOR #xx:3, @Rd
BOR #xx:3, @aa:8
1
2
21
1
BSET BSET #xx:3, Rd
BSET #xx:3, @Rd
BSET #xx:3, @aa:8
BSET Rn, Rd
BSET Rn, @Rd
BSET Rn, @aa:8
1
2
2
1
2
2
2
2
2
2
Note: All values left blank are zero.
346
Table A-4 Number of Cycles in Each Instruction (cont)
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word
Data
Access
M
Internal
Operation
N
BSR BSR d:8 2 1
BST BST #xx:3, Rd
BST #xx:3, @Rd
BST #xx:3, @aa:8
1
2
22
2
BTST BTST #xx:3, Rd
BTST #xx:3, @Rd
BTST #xx:3, @aa:8
BTST Rn, Rd
BTST Rn, @Rd
BTST Rn, @aa:8
1
2
2
1
2
2
1
1
1
1
BXOR BXOR #xx:3, Rd
BXOR #xx:3, @Rd
BXOR #xx:3, @aa:8
1
2
21
1
CMP CMP.B #xx:8, Rd
CMP.B Rs, Rd
CMP.W Rs, Rd
1
1
1
DAA DAA.B Rd 1
DAS DAS.B Rd 1
DEC DEC.B Rd 1
DIVXU DIVXU.B Rs, Rd 1 12
EEPMOV EEPMOV 2 2n+2* 1
INC INC.B Rd 1
JMP JMP @Rn
JMP @aa:16
JMP @@aa:8
2
2
21 2
2
JSR JSR @Rn
JSR @aa:16
JSR @@aa:8
2
2
21
1
1
12
LDC LDC #xx:8, CCR
LDC Rs, CCR 1
1
MOV MOV.B #xx:8, Rd
MOV.B Rs, Rd
MOV.B @Rs, Rd
MOV.B @(d:16,Rs), Rd
1
1
1
21
1
Notes: All values left blank are zero.
* n: Initial value in R4L. Source and destination are accessed n + 1 times each.
347
Table A-4 Number of Cycles in Each Instruction (cont)
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
I nternal
Operation
N
MOV MOV.B @Rs+, Rd
MOV.B @aa:8, Rd
MOV.B @aa:16, Rd
MOV.B Rs, @Rd
MOV.B Rs, @(d:16, Rd)
MOV.B Rs, @–Rd
MOV.B Rs, @aa:8
MOV.B Rs, @aa:16
MOV.W #xx:16, Rd
MOV.W Rs, Rd
MOV.W @Rs, Rd
MOV.W @(d:16, Rs), Rd
MOV.W @Rs+, Rd
MOV.W @aa:16, Rd
MOV.W Rs, @Rd
MOV.W Rs, @(d:16, Rd)
MOV.W Rs, @–Rd
MOV.W Rs, @aa:16
1
1
2
1
2
1
1
2
2
1
1
2
1
2
1
2
1
2
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
1
2
2
2
2
MOVFPE MOVFPE @aa:16, Rd Not supported
MOVTPE MOVTPERs, @aa:16 Not supported
MULXU MULXU.BRs, Rd 1 12
NEG NEG.B Rd 1
NOP NOP 1
NOT NOT.B Rd 1
OR OR.B #xx:8, Rd
OR.B Rs, Rd 1
1
ORC ORC #xx:8, CCR 1
POP POP Rd 1 1 2
PUSH PUSH Rd 1 1 2
ROTL ROTL.B Rd 1
ROTR ROTR.B Rd 1
ROTXL ROTXL.B Rd 1
ROTXR ROTXR.B Rd 1
RTE RTE 2 2 2
RTS RTS 2 1 2
Note: All values left blank are zero.
348
Table A-4 Number of Cycles in Each Instruction (cont)
Instruction Mnemonic
Instruction
Fetch
I
Branch
Addr. Read
J
Stack
Operation
K
Byte Data
Access
L
Word Data
Access
M
Internal
Operation
N
SHAL SHAL.B Rd 1
SHAR SHAR.B Rd 1
SHLL SHLL.B Rd 1
SHLR SHLR.B Rd 1
SLEEP SLEEP 1
STC STC CCR, Rd 1
SUB SUB.B Rs, Rd
SUB.W Rs, Rd 1
1
SUBS SUBS.W #1/2, Rd 1
SUBX SUBX.B #xx:8, Rd
SUBX.B Rs, Rd 1
1
XOR XOR.B #xx:8, Rd
XOR.B Rs, Rd 1
1
XORC XORC #xx:8, CCR 1
Note: All values left blank are zero.
349
Appendix B Internal I/O Register
B.1 Addresses
B.1.1 Addresses for H8/3534
Bit Names
Addr.
(Last
Byte) Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'80 External
addresses
(in expand-
ed modes)
H'81
H'82
H'83
H'84
H'85
H'86
H'87
H'88 SMR C/
$
CHR PE O/
(
STOP MP CKS1 CKS0 SCI1
H'89 BRR
H'8A SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'8B TDR
H'8C SSR TDRE RDRF ORER FER PER TEND MPB MPBT
H'8D RDR
H'8E — — — — — — — — —
H'8F — — — — — — — — —
H'90 TIER ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE — FRT
H'91 TCSR ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA
H'92 FRC (H)
H'93 FRC (L)
H'94 OCRA (H)
OCRB (H)
H'95 OCRA (L)
OCRB (L)
H'96 TCR IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0
H'97 TOCR — — — OCRS OEA OEB OLVLA OLVLB
H'98 ICRA (H)
H'99 ICRA (L)
H'9A ICRB (H)
H'9B ICRB (L)
H'9C ICRC (H)
H'9D ICRC (L)
H'9E ICRD (H)
H'9F ICRD (L)
Notes: FRT: 16-bit free-running timer (Continued on next page)
SCI1: Serial communication interface 1
350
(Continued from previous page)
Bit Names
Addr.
(Last
Byte) Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'A0 TCR OE OS — — — CKS2 CKS1 CKS0 PWM0
H'A1 DTR
H'A2 TCNT
H'A3 — — — — — — — — —
H'A4 TCR OE OS — — — CKS2 CKS1 CKS0 PWM1
H'A5 DTR
H'A6 TCNT
H'A7 — — — — — — — — —
H'A8 TCSR/
TCNT OVF WT/
,7
TME — RST/
10,
CKS2 CKS1 CKS0 WDT
H'A9 TCNT
H'AA — — — — — — — — —
H'AB — — — — — — — — —
H'AC P1PCR P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Port 1
H'AD P2PCR P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Port 2
H'AE P3PCR P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Port 3
H'AF — — — — — — ————
H'B0 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 1
H'B1 P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Port 2
H'B2 P1DR P17P16P15P14P13P12P11P10Port 1
H'B3 P2DR P27P26P25P24P23P22P21P20Port 2
H'B4 P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3
H'B5 P4DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Port 4
H'B6 P3DR P37P36P35P34P33P32P31P30Port 3
H'B7 P4DR P47P46P45P44P43P42P41P40Port 4
H'B8 P5DDR — — — — — P52DDR P51DDR P50DDR Port 5
H'B9 P6DDR P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Port 6
H'BA P5DR — — — — — P52P51P50Port 5
H'BB P6DR P67P66P65P64P63P62P61P60Port 6
Notes: PWM0: Pulse-width modulation timer channel 0 (Continued on next page)
PWM1: Pulse-width modulation timer channel 1
WDT: Watchdog timer
351
(Continued from preceding page)
Bit Names
Addr.
(Last
Byte Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'BC — — — ——————
H'BD P8DDR — P86DDR P85DDR P84DDR P83DDR P82DDR P81DDR P80DDR Port 8
H'BE P7PIN P77P76P75P74P73P72P71P70Port 7
H'BF P8DR — P86P85P84P83P82P81P80Port 8
H'C0 P9DDR P97DDR P96DDR P95DDR P94DDR P93DDR P92DDR P91DDR P90DDR Port 9
H'C1 P9DR P97P96P95P94P93P92P91P90
H'C2 WSCR (RAMS) (RAMO) CKDBL — WMS1 WMS0 WC1 WC0
H'C3 STCR (IICS) (IICD) (IICX) (IICE) (STAC) MPE ICKS1 ICKS0 —
H'C4 SYSCR SSBY STS2 STS1 STS0 XRST NMIEG (HIE) RAME
H'C5 MDCR — — ————MDS1 MDS0
H'C6 ISCR IRQ7SC IRQ6SC IRQ5SC IRQ4SC IRQ3SC IRQ2SC IRQ1SC IRQ0SC
H'C7 IER IRQ7E IRQ6E IRQ5E IRQ4E IRQ3E IRQ2E IRQ1E IRQ0E
H'C8 TCR CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR0
H'C9 TCSR CMFB CMFA OVF — OS3 OS2 OS1 OS0
H'CA TCORA
H'CB TCORB
H'CC TCNT
H'CD — — — ——————
H'CE — — — ——————
H'CF — — — ——————
H'D0 TCR CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR1
H'D1 TCSR CMFB CMFA OVF — OS3 OS2 OS1 OS0
H'D2 TCORA
H'D3 TCORB
H'D4 TCNT
H'D5 — — — ——————
H'D6 — — — ——————
H'D7 — — — ——————
Notes: TMR0: 8-bit timer channel 0 (Continued on next page)
TMR1: 8-bit timer channel 1
352
(Continued from preceding page)
Bit Names
Addr.
(Last
Byte Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'D8 SMR C/
$
CHR PE O/
(
STOP MP CKS1 CKS0 SCI0
H'D9 BRR
H'DA SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'DB TDR
H'DC SSR TDRE RDRF ORER FER PER TEND MPB MPBT
H'DD RDR
H'DE — — — — — — — — —
H'DF — — — — — — — — —
H'E0 ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D
H'E1 ADDRAL AD1 AD0 — — — — — —
H'E2 ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'E3 ADDRBL AD1 AD0 — — — — — —
H'E4 ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'E5 ADDRCL AD1 AD0 — — — — — —
H'E6 ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'E7 ADDRDL AD1 AD0 — — — — — —
H'E8 ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0
H'E9 ADCR TRGE — — — — — — —
H'EA — — — — — — — — —
H'EB — — — — — — — — —
H'EC — — — — — — — — — —
H'ED — — — — — — — — —
H'EE — — — — — — — — —
H'EF — — — — — — — — —
Notes: SCI0: Serial communication interface 0 (Continued on next page)
A/D: Analog-to-digital converter
353
(Continued from preceding page)
Bit Names
Addr.
(Last
Byte) Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'F0
H'F1 KMIMR KMIMR7 KMIMR6 KMIMR5 KMIMR4 KMIMR3 KMIMR2 KMIMR1 KMIMR0
H'F2 KMPCR KM7PCR KM6PCR KM5PCR KM4PCR KM3PCR KM2PCR KM1PCR KM0PCR Port6
H'F3
H'F4
H'F5
H'F6
H'F7
H'F8
H'F9
H'FA
H'FB
H'FC
H'FD
H'FE
H'FF
354
B.1.2 Addresses for H8/3522
Bit Names
Addr.
(Last
Byte Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'80 External
addresses
(in expand-
ed modes)
H'81
H'82
H'83
H'84
H'85
H'86
H'87
H'88 — — — — — — — — — —
H'89 — — — — — — — — —
H'8A — — — — — — — — —
H'8B — — — — — — — — —
H'8C — — — — — — — — —
H'8D — — — — — — — — —
H'8E — — — — — — — — —
H'8F — — — — — — — — —
H'90 TIER ICIAE ICIBE ICICE ICIDE OCIAE OCIBE OVIE — FRT
H'91 TCSR ICFA ICFB ICFC ICFD OCFA OCFB OVF CCLRA
H'92 FRCH
H'93 FRCL
H'94 OCRAH
OCRBH
H'95 OCRAL
OCRBL
H'96 TCR IEDGA IEDGB IEDGC IEDGD BUFEA BUFEB CKS1 CKS0
H'97 TOCR — — — OCRS OEA OEB OLVLA OLVLB
H'98 ICRAH
H'99 ICRAL
H'9A ICRBH
H'9B ICRBL
H'9C ICRCH
H'9D ICRCL
H'9E ICRDH
H'9F ICRDL
Note: FRT: 16-bit free-running timer (Continued on next page)
355
(Continued from preceding page)
Bit Names
Addr.
(Last
Byte) Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'A0 — — — — — — — — —
H'A1 — — — — — — — — —
H'A2 — — — — — — — — —
H'A3 — — — — — — — — —
H'A4 — — — — — — — — —
H'A5 — — — — — — — — —
H'A6 — — — — — — — — —
H'A7 — — — — — — — — —
H'A8 TCSR/
TCNT OVF WT/
,7
TME — RST/
10,
CKS2 CKS1 CKS0 WDT
H'A9 TCNT
H'AA — — — — — — — — —
H'AB — — — — — — — — —
H'AC P1PCR P17PCR P16PCR P15PCR P14PCR P13PCR P12PCR P11PCR P10PCR Port 1
H'AD P2PCR P27PCR P26PCR P25PCR P24PCR P23PCR P22PCR P21PCR P20PCR Port 2
H'AE P3PCR P37PCR P36PCR P35PCR P34PCR P33PCR P32PCR P31PCR P30PCR Port 3
H'AF — — — — — — ————
H'B0 P1DDR P17DDR P16DDR P15DDR P14DDR P13DDR P12DDR P11DDR P10DDR Port 1
H'B1 P2DDR P27DDR P26DDR P25DDR P24DDR P23DDR P22DDR P21DDR P20DDR Port 2
H'B2 P1DR P17P16P15P14P13P12P11P10Port 1
H'B3 P2DR P27P26P25P24P23P22P21P20Port 2
H'B4 P3DDR P37DDR P36DDR P35DDR P34DDR P33DDR P32DDR P31DDR P30DDR Port 3
H'B5 P4DDR P47DDR P46DDR P45DDR P44DDR P43DDR P42DDR P41DDR P40DDR Port 4
H'B6 P3DR P37P36P35P34P33P32P31P30Port 3
H'B7 P4DR P47P46P45P44P43P42P41P40Port 4
H'B8 P5DDR — — — — — P52DDR P51DDR P50DDR Port 5
H'B9 P6DDR P67DDR P66DDR P65DDR P64DDR P63DDR P62DDR P61DDR P60DDR Port 6
H'BA P5DR — — — — — P52P51P50Port 5
H'BB P6DR P67P66P65P64P63P62P61P60Port 6
H'BC — — — — — — ————
H'BD — — — — — — ————
H'BE P7PIN P77P76P75P74P73P72P71P70Port 7
H'BF — — — — — — ————
Note: WDT: Watchdog timer (Continued on next page)
356
(Continued from preceding page)
Bit Names
Addr.
(Last
Byte) Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'C0 — — — — — — ————
H'C1 — — — — — — ————
H'C2 WSCR — — CKDBL — WMS1 WMS0 WC1 WC0
H'C3 STCR — — — — — MPE ICKS1 ICKS0
H'C4 SYSCR SSBY STS2 STS1 STS0 XRST NMIEG — RAME
H'C5 MDCR — — — — — — MDS1 MDS0
H'C6 ISCR — — — — — IRQ2SC IRQ1SC IRQ0SC
H'C7 IER — — — — — IRQ2E IRQ1E IRQ0E
H'C8 TCR CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR0
H'C9 TCSR CMFB CMFA OVF — OS3 OS2 OS1 OS0
H'CA TCORA
H'CB TCORB
H'CC TCNT
H'CD — — — — — — — — —
H'CE — — — — — — — — —
H'CF — — — — — — — — —
H'D0 TCR CMIEB CMIEA OVIE CCLR1 CCLR0 CKS2 CKS1 CKS0 TMR1
H'D1 TCSR CMFB CMFA OVF — OS3 OS2 OS1 OS0
H'D2 TCORA
H'D3 TCORB
H'D4 TCNT
H'D5 — — — — — — — — —
H'D6 — — — — — — — — —
H'D7 — — — — — — — — —
H'D8 SMR C/
$
CHR PE O/
(
STOP MP CKS1 CKS0 SCI
H'D9 BRR
H'DA SCR TIE RIE TE RE MPIE TEIE CKE1 CKE0
H'DB TDR
H'DC SSR TDRE RDRF ORER FER PER TEND MPB MPBT
H'DD RDR
H'DE — — — — — — — — —
H'DF — — — — — — — — —
Notes: TMR0: 8-bit timer channel 0
TMR1: 8-bit timer channel 1
SCI: Serial communication interface (Continued on next page)
357
(Continued from preceding page)
Bit Names
Addr.
(Last
Byte) Register
Name Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Module
H'E0 ADDRAH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 A/D
H'E1 ADDRAL AD1 AD0 — — — — — —
H'E2 ADDRBH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'E3 ADDRBL AD1 AD0 — — — — — —
H'E4 ADDRCH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'E5 ADDRCL AD1 AD0 — — — — — —
H'E6 ADDRDH AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2
H'E7 ADDRDL AD1 AD0 — — — — — —
H'E8 ADCSR ADF ADIE ADST SCAN CKS CH2 CH1 CH0
H'E9 ADCR TRGE — — — — — — —
H'EA — — — — — — — — —
H'EB — — — — — — — — —
H'EC — — — — — — — — — —
H'ED — — — — — — — — —
H'EE — — — — — — — — —
H'EF — — — — — — — — —
H'F0 — — — — — — — — — —
H'F1 — — — — — — — — —
H'F2 — — — — — — — — —
H'F3 — — — — — — — — —
H'F4 — — — — — — — — —
H'F5 — — — — — — — — —
H'F6 — — — — — — — — —
H'F7 — — — — — — — — —
H'F8 — — — — — — — — —
H'F9 — — — — — — — — —
H'FA — — — — — — — — —
H'FB — — — — — — — — —
H'FC — — — — — — — — —
H'FD — — — — — — — — —
H'FE — — — — — — — — —
H'FF — — — — — — — — —
Note: A/D: Analog-to-digital converter
358
B.2 Function
TIER—Timer Interrupt Enable Register H'FF90 FRT
Bit No.
Initial value
Type of access permitted
R
W
R/W
Abbreviation
of register
name
Register name Address onto which
register is mapped
Name of
on-chip
supporting
module
Bit names
(abbreviations).
Bits marked “—”
are reserved.
Full name
of bit
Description
of bit function
Read only
Write only
Read or write
Bit
Initial value
Read/Write
7
ICIAE
0
R/W
6
ICIBE
0
R/W
5
ICICE
0
R/W
4
ICIDE
0
R/W
3
OCIAE
0
R/W
0
—
1
—
2
OCIBE
0
R/W
1
OVIE
0
R/W
Overflow Interrupt Enable
0
1Overflow interrupt request is disabled.
Overflow interrupt request is enabled.
Output Compare Interrupt B Enable
0
1Output compare interrupt request B is disabled.
Output compare interrupt request B is enabled.
Output Compare Interrupt A Enable
0
1Output compare interrupt request A is disabled.
Output compare interrupt request A is enabled.
Input Capture Interrupt D Enable
0
1Input capture interrupt request D is disabled.
Input capture interrupt request D is enabled.
359
SMR—Serial Mode Register [H8/3534 only] H'FF88 SCI1
Bit
Initial value
Read/Write
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Clock Select
0
0
1
1
0
1
0
1
ø clock
øP/4 clock
øP/16 clock
øP/64 clock
Multiprocessor Mode
0
1
Multiprocessor function disabled
Multiprocessor function enabled
Stop Bit Length
0
1
One stop bit
Two stop bits
Parity Mode
0
1
Even parity
Odd parity
Parity Enable
0Transmit:
Receive:
Character Length
0
1
8-bit per character
7-bit per character
Communication Mode
0
1
Asynchronous
Synchronous
Transmit:
Receive:
1
No parity bit added.
Parity bit not checked.
Parity bit added.
Parity bit checked.
360
BRR—Bit Rate Register [H8/3534 only] H'FF89 SCI1
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Constant that determines the bit rate
361
SCR—Serial Control Register [H8/3534 only] H'FF8A SCI1
Bit
Initial value
Read/Write
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Clock Enable 0
0
1
SCK pin not used
SCK pin uesd for serial clock output.
Clock Enable 1
0
1
Internal clock
External clock
Transmit End Interrupt Enable
0
1
TSR-empty interrupt request is disabled.
TSR-empty interrupt request is enabled.
Multiprocessor Interrupt Enable
0
1
Multiprocessor receive interrupt function is disabled.
Multiprocessor receive interrupt function is enabled.
Receive Enable
0
1
Receive disabled
Receive enabled
Transmit Enable
0
1
Transmit disabled
Transmit enabled
Receive Interrupt Enable
0
1
Receive end interrupt and receive error requests are disabled.
Receive end interrupt and receive error requests are enabled.
Transmit Interrupt Enable
0
1
TDR-empty interrupt request is disabled.
TDR-empty interrupt request is enabled.
362
TDR—Transmit Data Register [H8/3534 only] H'FF8B SCI1
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Transmit data
363
SSR—Serial Status Register [H8/3534 only] H'FF8C SCI1
Bit
Initial value
Read/Write
7
TDRE
1
R/(W)
6
RDRF
0
R/(W)
5
ORER
0
R/(W)
4
FER
0
R/(W)
3
PER
0
R/(W)
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Multiprocessor Bit Transfer
0
1
Multiprocessor bit = 0 in transmit data. (Initial value)
Multiprocessor bit = 1 in transmit data.
Multiprocessor Bit
Transmit End
0
1
Cleared by reading TDRE = 1, then writing 0 in TDRE.
Set to 1 when TE = 0, or when TDRE = 1 at the end of
character transmission. (Initial value)
Parity Error
0
1
Cleared by reading PER = 1, then writing 0 in PER. (Initial value)
Set when a parity error occurs (parity of receive data
does not match parity selected by O/E bit in SMR).
Framing Error
0
1
Cleared by reading FER = 1, then writing 0 in FER. (Initial value)
Set when a framing error occurs (stop bit is 0).
Overrun Error
0
1
Cleared by reading ORER = 1, then writing 0 in ORER. (Initial value)
Set when an overrun error occurs (next data is completely
received while RDRF bit is set to 1).
Receive Data Register Full
0
1
Cleared by reading RDRF = 1, then writing 0 in RDRF. (Initial value)
Set when one character is received normally and transferred from RSR to RDR.
Transmit Data Register Empty
0
1
Cleared by reading TDRE = 1, then writing 0 in TDRE.
Set when: (Initial value)
1. Data is transferred from TDR to TSR.
2. TE is cleared while TDRE = 0.
*
*
*
*
*
Note: * Software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits.
0
1
Multiprocessor bit = 0 in receive data. (Initial value)
Multiprocessor bit = 1 in receive data.
364
RDR—Receive Data Register [H8/3534 only] H'FF8D SCI1
Bit
Initial value
Read/Write
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Receive data
365
TIER—Timer Interrupt Enable Register H'FF90 FRT
Bit
Initial value
Read/Write
7
ICIAE
0
R/W
6
ICIBE
0
R/W
5
ICICE
0
R/W
4
ICIDE
0
R/W
3
OCIAE
0
R/W
0
—
1
—
2
OCIBE
0
R/W
1
OVIE
0
R/W
Timer Overflow Interrupt Enable
0
1
Timer Overflow interrupt request is disabled.
Timer Overflow interrupt request is enabled.
Output Compare Interrupt B Enable
0
1
Output compare interrupt request B is disabled.
Output compare interrupt request B is enabled.
Output Compare Interrupt A Enable
0
1
Output compare interrupt request A is disabled.
Output compare interrupt request A is enabled.
Input Capture Interrupt D Enable
0
1
Input capture interrupt request D is disabled.
Input capture interrupt request D is enabled.
Input Capture Interrupt C Enable
0
1
Input capture interrupt request C is disabled.
Input capture interrupt request C is enabled.
Input Capture Interrupt B Enable
0
1
Input capture interrupt request B is disabled.
Input capture interrupt request B is enabled.
Input Capture Interrupt A Enable
0
1
Input capture interrupt request A is disabled.
Input capture interrupt request A is enabled.
366
TCSR—Timer Control/Status Register H'FF91 FRT
Bit
Initial value
Read/Write
7
ICFA
0
R/(W)
6
ICFB
0
R/(W)
5
ICFC
0
R/(W)
4
ICFD
0
R/(W)
3
OCFA
0
R/(W)
0
CCLRA
0
R/W
2
OCFB
0
R/(W)
1
OVF
0
R/(W)
Counter Clear A
0
1FRC count is not cleared.
FRC count is cleared by compare-match A.
Timer Overflow Flag
Output Compare Flag B
0
1Cleared by reading OCFB = 1, then writing 0 in OCFB.
Set when FRC = OCRB.
Output Compare Flag A
0
1Cleared by reading OCFA = 1, then writing 0 in OCFA.
Set when FRC = OCRA.
Input Capture Flag D
0
1Cleared by reading ICFD = 1, then writing 0 in ICFD.
Set when an input capture signal is received.
Input Capture Flag C
0
1Cleared by reading ICFC = 1, then writing 0 in ICFC.
Set when an input capture signal is received.
Input Capture Flag B
0
1Cleared by reading ICFB = 1, then writing 0 in ICFB.
Set when FTIB input causes FRC to be copied to ICRB.
Input Capture Flag A
0
1Cleared by reading ICFA = 1, then writing 0 in ICFA.
Set when FTIA input causes FRC to be copied to ICRA.
*****
Note: * Software can write a 0 in bits 7 to 1 to clear the flags, but cannot write a 1 in these bits.
0
1Cleared by reading OVF = 1, then writing 0 in OVF.
Set when FRC changes from H'FFFF to H'0000.
**
367
FRC (H and L)—Free-Running Counter H'FF92, H'FF93 FRT
Bit
Initial value
Read/Write
15
0
R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
0
R/W
8
0
R/W
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Count value
368
OCRA (H and L)—Output Compare Register A H'FF94, H'FF95 FRT
Continually compared with FRC.→OCFA is set to 1 when OCRA = FRC.
Bit
Initial value
Read/Write
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
OCRB (H and L)—Output Compare Register B H'FF94, H'FF95 FRT
Continually compared with FRC.→OCFB is set to 1 when OCRB = FRC.
Bit
Initial value
Read/Write
15
1
R/W
14
1
R/W
13
1
R/W
12
1
R/W
11
1
R/W
10
1
R/W
9
1
R/W
8
1
R/W
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
2
1
R/W
1
1
R/W
0
1
R/W
369
TCR—Timer Control Register H'FF96 FRT
Bit
Initial value
Read/Write
7
IEDGA
0
R/W
6
IEDGB
0
R/W
5
IEDGC
0
R/W
4
IEDGD
0
R/W
3
BUFEA
0
R/W
0
CKS0
0
R/W
2
BUFEB
0
R/W
1
CKS1
0
R/W
Clock Select
0
0
1
1
0
1
0
1
Internal clock source: ø
P
/2
Internal clock source: ø
P
/8
Internal clock source: ø
P
/32
External clock source: counted on rising edge
Buffer Enable B
0
1ICRD is used for input capture D.
ICRD is buffer register for input capture B.
Buffer Enable A
0
1ICRC is used for input capture C.
ICRC is buffer register for input capture A.
Input Edge Select D
0
1Falling edge of FTID is valid.
Rising edge of FTID is valid.
Input Edge Select C
Input Edge Select B
0
1Falling edge of FTIB is valid.
Rising edge of FTIB is valid.
Input Edge Select A
0
1Falling edge of FTIA is valid.
Rising edge of FTIA is valid.
0
1Falling edge of FTIC is valid.
Rising edge of FTIC is valid.
370
TOCR—Timer Output Compare Control Register H'FF97 FRT
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
OCRS
0
R/W
3
OEA
0
R/W
0
OLVLB
0
R/W
2
OEB
0
R/W
1
OLVLA
0
R/W
Output Level B
0
1
Compare-match B causes 0 output.
Compare-match B causes 1 output.
Output Level A
0
1
Compare-match A causes 0 output.
Compare-match A causes 1 output.
Output Enable B
0
1
Output compare B output is disabled.
Output compare B output is enabled.
Output Enable A
Output Compare Register Select
0
1
OCRA is selected.
OCRB is selected..
0
1
Output compare A output is disabled.
Output compare A output is enabled.
371
ICRA (H and L)—Input Capture Register A H'FF98, H'FF99 FRT
Bit
Initial value
Read/Write
14
0
R
12
0
R
10
0
R
8
0
R
6
0
R
0
0
R
4
0
R
2
0
R
Contains FRC count captured on FTIA input.
13
0
R
11
0
R
9
0
R
7
0
R
5
0
R
3
0
R
1
0
R
15
0
R
ICRB (H and L)—Input Capture Register B H'FF9A, H'FF9B FRT
Bit
Initial value
Read/Write
14
0
R
12
0
R
10
0
R
8
0
R
6
0
R
0
0
R
4
0
R
2
0
R
Contains FRC count captured on FTIB input.
13
0
R
11
0
R
9
0
R
7
0
R
5
0
R
3
0
R
1
0
R
15
0
R
ICRC (H and L)—Input Capture Register C H'FF9C, H'FF9D FRT
Bit
Initial value
Read/Write
14
0
R
12
0
R
10
0
R
8
0
R
6
0
R
0
0
R
4
0
R
2
0
R
Contains FRC count captured on FTIC input, or old ICRA value in buffer mode.
13
0
R
11
0
R
9
0
R
7
0
R
5
0
R
3
0
R
1
0
R
15
0
R
372
ICRD (H and L)—Input Capture Register D H'FF9E, H'FF9F FRT
Bit
Initial value
Read/Write
14
0
R
12
0
R
10
0
R
8
0
R
6
0
R
0
0
R
4
0
R
2
0
R
Contains FRC count captured on FTID input, or old ICRB value in buffer mode.
13
0
R
11
0
R
9
0
R
7
0
R
5
0
R
3
0
R
1
0
R
15
0
R
TCR—Timer Control Register [H8/3534 only] H'FFA0 PWM0
Bit
Initial value
Read/Write
7
OE
0
R/W
6
OS
0
R/W
5
—
1
—
4
—
1
—
3
—
1
—
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Clock Select (Values when ø
P
= 10 MHz)
0
1
ø
P
/2
ø
P
/8
ø
P
/32
ø
P
/128
ø
P
/256
ø
P
/1024
ø
P
/2048
ø
P
/4096
Output Enable
0
1
PWM output disabled; TCNT cleared to H'00 and stops.
PWM output enabled; TCNT runs.
0
1
0
1
0
1
0
1
0
1
0
1
Resolution
Internal
clock freq. PWM
period PWM
frequency
200 ns
800 ns
3.2 µs
12.8 µs
25.6 µs
102.4 µs
204.8 µs
409.6 µs
50 µs
200 µs
800 µs
3.2 ms
6.4 ms
25.6 ms
51.2 ms
102.4 ms
20 kHz
5 kHz
1.25 kHz
312.5 Hz
156.3 Hz
39.1 Hz
19.5 Hz
9.8 Hz
Output Select
0
1
PWM direct output
PWM inverse output
373
DTR—Duty Register [H8/3534 only] H'FFA1 PWM0
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Pulse duty cycle
TCNT—Timer Counter [H8/3534 only] H'FFA2 PWM0
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Count value (runs from H'00 to H'F9, then repeats from H'00)
TCR—Timer Control Register [H8/3534 only] H'FFA4 PWM1
Bit
Initial value
Read/Write
7
OE
0
R/W
6
OS
0
R/W
5
—
1
—
4
—
1
—
3
—
1
—
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Note: Bit functions are the same as for PWM0.
DTR—Duty Register [H8/3534 only] H'FFA5 PWM1
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Note: Bit functions are the same as for PWM0.
374
TCNT—Timer Counter [H8/3534 only] H'FFA6 PWM1
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Note: Bit functions are the same as for PWM0.
375
TCSR—Timer Control/Status Register H’FFA8 WDT
Bit
Initial value
Read/Write
7
OVF
0
R/(W)*
6
WT/IT
0
R/W
5
TME
0
R/W
4
—
1
—
3
RST/NMI
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Clock Select 2 to 0
0
1
Timer Enable
0
1
Timer disabled: TCNT is initialized to H’00 and
stopped (initial value)
Timer enabled: TCNT runs; CPU interrupts can be
requested
Timer Mode Select
0
1
Interval timer mode (OVF request)
Watchdog timer mode (reset or NMI request)
Overflow Flag
0
1
Cleared by reading OVF = 1, then writing 1 in OVF (initial value)
Set when TCNT changes from H’FF to H’00
Note: * Only 0 can be written, to clear the flag.
0
1
0
1
ø
P
/2
ø
P
/32
ø
P
/64
ø
P
/128
ø
P
/256
ø
P
/512
ø
P
/2048
ø
P
/4096
0
1
0
1
0
1
0
1
Reset or NMI Select
0
1
Functions as NMI (initial value)
Functions as reset
376
TCNT—Timer Counter H’FFA9 (read), WDT
H’FFA8 (write)
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Count value
P1PCR—Port 1 Input Pull-Up Control Register H'FFAC Port 1
Bit
Initial value
Read/Write
7
P1
7
PCR
0
R/W
6
P1
6
PCR
0
R/W
5
P1
5
PCR
0
R/W
4
P1
4
PCR
0
R/W
3
P1
3
PCR
0
R/W
0
P1
0
PCR
0
R/W
2
P1
2
PCR
0
R/W
1
P1
1
PCR
0
R/W
Port 1 Input Pull-Up Control
0
1Input pull-up transistor is off.
Input pull-up transistor is on.
P2PCR—Port 2 Input Pull-Up Control Register H'FFAD Port 2
Bit
Initial value
Read/Write
7
P2
7
PCR
0
R/W
6
P2
6
PCR
0
R/W
5
P2
5
PCR
0
R/W
4
P2
4
PCR
0
R/W
3
P2
3
PCR
0
R/W
0
P2
0
PCR
0
R/W
2
P2
2
PCR
0
R/W
1
P2
1
PCR
0
R/W
Port 2 Input Pull-Up Control
0
1Input pull-up transistor is off.
Input pull-up transistor is on.
377
P3PCR—Port 3 Input Pull-Up Control Register H'FFAE Port 3
Bit
Initial value
Read/Write
7
P3
7
PCR
0
R/W
6
P3
6
PCR
0
R/W
5
P3
5
PCR
0
R/W
4
P3
4
PCR
0
R/W
3
P3
3
PCR
0
R/W
0
P3
0
PCR
0
R/W
2
P3
2
PCR
0
R/W
1
P3
1
PCR
0
R/W
Port 3 Input Pull-Up Control
0
1Input pull-up transistor is off.
Input pull-up transistor is on.
P1DDR—Port 1 Data Direction Register H'FFB0 Port 1
Bit
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
7
P1
7
DDR
1
—
0
W
6
P1
6
DDR
1
—
0
W
5
P1
5
DDR
1
—
0
W
4
P1
4
DDR
1
—
0
W
3
P1
3
DDR
1
—
0
W
0
P1
0
DDR
1
—
0
W
2
P1
2
DDR
1
—
0
W
1
P1
1
DDR
1
—
0
W
Port 1 Input/Output Control
0
1Input port
Output port
P1DR—Port 1 Data Register H'FFB2 Port 1
Bit
Initial value
Read/Write
7
P1
7
0
R/W
6
P1
6
0
R/W
5
P1
5
0
R/W
4
P1
4
0
R/W
3
P1
3
0
R/W
0
P1
0
0
R/W
2
P1
2
0
R/W
1
P1
1
0
R/W
378
P2DDR—Port 2 Data Direction Register H'FFB1 Port 2
Bit
Mode 1
Initial value
Read/Write
Modes 2 and 3
Initial value
Read/Write
7
P2
7
DDR
1
—
0
W
6
P2
6
DDR
1
—
0
W
5
P2
5
DDR
1
—
0
W
4
P2
4
DDR
1
—
0
W
3
P2
3
DDR
1
—
0
W
0
P2
0
DDR
1
—
0
W
2
P2
2
DDR
1
—
0
W
1
P2
1
DDR
1
—
0
W
Port 2 Input/Output Control
0
1Input port
Output port
P2DR—Port 2 Data Register H'FFB3 Port 2
Bit
Initial value
Read/Write
7
P2
7
0
R/W
6
P2
6
0
R/W
5
P2
5
0
R/W
4
P2
4
0
R/W
3
P2
3
0
R/W
0
P2
0
0
R/W
2
P2
2
0
R/W
1
P2
1
0
R/W
P3DDR—Port 3 Data Direction Register H'FFB4 Port 3
Bit
Initial value
Read/Write
7
P3
7
DDR
0
W
6
P3
6
DDR
0
W
5
P3
5
DDR
0
W
4
P3
4
DDR
0
W
3
P3
3
DDR
0
W
0
P3
0
DDR
0
W
2
P3
2
DDR
0
W
1
P3
1
DDR
0
W
Port 3 Input/Output Control
0
1Input port
Output port
379
P3DR—Port 3 Data Register H'FFB6 Port 3
Bit
Initial value
Read/Write
7
P3
7
0
R/W
6
P3
6
0
R/W
5
P3
5
0
R/W
4
P3
4
0
R/W
3
P3
3
0
R/W
0
P3
0
0
R/W
2
P3
2
0
R/W
1
P3
1
0
R/W
P4DDR—Port 4 Data Direction Register [H8/3534] H'FFB5 Port 4
Bit
Initial value
Read/Write
7
P4
7
DDR
0
W
6
P4
6
DDR
0
W
5
P4
5
DDR
0
W
4
P4
4
DDR
0
W
3
P4
3
DDR
0
W
0
P4
0
DDR
0
W
2
P4
2
DDR
0
W
1
P4
1
DDR
0
W
Port 4 Input/Output Control
0
1Input port
Output port
P4DR—Port 4 Data Register [H8/3534] H'FFB7 Port 4
Bit
Initial value
Read/Write
7
P4
7
0
R/W
6
P4
6
0
R/W
5
P4
5
0
R/W
4
P4
4
0
R/W
3
P4
3
0
R/W
0
P4
0
0
R/W
2
P4
2
0
R/W
1
P4
1
0
R/W
380
P4DDR—Port 4 Data Direction Register [H8/3522] H'FFB5 Port 4
Bit
Initial value
Read/Write
Modes 1
and 2
7
P4
7
DDR
0
W
6
P4
6
DDR
1
—
5
P4
5
DDR
0
W
4
P4
4
DDR
0
W
3
P4
3
DDR
0
W
0
P4
0
DDR
0
W
2
P4
2
DDR
0
W
1
P4
1
DDR
0
W
0
W0
W0
W0
W0
W0
W
0
W0
W
Port 4 Input/Output Control
0
1Input port
Output port
Initial value
Read/Write
Mode 3
P4DR—Port 4 Data Register [H8/3522] H'FFB7 Port 4
Bit
Initial value
Read/Write
7
P4
7
0
R/W
6
P4
6
—*
R
5
P4
5
0
R/W
4
P4
4
0
R/W
3
P4
3
0
R/W
0
P4
0
0
R/W
2
P4
2
0
R/W
1
P4
1
0
R/W
Note: * Depends on the level at pin P4
6
.
P5DDR—Port 5 Data Direction Register H'FFB8Port 5
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
P5
0
DDR
0
W
2
P5
2
DDR
0
W
1
P5
1
DDR
0
W
Port 5 Input/Output Control
0
1Input port
Output port
381
P5DR—Port 5 Data Register H'FFBA Port 5
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
P5
0
0
R/W
2
P5
2
0
R/W
1
P5
1
0
R/W
P6DDR—Port 6 Data Direction RegisterH'FFB9 Port 6
Bit
Initial value
Read/Write
7
P6
7
DDR
0
W
6
P6
6
DDR
0
W
5
P6
5
DDR
0
W
4
P6
4
DDR
0
W
3
P6
3
DDR
0
W
0
P6
0
DDR
0
W
2
P6
2
DDR
0
W
1
P6
1
DDR
0
W
Port 6 Input/Output Control
0
1Input port
Output port
P6DR—Port 6 Data Register H'FFBB Port 6
Bit
Initial value
Read/Write
7
P6
7
0
R/W
6
P6
6
0
R/W
5
P6
5
0
R/W
4
P6
4
0
R/W
3
P6
3
0
R/W
0
P6
0
0
R/W
2
P6
2
0
R/W
1
P6
1
0
R/W
P7PIN—Port 7 Input Data Register H'FFBE Port 7
Bit
Initial value
Read/Write
7
P77
—*
R
6
P76
—*
R
5
P75
—*
R
4
P74
—*
R
3
P73
—*
R
0
P70
—*
R
2
P72
—*
R
1
P71
—*
R
Note: Depends on the levels of pins P77 to P70.*
382
P8DDR—Port 8 Data Direction Register [H8/3534 only] H'FFBD Port 8
Bit
Initial value
Read/Write
7
—
1
—
6
P8
6
DDR
0
W
5
P8
5
DDR
0
W
4
P8
4
DDR
0
W
3
P8
3
DDR
0
W
0
P8
0
DDR
0
W
2
P8
2
DDR
0
W
1
P8
1
DDR
0
W
Port 8 Input/Output Control
0
1Input port
Output port
P8DR—Port 8 Data Register [H8/3534 only] H'FFBF Port 8
Bit
Initial value
Read/Write
7
—
1
—
6
P8
6
0
R/W
5
P8
5
0
R/W
4
P8
4
0
R/W
3
P8
3
0
R/W
0
P8
0
0
R/W
2
P8
2
0
R/W
1
P8
1
0
R/W
383
P9DDR—Port 9 Data Direction Register [H8/3534 only] H'FFC0 Port 9
Bit
Modes 1 and 2
Initial value
Read/Write
Mode 3
Initial value
Read/Write
7
P9
7
DDR
0
W
0
W
6
P9
6
DDR
1
—
0
W
5
P9
5
DDR
0
W
0
W
4
P9
4
DDR
0
W
0
W
3
P9
3
DDR
0
W
0
W
0
P9
0
DDR
0
W
0
W
2
P9
2
DDR
0
W
0
W
1
P9
1
DDR
0
W
0
W
Port 9 Input/Output Control
0
1Input port
Output port
P9DR—Port 9 Data Register [H8/3534 only] H'FFC1 Port 9
Bit
Initial value
Read/Write
7
P97
0
R/W
6
P96
—*
R
5
P95
0
R/W
4
P94
0
R/W
3
P93
0
R/W
0
P90
0
R/W
2
P92
0
R/W
1
P91
0
R/W
Note: Depends on the level of pin P96.
*
384
WSCR—Wait-State Control Register [H8/3534] H'FFC2 System control
Bit
Initial value
Read/Write
7
(RAMS)
0
R/W
6
(RAM0)
0
R/W
5
CKDBL
0
R/W
4
—
0
R/W
3
WMS1
1
R/W
0
WC0
0
R/W
2
WMS0
0
R/W
1
WC1
0
R/W
Wait Count
0
0
1
1
0
1
0
1
No wait states inserted by wait-state controller (initial value)
1 state inserted
2 states inserted
3 states inserted
Wait Mode Select
Clock Double
0
1Supporting module clock frequency is not divided (ø
P
= ø) (initial value)
Supporting module clock frequency is divided by two (ø
P
= ø/2)
0
0
1
1
0
1
0
1
Programmable wait mode
No wait states inserted by wait-state controller
Pin wait mode (initial value)
Pin auto-wait mode
Note: Do not write 1 to bits RAMS and RAM0.
385
WSCR—Wait-State Control Register [H8/3522] H'FFC2 System control
Bit
Initial value
Read/Write
7
—
0
R/W
6
—
0
R/W
5
CKDBL
0
R/W
4
—
0
R/W
3
WMS1
1
R/W
0
WC0
0
R/W
2
WMS0
0
R/W
1
WC1
0
R/W
Wait Count
0
0
1
1
0
1
0
1
No wait states inserted by wait-state controller (initial value)
1 state inserted
2 states inserted
3 states inserted
Wait Mode Select
Clock Double
0
1Supporting module clock frequency is not divided (øP = ø) (initial value)
Supporting module clock frequency is divided by two (øP = ø/2)
0
0
1
1
0
1
0
1
Programmable wait mode
No wait states inserted by wait-state controller
Pin wait mode (initial value)
Pin auto-wait mode
386
STCR—Serial/Timer Control Register [H8/3534] H'FFC3 System Control
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
ICKS0
0
R/W
2
MPE
0
R/W
1
ICKS1
0
R/W
Internal Clock Source Select
See TCR under TMR0 and TMR1.
Multiprocessor Enable
0
1Multiprocessor communication function is disabled.
Multiprocessor communication function is enabled.
STCR—Serial/Timer Control Register [H8/3522] H'FFC3 System Control
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
ICKS0
0
R/W
2
MPE
0
R/W
1
ICKS1
0
R/W
Internal Clock Source Select
See TCR under TMR0 and TMR1.
Multiprocessor Enable
0
1Multiprocessor communication function is disabled.
Multiprocessor communication function is enabled.
387
SYSCR—System Control Register [H8/3534] H'FFC4 System Control
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
(HIE)
0
R/W
RAM Enable
0
1On-chip RAM is disabled.
On-chip RAM is enabled. (initial value)
Standby Timer Select 2 to 0
0
0
0
0
1
1
Clock settling time = 8,192 states (initial value)
Clock settling time = 16,384 states
Clock settling time = 32,768 states
Clock settling time = 65,536 states
Clock settling time = 131,072 states
Unused
Software Standby
0
1SLEEP instruction causes transition to sleep mode. (initial value)
SLEEP instruction causes transition to software standby mode.
0
0
1
1
0
1
0
1
0
1
—
—
NMI Edge
0
1Falling edge of NMI is detected. (initial value)
Rising edge of NMI is detected.
External Reset
0
1Reset was caused by watchdog timer overflow
Reset was caused by external reset signal (initial value)
Note: Do not write 1 to bit HIE.
388
SYSCR—System Control Register [H8/3522] H'FFC4System Control
Bit
Initial value
Read/Write
7
SSBY
0
R/W
6
STS2
0
R/W
5
STS1
0
R/W
4
STS0
0
R/W
3
XRST
1
R
0
RAME
1
R/W
2
NMIEG
0
R/W
1
—
1
—
RAM Enable
0
1On-chip RAM is disabled.
On-chip RAM is enabled. (initial value)
Standby Timer Select 2 to 0
0
0
0
0
1
1
Clock settling time = 8,192 states (initial value)
Clock settling time = 16,384 states
Clock settling time = 32,768 states
Clock settling time = 65,536 states
Clock settling time = 131,072 states
Unused
Software Standby
0
1SLEEP instruction causes transition to sleep mode. (initial value)
SLEEP instruction causes transition to software standby mode.
0
0
1
1
0
1
0
1
0
1
—
—
NMI Edge
0
1Falling edge of NMI is detected. (initial value)
Rising edge of NMI is detected.
External Reset
0
1Reset was caused by watchdog timer overflow
Reset was caused by external reset signal (initial value)
389
MDCR—Mode Control Register H'FFC5System Control
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
0
—
3
—
0
—
0
MDS0
—*
R
2
—
1
—
1
MDS1
—*
R
Mode Select Bits
Value at mode pins.
Note: Determined by inputs at pins MD
1
and MD
0
.
*
ISCR—IRQ Sense Control Register [H8/3534] H'FFC6System Control
Bit
Initial value
Read/Write
7
IRQ7SC
0
R/W
6
IRQ6SC
0
R/W
5
IRQ5SC
0
R/W
4
IRQ4SC
0
R/W
3
IRQ3SC
0
R/W
0
IRQ0SC
0
R/W
2
IRQ2SC
0
R/W
1
IRQ1SC
0
R/W
IRQ0 to IRQ7 Sense Control
0
1IRQ
0
to IRQ
7
are level-sensed (active low).
IRQ
0
to IRQ
7
are edge-sensed (falling edge).
IER—IRQ Enable Register [H8/3534] H'FFC7System Control
Bit
Initial value
Read/Write
7
IRQ7E
0
R/W
6
IRQ6E
0
R/W
5
IRQ5E
0
R/W
4
IRQ4E
0
R/W
3
IRQ3E
0
R/W
0
IRQ0E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
IRQ0 to IRQ7 Enable
0
1IRQ
0
to IRQ
7
are disabled.
IRQ
0
to IRQ
7
are enabled.
390
ISCR—IRQ Sense Control Register [H8/3522] H'FFC6System Control
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IRQ0SC
0
R/W
2
IRQ2SC
0
R/W
1
IRQ1SC
0
R/W
IRQ0 to IRQ2 Sense Control
0
1IRQ
0
to IRQ
2
are level-sensed (active low).
IRQ
0
to IRQ
2
are edge-sensed (falling edge).
IER—IRQ Enable Register [H8/3522] H'FFC7System Control
Bit
Initial value
Read/Write
7
—
1
—
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
IRQ0E
0
R/W
2
IRQ2E
0
R/W
1
IRQ1E
0
R/W
IRQ0 to IRQ2 Enable
0
1IRQ
0
to IRQ
2
are disabled.
IRQ
0
to IRQ
2
are enabled.
391
TCR—Timer Control Register H'FFC8TMR0
Bit
Initial value
Read/Write
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Clock Select
CKS2
0
0
0
0
0
0
0
1
1
1
1
Timer stopped (Initial value)
ø
P
/8 internal clock, falling edge
ø
P
/2 internal clock, falling edge
ø
P
/64 internal clock, falling edge
ø
P
/32 internal clock, falling edge
ø
P
/1024 internal clock, falling edge
ø
P
/256 internal clock, falling edge
Timer stopped
External clock, rising edge
External clock, falling edge
External clock, rising and falling edges
Counter Clear
0
0
1
1
Counter is not cleared.
Cleared by compare-match A.
Cleared by compare-match B.
Cleared on rising edge of external reset input.
Timer Overflow Interrupt Enable
Compare-Match Interrupt Enable A
0
1
Compare-match A interrupt request is disabled.
Compare-match A interrupt request is enabled.
Compare-Match Interrupt Enable B
0
1
Compare-match B interrupt request is disabled.
Compare-match B interrupt request is enabled.
0
1
Timer overflow interrupt request is disabled.
Timer overflow interrupt request is enabled.
0
1
0
1
CKS1
0
0
0
1
1
1
1
0
0
1
1
CKS0
0
1
1
0
0
1
1
0
1
0
1
ICKS1
—
—
—
—
—
—
—
—
—
—
—
ICKS0
—
0
1
0
1
0
1
—
—
—
—
TCR STCR Description
Bit 2 Bit 1 Bit 0 Bit 1 Bit 0
392
TCSR—Timer Control/Status Register H'FFC9TMR0
Bit
Initial value
Read/Write
7
CMFB
0
R/(W)
6
CMFA
0
R/(W)
5
OVF
0
R/(W)
4
—
1
—
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
Output Select
0
0
1
1
No change on compare-match A.
Output 0 on compare-match A.
Output 1 on compare-match A.
Invert (toggle) output on compare-match A.
Output Select
0
0
1
1
No change on compare-match B.
Output 0 on compare-match B.
Output 1 on compare-match B.
Invert (toggle) output on compare-match B.
Timer Overflow Flag
0
1
Cleared by reading OVF = 1, then writing 0 in OVF.
Set when TCNT changes from H'FF to H'00.
Compare-Match Flag A
0
1
Cleared by reading CMFA = 1, then writing 0 in CMFA.
Set when TCNT = TCORA.
Compare-Match Flag B
0
1
Cleared by reading CMFB = 1, then writing 0 in CMFB.
Set when TCNT = TCORB.
When all four bits (OS3 to OS0) are cleared to 0, output is disabled.
Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits.
Notes: 1.
2.
*2 *2 *2
*1 *1 *1 *1
0
1
0
1
0
1
0
1
393
TCORA—Time Constant Register A H'FFCA TMR0
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
The CMFA bit is set to 1 when TCORA = TCNT.
TCORB—Time Constant Register B H'FFCB TMR0
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
The CMFB bit is set to 1 when TCORB = TCNT.
TCNT—Timer Counter H'FFCC TMR0
Bit
Initial value
Read/Write
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
Count value
394
TCR—Timer Control Register H'FFD0TMR1
Bit
Initial value
Read/Write
7
CMIEB
0
R/W
6
CMIEA
0
R/W
5
OVIE
0
R/W
4
CCLR1
0
R/W
3
CCLR0
0
R/W
0
CKS0
0
R/W
2
CKS2
0
R/W
1
CKS1
0
R/W
Clock Select
CKS2
0
0
0
0
0
0
0
1
1
1
1
Timer stopped
ø
P
/8 internal clock, falling edge
ø
P
/2 internal clock, falling edge
ø
P
/64 internal clock, falling edge
ø
P
/128 internal clock, falling edge
ø
P
/1024 internal clock, falling edge
ø
P
/2048 internal clock, falling edge
Timer stopped
External clock, rising edge
External clock, falling edge
External clock, rising and falling edges
Counter Clear
0
0
1
1
Counter is not cleared.
Cleared by compare-match A.
Cleared by compare-match B.
Cleared on rising edge of external reset input.
Timer Overflow Interrupt Enable
Compare-Match Interrupt Enable A
0
1
Compare-match A interrupt request is disabled.
Compare-match A interrupt request is enabled.
Compare-Match Interrupt Enable B
0
1
Compare-match B interrupt request is disabled.
Compare-match B interrupt request is enabled.
0
1
Timer overflow interrupt request is disabled.
Timer overflow interrupt request is enabled.
0
1
0
1
CKS1
0
0
0
1
1
1
1
0
0
1
1
CKS0
0
1
1
0
0
1
1
0
1
0
1
ICKS1
—
0
1
0
1
0
1
—
—
—
—
ICKS0
—
—
—
—
—
—
—
—
—
—
—
TCR STCR
Description
Bit 2 Bit 1 Bit 0 Bit 1 Bit 0
395
TCSR—Timer Control/Status Register H'FFD1TMR1
Bit
Initial value
Read/Write
7
CMFB
0
R/(W)
6
CMFA
0
R/(W)
5
OVF
0
R/(W)
4
—
1
—
3
OS3
0
R/W
0
OS0
0
R/W
2
OS2
0
R/W
1
OS1
0
R/W
*2 *2 *2
*1 *1 *1 *1
Bit functions are the same as for TMR0.
1. When all four bits (OS3 to OS0) are cleared to 0, output is disabled.
2. Software can write a 0 in bits 7 to 5 to clear the flags, but cannot write a 1 in these bits.
Notes:
TCORA—Time Constant Register A H'FFD2TMR1
Bit
Initial value
Read/Write
Note: Bit functions are the same as for TMR0.
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
TCORB—Time Constant Register B H'FFD3TMR1
Bit
Initial value
Read/Write
Note: Bit functions are the same as for TMR0.
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
396
TCNT—Timer Counter H'FFD4TMR1
Bit
Initial value
Read/Write
Note: Bit functions are the same as for TMR0.
7
0
R/W
6
0
R/W
5
0
R/W
4
0
R/W
3
0
R/W
0
0
R/W
2
0
R/W
1
0
R/W
397
SMR—Serial Mode Register H'FFD8SCI0
Bit
Initial value
Read/Write
7
C/A
0
R/W
6
CHR
0
R/W
5
PE
0
R/W
4
O/E
0
R/W
3
STOP
0
R/W
0
CKS0
0
R/W
2
MP
0
R/W
1
CKS1
0
R/W
Clock Select
0
0
1
1
0
1
0
1
ø clock
øP/4 clock
øP/16 clock
øP/64 clock
Multiprocessor Mode
0
1
Multiprocessor function disabled
Multiprocessor function enabled
Stop Bit Length
0
1
One stop bit
Two stop bits
Parity Mode
0
1
Even parity
Odd parity
Parity Enable
0Transmit:
Receive:
Character Length
0
1
8-bit per character
7-bit per character
Communication Mode
0
1
Asynchronous
Synchronous
Transmit:
Receive:
1
No parity bit added.
Parity bit not checked.
Parity bit added.
Parity bit checked.
Note: Bit functions are the same as for SCI1.
398
BRR—Bit Rate Register H'FFD9SCI0
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Constant that determines the bit rate
Note: Bit functions are the same as for SCI1.
399
SCR—Serial Control Register H'FFDA SCI0
Bit
Initial value
Read/Write
7
TIE
0
R/W
6
RIE
0
R/W
5
TE
0
R/W
4
RE
0
R/W
3
MPIE
0
R/W
0
CKE0
0
R/W
2
TEIE
0
R/W
1
CKE1
0
R/W
Clock Enable 0
0
1
SCK pin not used
SCK pin used for serial clock output.
Clock Enable 1
0
1
Internal clock
External clock
Transmit End Interrupt Enable
0
1
TSR-empty interrupt request is disabled.
TSR-empty interrupt request is enabled.
Multiprocessor Interrupt Enable
0
1
Multiprocessor receive interrupt function is disabled.
Multiprocessor receive interrupt function is enabled.
Receive Enable
0
1
Receive disabled
Receive enabled
Transmit Enable
0
1
Transmit disabled
Transmit enabled
Receive Interrupt Enable
0
1
Receive end interrupt and receive error requests are disabled.
Receive end interrupt and receive error requests are enabled.
Transmit Interrupt Enable
0
1
TDR-empty interrupt request is disabled.
TDR-empty interrupt request is enabled.
Note: Bit functions are the same as for SCI1.
400
TDR—Transmit Data Register H'FFDB SCI0
Bit
Initial value
Read/Write
7
1
R/W
6
1
R/W
5
1
R/W
4
1
R/W
3
1
R/W
0
1
R/W
2
1
R/W
1
1
R/W
Note: Bit functions are the same as for SCI1.
Transmit data
401
SSR—Serial Status Register H'FFDC SCI0
Bit
Initial value
Read/Write
7
TDRE
1
R/(W)
6
RDRF
0
R/(W)
5
ORER
0
R/(W)
4
FER
0
R/(W)
3
PER
0
R/(W)
0
MPBT
0
R/W
2
TEND
1
R
1
MPB
0
R
Multiprocessor Bit Transfer
0
1
Multiprocessor bit = 0 in transmit data. (Initial Value)
Multiprocessor bit = 1 in transmit data.
Multiprocessor Bit
Transmit End
0
1
Cleared by reading TDRE = 1, then writing 0 in TDRE.
Set to 1 when TE = 0, or when TDRE = 1 at the end of
character transmission. (Initial Value)
Parity Error
0
1
Cleared by reading PER = 1, then writing 0 in PER. (Initial Value)
Set when a parity error occurs (parity of receive data
does not match parity selected by O/E bit in SMR).
Framing Error
0
1
Cleared by reading FER = 1, then writing 0 in FER. (Initial Value)
Set when a framing error occurs (stop bit is 0).
Overrun Error
0
1
Cleared by reading ORER = 1, then writing 0 in ORER. (Initial Value)
Set when an overrun error occurs (next data is completely
received while RDRF bit is set to 1).
Receive Data Register Full
0
1
Cleared by reading RDRF = 1, then writing 0 in RDRF. (Initial Value)
Set when one character is received normally and transferred from RSR to RDR.
Transmit Data Register Empty
0
1
Cleared by reading TDRE = 1, then writing 0 in TDRE.
Set when: (Initial Value)
1. Data is transferred from TDR to TSR.
2. TE is cleared to 0 while TDRE = 0.
*
*
*
*
*
0
1
Multiprocessor bit = 0 in receive data. (Initial Value)
Multiprocessor bit = 1 in receive data.
Software can write a 0 in bits 7 to 3 to clear the flags, but cannot write a 1 in these bits.
Bit functions are the same as for SCI1.
Note: *
402
RDR—Receive Data Register H'FFDD SCI0
Bit
Initial value
Read/Write
Note: Bit functions are the same as for SCI1.
7
0
R
6
0
R
5
0
R
4
0
R
3
0
R
0
0
R
2
0
R
1
0
R
Receive data
ADDRA (H and L)—A/D Data Register A H'FFE0, H'FFE1 A/D
Bit
Initial value
Read/Write
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
A/D Conversion Data
10-bit data giving an A/D conversion result
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
ADDRA H ADDRA L
Reserved Bits
ADDRB (H and L)—A/D Data Register B H'FFE2, H'FFE3 A/D
Bit
Initial value
Read/Write
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
A/D Conversion Data
10-bit data giving an A/D conversion result
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
ADDRB H ADDRB L
Reserved Bits
403
ADDRC (H and L)—A/D Data Register C H'FFE4, H'FFE5 A/D
Bit
Initial value
Read/Write
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
A/D Conversion Data
10-bit data giving an A/D conversion result
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
ADDRC H ADDRC L
Reserved Bits
ADDRD (H and L)—A/D Data Register D H'FFE6, H'FFE7 A/D
Bit
Initial value
Read/Write
14
AD8
0
R
12
AD6
0
R
10
AD4
0
R
8
AD2
0
R
6
AD0
0
R
0
—
0
R
4
—
0
R
2
—
0
R
A/D Conversion Data
10-bit data giving an A/D conversion result
15
AD9
0
R
13
AD7
0
R
11
AD5
0
R
9
AD3
0
R
7
AD1
0
R
1
—
0
R
5
—
0
R
3
—
0
R
ADDRD H ADDRD L
Reserved Bits
404
ADCSR—A/D Control/Status Register H'FFE8A/D
Bit
Initial value
Read/Write
7
ADF
0
R/(W)
6
ADIE
0
R/W
5
ADST
0
R/W
4
SCAN
0
R/W
3
CKS
0
R/W
0
CH0
0
R/W
2
CH2
0
R/W
1
CH1
0
R/W
Channel Select
Clock Select
0
1
Conversion time = 266 states (max)
Conversion time = 134 states (max)
*
Note: * Only 0 can be written, to clear the flag.
CH2
0
1
CH1
0
1
0
1
CH0
0
1
0
1
0
1
0
1
Single Mode
AN0
AN1
AN2
AN3
AN4
AN5
AN6
AN7
Scan Mode
AN0
AN0, AN1
AN0 to AN2
AN0 to AN3
AN4
AN4, AN5
AN4 to AN6
AN4 to AN7
Scan Mode
0
1
Single mode
Scan mode
A/D Start
0
1
A/D conversion is halted.
A/D Interrupt Enable
0
1
The A/D interrupt request (ADI) is disabled.
The A/D interrupt request (ADI) is enabled.
A/D End Flag
0
1
Cleared from 1 to 0 when CPU reads ADF = 1, then writes 0 in ADF.
Set to 1 at the following times:
1. Single mode: at the completion of A/D conversion
2. Scan mode: when all selected channels have been converted.
Single mode:
One A/D conversion is performed, then this bit is automatically cleared to 0.
Scan mode:
A/C conversion starts and continues cyclically on all selected channels until 0 is
written in this bit.
1.
2.
Note: øP = ø
Group Selection Channel Selection
Description
405
ADCR—A/D Control Register H'FFE9A/D
Trigger Enable
0
1
ADTRG is disabled.
ADTRG is enabled. A/D conversion can be started by external trigger,
or by software.
Bit
Initial value
Read/Write
7
TRGE
0
R/W
6
—
1
—
5
—
1
—
4
—
1
—
3
—
1
—
0
—
1
—
2
—
1
—
1
—
1
—
KMIMR—Keyboard Matrix Interrupt Mask Register H'FFF1HIF
[H8/3534 only]
Bit
Initial value
Read/Write
7
KMIMR7
1
R/W
6
KMIMR6
0
R/W
5
KMIMR5
1
R/W
4
KMIMR4
1
R/W
3
KMIMR3
1
R/W
0
KMIMR0
1
R/W
2
KMIMR2
1
R/W
1
KMIMR1
1
R/W
Keyboard Matrix Interrupt Mask
0
1Key-sense input interrupt request enabled
Key-sense input interrupt request disabled (initial value)*
Note: * Initial value of KMIMR6 is 0.
KMPCR—Port 6 Input Pull-Up Control Register H'FFF2HIF
[H8/3534 only]
Bit
Initial value
Read/Write
7
KM
7
PCR
0
R/W
6
KM
6
PCR
0
R/W
5
KM
5
PCR
0
R/W
4
KM
4
PCR
0
R/W
3
KM
3
PCR
0
R/W
0
KM
0
PCR
0
R/W
2
KM
2
PCR
0
R/W
1
KM
1
PCR
0
R/W
Port 6 Input Pull-Up Control
0
1
Input pull-up transistor is off. (Initial value)
Input pull-up transistor is on.
406
407
Appendix C I/O Port Block Diagrams
C.1 Port 1 Block Diagram
WP1P:
WP1D:
WP1:
RP1P:
RP1:
n = 0 to 7
Note: *Set priority
Write to P1PCR
Write to P1DDR
Write to port 1
Read P1PCR
Read port 1
Reset
R
QD
C
P1
n
PCR
WP1P
ResetMode 1
RS
QD
C
P1
n
DDR
P1
n
WP1D
Reset
R
QD
C
P1
n
DR
WP1
RP1
*
RP1P
Hardware standby
Mode 3
Mode 1 or 2
Internal data bus
Internal lower address bus
Figure C-1 Port 1 Block Diagram
408
C.2 Port 2 Block Diagram
WP2P:
WP2D:
WP2:
RP2P:
RP2:
n = 0 to 7
Note: *Set priority
Write to P2PCR
Write to P2DDR
Write to port 2
Read P2PCR
Read port 2
Reset
R
QD
C
P2
n
PCR
WP2P
ResetMode 1
RS
QD
C
P2
n
DDR
P2
n
WP2D
Reset
R
QD
C
P2
n
DR
WP2
RP2
*
RP2P
Hardware standby
Mode 3
Mode 1 or 2
Internal data bus
Internal lower address bus
Figure C-2 Port 2 Block Diagram
409
C.3 Port 3 Block Diagram
WP3P:
WP3D:
WP3:
RP3P:
RP3:
n = 0 to 7
Write to P3PCR
Write to P3DDR
Write to port 3
Read P3PCR
Read port 3
Reset
R
QD
C
P3
n
PCR
WP3P
P3
n
External address
write
RP3P
Mode 3
Mode 1 or 2
R
QD
C
P3
n
DDR
WP3D
Reset
RD
C
P3
n
DR
Reset
WP3
Mode 3
Q
Internal data bus
External address
read
RP3
Figure C-3 Port 3 Block Diagram
410
C.4 Port 4 Block Diagrams [H8/3534]
WP4D:
WP4:
RP4:
n = 0, 2, 3, 5
Write to P4DDR
Write to port 4
Read port 4
Reset
R
QD
C
P4
n
DDR
WP4D
Reset
R
QD
C
P4
n
DR
WP4
P4
n
RP4
8-bit timer
Counter clock input
Counter reset input
Internal data bus
Figure C-4 (a) Port 4 Block Diagram (Pins P40, P42, P43, P45) [H8/3534]
411
WP4D:
WP4:
RP4:
n = 1, 4, 6, 7
Reset
8-bit timer output
Write to P4DDR
Write to port 4
Read port 4
Output enable
8-bit timer, PWM timer
R
QD
C
P4nDR
WP4
Reset
R
QD
C
P4
n
DDR
WP4D
P4
n
RP4
Internal data bus
PWM timer output
Figure C-4 (b) Port 4 Block Diagram (Pins P41, P44, P46, P47) [H8/3534]
412
C.5 Port 5 Block Diagrams
WP5D:
WP5:
RP5:
Reset
Serial transmit data
Write to P5DDR
Write to port 5
Read port 5
Output enable
SCI
R
QD
C
P50DR
WP5
Reset
R
QD
C
P50DDR
WP5D
P50
RP5
Internal data bus
Figure C-5 (a) Port 5 Block Diagram (Pin P50)
413
WP5D:
WP5:
RP5:
Reset
Serial receive data
Write to P5DDR
Write to port 5
Read port 5
Input enable
SCI
R
QD
C
P51DR
WP5
Reset
R
QD
C
P51DDR
WP5D
P51
RP5
Internal data bus
Figure C-5 (b) Port 5 Block Diagram (Pin P51)
414
WP5D:
WP5:
RP5:
Reset
Clock output
Write to P5DDR
Write to port 5
Read port 5
Clock output enable
SCI
R
QD
C
P52DR
WP5
Reset
R
QD
C
P52DDR
WP5D
P52
RP5
Clock input
Clock input enable
Internal data bus
Figure C-5 (c) Port 5 Block Diagram (Pin P52)
415
C.6 Port 6 Block Diagrams
WP6D:
WP6:
RP6:
RP6P:
WP6P:
n = 0, 2, 3, 4, 5
Write to P6DDR
Write to port 6
Read port 6
Read KMPCR
Write to KMPCR
Reset
R
QD
C
P6
n
DDR
WP6D
Reset
R
QD
C
P6
n
DR
WP6
P6
n
RP6
Free-running timer
Input capture input
Counter clock input
Internal data bus
Reset
WP6P
RP6P
Hardware standby
R
QD
C
KM
n
PCR
Key-sense interrupt input
KMIMR
n
Schmitt input
Figure C-6 (a) Port 6 Block Diagram (Pins P60, P62, P63, P64, P65) [H8/3534]
416
WP6D:
WP6:
RP6:
RP6P:
WP6P:
Reset
Output compare output
Write to P6DDR
Write to port 6
Read port 6
Read KMPCR
Write to KMPCR
Output enable
Free-running timer
R
QD
C
P6
1
DR
WP6
Reset
R
QD
C
P6
1
DDR
WP6D
P6
1
RP6
Internal data bus
Key-sense interrupt input
KMIMR
1
Reset
WP6P
RP6P
Hardware standby
R
QD
C
KM
1
PCR
Schmitt input
Figure C-6 (b) Port 6 Block Diagram (Pin P61) [H8/3534]
417
Reset
WP6P
RP6P
Hardware standby
R
QD
C
KM6PCR
WP6D:
WP6:
RP6:
RP6P:
WP6P:
Reset
Output compare
output
Write to P6DDR
Write to port 6
Read port 6
Read KMPCR
Write to KMPCR
Output enable
Free-running timer
IRQ enable register
R
QD
C
P66DR
WP6
Reset
R
QD
C
P66DDR
WP6D
P66
RP6
IRQ6 enable
IRQ6 input
Internal data bus
KMIMR6
Other key-sense
interrupt inputs
Schmitt input
Figure C-6 (c) Port 6 Block Diagram (Pin P66) [H8/3534]
418
Reset
WP6P
RP6P
Hardware standby
R
QD
C
KM
7
PCR
Reset
R
QD
C
P6
7
DDR
WP6D
Reset
R
QD
C
P6
7
DR
WP6
P6
7
RP6
WP6D:
WP6:
RP6:
RP6P:
WP6P:
Write to P6DDR
Write to port 6
Read port 6
Read KMPCR
Write to KMPCR
IRQ enable register
IRQ7 enable
IRQ7 input
Internal data bus
KMIMR
7
Key-sense interrupt input
Schmitt input
Figure C-6 (d) Port 6 Block Diagram (Pin P67) [H8/3534]
419
WP6D:
WP6:
RP6:
Write to P6DDR
Write to port 6
Read port 6
Reset
R
QD
C
P6
n
DDR
WP6D
Reset
R
QD
C
P6
n
DR
WP6
P6
n
RP6
Schmitt input
Free-running timer
8-bit timer
Counter clock input
Counter clock input
Internal data bus
Figure C-6 (e) Port 6 Block Diagram (Pin P60) [H8/3522]
420
WP6D:
WP6:
RP6:
Reset
Output compare output
Write to P6DDR
Write to port 6
Read port 6
Output enable
Free-running timer
R
QD
C
P61DR
WP6
Reset
R
QD
C
P61DDR
WP6D
P61
RP6
Internal data bus
Schmitt input
Figure C-6 (f) Port 6 Block Diagram (Pin P61) [H8/3522]
421
WP6D:
WP6:
RP6:
Write to P6DDR
Write to port 6
Read port 6
Reset
R
QD
C
P6
2
DDR
WP6D
Reset
R
QD
C
P6
2
DR
WP6
P6
2
RP6
Free-running timer
Input capture input
Internal data bus
Schmitt input
Figure C-6 (g) Port 6 Block Diagram (Pin P62) [H8/3522]
422
WP6D:
WP6:
RP6:
n= 3, 5
Write to P6DDR
Write to port 6
Read port 6
Reset
R
QD
C
P6
n
DDR
WP6D
Reset
R
QD
C
P6
n
DR
WP6
P6
n
RP6
Free-running timer
8-bit timer
Input capture input
Counter clock input
Counter reset input
Internal data bus
Schmitt input
Figure C-6 (h) Port 6 Block Diagram (Pins P63, P65) [H8/3522]
423
WP6D:
WP6:
RP6:
Reset
8-bit timer output
Write to P6DDR
Write to port 6
Read port 6
Output enable
8-bit timer
Free-running timer
Input capture input
R
QD
C
P64
DR
WP6
Reset
R
QD
C
P6
4
DDR
WP6D
P6
4
RP6
Internal data bus
Schmitt input
Figure C-6 (i) Port 6 Block Diagram (Pins P64) [H8/3522]
424
WP6D:
WP6:
RP6:
Reset
Output compare output
Write to P6DDR
Write to port 6
Read port 6
Output enable
8-bit timer
Free-running timer
Counter reset input
R
QD
C
P66DR
WP6
Reset
R
QD
C
P66DDR
WP6D
P66
RP6
Internal data bus
Schmitt input
Figure C-6 (j) Port 6 Block Diagram (Pins P66) [H8/3522]
425
WP6D:
WP6:
RP6:
Reset
8-bit timer output
Write to P6DDR
Write to port 6
Read port 6
Output enable
8-bit timer
R
QD
C
P6
7
DR
WP6
Reset
R
QD
C
P6
7
DDR
WP6D
P6
7
RP6
Internal data bus
Schmitt input
Figure C-6 (k) Port 6 Block Diagram (Pins P67) [H8/3522]
426
C.7 Port 7 Block Diagram
P7n
RP7:
n = 0 to 7
Read port 7
A/D converter
Analog input
Internal data bus
RP7
Figure C-7 Port 7 Block Diagram (Pins P70 to P77)
427
C.8 Port 8 Block Diagrams
WP8D:
WP8:
RP8:
n:
Write to P8DDR
Write to port 8
Read port 8
0, 1, 2, 3
Reset
R
QD
C
P8
n
DDR
WP8D
Reset
R
QD
C
P8
n
DR
WP8
P8
n
RP8
Internal data bus
HIE
Figure C-8 (a) Port 8 Block Diagram (Pins P80 to P83) [H8/3534]
428
WP8D:
WP8:
RP8:
Reset
Write to P8DDR
Write to port 8
Read port 8
R
QD
C
P8
4
DR
WP8
Reset
R
QD
C
P8
4
DDR
WP8D
P8
4
RP8
Internal data bus
IRQ enable register
IRQ3 enable
IRQ3 input
SCI
Output enable
Serial transmit data
Schmitt input
Figure C-8 (b) Port 8 Block Diagram (Pin P84) [H8/3534]
429
P8
5
Reset
WP8D:
WP8:
RP8:
Write to P9DDR
Write to port 8
Read port 8
R
QD
C
P8
5
DDR
WP8D
Reset
R
QD
C
P8
5
DR
WP8
RP8
IRQ4 input
IRQ enable register
IRQ4 enable
Internal data bus
SCI
Input enable
Serial receive data
Schmitt input
Figure C-8 (c) Port 8 Block Diagram (Pin P85) [H8/3534]
430
Reset
WP8
Reset
R
QD
C
P86DDR
WP8D
P86
RP8
Internal data bus
IRQ enable register
IRQ5 enable
IRQ5 input
SCI
Clock output enable
Clock output
Schmitt input
Clock input enable
Clock input
R
QD
C
P86DR
WP8D:
WP8:
RP8:
Write to P8DDR
Write to port 8
Read port 8
Figure C-8 (d) Port 8 Block Diagram (Pin P86) [H8/3534]
431
C.9 Port 9 Block Diagrams [H8/3534] and Port 4 Block Diagrams [H8/3522]
P9
0
Reset
WP9D:
WP9:
RP9:
Write to P9DDR
Write to port 9
Read port 9
R
QD
C
P9
0
DDR
WP9D
Reset
R
QD
C
P9
0
DR
WP9
RP9
IRQ2 input
IRQ2 enable
IRQ enable register
External trigger
input
A/D converter
Internal data bus
Schmitt input
Figure C-9 (a) Port 9 Block Diagram (Pin P90) [H8/3534]
Port 4 Block Diagram (Pin P40) [H8/3522]
432
P9
1
Reset
Internal data bus
WP9D:
WP9:
RP9:
n: 1, 2
Write to P9DDR
Write to port 9
Read port 9
R
QD
C
P9
n
DDR
WP9D
Reset
R
QD
C
P9
n
DR
WP9
RP9
IRQ1 enable
IRQ0 enable
IRQ enable register
IRQ1 input
IRQ0 input
Schmitt input
Figure C-9 (b) Port 9 Block Diagram (Pins P91, P92) [H8/3534]
Port 4 Block Diagram (Pins P41, P42) [H8/3522]
433
P9
n
Reset
Internal data bus
WP9D:
WP9:
RP9:
n = 3, 4, 5
Write to P9DDR
Write to port 9
Read port 9
R
QD
C
P9
n
DDR
WP9D
Reset
R
QD
C
P9
n
DR
WP9
RP9
Hardware standby Mode 1 or 2
Mode 3
RD output
WR output
AS output
Mode 1 or 2
Figure C-9 (c) Port 9 Block Diagram (Pins P93, P94, P95) [H8/3534]
Port 4 Block Diagram (Pins P43, P44, P45) [H8/3522]
434
P96
Reset
WP9D:
WP9:
RP9:
Note: *Set priority
Write to P9DDR
Write to port 9
Read port 9
RS
QD
C
P9
6
DDR
WP9D
RP9
ø
Hardware standby Mode 1 or 2
*
Internal data bus
Figure C-9 (d) Port 9 Block Diagram (Pin P96) [H8/3534]
Port 4 Block Diagram (Pin P46) [H8/3522]
435
P9
7
Mode 1 or 2 Reset
WP9D:
WP9:
RP9:
Write to P9DDR
Write to port 9
Read port 9
R
QD
C
P9
7
DDR
WP9D
Reset
R
QD
C
P9
7
DR
WP9
RP9
WAIT input
Note: For a block diagram when the SDA pin function is selected, see section 13, I
2
C Bus Interface.
Internal data bus
Wait input enable
Figure C-9 (e) Port 9 Block Diagram (Pin P97) [H8/3534]
Port 4 Block Diagram (Pin P47) [H8/3522]
436
437
Appendix D Port States in Each Mode
Table D-1 Port States
Pin Name Mode Reset Hardware
Standby Software
Standby Sleep
Mode Normal
Operation
P17 to P101 Low 3-state Low Prev. state A7 to A0
A7 to A02 3-state Low if DDR = 1,
prev. state if DDR =
0
(Addr. output
pins: last
address
accessed
Addr. output
or input port
3 Prev. state I/O port
P27 to P201 Low 3-state Low Prev. state A15 to A8
A15 to A82 3-state Low if DDR = 1,
prev. state if DDR =
0
(Addr. output
pins: last
address
accessed)
Addr. output
or input port
3 Prev. state I/O port
P37 to P301 3-state 3-state 3-state 3-state D7 to D0
D7 to D02
3 Prev. state Prev. state I/O port
P47 to P401 3-state 3-state Prev. state* Prev. state I/O port
[H8/3534] 2
3
P52 to P501 3-state 3-state Prev. state* Prev. state I/O port
2
3
Notes: 1. 3-state: High-impedance state
2. Prev. state: Previous state. Input ports are in the high-impedance state and output
ports hold their previous level. (For ports 1 to 3 and port 6 (H8/3534 only), the MOS
pull-up is on if DDR = 0 and PCR = 1.)
* On-chip supporting modules are initialized, so these pins revert to I/O ports according
to the DDR and DR bits.
438
Table D-1 Port States (cont)
Pin Name Mode Reset Hardware
Standby Software
Standby Sleep Mode Normal
Operation
P67 to P601 3-state 3-state Prev. state* Prev. state I/O port
2
3
P77 to P701 3-state 3-state 3-state 3-state Input port
2
3
P86 to P80
[H8/3534
only]
1 3-state 3-state Prev. state* Prev. state I/O port
2
3
P97/
:$,7
[H8/3534] 1 3-state 3-state 3-state/
prev. state* 3-state/
prev. state
:$,7
input or
I/O port
2
P47/
:$,7
[H8/3522] 3 Prev. state* Prev. state I/O port
P96/φ
[H8/3534] 1 Clock output 3-state High Clock Clock
P46/φ
[H8/3522] 2
3 3-state High if DDR = 1,
3-state if DDR = 0 Clock output if
DDR = 1, 3-
state if DDR =
0
Clock output
if DDR = 1,
input port if
DDR = 0
P95 to P93,
[H8/3534] 1 High 3-state High High
$6
,
:5
,
5'
2
P45 to P43
[H8/3522]
$6
,
:55'
3 3-state Prev. state Prev. state I/O port
P92 to P90
[H8/3534] 1 3-state 3-state Prev. state Prev. state I/O port
P42 to P46
[H8/3522] 2
3
Notes: 1. 3-state: High-impedance state
2. Prev. state: Previous state. Input ports are in the high-impedance state and output
ports hold their previous level. (For ports 1 to 3 and port 6 (H8/3534 only), the MOS
pull-up is on if DDR = 0 and PCR = 1.)
* On-chip supporting modules are initialized, so these pins revert to I/O ports according to
the DDR and DR bits.
439
Appendix E Timing of Transition to and Recovery from
Hardware Standby Mode
Timing of Transition to Hardware Standby Mode
(1) To retain RAM contents when the RAME bit in SYSCR is set to 1, drive the
5(6
signal low
10 system clock cycles before the
67%<
signal goes low, as shown below.
5(6
must remain
low until
67%<
goes low (minimum delay from
67%<
low to
5(6
high: 0 ns).
STBY
RES
t1 ≥ 10 tcyc t2 ≥ 0 ns
(2) When the RAME bit in SYSCR is cleared to 0 or when it is not necessary to retain RAM
contents,
5(6
does not have to be driven low as in (1).
Timing of Recovery From Hardware Standby Mode: Drive the
5(6
signal low
approximately 100 ns before
67%<
goes high.
STBY
RES
t ≥ 100 ns t
OSC
440
441
Appendix F Product Code Lineup
Table F-1 H8/3534, H8/3522 Product Code Lineup
Product Type Product
Code Mark Code Package
(Hitachi Package Code)
H8/3534 Mask ROM
version Standard
product HD6433534F HD6433534(***)F 80-pin QFP (FP-80A)
H8/3522 Mask ROM Standard HD6433522F HD6433522(***)F 64-pin QFP (FP-64A)
version product HD6433522P HD6433522(***)P 64-pin shrink DIP (DP-64S)
Note: (***) in mask ROM version codes is the ROM code
442
443
Appendix G Package Dimensions
Figure G-1 shows the dimensions of the FP-80A package. Figure G-2 shows the dimensions of
the FP-64A package. Figure G-3 shows the dimensions of the DP-64S package.
Unit: mm
60
0 – 5 °
0.10
0.12 M
17.2 ± 0.3
41
61
80 120
40
21
17.2 ± 0.3
0.30 ± 0.10
0.65
3.05 Max
0.10
1.60
0.80 ± 0.30
14.0
2.70
+0.20
–0.16
0.17
+0.08
–0.05
Figure G-1 Package Dimensions (FP-80A)
444
Unit: mm
0 – 5 °
0.1
0.15 M
17.2 ± 0.3
48 33
49
64 116
32
17
17.2 ± 0.3
0.35 ± 0.10
0.80
3.05 Max
0.1
1.6
0.8 – 0.3
14
2.70
+0.20
–0.16
0.17
+0.08
–0.05
Figure G-2 Package Dimensions (FP-64A)
445
Unit: mm
0.25
+ 0.11
– 0.05
0° – 15°
1.78 ± 0.25 0.48 ± 0.10
0.51 Min
2.54 Min 5.08 Max
19.05
57.6
58.50 Max
1.0
1
33
32
64
17.0
18.6 Max
Figure G-3 Package Dimensions (DP-64S)
