Preliminary: This document contains information on a new product. Specifications and information contained
herein are subject to change without notice.
HM514800D Series
HM51S4800D Series
524,288-word × 8-bit Dynamic RAM
ADE-203-687(Z)
Preliminary
Rev. 0.0
Dec. 3, 1996
Description
The Hitachi HM51(S)4800D are CMOS dynamic RAM organized as 524,288-word × 8-bit. HM51(S)4800D
have realized higher density, higher performance and various functions by employing 0.8 µm CMOS process
technology and some new CMOS circuit design technologies. The HM51(S)4800D offer Fast Page Mode as
a high speed access mode. They have the package variations of standard 400-mil 28-pin plastic SOJ and
standard 400-mil 28-pin plastic TSOPII. Internal refresh timer enables HM51S4800D self refresh operation.
Features
• Single 5 V (± 10%)
• Access time: 60 ns/70 ns/80 ns (max)
• Power dissipation
Active mode: 605 mW/550 mW/495 mW (max)
Standby mode: 11 mW (max)
: 1.1 mW (max) (L-version)
• Fast page mode capability
• Refresh cycles
1,024 refresh cycles: 16 ms
: 128 ms (L-version)
• 2 variations of refresh
RAS-only refresh
CAS-before-RAS refresh
• Battery backup operation (L-version)
• Self refresh operation (HM51S4800D)
HM514800D Series, HM51S4800D Series
2
Ordering Information
Type No. Access time Package
HM514800DJ-6
HM514800DJ-7
HM514800DJ-8
60 ns
70 ns
80 ns
400-mil 28-pin plastic SOJ (CP-28D)
HM514800DLJ-6
HM514800DLJ-7
HM514800DLJ-8
60 ns
70 ns
80 ns
HM51S4800DJ-6
HM51S4800DJ-7
HM51S4800DJ-8
60 ns
70 ns
80 ns
HM51S4800DLJ-6
HM51S4800DLJ-7
HM51S4800DLJ-8
60 ns
70 ns
80 ns
HM514800DTT-6
HM514800DTT-7
HM514800DTT-8
60 ns
70 ns
80 ns
400-mil 28-pin plastic TSOP II (TTP-28D)
HM514800DLTT-6
HM514800DLTT-7
HM514800DLTT-8
60 ns
70 ns
80 ns
HM51S4800DTT-6
HM51S4800DTT-7
HM51S4800DTT-8
60 ns
70 ns
80 ns
HM51S4800DLTT-6
HM51S4800DLTT-7
HM51S4800DLTT-8
60 ns
70 ns
80 ns
HM514800D Series, HM51S4800D Series
3
Pin Arrangement
HM514800DJ / DLJ Series
HM51S4800DJ / DLJ Series
(Top view)
HM514800DTT / DLTT Series
HM51S4800DTT / DLTT Series
(Top view)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
I/O0
I/O1
I/O2
I/O3
NC
WE
RAS
A9
A0
A1
A2
A3
VCC
VSS
I/O7
I/O6
I/O5
I/O4
CAS
OE
NC
A8
A7
A6
A5
A4
VSS
1
2
3
4
5
6
7
8
9
10
11
12
13
14
28
27
26
25
24
23
22
21
20
19
18
17
16
15
VCC
I/O0
I/O1
I/O2
I/O3
NC
WE
RAS
A9
A0
A1
A2
A3
VCC
VSS
I/O7
I/O6
I/O5
I/O4
CAS
OE
NC
A8
A7
A6
A5
A4
VSS
Pin Description
Pin name Function
A0 to A9 Address input
– Row address
– Column address
– Refresh address
A0 to A9
A0 to A8
A0 to A9
I/O0 to I/O7 Data-input/output
RAS Row address strobe
CAS Column address strobe
WE Read/write enable
OE Output enable
VCC Power supply
VSS Ground
NC No connection
HM514800D Series, HM51S4800D Series
4
Block Diagram
256 k Memory Array Mat
I/O Bus & Column Decoder
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
256 k Memory Array Mat
I/O Bus & Column Decoder
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
256 k Memory Array Mat
I/O Bus & Column Decoder
I/O Bus & Column Decoder
I/O Bus & Column Decoder
Row
Driver Row
Driver Row
Driver Row
Driver Row
Driver Row
Driver Row
Driver Row
Driver
Row Decoder & Peripheral Circuit
WE
RAS CAS
Row
Driver Row
Driver Row
Driver Row
Driver Row
Driver Row
Driver Row
Driver Row
Driver
Row Address Buffer Column Address Buffer
Address A0–A9
I/O6 Buff.
RAS Control
Circuit CAS Control
Circuit WE Control
Circuit
OE
OE Control
Circuit
I/O4 Buff.
I/O2 Buff.I/O0 Buff.
I/O0 I/O2 I/O4 I/O6
I/O1 Buff.
I/O1
I/O3 Buff.
I/O3
I/O5 Buff.
I/O5
I/O7 Buff.
I/O7
HM514800D Series, HM51S4800D Series
5
Operation Mode
The HM51(S)4800D series has the following 11 operation modes.
1. Read cycle
2. Early write cycle
3. Delayed write cycle
4. Read-modify-write cycle
5. RAS-only refresh cycle
6. CAS-before-RAS refresh cycle
7. Self refresh cycle (HM51S4800D)
8. Fast page mode read cycle
9. Fast page mode early write cycle
10.Fast page mode delayed write cycle
11.Fast page mode read-modify-write cycle
Inputs
RAS CAS WE OE Output Operation
HHDDOpen Standby
H L H L Valid Standby
L L H L Valid Read cycle
LLL
*2 D Open Early write cycle
LLL
*2 H Undefined Delayed write cycle
L L H to L L to H Valid Read-modify-write cycle
L H D D Open RAS-only refresh cycle
H to L L D D Open CAS-before-RAS refresh cycle
Self refresh cycle (HM51S4800D)
L H to L H L Valid Fast page mode read cycle
L H to L L*2 D Open Fast page mode early write cycle
L H to L L*2 H Undefined Fast page mode delayed write cycle
L H to L H to L L to H Valid Fast page mode read-modify-write cycle
L L H H Open Read cycle (Output disabled)
Notes: 1. H: High (inactive) L: Low (active) D: H or L
2. tWCS ≥ 0 ns Early write cycle
tWCS < 0 ns Delayed write cycle
HM514800D Series, HM51S4800D Series
6
Absolute Maximum Ratings
Parameter Symbol Value Unit
Voltage on any pin relative to VSS VT–1.0 to +7.0 V
Supply voltage relative to VSS VCC –1.0 to +7.0 V
Short circuit output current Iout 50 mA
Power dissipation PT1.0 W
Operating temperature range Topr 0 to +70 °C
Storage temperature range Tstg –55 to +125 °C
Recommended DC Operating Conditions (Ta = 0 to +70°C)
Parameter Symbol Min Typ Max Unit Notes
Supply voltage VSS 000V2
V
CC 4.5 5.0 5.5 V 1, 2
Input high voltage VIH 2.4 — 6.5 V 1
Input low voltage VIL –1.0 — 0.8 V 1
Notes: 1. All voltage referred to VSS.
2. The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) *5
HM514800D, HM51S4800D
-6 -7 -8
Parameter Symbol Min Max Min Max Min Max Unit Test conditions
Operating current*1, 2 ICC1 — 120 — 110 — 100 mA RAS, CAS cycling
tRC = min
Standby current ICC2 — 2 — 2 — 2 mA TTL interface
RAS, CAS = VIH
Dout = High-Z
— 1 — 1 — 1 mA CMOS interface
RAS, CAS ≥ VCC –0.2 V
Dout = High-Z
Standby current (L-version) ICC2 — 200 — 200 — 200 µA CMOS interface
RAS, CAS ≥ VCC –0.2 V
Dout = High-Z
RAS-only refresh current*2 ICC3 — 120 — 110 — 100 mA tRC = min
HM514800D Series, HM51S4800D Series
7
DC Characteristics (Ta = 0 to +70°C, VCC = 5 V ± 10%, VSS = 0 V) *5 (cont)
HM514800D, HM51S4800D
-6 -7 -8
Parameter Symbol Min Max Min Max Min Max Unit Test Conditions
CAS-before-RAS refresh
current*4 ICC6 — 120 — 110 — 100 mA tRC = min
Fast page mode current*1, 3 ICC7 — 120 — 110 — 100 mA tPC = min
Battery backup current*4
(Standby with CBR refresh)
(L-version)
ICC10 — 300 — 300 — 300 µA Standby: CMOS interface
Dout = High-Z
CBR refresh: tRC = 125 µs
tRAS ≤ 1 µs, CAS = VIL
WE = VIH
Self refresh mode current
(HM51S4800D) ICC11 — 1 — 1 — 1 mA CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
Self refresh mode current
(HM51S4800DL) ICC11 — 200 — 200 — 200 µA CMOS interface
RAS, CAS ≤ 0.2 V
Dout = High-Z
Input leakage current ILI –10 10 –10 10 –10 10 µA 0 V ≤ Vin ≤ 6.5 V
Output leakage current ILO –10 10 –10 10 –10 10 µA 0 V ≤ Vout ≤ 6.5 V
Dout = disable
Output high voltage VOH 2.4 VCC 2.4 VCC 2.4 VCC V High Iout = –5 mA
Output low voltage VOL 0 0.4 0 0.4 0 0.4 V Low Iout = 4.2 mA
Notes: 1. ICC depends on output load condition when the device is selected ICC max is specified at the output
open condition.
2. Address can be changed once or less while RAS = VIL.
3. Address can be changed once or less while CAS = VIH.
4. VIH ≥ VCC –0.2 V, VIL ≤ 0.2 V; Address can be changed once or less while CAS = VIL.
5. The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
Capacitance (Ta = 25°C, VCC = 5 V ± 10%)
Parameter Symbol Typ Max Unit Notes
Input capacitance (Address) CI1 — 5 pF 1
Input capacitance (Clocks) CI2 — 7 pF 1
Output capacitance (Data-in, Data-out) CI/O — 10 pF 1, 2
Notes: 1. Capacitance measured with Boonton Meter or effective capacitance measuring method.
2. CAS = VIH to disable Dout.
HM514800D Series, HM51S4800D Series
8
AC Characteristics (Ta = 0 to 70°C, VCC = 5 V ± 10%, VSS = 0 V) *1, *14, *15
Test conditions
• Input rise and fall time: 5 ns
• Input levels: 0 V, 3 V
• Input timing reference levels: 0.8 V, 2.4 V
• Output load: 2 TTL gate + CL (100 pF) (Including scope and jig)
Read, Write, Read-Modify-Write and Refresh Cycles (Common Parameters)
HM514800D, HM51S4800D
-6 -7 -8
Parameter Symbol Min Max Min Max Min Max Unit Notes
Random read or write cycle time tRC 110 — 130 — 150 — ns
RAS precharge time tRP 40 — 50 — 60 — ns
RAS pulse width tRAS 60 10000 70 10000 80 10000 ns
CAS pulse width tCAS 15 10000 20 10000 20 10000 ns
Row address setup time tASR 0— 0— 0— ns
Row address hold time tRAH 10 — 10 — 10 — ns
Column address setup time tASC 0— 0— 0— ns
Column address hold time tCAH 15 — 15 — 15 — ns
RAS to CAS delay time tRCD 20 45 20 50 20 60 ns 8
RAS to column address delay time tRAD 15 30 15 35 15 40 ns 9
RAS hold time tRSH 20 — 20 — 20 — ns
CAS hold time tCSH 60 — 70 — 80 — ns
CAS to RAS precharge time tCRP 10 — 10 — 10 — ns
OE to Din delay time tODD 15 — 20 — 20 — ns
OE delay time from Din tDZO 0— 0— 0— ns
CAS setup time from Din tDZC 0— 0— 0— ns
Transition time (rise and fall) tT350 350 350 ns7
Refresh period tREF —16 —16 —16 ms
Refresh period (L-version) tREF — 128 — 128 — 128 ms
HM514800D Series, HM51S4800D Series
9
Read Cycle
HM514800D, HM51S4800D
-6 -7 -8
Parameter Symbol Min Max Min Max Min Max Unit Notes
Access time from RAS tRAC — 60 — 70 — 80 ns 2, 3
Access time from CAS tCAC — 15 — 20 — 20 ns 3, 4, 13
Access time from address tAA — 30 — 35 — 40 ns 3, 5, 13
Access time from OE tOAC —15 —20 —20 ns
Read command setup time tRCS 0— 0— 0— ns
Read command hold time to CAS tRCH 0— 0— 0— ns
Read command hold time to RAS tRRH 0— 0— 0— ns
Column address to RAS lead time tRAL 30 — 35 — 40 — ns
Output buffer turn-off time tOFF1 015 015 015 ns6
Output buffer turn-off to OE tOFF2 015 015 015 ns6
CAS to Din delay time tCDD 15 — 15 — 15 — ns
Write Cycle
HM514800D, HM51S4800D
-6 -7 -8
Parameter Symbol Min Max Min Max Min Max Unit Notes
Write command setup time tWCS 0— 0— 0— ns10
Write command hold time tWCH 15 — 15 — 15 — ns
Write command pulse width tWP 10 — 10 — 10 — ns
Write command to RAS lead time tRWL 15 — 20 — 20 — ns
Write command to CAS lead time tCWL 15 — 20 — 20 — ns
Data-in setup time tDS 0— 0— 0— ns11
Data-in hold time tDH 15 — 15 — 15 — ns 11
CAS to OE delay time tCOD —0 —0 —0 ns18
HM514800D Series, HM51S4800D Series
10
Read-Modify-Write Cycle
HM514800D, HM51S4800D
-6 -7 -8
Parameter Symbol Min Max Min Max Min Max Unit Notes
Read-modify-write cycle time tRWC 150 — 180 — 200 — ns
RAS to WE delay time tRWD 80 — 95 — 105 — ns 10
CAS to WE delay time tCWD 35 — 45 — 45 — ns 10
Column address to WE delay time tAWD 50 — 60 — 65 — ns 10
OE hold time from WE tOEH 15 — 20 — 20 — ns
Refresh Cycle
HM514800D, HM51S4800D
-6 -7 -8
Parameter Symbol Min Max Min Max Min Max Unit Notes
CAS setup time (CBR refresh cycle) tCSR 10 — 10 — 10 — ns
CAS hold time (CBR refresh cycle) tCHR 10 — 10 — 10 — ns
RAS precharge to CAS hold time tRPC 10 — 10 — 10 — ns
CAS precharge time in normal mode tCPN 10 — 10 — 10 — ns
Fast Page Mode Cycle
HM514800D, HM51S4800D
-6 -7 -8
Parameter Symbol Min Max Min Max Min Max Unit Notes
Fast page mode cycle time tPC 40 — 45 — 50 — ns
Fast page mode CAS precharge time tCP 10 — 10 — 10 — ns
Fast page mode RAS pulse width tRASC — 100000 — 100000 — 100000 ns 12
Access time from CAS precharge tACP — 35 — 40 — 45 ns 3, 13
RAS hold time from CAS precharge tRHCP 35 — 40 — 45 — ns
HM514800D Series, HM51S4800D Series
11
Fast Page Mode Read-Modify-Write Cycle
HM514800D, HM51S4800D
-6 -7 -8
Parameter Symbol Min Max Min Max Min Max Unit Notes
Fast page mode read-modify-write
cycle CAS precharge to WE delay
time
tCPW 55 — 65 — 70 — ns
Fast page mode read-modify-write
cycle time tPCM 80 — 95 — 100 — ns
Self-Refresh Mode
HM514800D, HM51S4800D
-6 -7 -8
Parameter Symbol Min Max Min Max Min Max Unit Notes
RAS pulse width (self-refresh) tRASS 100 — 100 — 100 — µs 19, 20,
21, 22
RAS precharge time (self-refresh) tRPS 110 — 130 — 150 — ns
CAS hold time (self-refresh) tCHS -50 — -50 — -50 — ns
HM514800D Series, HM51S4800D Series
12
Notes: 1. AC measurements assume tT = 5 ns.
2. Assumes that tRCD ≤ tRCD (max) and tRAD ≤ tRAD (max). If tRCD or tRAD is greater than the maximum
recommended value shown in this table, tRAC exceeds the value shown.
3. Measured with a load circuit equivalent to 2 TTL loads and 100 pF.
4. Assumes that tRCD ≥ tRCD (max) and tRAD ≤ tRAD (max).
5. Assumes that tRCD ≤ tRCD (max) and tRAD ≥ tRAD (max).
6. tOFF (max) defines the time at which the output achieves the open circuit condition and is not
referred to output voltage levels.
7. VIH (min) and VIL (max) are reference levels for measuring timing of input signals. Also, transition
times are measured between VIH and VIL.
8. Operation with the tRCD (max) limit insures that tRAC (max) can be met, tRCD (max) is specified as a
reference point only, if tRCD is greater than the specified tRCD (max) limit, then access time is
controlled exclusively by tCAC.
9. Operation with the tRAD (max) limit insures that tRAC (max) can be met, tRAD (max) is specified as a
reference point only, if tRAD is greater than the specified tRAD (max) limit, then access time is
controlled exclusively by tAA.
10.tWCS, tRWD, tCWD and tAWD are not restrictive operating parameters. They are included in the data sheet
as electrical characteristics only: if tWCS ≥ tWCS (min), the cycle is an early write cycle and the data out
pin will remain open circuit (high impedance) throughout the entire cycle; if tRWD ≥ tRWD (min), tCWD ≥
tCWD (min), tAWD ≥ tAWD (min) and tCPW ≥ tCPW (min), the cycle is a read-modify-write and the data output
will contain data read from the selected cell; if neither of the above sets of conditions is satisfied,
the condition of the data out (at access time) is indeterminate.
11.These parameters are referred to CAS leading edge in an early write cycle and to WE leading edge
in a delayed write or a read-modify-write cycle.
12.tRASC defines RAS pulse width in fast page mode cycles.
13.Access time is determined by the longest among tAA, tCAC and tACP.
14.An initial pause of 100 µs is required after power up followed by a minimum of eight initialization
cycles (RAS-only refresh cycle or CAS-before-RAS refresh cycle). If the internal refresh counter is
used, a minimum of eight CAS-before-RAS refresh cycles is required.
15.In delayed write or read-modify-write cycles, OE must disable output buffer prior to applying data to
the device.
16.Either tRCH or tRRH must be satisfied for a read cycle.
17.The supply voltage with all VCC pins must be on the same level.
The supply voltage with all VSS pins must be on the same level.
18.Do not enable Dout buffer when using delayed write timing.
19.Please do not use tRASS timing, 10 µs ≤ tRASS ≤100 µs. During this period, the device is in transition
state from normal operation mode to self refresh mode. if tRASS ≥ 100 µs, then RAS precharge time
should use tRPS instead of tRP.
20.If you use distributed CBR refresh mode with 15.6 µs interval in normal read/write cycle,
CBRrefresh should be executed within 15.6 µs immediately after exiting from and before entering
into self refresh mode.
21.If you use RAS only refresh or CBR burst refresh mode in normal read/write cycle, 1024 cycles of
distributed CBR refresh with 15.6 µs interval should be executed within 16 ms immediately after
exiting from and before entering into the self refresh mode.
22.Repetitive self refresh mode without refreshing all memory is not allowed. Once you exit from self
refresh mode, all memory cells need to be refreshed before re-entering the self refresh mode
again.
HM514800D Series, HM51S4800D Series
13
23.XXX H or L (H: VIH (min) ≤ VIN ≤ VIH (max), L: VIL (min) ≤ VIN ≤ VIL (max))
/////// Invalid Dout
When the address, clock and input pins are not described on timing waveforms, their pins must be
applied VIH or VIL.
HM514800D Series, HM51S4800D Series
14
Timing Waveforms*23
Read Cycle
RAS
CAS
Address
WE
Dout
OE
Din
tRC
tRAS
tRP
tCRP
tRCD tRSH
tCAS
tT
tRAD tRAL
tASC tCAH
tASR
Row Column
tRAH
tRCS tRCH
tRRH
tDZC
High-Z
High-Z Dout
tDZO tODD
tRAC
tAA
tCAC tOFF1
tCSH
tCDD
tOFF2
tOAC
HM514800D Series, HM51S4800D Series
15
Early Write Cycle
RAS
CAS
Address
WE
Din
Dout
tRC
tRAS
tRP
tCRP
tCSH
tRCD
tRSH
tCAS
tT
tASR tRAH tASC tCAH
Column
Row
tWCS tWCH
tDS tDH
Din
High-Z
HM514800D Series, HM51S4800D Series
16
Delayed Write Cycle*15
Address
CAS
RAS
WE
Din
OE
Dout
tRC
tRAS tRP
tCSH
tRCD tRSH
tCAS
tCRP
tT
Column
Row
tASR tRAH tASC tCAH
tRCS
tCWL
tRWL
tWP
tDZC
tDS tDH
tDZO tODD
tCOD
tOEH
tOFF2
*
High-Z Din
Do not enable Dout during delayed write cycle.
Invalid Dout*
*
HM514800D Series, HM51S4800D Series
17
Read-Modify-Write Cycle*15
Address
RAS
Din
Dout
OE
WE
CAS
tRWC tRP
tCRP
tCAS
tRCD
tT
tRAD
tASR
ttASC tCAH
Column
Row
tRCS tCWD tCWL
tAWD
tRWD
tRWL
tWP
tDZC
tDH
tDS
Din
High-Z
tDZO
t
ODD
t
tCAC
tAA
tOAC
t
RAC
t
OFF2 OEH
RAH
Dout
HM514800D Series, HM51S4800D Series
18
RAS-Only Refresh Cycle
CAS
RAS
Address
tRC
tRAS tRP
tT
tCRP tRPC tCRP
tASR tRAH
Row
High-Z
Dout
HM514800D Series, HM51S4800D Series
19
CAS-Before-RAS Refresh Cycle
")
,
,
RAS
Address
Dout
t
RC
t
RC
t
RP
t
RAS
t
RP
t
RAS
t
RP
t
RPC
t
T
t
CPN
t
CSR
t
CHR
t
CPN
t
CSR
t
RPC
t
CHR
t
CRP
t
OFF1
High-Z
CAS
*Do not extend t > t (max).
Untested self refresh mode may be
activated and loss of data may be
resulted (HM514800D).
RAS RAS
*
_
*
HM514800D Series, HM51S4800D Series
20
Fast Page Mode Read Cycle
WE
Din
OE
Dout
Address
CAS
RAS
t
RASC
t
RHCP
t
RP
t
T
t
CSH
t
RCD
t
CAS
t
CP
t
CAS
t
PC
t
RSH
t
CP
t
CAS
t
CRP
t
RAL
t
CAH
t
ASC
t
t
ASC
t
t
RAD
t
ASR
t
RAH
tt
RCH
t
RCH
ttt
RRH
t
RCH
t
CDD
High-Z
t
DZC
t
CDD
t
DZC
t
CDD
t
High-ZHigh-Z
t
DZO
t
ODD
t
DZO
t
ODD
t
AA
t
AA
t
ACP
t
t
RAC
t
AA
t
CAC
t
CAC
t
OAC
t
CAC
t
OFF1
Dout Dout
Dout
Row Column
CAH CAH
RCS
ASC
t
RCS
DZC
ACP
t
OFF1
t
OFF1
t
OFF2
t
ODD
t
OAC
t
OFF2
t
OFF2
t
OAC
t
DZO
RCS
ColumnColumn
HM514800D Series, HM51S4800D Series
21
Fast Page Mode Early Write Cycle
RAS
CAS
Address
WE
Din
Dout
t
RASC
t
RP
t
T
t
CSH
t
PC
t
RSH
t
CRP
t
CAS
t
CP
t
CAS
t
CP
t
CAS
t
RCD
t
ASR
t
RAH
t
ASC
t
CAH
t
ASC
t
CAH
t
ASC
t
CAH
Row
t
WCS
t
WCS
t
WCS
t
WCH
t
WCH
t
WCH
t
DS
t
DH
t
DS
t
DH
t
DS
t
DH
Din Din Din
High-Z
Column
Column Column
HM514800D Series, HM51S4800D Series
22
Fast Page Mode Delayed Write Cycle*15
Din
WE
Address
RAS
Dout
CAS
t
RASC
t
RP
t
T
t
CSH
t
PC
t
RSH
t
CAS
t
RCD
t
CP
t
CAS
t
CP
t
CAS
t
CRP
t
ASR
t
RAH
t
ASC
tt
ASC
t
CAH
t
ASC
t
CAH
Row Column
t
t
RCS
tt
WP
t
CWL
t
CWL
t
t
t
t
DS
t
t
DS
t
DH
Din Din Din
t
RWL
t
RCS
WP
CAH
t
RCS
WP
CWL
DH
DS
DH
OE
t
ODD
t
OEH
High-Z
ColumnColumn
HM514800D Series, HM51S4800D Series
23
Fast Page Mode Read-Modify-Write Cycle*15
Din
Dout
Address
RAS
t
RASC
t
t
CP
t
PCM
t
T
t
RCD
t
t
CP
t
RAD
t
ASR
t
ASC
tt
t
RAH
t
t
CAH
t
t
CPW
t
t
CPW
t
CWL
t
RWD
t
AWD
t
AWD
t
AWD
t
CWD
t
t
CWD
t
CWD
t
RCS
t
WP
t
t
WP
t
DS
t
t
DH
t
t
DS
t
DZC
t
DH
t
ODD
t
DH
t
CAC
t
DZO
t
OEH
t
OEH
t
OEH
t
AA
t
t
OFF2
Din Din Din
t
RP
t
RWL
t
OAC
t
ODD
t
OFF2
t
t
ODD
t
DZO
t
OFF2
t
t
t
DZO
AA
t
WE
CAS
OE
Dout
Dout
Dout
t
CAH
t
DS
Column
Column
Column
Row
RAC
CWL
ACP
WP
CWL
t
CRP
ASC
ACP
t
ASC
RCS
High-Z High-Z
OAC
t
DZC DZC
RCS
OAC
t
CAS
t
CAS
t
CAS
CAH
CAC
CAC
High-Z
HM514800D Series, HM51S4800D Series
24
Self Refresh Cycle*19, 20, 21, 22
t
RASS
t
RP
t
RPC
t
CSR
t
CPN
t
OFF1
t
RPS
t
CRP
t
CHS
High-Z
RAS
CAS
Dout
Address
t
T
HM514800D Series, HM51S4800D Series
25
Package Dimensions
HM51(S)4800DJ/DLJ Series (CP-28D) Unit: mm
9.40 ± 0.25
114
0.10
0.43 ± 0.10
3.50 ± 0.26
+ 0.21
– 0.24
2.40
15
28 18.54 Max
18.17
0.74
10.16 ± 0.13
11.18 ± 0.13
1.30 Max
1.27
+ 0.25
– 0.17
0.80
Hitachi Code
JEDEC Code
EIAJ Code
Weight
CP-28D
MO-061-AA
SC-637-B
1.16 g
0.41 ± 0.08
HM514800D Series, HM51S4800D Series
26
HM51(S)4800DTT/DLTT Series (TTP-28D) Unit: mm
1.27
0.21 M
0.42 ± 0.08
0.10
10.16
18.41
18.81 Max 15
14
28
1
1.20 Max
0 – 5°
0.13 ± 0.05
0.17 ± 0.05
11.76 ± 0.20
0.50 ± 0.10
1.15 Max
0.80
Hitachi Code
JEDEC Code
EIAJ Code
Weight
TTP-28D
MO-133AA
—
0.43 g
0.40 ± 0.06
0.125 ± 0.04
HM514800D Series, HM51S4800D Series
27
When using this document, keep the following in mind:
1. This document may, wholly or partially, be subject to change without notice.
2. All rights are reserved: No one is permitted to reproduce or duplicate, in any form, the whole or part of
this document without Hitachi’s permission.
3. Hitachi will not be held responsible for any damage to the user that may result from accidents or any other
reasons during operation of the user’s unit according to this document.
4. Circuitry and other examples described herein are meant merely to indicate the characteristics and
performance of Hitachi’s semiconductor products. Hitachi assumes no responsibility for any intellectual
property claims or other problems that may result from applications based on the examples described
herein.
5. No license is granted by implication or otherwise under any patents or other rights of any third party or
Hitachi, Ltd.
6. MEDICAL APPLICATIONS: Hitachi’s products are not authorized for use in MEDICAL
APPLICATIONS without the written consent of the appropriate officer of Hitachi’s sales company. Such
use includes, but is not limited to, use in life support systems. Buyers of Hitachi’s products are requested
to notify the relevant Hitachi sales offices when planning to use the products in MEDICAL
APPLICATIONS.
Hitachi, Ltd.
Semiconductor & IC Div.
Nippon Bldg., 2-6-2, Ohte-machi, Chiyoda-ku, Tokyo 100, Japan
Tel: Tokyo (03) 3270-2111
Fax: (03) 3270-5109
For further information write to:
Hitachi America, Ltd.
Semiconductor & IC Div.
2000 Sierra Point Parkway
Brisbane, CA. 94005-1835
U S A
Tel: 415-589-8300
Fax: 415-583-4207
Hitachi Europe GmbH
Electronic Components Group
Continental Europe
Dornacher Straße 3
D-85622 Feldkirchen
München
Tel: 089-9 91 80-0
Fax: 089-9 29 30 00
Hitachi Europe Ltd.
Electronic Components Div.
Northern Europe Headquarters
Whitebrook Park
Lower Cookham Road
Maidenhead
Berkshire SL6 8YA
United Kingdom
Tel: 0628-585000
Fax: 0628-778322
Hitachi Asia Pte. Ltd.
16 Collyer Quay #20-00
Hitachi Tower
Singapore 0104
Tel: 535-2100
Fax: 535-1533
Hitachi Asia (Hong Kong) Ltd.
Unit 706, North Tower,
World Finance Centre,
Harbour City, Canton Road
Tsim Sha Tsui, Kowloon
Hong Kong
Tel: 27359218
Fax: 27306071
HM514800D Series, HM51S4800D Series
28
Revision Record
Rev. Date Contents of Modification Drawn by Approved by
0.0 Dec. 3, 1996 Initial issue