06 February 2012 Broadcom Europe Ltd. 406 Science Park Milton Road Cambridge CB4 0WW Page 121
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In frame sync master mode (FSM=0), the PCM_FS is internally generated and is treated as a
data output that changes on the positive edge of the clock. The length and polarity of the
frame sync is fully programmable and it can be used as a standard frame sync signal, or as an
L-R signal for I2S.
In frame sync slave mode (FSM=1), the PCM_FS is treated as a data input and is sampled on
the negative edge of PCM_CLK. The first clock of a frame is taken as the first clock period
where PCM_FS is sampled as a 1 following a period or periods where it was previously a 0.
The PCM audio interface locks onto the incoming frame sync and uses this to indicate where
the data channels are positioned. The precise timing at the start of frame is shown in Figure
8-3.
Note that in frame sync slave mode there are two synchronising methods. The legacy method
is used when the frame length = 0. In this case the internal frame logic has to detect the
incoming PCM_FS signal and reset the internal frame counter at the start of every frame.
The logic relies on the PCM_FS to indicate the length of the frame and so can cope with
adjacent frames of different lengths. However, this creates a short timing path that will
corrupt the PCM_DOUT for one specific frame/channel setting.
The preferred method is to set the frame length to the expected length. Here the incoming
PCM_FS is used to resynchronise the internal frame counter and this eliminates the short
timing path.
8.3 Operation
The PCM interface runs asynchronously at the PCM_CLK rate and automatically transfers
transmit and receive data across to the internal APB clock domain. The control registers are
NOT synchronised and should be programmed before the device is enabled and should NOT
be changed whilst the interface is running.
Only the EN, RXON and TXON bits of the PCMCS register are synchronised across the
PCM - APB clock domain and are allowed to be changed whilst the interface is running.
The EN bit is a global power-saving enable. The TXON and RXON bits enable transmit and
receive, and the interface is running whenever either TXON or RXON is enabled.
In operation, the PCM format is programmed by setting the appropriate frame length, frame
sync, channel position values, and signal polarity controls. The transmit FIFO should be
preloaded with data and the interface can then be enabled and started, and will run
continuously until stopped. If the transmit FIFO becomes empty or the receive FIFO
becomes full, the RXERR or TXERR error flags will be set, but the interface will just
continue. If the RX FIFO overflows, new samples are discarded and if the TX FIFO
underflows, zeros are transmitted.
Normally channel data is read or written into the appropriate FIFO as a single word. If the
channel is less than 32 bits, the data is right justified and should be padded with zeros. If the
RXSEX bit is set then the received data is sign extended up to the full 32 bits. When a frame
is programmed to have two data channels, then each channel is written/read as a separate
word in the FIFO, producing an interleaved data stream. When initialising the interface, the
first word read out of the TX FIFO will be used for the first channel, and the data from the
first channel on the first frame to be received will be the first word written into the RX FIFO.
If a FIFO error occurs in a two channel frame, then channel synchronisation may be lost
which may result in a left right audio channel swap. RXSYNC and TXSYNC status bits are