DuSLIC Chip Set Selection Guide - Infineon Technologies

DuSLIC

Dual Channel Subscriber Line

Interface Concept

PEB 3264/-2 Version 1.3

PEB 4264/-2 Version 1.1

PEB 3265 Version 1.3

PEB 4265/-2 Version 1.1

PEB 4266 Version 1.1

Chip Set Selection Guide, DS2, Oct. 2000

Wired Communications

Never stop thinking.

Edition 2000-11-09

Published by Infineon Technologies A G,

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Wired Communications

Preliminary

DuSLIC

Dual Channel Subscriber Line

Interface Concept

PEB 3264/-2 Version 1.3

PEB 4264/-2 Version 1.1

PEB 3265 Version 1.3

PEB 4265/-2 Version 1.1

PEB 4266 Version 1.1

Chip Set Selection Guide, DS2, Oct. 2000

Never stop thinking.

For questions on technology, delivery and prices please contact the Infineon

Technologies Offices in Germany or the Infineon Technologies Companies and

Representatives worldwide: see our webpage at http://www.infineon.com

DuSLIC

Preliminary

Revisi on History: 2000-11-09 DS2

Previous Version: Chip Set Selection Guide DS1

Page Subjec ts (major c hanges sinc e last revis i on)

all new co ncept and layo ut ap plied

DuSLIC

Chip Set Selection Guide 1 2000-11-0 9

Preliminary

Preface

This document summarizes the technical features and differences of all DuSLIC chip

sets comprising a programmable dual channel SLICOFI-2x codec and two single

chann el high-voltag e SLIC ch ips. For m ore DuSLIC related d ocuments ple ase see our

webpage at http://www.infineon.com/duslic .

To sim plify m at ters, the following s ynony m s are used:

SLICOFI-2x: Synonym used f or all codec v ers ions SLIC OFI-2/-2S/ -2S2

SLIC: Synonym used for all SLIC versions SLIC-S /-S2 , SL IC-E/-E2 and

SLIC-P

DuSLIC

DuSLIC Chip Set Ov erview

Chip Set Selection Guide 2 2000-11-0 9

Preliminary

1 DuSLIC Chip Set Overview

DuSLIC is a chip set, comprising one dual channel SLICOFI-2x codec and two single-

chann el SLIC chips. It is a highly flexible codec/SLIC solution for a n analog line circuit

and is widely programmable. Users can now access different markets with a single

hardware design that meets all different standards worldwide.

The interconnections between the single channel high-voltage SLIC and the dual

channel SLICOFI-2x codec are a seamless fit. This guarantees maximum transmission

perform ance wit h a m inimum of necessary comp onents.

All line circuit functions are implemented on the DuSLIC chip set:

• BORSC H T f unc t ions

• Internal balanced/unbalanced ring ing capability up to 85 V rm s

• Mete ring by Polarity Reversal and by 12/16 kHz s inusoidal burst s

• Dual-Tone Multif requenc y (DTM F ) detecti on and generation

• Caller ID generation

• Three-party C onf erencing1)

• Universal Tone Detection (UTD) unit for fax-/modemtone detection

• Line Echo Cancellation unit (LEC)

Integrated battery switches guarantee minimum power consumption during the off-hook,

on-hook and ringing modes. Test and diagnosis functions have been integrated to

simplify testing (ITDF). No external test equipment is needed for either subscriber line

testing in the fi eld or board t es t ing during production or in the field.

Chip Technology

The co dec dev ices SLIC OFI-2, SL ICOFI- 2S and SLIC OFI-2S2 are manuf actured in an

advanced 0.35 µm 3. 3 V CMOS proce ss.

The SLIC-E, SLIC-E2 and SLIC-P devices are manufactured in Infineon Technologies

robu st and well proven 170 V Sm art Pow er tec hnology.

The SLIC-S and SLIC-S2 devices are manufactured in Infineon Technologies 90 V

Smart Power technology.

DuSLIC Architecture

Unlike traditional designs, DuSLIC splits the SLIC function into high-voltage SLIC

functions and low-voltage SLIC functions.

The low-voltage functions are handled in the SLICOFI-2x device. The partitioning of the

functions is shown in Figure 1.

1) Cascading DuSLIC channels allows even Multi-party Conferencing

DuSLIC

DuSLIC Chip Set Ov erview

Chip Set Selection Guide 3 2000-11-0 9

Preliminary

Figure 1 DuSLIC Chip Set

ezm14034.wmf

SLICOFI-2x

HV SLIC Functions LV SLIC Functions Codec Fi lter Functions

Voltage feeding Programmable DC feeding Filtering

Transversal current Ring generation PCM compression/expansion

sensing Supervision Programmable gain

Longitudinal current Teletax generation Programmable frequency

sensing Teletax notch filter Impedance matching

Overload protection Ring trip detection Hybrid balance

Battery switching Ground key det ection DTMF generation

Ring amplification Hook switch detection DTMF detection

On-hook transmission FSK generation (Caller ID)

Pola rity reversal Linear mode support

(16-bit uncompressed voice data)

IOM-2 and PCM/µC int erface

Integrated Test and Diagnosis Function s (IDTF)

Line Echo Cancel l in g (LE C)

Universal Tone De te ctio n (UTD)

Three-party conferencing

Message waiting lamp support

SLIC

SLIC IOM

-2

PCM

µC

DuSLIC

DuSLIC Chip Set Selection

Chip Set Selection Guide 4 2000-11-0 9

Preliminary

2 DuSLIC Chip Set Selection

This chapter summarizes the features of the different DuSLIC chip sets and tries to

provide selection criteria for your design.

The DuSLIC family comprises five different chip sets (see Table 1):

– Three basic Du SLIC chip sets optim iz ed for different applications:

DuSLIC-S (Standard Feature Set),

DuSLI C -E (Enh anc ed Feature Set),

DuSLI C -P (Enhanc ed Power Manage m ent).

– Two different performance versions of the basic DuSLIC-E and DuSLIC-S chip sets

(mainly regarding longitudin al balance and maxim um DC feeding):

DuSLI C -E2 (usin g SLIC-E 2 PEB 4265-2 c om pared to D uSLIC-E)

DuSLI C -S2 (usin g SLIC-S 2 PEB 4264-2 and SLICOFI-2S2 PEB 3264-2)

Table 1 DuSLIC Chip Sets

Chip Set DuSLIC-S DuSLIC-S2 DuSLIC-E DuSLIC-E2 DuSLIC-P

Marketing Name SLICOFI-2S/

SLIC-S SLICOFI-2S2/

SLIC-S2 SLICOFI-2/

SLIC-E SLICOFI-2/

SLIC-E2 SLICOFI-2/

SLIC-P

Product ID PEB 3264/

PEB 4264 PEB 3264-2/

PEB 4264-21)

1) Nevertheless marked on the chip as PEB 4264

PEB 3265/

PEB 4265 PEB 3265/

PEB 4265-22)

2) Nevertheless marked on the chip as PEB 4265

PEB 3265/

PEB 4266

Longitudinal

Balance 53 dB 60 dB 53 dB 60 dB 53 dB

Maxim u m D C

feeding 32 mA 50 mA 32 mA 50 mA 32 mA

Neg. Battery

Voltages 22222/3

Add. positive

Voltages 11110

Internal Ringing 45 Vrms

balanced no 85 Vrms

balanced 85 Vrms

balanced 85 Vrms bal.,

50 Vrms unbal.

ITDF3)

3) Integrated Test and Diagnosis Functions (board or line testing)

no no yes yes yes

TTX 1.2 Vrms no 2.5 Vrms 2.5 Vrms 2.5 Vrms

Add-Ons4)

4) The add-on functions are DTMF d etection, Caller ID generation, Message Waiting lamp support , Three-party

Conferencing, Universal Tone Detection (UTD), Line Echo Cancellation (LEC) and Sleep Mode.

no no yes yes yes

DuSLIC

DuSLIC Chip Set Selection

Chip Set Selection Guide 5 2000-11-0 9

Preliminary

Figure 2 allows the selection of a DuSLIC chip set according to the required technical

features an d c haracteristics (for alternative represen tation s e e also Table 1).

Figure 2 DuSLIC Chip Set Feature Selection1)

1) For an explanation of the abbreviations in Figure 2 see the footnotes below Table 1.

ezm38000.emf

50 mA

DC feeding

60 dB

long. bal.

2-8 lines

TTX

Add-Ons

Internal

Ringing

DuSLIC-S DuSLIC-E

Internal

balanced

Ringing

Add-Ons

TTX

DuSLIC-S2 DuSLIC-E2

ITDF

(Testing) ITDF

(Testing)

balanced

85 Vrms

balanced

45 Vrms

yes

1.2 Vrms

2.5 Vrms

Add-Ons:

- DTMF detection,

- Caller ID generation,

- Message Waiting lam p support,

- Three-party Conferencing,

- Universal Tone Detection (UTD),

- Line Echo Cancellation (LEC)

- Sleep Mode

unbalanced

50 Vrms

DuSLIC-P

yes

2.5 Vrms

DuSLIC

Short Description

Chip Set Selection Guide 6 2000-11-0 9

Preliminary

3 Short Description

3.1 DuSLIC-S Chip Set

DuSLI C-S is the s tandard Du SLIC chip set feat uring basic functiona lity like BO RSCHT

functi ons, Tele tax (TTX) mete ring, in ternal r inging with ringing amplit udes up to 45 Vrms

and support f or ex t ernal ringing.

The DuSLIC-S chip set consists of the SLICOFI-2S (PEB 3264) and the SLIC-S

(PEB 4264).

3.2 DuSLIC-S2 Chip Set

DuSLI C-S2 i s a high er perfo rman ce vers ion of th e DuSLI C-S c hip set consis ting of the

SLICOF I-2S2 (P EB 3264-2) and the SLIC-S2 (PEB 4264-2 ).

Compared to the DuSLIC-S chip set, DuSLIC-S2 offers no support for internal ringing

and Teletax metering and higher performance for longitudinal balance and maximum DC

feedin g (s ee Table 2).

Table 2 Performance Differences DuSLIC-S2 to DuSLIC-S Chip Set

Chip Set DuSLIC-S21)

1) see also Table 1 for general overview

DuSLIC-S

Longitudinal

Balance 60 dB 53 dB

Maxim u m D C

feeding 50 mA 32 mA

Internal Ringing no 45 Vrms

balanced

TTX no 1.2 Vrms

DuSLIC

Short Description

Chip Set Selection Guide 7 2000-11-0 9

Preliminary

3.3 DuSLIC-E Chip Set

DuSLIC-E is a chip set featuring extended functionality compared to the standard

version DuSLIC-S.

Compared to the Du SLIC-S chip set, DuSLIC-E additionally offers the following powerful

functions:

– Higher internal ringing amplitude up to 85 Vrms

– Higher Teletax (TTX) metering volt age of 2.5 Vrms

– Integrat ed Test an d D iagnosis F unctions (IDTF)

– DTMF det ec t ion

– Caller ID generation

– Message waitin g lamp support

– Three-party c onf erencing

– Universal Tone Detec tion (UTD )

– Line Echo Cancellation (LEC)

– Sleep M ode

The DuSLIC-E chip set consists of the SLICOFI-2 (PEB 3265) and the SLIC-E

(PEB 4265).

3.4 DuSLIC-E2 Chip Set

DuSLI C-E2 i s a high er perfo rman ce vers ion of th e DuSLI C-E c hip set consis ting of the

SLICOFI-2 (PEB 3265) and the SLIC-E2 (PEB 4265-2). Compared to the DuSLIC-E chip

set, DuSLIC-E2 offers higher performance for longitudinal balance and maximum DC

feedin g (s ee Table 3).

Table 3 Performance Differences DuSLIC-E2 to DuSLIC-E Chip Set

Chip Set DuSLIC-E21)

1) see also Table 1 for general overview

DuSLIC-E

Longitudinal

Balance 60 dB 53 dB

Maxim u m D C

feeding 50 mA 32 mA

DuSLIC

Short Description

Chip Set Selection Guide 8 2000-11-0 9

Preliminary

3.5 DuSLIC-P Chip Set

DuSLIC-P is a chip set for extremely power sensitive applications or for applications

usin g int ernal unbalance d ringing .

The DuSLIC-P chip set consists of the SLICOFI-2 (PEB 3265) and the SLIC-P

(PEB 4266).

Compared to the D uSLIC-E chip set, DuSLIC -P additionally offers unba lanced internal

ringin g up to 50 Vrms or balance d r inging up to 85 Vrms. Additiona lly externa l ringing is

suppo rted gi vin g the pos sibili ty of havin g up to three b at tery fe edin g voltage s to re duce

power consumption even further (see Table 4).

Table 4 Feature Differences DuSLIC-P to DuSLIC-E Chip Set

Chip Set DuSLIC-P1)

1) see also Table 1 for general overview

DuSLIC-E

Neg. Battery

Voltages 2/3 2

Add. positive

Voltages 01

Internal Ringing 85 Vrms bal.,

50 Vrms unbal. 85 Vrms

balanced

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