ADS7809U/1KE4 - Texas Instruments

16-Bit 10µs Serial CMOS Sampling

ANALOG-TO-DIGITAL CONVERTER

FEATURES

●100kHz SAMPLING RATE

●86dB SINAD WITH 20kHz INPUT

● ±2LSB INL

●DNL: 16 Bits No Missing Codes

● SIX SPECIFIED INPUT RANGES

● SERIAL OUTPUT

● SINGLE +5V SUPPLY OPERATION

●PIN-COMPATIBLE WITH 12-BIT ADS7808

●USES INTERNAL OR EXTERNAL

REFERENCE

●100mW MAX POWER DISSIPATION

●0.3" SO-20

●SIMPLE DSP INTERFACE

DESCRIPTION

The ADS7809 is a complete 16-bit sampling Analog-to-

Digital (A/D) converter using state-of-the-art CMOS struc-

tures. It contains a 16-bit capacitor-based Successive Ap-

proximation Register (SAR) A/D converter with sample-and-

hold, reference, clock, and a serial data interface. Data can

be outputted using the internal clock, or can be synchronized

to an external data clock. The ADS7809 also provides an

output synchronization pulse for ease of use with standard

DSP processors.

The ADS7809 is specified at a 100kHz sampling rate, and

specified over the full temperature range. Laser-trimmed

scaling resistors provide various input ranges including ±10V

and 0V to 5V, while an innovative design operates from a

single +5V supply, with power dissipation under 100mW.

The ADS7809 is available in a 0.3" SO-20, and is fully

specified for operation over the industrial –40°C to +85°C

range.

10kΩ

CDAC

4kΩ

20kΩ

5kΩ

Internal

+2.5V Ref

Clock

BUSY

Data Clock

Serial Data

Successive Approximation Register and Control Logic

Serial

Data

Out

Comparator

Buffer

20kΩ

R/C CS Power

Down

R1IN

R2IN

R3IN

REF

CAP

ADS7809

SBAS017C – NOVEMBER 1996 – REVISED OCTOBER 2006

www.ti.com

PRODUCTION DATA information is current as of publication date.

Products conform to specifications per the terms of Texas Instruments

standard warranty. Production processing does not necessarily include

testing of all parameters.

Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of

Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.

All trademarks are the property of their respective owners.

ADS7809

2SBAS017C

www.ti.com

Analog Inputs: R1IN .......................................................................... ±25V

R2IN .......................................................................... ±25V

R3IN .......................................................................... ±25V

REF ................................. VANA + 0.3V to AGND2 – 0.3V

CAP ....................................... Indefinite Short to AGND2,

......................................................................... Momentary Short to VANA

Ground Voltage Differences: DGND, AGND2.................................±0.3V

VANA ...................................................................................................... 7V

VDIG to VANA ....................................................................................... +0.3

VDIG ....................................................................................................... 7V

Digital Inputs ............................................................–0.3V to VDIG + 0.3V

Maximum Junction Temperature .................................................. +165°C

Internal Power Dissipation............................................................ 700mW

Lead Temperature (soldering, 10s) .............................................. +300°C

ABSOLUTE MAXIMUM RATINGS(1)

MINIMUM

SIGNAL-TO-

MAXIMUM NO MISSING (NOISE + SPECIFIED

LINEARITY CODE LEVEL DISTORTION) PACKAGE- PACKAGE TEMPERATURE PACKAGE ORDERING TRANSPORT

PRODUCT ERROR (LSB) (LSB) RATIO (dB) LEAD DESIGNATOR RANGE MARKING NUMBER MEDIA, QUANTITY

ADS7809U ±31583SO-20DW–40°C to +85°C ADS7809U ADS7809U Rail, 38

"""""" " "ADS7809U/1K Tape and Reel, 1000

ADS7809UB ±21686

"" "ADS7809UB ADS7809UB Rail, 38

"""""" " "ADS7809UB/1K Tape and Reel, 1000

NOTE: (1) For the most current package and ordering information, see the Package Option Addendum at the end of this document, or see the TI web site at www.ti.com.

PACKAGE/ORDERING INFORMATION

(1)

ELECTROSTATIC

DISCHARGE SENSITIVITY

This integrated circuit can be damaged by ESD. Texas Instru-

ments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling

and installation procedures can cause damage.

ESD damage can range from subtle performance degrada-

tion to complete device failure. Precision integrated circuits

may be more susceptible to damage because very small

parametric changes could cause the device not to meet its

published specifications.

NOTE: (1) Stresses above those listed under

Absolute Maximum Ratings

may

cause permanent damage to the device. Exposure to absolute maximum

conditions for extended periods may affect device reliability.

ADS7809 3

SBAS017C www.ti.com

ELECTRICAL CHARACTERISTICS

At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors (see Figure 4), unless otherwise specified.

ADS7809U ADS7809UB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

RESOLUTION 16 ✻Bits

ANALOG INPUT

Voltage Ranges ±10, 0V to 5V, etc. (See Table I)

Impedance See Table I

Capacitance 35 ✻pF

THROUGHPUT SPEED

Complete Cycle Acquire and Convert 10 ✻µs

Throughput Rate 100 ✻kHz

DC ACCURACY

Integral Linearity Error ±3±2 LSB(1)

Differential Linearity Error +3, –2±1LSB

No Missing Codes 15 16 Bits

Transition Noise(2) 1.3 ✻LSB

Full-Scale Error(3,4) ±0.5 ✻%

Full-Scale Error Drift ±7✻ppm/°C

Full-Scale Error(3,4) Ext. 2.5000V Ref ±0.5 ✻%

Full-Scale Error Drift Ext. 2.5000V Ref ±2✻ppm/°C

Bipolar Zero Error(3) Bipolar Ranges ±10 ✻mV

Bipolar Zero Error Drift Bipolar Ranges ±2✻ppm/°C

Unipolar Zero Error(3) 0V to 10V Ranges ±5✻mV

Unipolar Zero Error(3) 0V to 4V, 0V to 5V Ranges ±3✻mV

Unipolar Zero Error Drift Unipolar Ranges ±2✻ppm/°C

Recovery to Rated Accuracy 1µF Capacitor to CAP 1 ✻ms

after Power-Down

Power-Supply Sensitivity +4.75V < VD < +5.25V ±8✻LSB

(VDIG = VANA = VD)

AC ACCURACY

Spurious-Free Dynamic Range fIN = 20kHz 90 100 96 ✻dB(5)

Total Harmonic Distortion fIN = 20kHz –100 –90 ✻–94 dB

Signal-to-(Noise + Distortion) fIN = 20kHz 83 88 86 ✻dB

–60dB Input 30 32 dB

Signal-to-Noise fIN = 20kHz 83 88 86 ✻dB

Full-Power Bandwidth(6) 250 ✻kHz

SAMPLING DYNAMICS

Aperture Delay 40 ✻ns

Transient Response FS Step 2 ✻µs

Overvoltage Recovery(7) 150 ✻ns

REFERENCE

Internal Reference Voltage No Load 2.48 2.5 2.52 ✻✻✻ V

Internal Reference Source Current 1 ✻µA

(Must use external buffer)

External Reference Voltage Range 2.3 2.5 2.7 ✻✻✻ V

For Specified Linearity

External Reference Current Drain Ext. 2.5000V Ref 100 ✻µA

DIGITAL INPUTS

Logic Levels

VIL –0.3 +0.8 ✻✻V

VIH(8) +2.0 VD + 0.3V ✻✻V

IIL VIL = 0V ±10 ✻µA

IIH VIH = 5V ±10 ✻µA

ADS7809

4SBAS017C

www.ti.com

ELECTRICAL CHARACTERISTICS (Cont.)

At TA = –40°C to +85°C, fS = 100kHz, VDIG = VANA = +5V, using internal reference and fixed resistors as shown in Figure 4, unless otherwise specified.

ADS7809U ADS7809UB

PARAMETER CONDITIONS MIN TYP MAX MIN TYP MAX UNITS

DIGITAL OUTPUTS

Data Format Serial 16 bits

Data Co Binary Two’s Complement or Straight Binary

Pipeline Delay Conversion results only available after completed conversion.

Data Clock Selectable for internal or external data clock

Internal EXT/INT LOW 2.3 ✻MHz

(Output Only When

Transmitting Data)

External EXT/INT HIGH 0.1 10 ✻✻MHz

(Can Run Continually)

VOL ISINK = 1.6mA +0.4 ✻V

VOH ISOURCE = 500µA+4 ✻V

Leakage Current High-Z State, ±5✻µA

VOUT = 0V to VDIG

Output Capacitance High-Z State 15 ✻pF

POWER SUPPLIES

Specified Performance

VDIG Must be ≤ VANA +4.75 +5 +5.25 ✻✻✻ V

VANA +4.75 +5 +5.25 ✻✻✻ V

IDIG 0.3 ✻mA

IANA 16 ✻mA

Power Dissipation: PWRD LOW VANA = VDIG = 5V, fS = 100kHz 100 ✻mW

PWRD HIGH 50 ✻µW

TEMPERATURE RANGE

Specified Performance –40 +85 ✻✻°C

Derated Performance –55 +125 ✻✻°C

Storage –65 +150 ✻✻°C

Thermal Resistance (

JA)

SO 75 ✻°C/W

✻ Same as specification for ADS7809U.

NOTES: (1) LSB means Least Significant Bit. For the ±10V input range, one LSB is 305µV.

(2) Typical rms noise at worst case transitions and temperatures.

(3) As measured with fixed resistors shown in Figure 4. Adjustable to zero with external potentiometer.

(4) For bipolar input ranges, full-scale error is the worst case of –Full Scale or +Full Scale untrimmed deviation from ideal first and last code transitions,

divided by the transition voltage (not divided by the full-scale range) and includes the effect of offset error. For unipolar input ranges, full-scale error

is the deviation of the last code transition divided by the transition voltage. It also includes the effect of offset error.

(5) All specifications in dB are referred to a full-scale ±10V input.

(6) Full-Power Bandwidth defined as Full-Scale input frequency at which Signal-to-(Noise + Distortion) degrades to 60dB.

(7) Recovers to specified performance after 2 • FS input overvoltage.

(8) The minimum VIH level for the DATACLK signal is 3V.

ADS7809 5

SBAS017C www.ti.com

PIN # NAME DESCRIPTION

PIN ASSIGNMENTS

1R1

IN Analog Input. See Table I and Figure 4 for input range connections.

2 AGND1 Analog Ground. Used internally as ground reference point. Minimal current flow.

3R2

IN Analog Input. See Table I and Figure 4 for input range connections.

4R3

IN Analog Input. See Table I and Figure 4 for input range connections.

5 CAP Reference Buffer Capacitor. 2.2µF Tantalum to ground.

6 REF Reference Input/Output. Outputs internal 2.5V reference. Can also be driven by external system reference. In both cases,

bypass to ground with a 2.2µF Tantalum capacitor.

7 AGND2 Analog Ground

8 SB/BTC Select Straight Binary or Binary Two’s Complement data output format. If HIGH, data will be output in a Straight Binary format. If

LOW, data will be output in a Binary Two’s Complement format.

9 EXT/INT Select External or Internal Clock for transmitting data. If HIGH, data will be output synchronized to the clock input on DATACLK. If

LOW, a convert command will initiate the transmission of the data from the previous conversion, along with 16 clock pulses output

on DATACLK.

10 DGND Digital Ground

11 SYNC Synch Output. If EXT/INT is HIGH, either a rising edge on R/C with CS LOW or a falling edge on CS with R/C HIGH will output a

pulse on SYNC synchronized to the external DATACLK.

12 DATACLK Either an input or an output depending on the EXT/INT level. Output data will be synchronized to this clock. If EXT/INT is LOW,

DATACLK will transmit 16 pulses after each conversion, and then remain LOW between conversions.

13 DATA Serial Data Output. Data will be synchronized to DATACLK, with the format determined by the level of SB/BTC. In the external clock

mode, after 16 bits of data, the ADS7809 will output the level input on TAG as long as CS is LOW and R/C is HIGH (see Figure 3). If

EXT/INT is LOW, data will be valid on both the rising and falling edges of DATACLK, and between conversions DATA will stay at the

level of the TAG input when the conversion was started.

14 TAG Tag Input for use in external clock mode. If EXT/INT is HIGH, digital data input on TAG will be output on DATA with a delay of 16

DATACLK pulses as long as CS is LOW and R/C is HIGH. See Figure 3.

15 R/C Read/Convert Input. With CS LOW, a falling edge on R/C puts the internal sample-and-hold into the hold state and starts a conversion.

When EXT/INT is LOW, this also initiates the transmission of the data results from the previous conversion. If EXT/INT is HIGH, a

rising edge on R/C with CS LOW, or a falling edge on CS with R/C HIGH, transmits a pulse on SYNC and initiates the transmission of

data from the previous conversion.

16 CS Chip Select. Internally OR’ed with R/C.

17 BUSY Busy Output. Falls when a conversion is started, and remains LOW until the conversion is completed and the data is latched into the

output shift register. CS or R/C must be HIGH when BUSY rises, or another conversion will start without time for signal acquisition.

18 PWRD Power Down Input. If HIGH, conversions are inhibited and power consumption is significantly reduced. Results from the previous

conversion are maintained in the output shift register.

19 VANA Analog Supply Input. Nominally +5V. Connect directly to pin 20, and decouple to ground with 0.1µF ceramic and 10µF tantalum

capacitors.

20 VDIG Digital Supply Input. Nominally +5V. Connect directly to pin 19. Must be ≤ VANA.

PIN CONFIGURATION

VDIG

VANA

PWRD

BUSY

R/C

TAG

DATA

DATACLK

SYNC

R1IN

AGND1

R2IN

R3IN

CAP

REF

AGND2

SB/BTC

EXT/INT

DGND

ADS7809

ANALOG CONNECT R1IN CONNECT R2IN

INPUT VIA 200ΩVIA 100ΩCONNECT R3IN

RANGE TO TO TO IMPEDANCE

±10V VIN AGND CAP 22.9kΩ

±5V AGND VIN CAP 13.3kΩ

±3.33V VIN VIN CAP 10.7kΩ

0V to 10V AGND VIN AGND 13.3kΩ

0V to 5V AGND AGND VIN 10.0kΩ

0V to 4V VIN AGND VIN 10.7kΩ

TABLE I. Input Range Connections. See Figure 4 for complete

information.

FIGURE 1. Basic Conversion Timing.

MODE Acquire

Convert Acquire

BUSY

CS, R/C

ADS7809

6SBAS017C

www.ti.com

TABLE II. Conversion and Data Timing. TA = –40°C to +85°C.

FIGURE 2. Serial Data Timing Using Internal Clock. (

EXT/INT

and TAG Tied LOW.)

SYMBOL DESCRIPTION MIN TYP MAX UNITS

t1Convert Pulse Width 40 6000 ns

BUSY

Delay 65 ns

BUSY

LOW 8µs

BUSY

Delay After End of Conversion 220 ns

t5Aperture Delay 40 ns

t6Conversion Time 7.6 8 µs

t7Acquisition Time 2 µs

t6 + t7Throughput Time 9 10 µs

R/C

LOW to DATACLK Delay 450 ns

t9DATACLK Period 440 ns

t10 Data Valid to DATACLK HIGH Delay 20 75 ns

t11 Data Valid After DATACLK LOW Delay 100 125 ns

t12 External DATACLK 100 ns

t13 External DATACLK HIGH 20 ns

t14 External DATACLK LOW 30 ns

t15 DATACLK HIGH Setup Time 20 t12 + 5 ns

t16

R/C

Setup Time 10 ns

t17 SYNC Delay After DATACLK HIGH 15 35 ns

t18 Data Valid Delay 25 55 ns

t19

to Rising Edge Delay 25 ns

t20 Data Available after

LOW 6 µs

MSB Valid

R/C

DATACLK

SDATA

t11

t10

2 3 15 16

Bit 14 Valid Bit 1 ValidBit 13 Valid LSB Valid

t2t3

BUSY

ADS7809 7

SBAS017C www.ti.com

ANALOG INPUT

SPECIFIC FUNCTION CS R/C BUSY EXT/INT DATACLK PWRD SB/BTC OPERATION

Initiate Conversion and 1 > 0 0 1 0 Output 0 x Initiates conversion “n”. Data from conversion “n – 1”

Output Data Using clocked out on DATA synchronized to 16 clock

Internal Clock pulses output on DATACLK.

0 1 > 0 1 0 Output 0 x Initiates conversion “n”. Data from conversion “n – 1”

clocked out on DATA synchronized to 16 clock

pulses output on DATACLK.

1 > 0 0 1 1 Input 0 x Initiates conversion “n”.

0 1 > 0 1 1 Input 0 x Initiates conversion “n”.

1 > 0 1 1 1 Input x x Outputs a pulse on SYNC followed by data from

conversion “n” clocked out synchronized to external

DATACLK.

1 > 0 1 0 1 Input 0 x Outputs a pulse on SYNC followed by data from

conversion “n – 1” clocked out synchronized to

external DATACLK.(1) Conversion “n” in process.

0 0 > 1 0 1 Input 0 x Outputs a pulse on SYNC followed by data from

conversion “n – 1” clocked out synchronized to

external DATACLK .(1) Conversion “n” in process.

Incorrect Conversions 0 0 0 > 1 x x 0 x

R/C

must be HIGH or a new conversion will

be initiated without time for acquisition.

Power-Down x x x x x 0 x Analog circuitry powered. Conversion can proceed.

x x x x x 1 x Analog circuitry disabled. Data from previous

conversion maintained in output registers.

Selecting Output Format x x x x x x 0

Serial data is output in Binary Two’s Complement format.

x x x x x x 1 Serial data is output in Straight Binary format.

NOTE: (1) See Figure 3b for constraints on previous data valid during conversion.

Initiate Conversion and

Output Data Using External

Clock

TABLE III. Control Truth Table.

BINARY TWO’S COMPLEMENT STRAIGHT BINARY

(SB/BTC LOW) (SB/BTC HIGH)

DIGITAL OUTPUT

TABLE IV. Output Codes and Ideal Input Voltages.

HEX HEX

DESCRIPTION BINARY CODE CODE BINARY CODE CODE

Full-Scale Range ±10 ±5±3.33V 0V to 10V 0V to 5V 0V to 4V

Least Significant Bit (LSB)

305µV 153µV 102µV 153µV76µV61µV

+Full Scale (FS – 1LSB)

9.999695V 4.999847V 3.333231V 9.999847V 4.999924V 3.999939V 0111 1111 1111 1111 7FFF 1111 1111 1111 1111 FFFF

Midscale 0V 0V 0V 5V 2.5V 2V 0000 0000 0000 0000 0000 1000 0000 0000 0000 8000

One LSB Below Midscale

–305µV–153µV–102µV 4.999847V 2.499924V 1.999939V 1111 1111 1111 1111 FFFF 0111 1111 1111 1111 7FFF

–Full Scale –10V –5V –3.333333V 0V 0V 0V 1000 0000 0000 0000 8000 0000 0000 0000 0000 0000

ADS7809

8SBAS017C

www.ti.com

EXTERNAL

DATACLK

Bit 15 (MSB)

R/C

DATA

TAG

BUSY

SYNC

12 34 1314

Bit 14 Bit 1

Bit 0 (LSB)

Tag 0

Tag 1

Tag 1 Tag 2 Tag 15 Tag 16

Tag 17 Tag 18

Tag 0

Tag 19

t18

t17

t12

t16

t12

t13 t14

t15

FIGURE 3a. Conversion and Read Timing with External Clock. (

EXT/INT

Tied High.) Read After Conversion.

ADS7809 9

SBAS017C www.ti.com

Bit 15 (MSB)

Bit 0 (LSB)

ag 0 Tag 1

Tag 1 Tag 16 Tag 17 Tag 18 Tag 19

Tag 0

TAG

EXTERNAL

DATACLK

R/C

DATA

BUSY

SYNC

FIGURE 3b. Conversion and Read Timing with External Clock. (

EXT/INT

Tied High.) Read During Conversion (Previous

Conversion Results).

ADS7809

10 SBAS017C

www.ti.com

200Ω

AGND2

REF

CAP

R2IN

AGND1

R1IN

R3IN

100Ω

2.2µF

VIN

+5V

33.2kΩ

576kΩ

50kΩ

50kΩ2.2µF+

With Trim

Input Range Without Trim (Adjust offset first at 0V, then adjust gain)

FIGURE 4a. Offset/Gain Circuits for Unipolar Input Ranges.

0V-10V

0V-5V

0V-4V

200Ω

AGND2

REF

CAP

AGND1

100Ω

2.2µF

33.2kΩ

200Ω

AGND2

REF

CAP

R2IN

AGND1

R1IN

R3IN

100Ω

2.2µF

VIN

33.2kΩ

200Ω

AGND2

REF

CAP

R2IN

AGND1

R1IN

VIN

R3IN

100Ω

33.2kΩ

2.2µF

200Ω

AGND2

REF

CAP

AGND1

100Ω

2.2µF

+5V

33.2kΩ

2.2µF

576kΩ

50kΩ

200Ω

AGND

REF

CAP

AGND1

100Ω

33.2kΩ

2.2µF

+5V

50kΩ50kΩ576kΩ

+5V +

ADS7809 11

SBAS017C www.ti.com

With Trim

Input Range Without Trim (Adjust offset first at 0V, then adjust gain)

FIGURE 4b. Offset/Gain Circuits for Bipolar Input Ranges.

±10V

± 5V

±3.3V

200Ω

AGND2

REF

CAP

AGND1

100Ω

33.2kΩ

2.2µF

200Ω

AGND2

REF

CAP

AGND1

100Ω

33.2kΩ

2.2µF

+5V

50kΩ

50kΩ576kΩ

+5V +

200Ω

AGND2

REF

CAP

AGND1

100Ω

2.2µF

33.2kΩ

200Ω

AGND2

REF

CAP

AGND1

100Ω

2.2µF

+5V

33.2kΩ

2.2µF

576kΩ

50kΩ

200Ω

AGND2

REF

CAP

AGND1

33.2kΩ

2.2µF

100Ω

200Ω

AGND2

REF

CAP

AGND1

33.2kΩ2.2µF

2.2µF

100Ω

+5V

50kΩ+5V

50kΩ576kΩ

ADS7809

12 SBAS017C

www.ti.com

DATE REVISION PAGE SECTION DESCRIPTION

3 Absolute Maximum Ratings CAP and REF were switched.

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

10/06 C

PACKAGE OPTION ADDENDUM

www.ti.com 29-Jul-2010

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status (1) Package Type Package

Drawing Pins Package Qty Eco Plan (2) Lead/

Ball Finish MSL Peak Temp (3) Samples

(Requires Login)

ADS7809P OBSOLETE PDIP N 20 TBD Call TI Call TI Samples Not Available

ADS7809PB OBSOLETE PDIP N 20 TBD Call TI Call TI Samples Not Available

ADS7809U NRND SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Replaced by ADS8509IDW

ADS7809U/1K NRND SOIC DW 20 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Replaced by ADS8509IDWR

ADS7809U/1KE4 NRND SOIC DW 20 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Replaced by

ADS8509IBDWRG4

ADS7809UB NRND SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Replaced by ADS8509IBDW

ADS7809UB/1K NRND SOIC DW 20 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Replaced by ADS8509IBDWR

ADS7809UB/1KE4 NRND SOIC DW 20 1000 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples Not Available

ADS7809UBE4 NRND SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Replaced by

ADS8509IBDWRG4

ADS7809UBG4 NRND SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples Not Available

ADS7809UE4 NRND SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Replaced by ADS8509IDWG4

ADS7809UG4 NRND SOIC DW 20 25 Green (RoHS

& no Sb/Br) CU NIPDAU Level-3-260C-168 HR Samples Not Available

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability

information and additional product content details.

TBD: The Pb-Free/Green conversion plan has not been defined.

Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that

lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.

PACKAGE OPTION ADDENDUM

www.ti.com 29-Jul-2010

Addendum-Page 2

Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between

the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.

Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight

in homogeneous material)

(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

ADS7809U/1K SOIC DW 20 1000 330.0 24.4 10.8 13.3 2.7 12.0 24.0 Q1

ADS7809UB/1K SOIC DW 20 1000 330.0 24.4 10.8 13.0 2.7 12.0 24.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

ADS7809U/1K SOIC DW 20 1000 367.0 367.0 45.0

ADS7809UB/1K SOIC DW 20 1000 367.0 367.0 45.0

PACKAGE MATERIALS INFORMATION

www.ti.com 14-Jul-2012

Pack Materials-Page 2

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