PD - 97263B IRF1324S-7PPbF HEXFET(R) Power MOSFET Applications l High Efficiency Synchronous Rectification in SMPS l Uninterruptible Power Supply l High Speed Power Switching l Hard Switched and High Frequency Circuits D G S Benefits l Improved Gate, Avalanche and Dynamic dV/dt Ruggedness l Fully Characterized Capacitance and Avalanche SOA l Enhanced body diode dV/dt and dI/dt Capability l Lead-Free VDSS RDS(on) typ. max. ID (Silicon Limited) ID (Package Limited) 24V 0.8m 1.0m 429A 240A c D S G S S S S D 2Pak 7 Pin G D S Gate Drain Source Absolute Maximum Ratings Symbol ID @ TC = 25C ID @ TC = 100C ID @ TC = 25C IDM PD @TC = 25C VGS Parameter Continuous Drain Current, VGS @ 10V (Silicon Limited) Continuous Drain Current, VGS @ 10V (Package Limited) d Pulsed Drain Current Maximum Power Dissipation Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery Operating Junction and Storage Temperature Range Soldering Temperature, for 10 seconds f dv/dt TJ TSTG Avalanche Characteristics EAS (Thermally limited) IAR EAR Single Pulse Avalanche Energy Avalanche Current Repetitive Avalanche Energy c Max. Units 429 303 240 1640 300 2.0 20 1.6 -55 to + 175 A c c Continuous Drain Current, VGS @ 10V (Silicon Limited) W W/C V V/ns C 300 (1.6mm from case) e 230 See Fig. 14, 15, 22a, 22b, g mJ A mJ Thermal Resistance Symbol RJC RJA www.irf.com Parameter Junction-to-Case k 2 Junction-to-Ambient (PCB Mount) , D Pak j Typ. Max. Units --- 0.50 40 C/W --- 1 12/21/10 IRF1324S-7PPbF Static @ TJ = 25C (unless otherwise specified) Symbol Parameter V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current IGSS Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance RG Min. Typ. Max. Units 24 --- --- 2.0 --- --- --- --- --- --- --- 0.023 --- 0.80 1.0 --- 4.0 --- 20 --- 250 --- 200 --- -200 3.0 --- Conditions V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 5mA m VGS = 10V, ID = 160A V VDS = VGS, ID = 250A A VDS = 24V, VGS = 0V VDS = 19V, VGS = 0V, TJ = 125C nA VGS = 20V VGS = -20V d g Dynamic @ TJ = 25C (unless otherwise specified) Symbol gfs Qg Qgs Qgd Qsync td(on) tr td(off) tf Ciss Coss Crss Coss eff. (ER) Coss eff. (TR) Parameter Min. Typ. Max. Units Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Total Gate Charge Sync. (Qg - Qgd) Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance 270 --- --- --- --- --- --- --- --- --- --- --- Effective Output Capacitance (Energy Related) --- --- Effective Output Capacitance (Time Related) h --- 180 47 58 122 19 240 86 93 7700 3380 1930 4780 4970 --- 252 --- --- --- --- --- --- --- --- --- --- --- --- S nC Conditions VDS = 50V, ID = 160A ID = 75A VDS =12V VGS = 10V ID = 75A, VDS =0V, VGS = 10V VDD = 16V ID = 160A RG =2.7 VGS = 10V VGS = 0V VDS = 19V = 1.0MHz, See Fig.5 VGS = 0V, VDS = 0V to 19V , See Fig.11 VGS = 0V, VDS = 0V to 19V g ns pF g g i h Diode Characteristics Symbol IS Parameter Continuous Source Current VSD trr (Body Diode) Pulsed Source Current (Body Diode) Diode Forward Voltage Reverse Recovery Time Qrr Reverse Recovery Charge IRRM ton Reverse Recovery Current Forward Turn-On Time ISM d Min. Typ. Max. Units Conditions c A MOSFET symbol 1636 A showing the integral reverse --- --- 429 --- --- D G p-n junction diode. TJ = 25C, IS = 160A, VGS = 0V TJ = 25C VR = 20V, TJ = 125C IF = 160A di/dt = 100A/s TJ = 25C g S --- --- 1.3 V --- 71 107 ns --- 74 110 --- 83 120 nC TJ = 125C --- 92 140 --- 2.0 --- A TJ = 25C Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD) g Notes: Calculated continuous current based on maximum allowable junction ISD 160A, di/dt 600A/s, VDD V(BR)DSS, TJ 175C. Pulse width 400s; duty cycle 2%. temperature. Package limitation current is 240A. Note that current Coss eff. (TR) is a fixed capacitance that gives the same charging time limitations arising from heating of the device leads may occur with as Coss while VDS is rising from 0 to 80% VDSS. some lead mounting arrangements.(Refer to AN-1140 C oss eff. (ER) is a fixed capacitance that gives the same energy as http://www.irf.com/technical-info/appnotes/an-1140.pdf C oss while V DS is rising from 0 to 80% VDSS . Repetitive rating; pulse width limited by max. junction When mounted on 1" square PCB (FR-4 or G-10 Material). For recom temperature. mended footprint and soldering techniques refer to application note #AN-994. Limited by TJmax, starting TJ = 25C, L = 0.018mH R is measured at TJ approximately 90C RG = 25, IAS = 160A, VGS =10V. Part not recommended for use above this value. 2 www.irf.com IRF1324S-7PPbF 1000 1000 VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V BOTTOM TOP ID, Drain-to-Source Current (A) ID, Drain-to-Source Current (A) TOP 100 BOTTOM 100 4.5V 10 0.1 60s PULSE WIDTH Tj = 175C 60s PULSE WIDTH Tj = 25C 1 10 4.5V 10 100 0.1 V DS, Drain-to-Source Voltage (V) 10 100 Fig 2. Typical Output Characteristics 1000 1.8 100 RDS(on) , Drain-to-Source On Resistance (Normalized) ID, Drain-to-Source Current (A) 1 V DS, Drain-to-Source Voltage (V) Fig 1. Typical Output Characteristics T J = 175C 10 TJ = 25C 1 VDS = 15V 60s PULSE WIDTH 0.1 2 3 4 5 6 7 8 1.4 1.2 1.0 0.8 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Junction Temperature (C) Fig 4. Normalized On-Resistance vs. Temperature 12.0 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd VGS, Gate-to-Source Voltage (V) ID= 75A C oss = C ds + C gd Ciss Coss 10000 VGS = 10V 1.6 0.6 Fig 3. Typical Transfer Characteristics 100000 ID = 160A 9 VGS, Gate-to-Source Voltage (V) C, Capacitance (pF) VGS 15V 10V 8.0V 6.0V 5.5V 5.0V 4.8V 4.5V Crss 1000 10.0 VDS= 19V VDS= 12V 8.0 6.0 4.0 2.0 0.0 1 10 100 VDS, Drain-to-Source Voltage (V) Fig 5. Typical Capacitance vs. Drain-to-Source Voltage www.irf.com 0 50 100 150 200 QG, Total Gate Charge (nC) Fig 6. Typical Gate Charge vs. Gate-to-Source Voltage 3 IRF1324S-7PPbF 10000 ID, Drain-to-Source Current (A) ISD, Reverse Drain Current (A) 1000 T J = 175C OPERATION IN THIS AREA LIMITED BY R DS(on) 1000 100 1msec 100 T J = 25C 10 10msec 10 Tc = 25C Tj = 175C Single Pulse VGS = 0V 1.0 0.5 1.0 1.5 2.0 2.5 0 VSD, Source-to-Drain Voltage (V) 300 250 200 150 100 50 0 50 75 100 125 150 175 V(BR)DSS , Drain-to-Source Breakdown Voltage (V) Limited By Package 350 25 100 32 Id = 5mA 31 30 29 28 27 26 25 24 -60 -40 -20 0 20 40 60 80 100120140160180 T J , Temperature ( C ) T C , Case Temperature (C) Fig 10. Drain-to-Source Breakdown Voltage Fig 9. Maximum Drain Current vs. Case Temperature 1.4 EAS , Single Pulse Avalanche Energy (mJ) 1000 1.2 1.0 Energy (J) 10 Fig 8. Maximum Safe Operating Area 450 400 1 VDS, Drain-to-Source Voltage (V) Fig 7. Typical Source-Drain Diode Forward Voltage 0.8 0.6 0.4 0.2 0.0 ID TOP 45A 80A BOTTOM 160A 900 800 700 600 500 400 300 200 100 0 -5 0 5 10 15 20 VDS, Drain-to-Source Voltage (V) Fig 11. Typical COSS Stored Energy 4 DC 1 0.0 ID, Drain Current (A) 100sec 25 25 50 75 100 125 150 175 Starting T J , Junction Temperature (C) Fig 12. Maximum Avalanche Energy vs. DrainCurrent www.irf.com IRF1324S-7PPbF Thermal Response ( Z thJC ) C/W 1 D = 0.50 0.1 0.20 0.10 0.05 J 0.02 0.01 0.01 R1 R1 J 1 R2 R2 R3 R3 C 2 1 2 3 3 4 4 Ci= i/Ri Ci i/Ri 1E-005 i (sec) 0.02070 0.000010 0.08624 0.000070 0.24491 0.001406 0.15005 0.009080 Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc SINGLE PULSE ( THERMAL RESPONSE ) 0.001 1E-006 Ri (C/W) R4 R4 0.0001 0.001 0.01 0.1 t1 , Rectangular Pulse Duration (sec) Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case 1000 Avalanche Current (A) Duty Cycle = Single Pulse Allowed avalanche Current vs avalanche pulsewidth, tav, assuming Tj = 150C and Tstart =25C (Single Pulse) 0.01 100 0.05 0.10 10 Allowed avalanche Current vs avalanche pulsewidth, tav, assuming j = 25C and Tstart = 150C. 1 1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01 tav (sec) Fig 14. Typical Avalanche Current vs.Pulsewidth www.irf.com 5 IRF1324S-7PPbF EAR , Avalanche Energy (mJ) 250 Notes on Repetitive Avalanche Curves , Figures 14, 15: (For further info, see AN-1005 at www.irf.com) 1. Avalanche failures assumption: Purely a thermal phenomenon and failure occurs at a temperature far in excess of Tjmax. This is validated for every part type. 2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded. 3. Equation below based on circuit and waveforms shown in Figures 16a, 16b. 4. PD (ave) = Average power dissipation per single avalanche pulse. 5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase during avalanche). 6. Iav = Allowable avalanche current. 7. T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as 25C in Figure 14, 15). tav = Average time in avalanche. D = Duty cycle in avalanche = tav *f ZthJC(D, tav ) = Transient thermal resistance, see Figures 13) TOP Single Pulse BOTTOM 1.0% Duty Cycle ID = 160A 200 150 100 50 0 25 50 75 100 125 150 PD (ave) = 1/2 ( 1.3*BV*Iav) = DT/ ZthJC Iav = 2DT/ [1.3*BV*Zth] EAS (AR) = PD (ave)*tav 175 Starting T J , Junction Temperature (C) Fig 15. Maximum Avalanche Energy vs. Temperature VGS(th) , Gate threshold Voltage (V) 4.5 4.0 3.5 3.0 2.5 ID = 250A ID = 1.0mA ID = 1.0A 2.0 1.5 1.0 -75 -50 -25 0 25 50 75 100 125 150 175 200 T J , Temperature ( C ) Fig 16. Threshold Voltage Vs. Temperature 6 www.irf.com IRF1324S-7PPbF Driver Gate Drive D.U.T - - - * D.U.T. ISD Waveform Reverse Recovery Current + RG * * * * dv/dt controlled by RG Driver same type as D.U.T. I SD controlled by Duty Factor "D" D.U.T. - Device Under Test VDD P.W. Period VGS=10V Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer + D= Period P.W. + + - Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt Re-Applied Voltage Body Diode VDD Forward Drop Inductor Current Inductor Curent ISD Ripple 5% * VGS = 5V for Logic Level Devices Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel HEXFET(R) Power MOSFETs V(BR)DSS tp 15V DRIVER L VDS D.U.T RG + V - DD IAS 20V A 0.01 tp I AS Fig 22a. Unclamped Inductive Test Circuit LD Fig 22b. Unclamped Inductive Waveforms VDS VDS 90% + VDD D.U.T 10% VGS VGS Second Pulse Width < 1s Duty Factor < 0.1% td(on) Fig 23a. Switching Time Test Circuit td(off) tr tf Fig 23b. Switching Time Waveforms Id Vds Vgs L DUT 0 1K 20K VCC Vgs(th) S Qgodr Fig 24a. Gate Charge Test Circuit www.irf.com Qgd Qgs2 Qgs1 Fig 24b. Gate Charge Waveform 7 IRF1324S-7PPbF D2Pak - 7 Pin Package Outline Dimensions are shown in millimeters (inches) Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ 8 www.irf.com IRF1324S-7PPbF D2Pak - 7 Pin Part Marking Information 14 D2Pak - 7 Pin Tape and Reel Note: For the most current drawing please refer to IR website at http://www.irf.com/package/ Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site. www.irf.com IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information. 12/10 9