12/21/10
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HEXFET® Power MOSFET
S
D
G
Benefits
lImproved Gate, Avalanche and Dynamic dV/dt
Ruggedness
lFully Characterized Capacitance and Avalanche
SOA
lEnhanced body diode dV/dt and dI/dt Capability
l Lead-Free
Applications
l High Efficiency Synchronous Rectification in SMPS
l Uninterruptible Power Supply
l High Speed Power Switching
l Hard Switched and High Frequency Circuits
IRF1324S-7PPbF
GDS
Gate Drain Source
D2Pak 7 Pin
G
SS
D
SS
S
V
DSS
24V
R
DS
(
on
)
typ. 0.8mΩ
max. 1.0mΩ
I
D
(
Silicon Limited
)
429A
c
I
D (Package Limited)
240A
Absolute Maximum Ratings
Symbol Parameter Units
I
D
@ T
C
= 25°C Continuous Drain Current, V
GS
@ 10V (Silicon Limited) A
I
D
@ T
C
= 100°C Continuous Drain Current, VGS @ 10V (Silicon Limited)
I
D
@ T
C
= 25°C Continuous Drain Current, V
GS
@ 10V (Package Limited)
I
DM
Pulsed Drain Current
d
P
D
@T
C
= 25°C Maximum Power Dissipation W
Linear Derating Factor W/°C
V
GS
Gate-to-Source Voltage V
dv/dt Peak Diode Recovery
f
V/ns
T
J
Operating Junction and °C
T
STG
Storage Temperature Range
Soldering Temperature, for 10 seconds
Avalanche Characteristics
E
AS (Thermally limited)
Sin
g
le Pulse Avalanche Ener
g
y
e
mJ
I
AR
Avalanche Current
c
A
E
AR
Repetitive Avalanche Ener
g
y
g
mJ
Thermal Resistance
Symbol Parameter Typ. Max. Units
R
θJC
Junction-to-Case
k
––– 0.50 °C/W
R
θJA
Junction-to-Ambient (PCB Mount) , D
2
Pak
j
––– 40
230
See Fig. 14, 15, 22a, 22b,
300
1.6
-55 to + 175
± 20
2.0
300 (1.6mm from case)
Max.
429
c
303
c
1640
240
PD - 97263B
IRF1324S-7PPbF
2www.irf.com
Notes:
Calculated continuous current based on maximum allowable junction
temperature. Package limitation current is 240A. Note that current
limitations arising from heating of the device leads may occur with
some lead mounting arrangements.(Refer to AN-1140
http://www.irf.com/technical-info/appnotes/an-1140.pdf
Repetitive rating; pulse width limited by max. junction
temperature.
Limited by TJmax, starting TJ = 25°C, L = 0.018mH
RG = 25Ω, IAS = 160A, VGS =10V. Part not recommended for use
above this value.
S
D
G
ISD ≤ 160A, di/dt ≤ 600A/µs, VDD ≤ V(BR)DSS, TJ ≤ 175°C.
Pulse width ≤ 400µs; duty cycle ≤ 2%.
Coss eff. (TR) is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS.
Coss eff. (ER) is a fixed capacitance that gives the same energy as
Coss while VDS is rising from 0 to 80% VDSS.
When mounted on 1" square PCB (FR-4 or G-10 Material). For recom
mended footprint and soldering techniques refer to application note #AN-994.
Rθ is measured at TJ approximately 90°C
Static @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
V(BR)DSS Drain-to-Source Breakdown Volta
g
e 24 ––– ––– V
∆V(BR)DSS
/
∆TJ Breakdown Volta
g
e Temp. Coefficient ––– 0.023 ––– V/°C
RDS(on) Static Drain-to-Source On-Resistance ––– 0.80 1.0 mΩ
VGS(th) Gate Threshold Volta
g
e 2.0 ––– 4.0 V
IDSS Drain-to-Source Leaka
g
e Current ––– ––– 20 µA
––– ––– 250
IGSS Gate-to-Source Forward Leaka
g
e ––– ––– 200 nA
Gate-to-Source Reverse Leaka
g
e ––– ––– -200
RGInternal Gate Resistance ––– 3.0 ––– Ω
Dynamic @ TJ = 25°C (unless otherwise specified)
Symbol Parameter Min. Typ. Max. Units
g
fs Forward Transconductance 270 ––– ––– S
QgTotal Gate Char
g
e ––– 180 252 nC
Qgs Gate-to-Source Char
g
e ––– 47 –––
Qgd Gate-to-Drain ("Miller") Char
g
e ––– 58 –––
Qsync Total Gate Char
g
e Sync. (Qg - Qgd)––– 122 –––
td(on) Turn-On Delay Time ––– 19 ––– ns
trRise Time ––– 240 –––
td(off) Turn-Off Delay Time ––– 86 –––
tfFall Time ––– 93 –––
Ciss Input Capacitance ––– 7700 ––– pF
Coss Output Capacitance ––– 3380 –––
Crss Reverse Transfer Capacitance ––– 1930 –––
Coss eff. (ER) Effective Output Capacitance (Ener
g
y Related) ––– 4780 –––
Coss eff. (TR) Effective Output Capacitance (Time Related)
h
––– 4970 –––
Diode Characteristics
Symbol Parameter Min. Typ. Max. Units
ISContinuous Source Current ––– ––– 429
c
A
(Body Diode)
ISM Pulsed Source Current ––– ––– 1636 A
(Body Diode)
d
VSD Diode Forward Volta
g
e ––– ––– 1.3 V
trr Reverse Recovery Time ––– 71 107 ns TJ = 25°C VR = 20V,
––– 74 110 TJ = 125°C IF = 160A
Qrr Reverse Recovery Char
g
e ––– 83 120 nC TJ = 25°C di
/
dt = 100A
/
µs
g
––– 92 140 TJ = 125°C
IRRM Reverse Recovery Current ––– 2.0 ––– A TJ = 25°C
ton Forward Turn-On Time Intrinsic turn-on time is ne
g
li
g
ible (turn-on is dominated by LS+LD)
Conditions
VDS = 50V, ID = 160A
ID = 75A
VGS = 20V
VGS = -20V
MOSFET symbol
showing the
VDS =12V
Conditions
VGS = 10V
g
VGS = 0V
VDS = 19V
ƒ = 1.0MHz, See Fig.5
VGS = 0V, VDS = 0V to 19V
i
, See Fig.11
VGS = 0V, VDS = 0V to 19V
h
TJ = 25°C, IS = 160A, VGS = 0V
g
integral reverse
p-n junction diode.
Conditions
VGS = 0V, ID = 250µA
Reference to 25°C, ID = 5mA
d
VGS = 10V, ID = 160A
g
VDS = VGS, ID = 250µA
VDS = 24V, VGS = 0V
VDS = 19V, VGS = 0V, TJ = 125°C
ID = 160A
RG =2.7Ω
VGS = 10V
g
VDD = 16V
ID = 75A, VDS =0V, VGS = 10V
g
IRF1324S-7PPbF
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Fig 1. Typical Output Characteristics
Fig 3. Typical Transfer Characteristics Fig 4. Normalized On-Resistance vs. Temperature
Fig 2. Typical Output Characteristics
Fig 6. Typical Gate Charge vs. Gate-to-Source VoltageFig 5. Typical Capacitance vs. Drain-to-Source Voltage
2 3 4 5 6 7 8 9
VGS, Gate-to-Source Voltage (V)
0.1
1
10
100
1000
ID, Drain-to-Source Current (A)
TJ = 25°C
TJ = 175°C
VDS = 15V
≤60µs PULSE WIDTH
-60 -40 -20 020 40 60 80 100120140160180
TJ , Junction Temperature (°C)
0.6
0.8
1.0
1.2
1.4
1.6
1.8
RDS(on) , Drain-to-Source On Resistance
(Normalized)
ID = 160A
VGS = 10V
110 100
VDS, Drain-to-Source Voltage (V)
1000
10000
100000
C, Capacitance (pF)
VGS = 0V, f = 1 MHZ
Ciss = C gs + Cgd, C ds SHORTED
Crss = Cgd
Coss = Cds + Cgd
Coss
Crss
Ciss
0 50 100 150 200
QG, Total Gate Charge (nC)
0.0
2.0
4.0
6.0
8.0
10.0
12.0
VGS, Gate-to-Source Voltage (V)
VDS= 19V
VDS= 12V
ID= 75A
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
≤60µs PULSE WIDTH
Tj = 25°C
4.5V
0.1 110 100
VDS, Drain-to-Source Voltage (V)
10
100
1000
ID, Drain-to-Source Current (A)
4.5V
≤60µs PULSE WIDTH
Tj = 175°C
VGS
TOP 15V
10V
8.0V
6.0V
5.5V
5.0V
4.8V
BOTTOM 4.5V
IRF1324S-7PPbF
4www.irf.com
Fig 8. Maximum Safe Operating Area
Fig 10. Drain-to-Source Breakdown Voltage
Fig 7. Typical Source-Drain Diode
Forward Voltage
Fig 11. Typical COSS Stored Energy
Fig 9. Maximum Drain Current vs.
Case Temperature
Fig 12. Maximum Avalanche Energy vs. DrainCurrent
0.0 0.5 1.0 1.5 2.0 2.5
VSD, Source-to-Drain Voltage (V)
1.0
10
100
1000
ISD, Reverse Drain Current (A)
TJ = 25°C
TJ = 175°C
VGS = 0V
-5 0 5 10 15 20 25
VDS, Drain-to-Source Voltage (V)
0.0
0.2
0.4
0.6
0.8
1.0
1.2
1.4
Energy (µJ)
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
100
200
300
400
500
600
700
800
900
1000
EAS , Single Pulse Avalanche Energy (mJ)
ID
TOP 45A
80A
BOTTOM 160A
0 1 10 100
VDS, Drain-to-Source Voltage (V)
1
10
100
1000
10000
ID, Drain-to-Source Current (A)
OPERATION IN THIS AREA
LIMITED BY R DS(on)
Tc = 25°C
Tj = 175°C
Single Pulse
100µsec
1msec
10msec
DC
-60 -40 -20 020 40 60 80 100120140160180
TJ , Temperature ( °C )
24
25
26
27
28
29
30
31
32
V(BR)DSS, Drain-to-Source Breakdown Voltage (V)
Id = 5mA
25 50 75 100 125 150 175
TC , Case Temperature (°C)
0
50
100
150
200
250
300
350
400
450
ID, Drain Current (A)
Limited By Package
IRF1324S-7PPbF
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Fig 14. Typical Avalanche Current vs.Pulsewidth
1.0E-06 1.0E-05 1.0E-04 1.0E-03 1.0E-02 1.0E-01
tav (sec)
1
10
100
1000
Avalanche Current (A)
0.05
Duty Cycle = Single Pulse
0.10
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Τ j = 25°C and
Tstart = 150°C.
0.01
Allowed avalanche Current vs avalanche
pulsewidth, tav, assuming
∆Tj = 150°C and
Tstart =25°C (Single Pulse)
Fig 13. Maximum Effective Transient Thermal Impedance, Junction-to-Case
1E-006 1E-005 0.0001 0.001 0.01 0.1
t1 , Rectangular Pulse Duration (sec)
0.001
0.01
0.1
1
Thermal Response ( Z thJC ) °C/W
0.20
0.10
D = 0.50
0.02
0.01
0.05
SINGLE PULSE
( THERMAL RESPONSE )
Notes:
1. Duty Factor D = t1/t2
2. Peak Tj = P dm x Zthjc + Tc
τJ
τJ
τ1
τ1
τ2
τ2τ3
τ3
R1
R1R2
R2R3
R3
Ci i/Ri
Ci= τi/Ri
τ
τC
τ4
τ4
R4
R4Ri (°C/W) τi (sec)
0.02070 0.000010
0.08624 0.000070
0.24491 0.001406
0.15005 0.009080
IRF1324S-7PPbF
6www.irf.com
Fig 15. Maximum Avalanche Energy vs. Temperature
Notes on Repetitive Avalanche Curves , Figures 14, 15:
(For further info, see AN-1005 at www.irf.com)
1. Avalanche failures assumption:
Purely a thermal phenomenon and failure occurs at a temperature far in
excess of Tjmax. This is validated for every part type.
2. Safe operation in Avalanche is allowed as long asTjmax is not exceeded.
3. Equation below based on circuit and waveforms shown in Figures 16a, 16b.
4. PD (ave) = Average power dissipation per single avalanche pulse.
5. BV = Rated breakdown voltage (1.3 factor accounts for voltage increase
during avalanche).
6. Iav = Allowable avalanche current.
7. ∆T = Allowable rise in junction temperature, not to exceed Tjmax (assumed as
25°C in Figure 14, 15).
tav = Average time in avalanche.
D = Duty cycle in avalanche = tav ·f
ZthJC(D, tav) = Transient thermal resistance, see Figures 13)
PD (ave) = 1/2 ( 1.3·BV·Iav) = DT/ ZthJC
Iav = 2DT/ [1.3·BV·Zth]
EAS (AR) = PD (ave)·tav
25 50 75 100 125 150 175
Starting TJ , Junction Temperature (°C)
0
50
100
150
200
250
EAR , Avalanche Energy (mJ)
TOP Single Pulse
BOTTOM 1.0% Duty Cycle
ID = 160A
Fig 16. Threshold Voltage Vs. Temperature
-75 -50 -25 025 50 75 100 125 150 175 200
TJ , Temperature ( °C )
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
VGS(th), Gate threshold Voltage (V)
ID = 250µA
ID = 1.0mA
ID = 1.0A
IRF1324S-7PPbF
www.irf.com 7
Fig 23a. Switching Time Test Circuit Fig 23b. Switching Time Waveforms
Fig 22b. Unclamped Inductive Waveforms
Fig 22a. Unclamped Inductive Test Circuit
Fig 24a. Gate Charge Test Circuit Fig 24b. Gate Charge Waveform
Fig 21. Peak Diode Recovery dv/dt Test Circuit for N-Channel
HEXFET® Power MOSFETs
Circuit Layout Considerations
• Low Stray Inductance
• Ground Plane
• Low Leakage Inductance
Current Transformer
P.W. Period
di/dt
Diode Recovery
dv/dt
Ripple ≤5%
Body Diode Forward Drop
Re-Applied
Voltage
Reverse
Recovery
Current
Body Diode Forward
Current
V
GS
=10V
V
DD
I
SD
Driver Gate Drive
D.U.T. I
SD
Waveform
D.U.T. V
DS
Waveform
Inductor Curent
D = P. W .
Period
* VGS = 5V for Logic Level Devices
*
+
-
+
+
+
-
-
-
RGVDD
• dv/dt controlled by RG
• Driver same type as D.U.T.
• ISD controlled by Duty Factor "D"
• D.U.T. - Device Under Test
D.U.T
Inductor Current
R
G
I
AS
0.01
Ω
t
p
D.U.T
L
VDS
+
-V
DD
DRIVER
A
15V
20V
VGS
VDD
VDS
LD
D.U.T
+
-
Second Pulse Width < 1µs
Duty Factor < 0.1%
tp
V
(BR)DSS
I
AS
1K
VCC
DUT
0
L
S
20K
Vds
Vgs
Id
Vgs(th)
Qgs1
Qgs2QgdQgodr
VGS
VDS
90%
10%
td(on) td(off)
trtf
IRF1324S-7PPbF
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D2Pak - 7 Pin Package Outline
Dimensions are shown in millimeters (inches)
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
IRF1324S-7PPbF
www.irf.com 9
14
D2Pak - 7 Pin Part Marking Information
D2Pak - 7 Pin Tape and Reel
Data and specifications subject to change without notice.
This product has been designed and qualified for the Industrial market.
Qualification Standards can be found on IR’s Web site.
IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105
TAC Fax: (310) 252-7903
Visit us at www.irf.com for sales contact information. 12/10
Note: For the most current drawing please refer to IR website at http://www.irf.com/package/
