WXSC145.xxx - Wire Bonding Extreme Silicon Vertical Capacitor Rev 3.1 Key features Key applications n Full compatible to monolithic ceramic capacitors n n Ultra high stability of capacitance value: Any demanding applications, such as medical, aerospace, automotive industrial... n Applicable for standard wire bonding approach ( ball and wedge) w Temperature 2% (-55C to +250C) w Voltage <0.1%/Volts w Negligible capacitance loss through ageing n Custom sizes, values, shapes, tolerances and higher voltage n Decoupling / Filtering / Charge pump (i.e: Pacemakers / defibrillators) n High reliability applications n Downsizing n Low leakage current down to 100pA n Low profile Thanks to the unique IPDiA Silicon capacitor The IPDiA technology is the most appropriate technology, most of the problems encountered in solution for Chip On Board, Chip On Foil, Chip On demanding applications can be solved. Glass, Chip On Ceramic, when designers are The capacitor 250nF/mm ) integration (up to looking at utmost decoupling behaviours. than This Silicon based technology is ROHS compliant ceramic alternative to answer strong volumes and compatible with lead free reflow soldering constraints. process. This allows capability technology smaller provides footprint industry leading performances relative to the capacitor stability over the full operating voltage & temperature range. WXSC provide the highest capacitor stability over the full -55C/+250C temperature range in the market with a TC<2%. WXSC145.xxx Electrical specification Capacitance value 10 1pF 15 22 10pF: 935.145.522.210 15pF: 935.145.528.210 935.145.528.215 100pF: 33 47 Parameters Capacitance range Capacitance tolerances Operating temperature range Storage temperatures Temperature coefficient Breakdown Voltage (BV) Capacitance variation versus RVDC Equivalent Serial Inductor (ESL) Equivalent Serial Resistor (ESR) 68 22pF: 33pF: 47pF: 68pF: 935.145.528.222 935.145.528.233 935.145.528.247 935.145.528.268 150pF: 220pF: 330pF: Contact IPDIA Sales 680pF: 935.145.521.368 Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales 10pF 935.145.522.310 935.145.522.315 935.145.528.322 935.145.528.333 935.145.521.310 935.145.528.315 Contact IPDIA Sales Contact IPDIA Sales 1nF 10nF: 935.145.620.510 Contact IPDIA Sales 22nF: 935.145.827.522 935.145.624.522 Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales Contact IPDIA Sales 10nF Contact IPDIA Sales Insulation resistance Aging Reliability Capacitor height 2%, from -55 to +250C 90, 50, 30(*) 0.1 % /V (from 0 V to RVDC) Max 100 pH Max 100 mW 100GW @16V,25C 10GW @16V,250C Negligible, < 0.001% / 1000h FIT<0.017 parts / billions hours, RVDC, from -55 to +250C Max 250m (*) (*) Other values on request DC Voltage stability MLCC capacitors vs. PICS 20 10 PICS 10 0 PICS 0 C0G C0G -10 X8R -10 X8R X7R X7R -20 PICS Capacitance change (%) Capacitance change (%) Capacitance change (%) Temperature coefficient PICS vs. MLCC capacitors Capacitance change (%) Unit 0.1nF Value 10pF to 22nF 15%(*) -55 to 250 C(*) - 70 to 265 C Z5U -30 -40 Y5V -50 Z5U Z5U -60 C0G -20 -30 X7R -40 -50 -60 -70 Temperature (C) -80 -70 Y5V Y5V -50 0 50 100 Y5V -90 -80 150 -100 200 0 Temperature (C) Temperature (C) 1 2 3 4 5 6 7 Bias voltage (V) Fig.1 Capacitance change versus temperature variation compared to alternative technologies Fig.2 Capacitance change versus voltage variation compared to alternative technologies Part Number 935.145 B.2 S. Breakdown Voltage i.e: 10nF/0303 case (WXSC type) a 935.145.620.510 U Size 0= 0303 7 = 0402 1= 0202 8 = 0201 2 = 0101 3 = 0404 4 = 0504 5 = 0302 6 = 0503 8= 30V 6= 50V 5= 90V 52=90V Unit 0 = 10 f 1 = 0.1 p 2=1p 3 = 10 p 4 = 0.1 n xx Value (E6) 10 15 22 33 47 68 5=1n 6 = 10 n 7 = 0.1 8=1 9 = 10 Termination & Outline Termination Outer electrodes in 3um Aluminum (Al/Si/Cu: 98.96%/1%/0;04%) or Nickel Gold electroless (Au:0.1um/Ni:5um), other finishings are available on request such as thin fine Gold Titanium (Au: 2um) or Copper (Cu:5um). Applicable for standard wire bonding approach (ball and wedge). Package outline Typ. 0101 0201 0202 0.463 COB 0.463 0.05 60m 0.05 0.26 100m 0.463 0.05 L 0.02 0.05 Top Comp. 0.26 A size Pads opening 0.02 Min B pitch 0.26 0.02 Back Comp. size metalization A W L area Comp. size Comp. size Typical dimensions, all dimensions in mm. B 0303 0402 0404 0504 0.80 0.05 0.80 0.05 1.02 0.05 0.463 0.05 1.02 0.05 1.02 0.05 1.37 0.05 1.02 0.05 metalization area C 0.05 0.05 W 0.05 L W 0.05 0.05 e d Packaging Tape and reel, tray, waffle pack or wafer delivery. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. For more information, please visit: http://www.ipdia.com To contact us, email to: sales@ipdia.com Date of release: 28th February 2014 Document identifier : CL 431 111 615 149 IPD Capacitor Assembly Set Up Rev 1.0 Application Note Outline Silicon Capacitor for surface mounting device (SMD) assembly is a Wafer Level Chip Scale Packaging with the following features: x x x x Package dedicated to solve tombstoning effect of small SMD package; Package compatible with SMD assembly; Package without underfilling step; Interconnect available with various optional finishing for specific assembly. Assembly consideration x x x Standard pick & place equipment dedicated to WLCSP down to 400m pitch. Solder paste type 3 in most cases of EIA size. Reflow has to be done with standard lead-free profile (for SAC alloys) or according to JEDEC recommendations J-STD 020D-01. Lead Leadfree Tp: 235 C Tp: 260 C TL: 183 C TL: 217 C Ts min: 100 C Ts min: 150 C Ts max: 150 C Ts max: 200 C tL: 60-150 s tL: 60-150 s Process recommendation After soldering, no solder paste should touch the side of the capacitor die as that might results in leakage currents due to remaining flux. In order to use IPDiA standard capacitors within the JEDEC format and recommendation, the solder flux must be cleaned after reflow soldering step. Notes: for a proper flux cleaning process, "rosin" flux type (R) or "water soluble" flux type (WS) is recommended for the solder printing material. "No clean" flux (NC) solder paste is not recommended. In case the flux is not cleaned after the reflow soldering, the standard JEDEC would probably not be appropriate and the solder volume must be controlled: - using smallest aperture design for the stencil, and using finer solder paste type 4 or 5 for a proper printing process. - Mirroring pads would be the best recommendation Application Note Pad recommendation The capacitor is compatible with generic requirements for flip chip design (IPC7094). Standard IPDiA 3D package can be compliant with established EIA size (0201, 0402, 0603, ...). Die size and land pattern dimensions is set up according to following range : EIA size 0201 0402 0603 0805 1206 1812 Dimension max(X1 x X2) mm 0.86x0.66 1.26x0.76 1.86x1.16 2.26x1.46 3.46x1.86 4.76x3.66 Typical . die thickness X3 (mm) 0.1 or 0.4 Typical pad size* (mm) 0.15x0.40 0.30x0.50 0.40x0.90 0.50x1.20 0.60x1.60 0.90x3.40 Typical pad separation (X4 mm) 0.3 0.4 0.8 1 2 2.7 X3 X2 X1 Top side silicon Typ.UBM thickness 3 to 5 m X4 After soldering, no solder paste should touch the side of the capacitor die as that might result in leakage currents due to remaining flux. Rev 1.0 2 of 3 Application Note Manual Handling Considerations These capacitors are designed to be mounted with a standard SMT line, using solder printing step, pick and place machine and a final reflow soldering step. In case of manual handling and mounting conditions, please follow below recommendations: x x x x Minimize mechanical pressure on the capacitors (use of a vacuum nozzle is recommended). Use of organic tip instead of metal tip for the nozzle. Minimize temperature shocks (Substrate pre-heating is recommended). No wire bonding on 0402 47nF, 0402 100nF, 1206 1F and 1812 3,3F Process steps: x On substrate, form the solder meniscus on each land pattern targeting 100 m height after reflow (screen printing, dispensing solder paste or by wire soldering). x Pick the capacitor from the tape & reel or the Gel Pack keeping backside visible using a vacuum nozzle and organic tip. x Temporary place the capacitor on land pattern assuming the solder paste (Flux) will stick and maintain the capacitor. x Reflow the assembly module with a dedicated thermal profile (see reflow recommendation profile). Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights. For more information, please visit: http://www.ipdia.com To contact us, email to: sales@ipdia.com Date of release: 20th April 2012 Document identifier: Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: IPDiA: 935145620510-T1O 935145620510-T3O