a
AD9731
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reliable. However, no responsibility is assumed by Analog Devices for its
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may result from its use. No license is granted by implication or otherwise
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Tel: 781/329-4700 www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
REV. B
10-Bit, 170 MSPS
D/A Converter
FUNCTIONAL BLOCK DIAGRAM
ANALOG
RETURN
IOUT
IOUT
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
CLOCK
REF IN
AMP OUT
DECODERS
AND
DRIVERS
REGISTER SWITCH
NETWORK
TTL
DRIVE
LOGIC
CONTROL
AMP
INTERNAL VOLTAGE
REFERENCE
RSET REF OUT CONTROL
AMP IN
DIGITAL
–VS
DIGITAL
+VS
ANALOG
–VS
FEATURES
170 MSPS Update Rate
TTL/High Speed CMOS-Compatible Inputs
Wideband SFDR: 66 dB @ 2 MHz/50 dB @ 65 MHz
Pin-Compatible, Lower Cost Replacement for
Industry Standard AD9721 DAC
Low Power: 439 mW @ 170 MSPS
Fast Settling: 3.8 ns to 1/2 LSB
Internal Reference
Two Package Styles: 28-Lead SOIC and SSOP
APPLICATIONS
Digital Communications
Direct Digital Synthesis
Waveform Reconstruction
High Speed Imaging
5 MHz to 65 MHz HFC Upstream Path
GENERAL DESCRIPTION
The AD9731 is a 10-bit, 170 MSPS, bipolar D/A converter that is
optimized to provide high dynamic performance, yet offer lower
power dissipation and more economical pricing than afforded by
previous bipolar high performance DAC solutions. The AD9731
was designed primarily for demanding communications systems
applications where wideband spurious-free dynamic range (SFDR)
requirements are strenuous and could previously only be met by
using a high performance DAC such as the industry-standard
AD9721. The proliferation of digital communications into base
station and high volume subscriber-end markets has created a
demand for excellent DAC performance delivered at reduced
levels of power dissipation and cost. The AD9731 is the answer
to that demand.
Optimized for direct digital synthesis (DDS) waveform recon-
struction, the AD9731 provides 50 dB of wideband harmonic
suppression over a dc-to-65 MHz analog output bandwidth.
This signal bandwidth addresses the transmit spectrum in many
of the emerging digital communications applications where
signal purity is critical. Narrowband, the AD9731 provides an
SFDR of greater than 79 dB. This excellent wideband and
narrowband ac performance, coupled with a lower pricing structure,
make the AD9731 the optimum high performance DAC value.
The AD9731 is packaged in 28-lead SOIC (same footprint
as the industry-standard AD9721) and super space-saving
28-lead SSOP; both are specified to operate over the extended
industrial temperature range of –40∞C to +85∞C.
REV. B
–2–
AD9731–SPECIFICATIONS
(+VS = +5 V, –VS = –5.2 V, CLOCK = 125 MHz, RSET = 1.96 k⍀ for 20.4 mA IOUT,
VREF = –1.25 V, unless otherwise noted.)
Test
Parameter Temp Level Min Typ Max Unit
RESOLUTION 10 Bits
MAX CONVERSION RATE –40∞C to +85∞CIV 170 MHz
DC ACCURACY
Differential Nonlinearity 25∞CI 0.25 1 LSB
Full VI 0.35 1.5 LSB
Integral Nonlinearity 25∞CI 0.6 1 LSB
Full VI 0.7 1.5 LSB
INITIAL OFFSET ERROR
Zero-Scale Offset Error 25∞CI 3570 mA
Full VI 40 100 mA
Full-Scale Gain Error
1
25∞CI 2.5 5 % FS
Full VI 2.5 5 % FS
Offset Drift Coefficient V 0.04 mA/∞C
REFERENCE/CONTROL AMP
Internal Reference Voltage
2
25∞CI–1.35 –1.25 –1.15 V
Internal Reference Voltage Drift Full IV 100 mV/∞C
Internal Reference Output Current
3
Full VI –50 +500 mA
Amplifier Input Impedance 25∞CV 50 kW
Amplifier Bandwidth 25∞CV 2.5 MHz
REFERENCE INPUT
4
Reference Input Impedance 25∞CV 4.6 kW
Reference Multiplying Bandwidth
5
25∞CV 75 MHz
OUTPUT PERFORMANCE
Output Current
4, 6
25∞CV 20 mA
Output Compliance 25∞CIV–1.5 +3 V
Output Resistance 25∞CV 240 W
Output Capacitance 25∞CV 5 pF
Voltage Settling Time to 1/2 LSB (t
ST
)
7
25∞CV 3.8 ns
Propagation Delay (t
PD
)
8
25∞CV 2.9 ns
Glitch Impulse
9
25∞CV 4.1 pVs
Output Slew Rate
10
25∞CV 400 V/ms
Output Rise Time
10
25∞CV 1 ns
Output Fall Time
10
25∞CV 1 ns
DIGITAL INPUTS
Input Capacitance Full IV 2 pF
Logic “1” Voltage Full VI 2.0 V
Logic “0” Voltage Full VI 0.8 V
Logic “1” Current 25∞CVI 850mA
Logic “0” Current 25∞CVI 30100 mA
Data Setup Time (t
S
)
11
25∞CIV2 ns
Full IV 2.5 ns
Data Hold Time (t
H
)
12
25∞CIV1.0 0.1 ns
Full IV 1.0 0.1 ns
Clock Pulsewidth Low (pw
MIN
)25∞CIV2 ns
Clock Pulsewidth High (pw
MAX
)25∞CIV2 ns
SFDR PERFORMANCE (Wideband)
13
A
OUT
= 0 dBFS
2 MHz f
OUT
25∞CV 66 dB
10 MHz f
OUT
25∞CV 62 dB
20 MHz f
OUT
25∞CV 61 dB
40 MHz f
OUT
25∞CV 55 dB
65 MHz f
OUT
(Clock = 170 MHz) 25∞CV 50 dB
70 MHz f
OUT
(Clock = 170 MHz) 25∞CV 47 dB
REV. B –3–
AD9731
SPECIFICATIONS
CODE 2
CODE 3
CODE 4
CODE 1
CODE 2
DATA
CODE 1
DATA
CODE 3
DATA
CODE 4
DATA
tS tH
pw
MIN
pw
MAX
CLOCK
DATA
ANALOG OUTPUT
CLOCK
ANALOG OUTPUT
tPD
tST
SPECIFIED
ERROR BAND H
W
GLITCH AREA =
1/2 HEIGHT ⴛ WIDTH
DETAIL OF SETTLING TIME
Figure 1. Timing Diagrams
Test
Parameter Temp Level Min Typ Max Unit
SFDR PERFORMANCE (Narrowband)
13
2 MHz; 2 MHz Span 25∞CV 79 dB
25 MHz, 2 MHz Span 25∞CV 61 dB
10 MHz, 5 MHz Span (Clock = 170 MHz) 25∞CV 73 dB
INTERMODULATION DISTORTION
14
F1 = 800 kHz, F2 = 900 kHz 25∞CV 58 dB
POWER SUPPLY
15
Digital –V Supply Current 25∞CI 2737 mA
Full VI 27 42 mA
Analog –V Supply Current 25∞CI 4553 mA
Full VI 45 66 mA
Digital +V Supply Current 25∞CI 1320 mA
Full VI 15 22 mA
Power Dissipation 25∞CV 439 mW
Full V 449 mW
PSRR 25∞CV 100 mA/V
NOTES
1
Measured as an error in ratio of full-scale current to current through R
SET
(640 mA nominal); ratio is nominally 32. DAC load is virtual ground.
2
Internal reference voltage is tested under load conditions specified in Internal Reference Output current specification.
3
Internal reference output current defines load conditions applied during Internal Reference Voltage test.
4
Full-scale current variations among devices are higher when driving REFERENCE IN directly.
5
Frequency at which a 3 dB change in output of DAC is observed; R
L
= 50 W; 100 mV modulation at midscale.
6
Based on I
FS
= 32 (CONTROL AMP IN/R
SET
) when using internal control amplifier. DAC load is virtual ground.
7
Measured as voltage settling at midscale transition to ±0.5 LSB, R
L
= 50 W.
8
Measured from 50% point of rising edge of CLOCK signal to 1/2 LSB change in output signal.
9
Peak glitch impulse is measured as the largest area under a single positive or negative transient.
10
Measured with R
L
= 50 W and DAC operating in latched mode.
11
Data must remain stable for specified time prior to rising edge of CLOCK.
12
Data must remain stable for specified time after rising edge of CLOCK.
13
SFDR is defined as the difference in signal energy between the full-scale fundamental signal and worst-case spurious frequencies in the output spectrum window.
The frequency span is dc-to-Nyquist unless otherwise noted.
14
Intermodulation distortion is the measure of the sum and difference products produced when a two-tone input is driven into the DAC. The distortion products
created will manifest themselves at (2F
2
–F
1
) and (2F
1
–F
2
) of the two tones.
15
Supply voltages should remain stable within ±5% for nominal operation.
Specifications subject to change without notice.
REV. B
AD9731
–4–
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD9731 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
ORDERING GUIDE
Temperature Package Package
Model Range Description Options
AD9731BR –40∞C to +85∞C28-Lead Wide Body (SOIC) R-28
AD9731BR-REEL –40∞C to +85∞C28-Lead Wide Body (SOIC) R-28
AD9731BRS –40∞C to +85∞C28-Lead Shrink Small (SSOP) RS-28
AD9731BRS-REEL –40∞C to +85∞C28-Lead Shrink Small (SSOP) RS-28
AD9731-PCB 0∞C to 70∞CPCB
EXPLANATION OF TEST LEVELS
Test Level Definition
I100% production tested
II The parameter is 100% production tested at
25∞C; sampled at temperature production.
III Sample tested only
IV Parameter is guaranteed by design and
characterization testing.
VParameter is a typical value only.
VI All devices are 100% production tested at 25∞C;
guaranteed by design and characterization testing
for industrial temperature range devices.
ABSOLUTE MAXIMUM RATINGS*
Analog Output . . . . . . . . . . . . . . . . . . . . . . . . . . . . –V
S
to +V
S
+V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +6 V
Digital Inputs . . . . . . . . . . . . . . . . . . . . . . . . . –0.7 V to +V
S
–V
S
. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . –7 V
Analog Output Current . . . . . . . . . . . . . . . . . . . . . . . . 30 mA
Control Amplifier Input Voltage Range . . . . . . . . 0 V to –4 V
Reference Input Voltage Range . . . . . . . . . . . . . . . 0 V to –V
S
Maximum Junction Temperature . . . . . . . . . . . . . . . . 150∞C
Operating Temperature Range . . . . . . . . . . . –40∞C to +85∞C
Internal Reference Output Current . . . . . . . . . . . . . . . 500 mA
Lead Temperature (10 sec Soldering) . . . . . . . . . . . . . 300∞C
Storage Temperature . . . . . . . . . . . . . . . . . . –65∞C to +165∞C
Control Amplifier Output Current . . . . . . . . . . . . . ±2.5 mA
*Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
REV. B
AD9731
–5–
PIN FUNCTION DESCRIPTIONS
Pin No. Mnemonic Function
1D9(MSB) Most significant data bit of digital input word
2–9 D8–D1 Eight bits of 10-bit digital input word
10 D0(LSB) Least significant data bit of digital input word
11 CLOCK TTL-compatible edge-triggered latch enable signal for on-board registers
12, 13 NC No internal connection to this pin
14 DIGITAL +V
S
5 V supply voltage for digital circuitry
15, 18, 28 GND Converter ground
16 DIGITAL –V
S
–5.2 V supply voltage for digital circuitry
17 R
SET
Connection for external reference set resistor; nominal 1.96 kW. Full-scale output
current = 32 (control amp in V/R
SET
).
19 ANALOG RETURN Analog return. This point and the reference side of the DAC load resistors should be
connected to the same potential (nominally ground).
20 I
OUT
Analog current output; full-scale current occurs with a digital word input of all “1s.” With
external load resistor, output voltage = I
OUT
(R
LOAD
储R
INTERNAL
). R
INTERNAL
is
nominally 240 W.
21 I
OUTB
Complementary analog current output; full-scale current occurs with a digital word input
of all “0s.”
22 ANALOG –V
S
Negative analog supply, nominally –5.2 V
23 REF IN Normally connected to CONTROL AMP OUT (Pin 24). Direct line to DAC current
source network. Voltage changes (noise) at this point have a direct effect on the full-scale
output current of the DAC. Full-scale current output = 32 (CONTROL AMP IN/R
SET
)
when using the internal amplifier. DAC load is virtual ground.
24 CONTROL AMP OUT Normally connected to REF IN (Pin 23). Output of internal control amplifier that provides
a reference for the current switch network.
25 REF OUT Normally connected to CONTROL AMP IN (Pin 26). Internal voltage reference,
nominally –1.25 V.
26 CONTROL AMP IN Normally connected to REF Out (Pin 25) if not connected to external reference.
27 DIGITAL –V
S
Negative digital supply, nominally –5.2 V.
GND
DIGITAL –VS
CONTROL AMP IN
REF OUT
CONTROL AMP OUT
REF IN
ANALOG –VS
IOUTB
IOUT
ANALOG RETURN
GND
RSET
DIGITAL –VS
GND
D8
D7
D9(MSB)
D6
D5
D4
D3
D2
D1
D0(LSB)
CLOCK
NC
NC
DIGITAL +VS
TOP VIEW
(Not to Scale)
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
3
4
5
6
7
8
9
10
11
12
13
14
AD9731
NC = NO CONNECT
PIN CONFIGURATION
REV. B
AD9731
–6–
–Typical Performance Characteristics
fOUT – MHz
80
10
SFDR – dB
75
70
65
60
55
50 20 30 40 50 60 70 80
TPC 1. Narrowband SFDR (Clock = 170 MHz) vs.
f
OUT
Frequency
f
OUT
– MHz
80
10
SFDR – dB
75
70
65
60
55
50 20 30 40 50 60
85
TPC 2. Narrowband SFDR (Clock = 125 MHz) vs.
f
OUT
Frequency
f
OUT
– MHz
0
SFDR – dB
75
70
65
60
510
55
50
15 20
45
40
0dBFS
–6dBFS
–12dBFS
TPC 3. Wideband SFDR, f
CLK
= 50 MSPS
TPC 4. Wideband SFDR, f
CLK
= 125 MSPS
TPC 5. Wideband SFDR, f
CLK
= 170 MSPS
TPC 6. SINAD, A
OUT
= 0 dBFS
f
OUT – MHz
0
SFDR – dB
75
70
65
60
10 20 30
55
50
40 50
45
40
0dBFS
–6dBFS
–12dBFS
fOUT – MHz
0
SFDR – dB
70
65
60
10 20 30 40 50
55
50
60 70 80
45
40
0dBFS
–6dBFS
–12dBFS
fCLK – MHz
SINAD – dB
60
55
50
50 100
45
40
150 200
35
fOUT = 1MHz
fOUT = 10MHz
fOUT = 20MHz
fOUT = 40MHz
0
REV. B
AD9731
–7–
IOUT – mA
SFDR – dB
60
55
50
20 18 10 6 2
45
40 16 14 12 8 4
TPC 7. SFDR vs. I
OUT
(Clock =125 MHz/f
OUT
= 40 MHz)
LSB
0.4
–0.4
–0.3
–0.2
–0.1
0
0.3
0.2
0.1
TPC 8. Typical Differential Nonlinearity
Performance (DNL)
LSB
0.4
–0.6
–0.4
–0.2
0
0.2
0.6
TPC 9. Typical Integral Nonlinearity
Performance (INL)
TPC 10. Wideband SFDR 2 MHz f
OUT
; 125 MHz Clock
TPC 11. Wideband SFDR 10 MHz f
OUT
;
125 MHz Clock
TPC 12. Wideband SFDR 20 MHz f
OUT
;
125 MHz Clock
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
ENCODE = 125MHz
f
OUT
= 2MHz
SPAN = 62.5MHz
0Hz
START
6.25MHz/DIV 62.5MHz
STOP
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
ENCODE = 125MHz
fOUT = 10MHz
SPAN = 62.5MHz
0Hz
START
6.25MHz/DIV 62.5MHz
STOP
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
ENCODE = 125MHz
f
OUT
= 20MHz
SPAN = 62.5MHz
0Hz
START
6.25MHz/DIV 62.5MHz
STOP
REV. B
AD9731
–8–
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
ENCODE = 125MHz
f
OUT
= 40MHz
SPAN = 62.5MHz
0Hz
START
6.25MHz/DIV 62.5MHz
STOP
TPC 13. Wideband SFDR 40 MHz f
OUT
;
125 MHz Clock
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0Hz
START
8.5MHz/DIV 85MHz
STOP
ENCODE = 170MHz
f
OUT
= 65MHz
SPAN = 85MHz
TPC 14. Wideband SFDR 65 MHz f
OUT
; 170 MHz Clock
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0Hz
START
8.5MHz/DIV 85MHz
STOP
ENCODE = 170MHz
f
OUT
= 70MHz
SPAN = 85MHz
TPC 15. Wideband SFDR 70 MHz f
OUT
;
170 MHz Clock
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0Hz
START
200kHz/DIV 2MHz
STOP
ENCODE = 125MHz
AOUT1 = 800kHz
AOUT2 = 900kHz
SPAN = 2MHz
TPC 16. Wideband Intermodulation Distortion
F1 = 800 kHz; F2 = 900 kHz; 125 MHz Clock;
Span = 2 MHz
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0Hz
START
6.25MHz/DIV 62.5MHz
STOP
ENCODE = 125MHz
AOUT1 = 800kHz
AOUT2 = 900kHz
SPAN = 62.5MHz
TPC 17. Wideband Intermodulation Distortion
F1 = 800 kHz; F2 = 900 kHz; 125 MHz Clock;
Span = 62.5 MHz
REV. B
AD9731
–9–
THEORY AND APPLICATIONS
The AD9731 high speed digital-to-analog converter utilizes
most significant bit decoding and segmentation techniques to
reduce glitch impulse and deliver high dynamic performance
on lower power consumption than previous bipolar DAC
technologies.
The design is based on four main subsections: the decoder/
driver circuits, the edge-triggered data register, the switch net-
work, and the control amplifier. An internal band gap reference
is included to allow operation of the device with minimum
external support components.
Digital Inputs/Timing
The AD9731 has TTL/high speed CMOS-compatible single-ended
inputs for data inputs and clock. The switching threshold is 1.5 V.
In the decoder/driver section, the three MSBs are decoded to
seven “thermometer code” lines. An equalizing delay is included
for the seven least significant bits and the clock signals. This
delay minimizes data skew and data setup and hold times at the
register inputs.
The on-board register is rising edge triggered and should be
used to synchronize data to the current switches by applying a
pulse with proper data setup and hold times as shown in the
timing diagram. Although the AD9731 is designed to provide
isolation of the digital inputs to the analog output, some cou-
pling of digital transitions is inevitable. Digital feedthrough can
be minimized by forming a low pass filter at the digital input by
using a resistor in series with the capacitance of each digital
input. This common high speed DAC application technique has
the effect of isolating digital input noise from the analog output.
Input Clock and Data Timing Relationship
SINAD in a DAC is dependent on the relationship between the
position of the clock edges and the point in time at which the
input data changes. The AD9731 is rising edge triggered, and so
exhibits SINAD sensitivity when the data transition is close to
this edge. In general, the goal when applying the AD9731 is to
make the data transition close to the falling clock edge. This
becomes more important as the sample rate increases. Figure 2
shows the relationship of SINAD to clock placement from the
AD9731 and a competitive part, both sampling at 125 MSPS.
The AD9731 has excellent performance as far as the narrowness
of the “window” in which it is sensitive to SINAD.
TIME OF DATA PLACEMENT RELATIVE TO
RISING EDGE OF CLOCK – ns
60
–4
SINAD – dB
50
40
30
20
10
0
–3 –2 –1 0 1 2 3 4
COMPETITION
AD9731
Figure 2. SINAD vs. Clock Placement; f
CLK
= 125 MSPS,
f
OUT
= 20 MHz
References
The internal band gap reference, control amplifier, and refer-
ence input are pinned out to provide maximum user flexibility
in configuring the reference circuitry for the AD9731. When
using the internal reference, REF OUT (Pin 25) should be con-
nected to CONTROL AMP IN (Pin 26). CONTROL AMP OUT
(Pin 24) should be connected to REF IN (Pin 23). A 0.1 mF
ceramic capacitor connected from Pin 23 to Analog –V
S
(Pin 22)
improves settling time by decoupling switching noise from the
current sink baseline. A reference current cell provides feedback
to the control amplifier by sinking current through R
SET
(Pin 17).
Full-scale current is determined by CONTROL AMP IN and
R
SET
according to the following equation:
I
OUT
(FS) = 32(CONTROL AMP IN/R
SET
)
The internal reference is nominally –1.25 V with a tolerance of
±8% and typical drift over temperature of 100 ppm/∞C. If
greater accuracy or temperature stability is required, an external
reference can be used. The AD589 reference features 10 ppm/∞C
drift over the 0∞C to 70∞C temperature range.
Two modes of multiplying operation are possible with the
AD9731. Signals with bandwidths up to 2.5 MHz and input
swings from –0.6 V to –1.2 V can be applied to the CONTROL
AMP IN pin as shown in Figure 3. Because the control ampli-
fier is internally compensated, the 0.1 mF capacitor discussed
above can be reduced to maximize the multiplying bandwidth.
However, it should be noted that output settling time, for
changes in the digital word, will be degraded.
R
SET
–0.6 TO –1.2V
2.5MHz TYPICAL
R
T
0.1␮F
R
SET
CONTROL
AMP IN
CONTROL
AMP OUT
REFERENCE IN
AD9731
ANALOG –V
S
Figure 3. Low Frequency Multiplying Circuit
REV. B
AD9731
–10–
The REFERENCE IN pin can also be driven directly for wider
bandwidth multiplying operation. The analog signal for this mode
of operation must have a signal swing in the range of –3.3 V to
–4.25 V. This can be implemented by capacitively coupling into
REFERENCE IN a signal with a dc bias of –3.3 V (I
OUT
ª
22.5 mA) to –4.25 V (I
OUT
ª 3 mA), as shown in Figure 4, or by
dividing REFERENCE IN with a low impedance op amp whose
signal swing is limited to the stated range.
NOTE: When using an external reference, the external refer-
ence voltage must be applied prior to applying –V
S
.
REFERENCE IN
AD9731
–V
S
APPROX
–3.8V
–V
S
Figure 4. Wideband Multiplying Circuit
Analog Output
The switch network provides complementary current outputs
I
OUT
and I
OUTB
. The design of the AD9731 is based on statisti-
cal current source matching, which provides a 10-bit linearity
without trim. Current is steered to either I
OUT
or I
OUTB
in pro-
portion to the digital input word. The sum of the two currents is
always equal to the full-scale output current minus 1 LSB. The
current can be converted to a voltage by resistive loading as
shown in the block diagram. Both I
OUT
and I
OUTB
should be
equally loaded for best overall performance. The voltage that is
developed is the product of the output current and the value of
the load resistor.
An operational amplifier can also be used to perform the I-to-V
conversion of the DAC output. Figure 5 shows an example of a
circuit that uses the AD9631, a high speed, current feedback
amplifier. The resistor values in Figure 5 provide a 4.096 V
swing, centered at ground, at the output of the AD9631 amplifier.
AD9631
AD9731
R1
200⍀
10k⍀
1/2
AD708
10k⍀
R2
100⍀
RFB
400⍀
IOUT
IOUTB
CONTROL
AMP IN
REF
OUT RFF
25⍀
RL
25⍀
1/2
AD708
2048V
V
OUT
IFS
IFS
25⍀
Figure 5. I-to-V Conversion Using a Current Feedback
Amplifier
EVALUATION BOARD
The performance characteristics of the AD9731 make it ideally
suited for direct digital synthesis (DDS) and other waveform
synthesis applications. The AD9731 evaluation board provides a
platform for analyzing performance under optimum layout con-
ditions. The AD9731 also provides a reference for high speed
circuit board layout techniques.
REV. B
AD9731
–11–
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
P1
11
12
13
14
15
16
17
18
19
20
1
2
3
4
5
6
7
8
9
10
DGND
DGND
DGND
PA0
PA1
PA2
PA3
PA4
PA5
PA6
PA7
29
+V DIG
DGND
R16
50⍀
D1
U2 R1 U21
D2
D3
D4
D5
D6
D7
D8
D9
D10
DAC CLOCK
NC1
NC2
+5 DIG
1
2
3
4
5
6
7
8
9
10
11
12
13
14
GND3
DIGITAL –VS
CONTROL AMP IN
REF OUT
CONTROL AMP OUT
REF IN
ANALOG –VS
IOUT
IOUT
ANA RETURN
GND1
RSET
DIGITAL –VS
GND
28
27
26
25
24
23
22
21
20
19
18
17
16
15
U3 R2 U20
U4 R3 U19
U5 R4 U18
U6 R5 U17
U7 R6 U16
U8 R7 U15
U9 R8 U14
U10 R9 U13
U11 R10 U12
+V DIG
–V DIG
DGND
–V DIG
DGND
AGND
–V ANA
BNC1J2
AGND
AGND
R15
25⍀
R14
1960⍀
AGND
C1
0.1␮F
C2
10␮F
NOTE: R1–R10 = 50⍀
AD9731
U1
10
9
8
7
6
5
4
3
PB0
PB1
PB2
PB3
PB4
PB5
PB6
PB7
15
13
11
GND4
GND5
GND6
DGND
GND
–V
+V
–V DIG
DGND
+V DIG
28
27
26
25
24
23
22
PC0
PC1
PC2
PC3
PC4
PC5
PC6
PC7
20
18
16
14
12
+5V1
+5V2
+12V
–12V
–5V
2
1
IEN
II
37
36
35
34
33
32
31
30
E1 E2
E4E3
+VD
–VD
C37DRPF
CON1
DGND
21
19
17
GND1
GND2
GND3
CLOCK SWITCH MATRIX
JUMPER SOURCE NOTES
E5 TO E7 CON 1 PIN 10 COMPUTER PROVIDES CLOCK
E6 TO E8 J1 BNC REMOVE Y1
E6 TO E8 Y1 REMOVE R12
E8 TO E10 DG2020 DATA
EXT. CLK TO E7 GENERATOR
EXT. GND TO E9
–V DIG –VA
DGND
C7
10␮F
C8
0.1␮FC6
0.1␮F
C3
10␮F
C9
0.1␮F
C4
0.1␮F
AGND DGND
DGND
PWR
OUT
GND
BNC
Y1
OSCILLATOR
OPTIONAL
+V DIG
+V DIG+V DIG
PWR3 4
3
2
C5
0.1␮F
4.9k⍀
RP2
OPTIONAL
4.9k⍀
RP1
OPTIONAL
BNC1 DGND
R12
50⍀
J1
E6E5
E8
E7
E9 E10
R13
50⍀
+VD
R11
4.9k⍀
BNC
Figure 6. PCB Evaluation Board Schematic
REV. B
–12–
C00609–0–5/03(B)
AD9731
OUTLINE DIMENSIONS
28-Lead Standard Small Outline Package [SOIC]
Wide Body
(R-28)
Dimensions shown in millimeters and (inches)
CONTROLLING DIMENSIONS ARE IN MILLIMETERS; INCH DIMENSIONS
(IN PARENTHESES) ARE ROUNDED-OFF MILLIMETER EQUIVALENTS FOR
REFERENCE ONLY AND ARE NOT APPROPRIATE FOR USE IN DESIGN
COMPLIANT TO JEDEC STANDARDS MS-013AE
0.32 (0.0126)
0.23 (0.0091)
8ⴗ
0ⴗ
0.75 (0.0295)
0.25 (0.0098) ⴛ 45ⴗ
1.27 (0.0500)
0.40 (0.0157)
SEATING
PLANE
0.30 (0.0118)
0.10 (0.0039)
0.51 (0.0201)
0.33 (0.0130)
2.65 (0.1043)
2.35 (0.0925)
1.27 (0.0500)
BSC
28 15
14
1
18.10 (0.7126)
17.70 (0.6969)
10.65 (0.4193)
10.00 (0.3937)
7.60 (0.2992)
7.40 (0.2913)
COPLANARITY
0.10
28-Lead Shrink Small Outline Package [SSOP]
(RS-28)
Dimensions shown in millimeters
0.25
0.09
0.95
0.75
0.55
8ⴗ
4ⴗ
0ⴗ
0.05
MIN
1.85
1.75
1.65
2.00 MAX
0.38
0.22 SEATING
PLANE
0.65
BSC
0.10
COPLANARITY
28 15
14
1
10.50
10.20
9.90
5.60
5.30
5.00
8.20
7.80
7.40
COMPLIANT TO JEDEC STANDARDS MO-150AH
Revision History
Location Page
5/03–Data Sheet changed from REV. A to REV. B.
Renumbered Figures and TPCs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .Universal
Changes to SPECIFICATIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Changes to ORDERING GUIDE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Updated TPCs 1, 2, 7, 10–15 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Added TPCs 3, 4, 5, 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Added Input Clock and Data Timing Relationship section and Figure 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9
Updated Figure 5 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
Updated OUTLINE DIMENSIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12