LTC3859AEUHF#PBF - Linear Technology Corporation

LTC3859A

3859af

Typical applicaTion

DescripTion

Low IQ, Triple Output,

Buck/Buck/Boost Synchronous Controller

with Improved Burst Mode Operation

The LTC

3859A is a high performance triple output (buck/

buck/boost) synchronous DC/DC switching regulator

controller that drives all N-channel power MOSFET stages.

Constant frequency current mode architecture allows

a phase-lockable switching frequency of up to 850kHz.

The LTC3859A operates from a wide 4.5V to 38V input

supply range. When biased from the output of the boost

converter or another auxiliary supply, the LTC3859A can

operate from an input supply as low as 2.5V after start-up.

The 55μA no-load quiescent current extends operating

runtime in battery powered systems. OPTI-LOOP com-

pensation allows the transient response to be optimized

over a wide range of output capacitance and ESR values.

The LTC3859A features a precision 0.8V reference for the

bucks, 1.2V reference for the boost and a power good

output indicator. The PLLIN/MODE pin selects among

Burst Mode operation, pulse-skipping mode, or continu-

ous inductor current mode at light loads.

Compared to the LTC3859, the LTC3859A's boost controller

has improved performance in Burst Mode operation when

the input voltage is higher than the regulated output voltage.

L, LT, LTC, LTM, Burst Mode, OPTI-LOOP and µModule are registered trademarks and

No RSENSE is a trademark of Linear Technology Corporation. All other trademarks are the

property of their respective owners. Protected by U.S. Patents including 5481178, 5705919,

5929620, 6144194, 6177787, 6580258.

FeaTures

applicaTions

n Dual Buck Plus Single Boost Synchronous Controllers

n Outputs Remain in Regulation Through Cold Crank

Down to 2.5V

n Low Operating IQ: 55μA (One Channel On)

n Wide Bias Input Voltage Range: 4.5V to 38V

n Buck Output Voltage Range: 0.8V ≤ VOUT ≤ 24V

n Boost Output Voltage Up to 60V

n RSENSE or DCR Current Sensing

n 100% Duty Cycle for Boost Synchronous MOSFET

Even in Burst Mode

Operation

n Phase-Lockable Frequency (75kHz to 850kHz)

n Programmable Fixed Frequency (50kHz to 900kHz)

n Selectable Continuous, Pulse-Skipping or Low Ripple

Burst Mode Operation at Light Loads

n Very Low Buck Dropout Operation: 99% Duty Cycle

n Adjustable Output Voltage Soft-Start or Tracking

n Low Shutdown IQ: 14μA

n Small 38-Pin 5mm × 7mm QFN and TSSOP Packages

n Automotive Always-On and Start-Stop Systems

n Battery Operated Digital Devices

n Distributed DC Power Systems

n Multioutput Buck-Boost Applications

Efﬁciency vs Input Voltage

3859 TA01a

LTC3859A

VFB3

TG3

BG3

SENSE3–

SENSE3+

INTVCC

BOOST1, 2, 3

ITH1, 2, 3

TRACK/SS1, 2

SS3

SW1

SENSE1+

SENSE1–

VFB1

RUN1, 2, 3

EXTVCC

TG2

SW2

BG2

SENSE2+

SENSE2–

VFB2

PGND SGND

VBIAS

4.9µH 6mΩ

357k 220µF

1µF

68.1k

649k 68µF68.1k

1.2µH

2mΩ

499k

4.7µF

SW1, 2, 3 0.1µF

0.1µF

VIN

2.5V TO 38V

(START-UP ABOVE 5V)

VOUT1

VOUT2

8.5V

220µF

VOUT3

REGULATED AT 10V WHEN VIN < 10V

FOLLOWS VIN WHEN VIN > 10V

6.5µH 8mΩ

TG1

SW3 BG1

INPUT VOLTAGE (V)

EFFICIENCY (%)

100

50 2010 30

3859A TA01b

4015 355 25

FIGURE 12 CIRCUIT

ILOAD = 2A

VOUT2 = 8.5V

VOUT1 = 5V

LTC3859A

3859af

absoluTe MaxiMuM raTings

Bias Input Supply Voltage (VBIAS) .............. –0.3V to 40V

Buck Top Side Driver Voltages

(BOOST1, BOOST2) ............................. –0.3V to 46V

Boost Top Side Driver Voltages

(BOOST3) ............................................ –0.3V to 76V

Buck Switch Voltage (SW1, SW2) ................–5V to 40V

Boost Switch Voltage (SW3) ........................–5V to 70V

INTVCC, (BOOST1–SW1),

(BOOST2–SW2), (BOOST3–SW3), .......... –0.3V to 6V

RUN1, RUN2, RUN3 .................................... –0.3V to 8V

Maximum Current Sourced Into Pin

from Source >8V...............................................100µA

(Notes 1, 3)

TOP VIEW

FE PACKAGE

38-LEAD PLASTIC TSSOP

ITH1

VFB1

SENSE1+

SENSE1–

FREQ

PLLIN/MODE

SS3

SENSE3+

SENSE3–

VFB3

ITH3

SGND

RUN1

RUN2

RUN3

SENSE2–

SENSE2+

VFB2

ITH2

TRACK/SS1

PGOOD1

TG1

SW1

BOOST1

BG1

SW3

TG3

BOOST3

BG3

VBIAS

EXTVCC

INTVCC

BG2

BOOST2

SW2

TG2

OV3

TRACK/SS2

PGND

TJMAX = 150°C, qJA = 25°C/W

EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB

13 14 15 16

TOP VIEW

PGND

UHF PACKAGE

38-LEAD (5mm × 7mm) PLASTIC QFN

17 18 19

38 37 36 35 34 33 32

1FREQ

PLLIN/MODE

SS3

SENSE3+

SENSE3–

VFB3

ITH3

SGND

RUN1

RUN2

RUN3

SENSE2–

SW1

BOOST1

BG1

SW3

TG3

BOOST3

BG3

VBIAS

EXTVCC

INTVCC

BG2

BOOST2

SENSE1–

SENSE1+

VFB1

ITH1

TRACK/SS1

PGOOD1

TG1

SENSE2+

VFB2

ITH2

TRACK/SS2

OV3

TG2

SW2

TJMAX = 150°C, qJA = 34.7°C/W

EXPOSED PAD (PIN 39) IS PGND, MUST BE SOLDERED TO PCB

pin conFiguraTion

SENSE1+, SENSE2+, SENSE1–

SENSE2– Voltages .....................................–0.3V to 28V

SENSE3+, SENSE3– Voltages .....................–0.3V to 40V

FREQ Voltages ......................................–0.3V to INTVCC

EXTVCC ....................................................... –0.3V to 14V

ITH1, ITH2, ITH3, VFB1, VFB2, VFB3 Voltages ....–0.3V to 6V

PLLIN/MODE, PGOOD1, OV3 Voltages .......–0.3V to 6V

TRACK/SS1, TRACK/SS2, SS3 Voltages .....–0.3V to 6V

Operating Junction Temperature Range (Note 2)

LTC3859AE, LTC3859AI .....................–40°C to 125°C

LTC3859AH ........................................ –40°C to 150°C

LTC3859AMP ..................................... –55°C to 150°C

Storage Temperature Range ..............–65°C to 150°C

LTC3859A

3859af

elecTrical characTerisTics

orDer inForMaTion

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

VBIAS Bias Input Supply Operating Voltage

Range 4.5 38 V

VFB1,2 Buck Regulated Feedback Voltage (Note 4); ITH1,2 Voltage = 1.2V

–40°C to 85°C, All Grades

LTC3859AE, LTC3859AI

LTC3859AH, LTC3859AMP

0.792

0.788

0.786

0.800

0.808

0.812

VFB3 Boost Regulated Feedback Voltage (Note 4); ITH3 Voltage = 1.2V

–40°C to 85°C, All Grades

LTC3859AE, LTC3859AI

LTC3859AH, LTC3859AMP

1.188

1.182

1.179

1.200

1.212

1.218

IFB1,2,3 Feedback Current (Note 4) –10 ±50 nA

VREFLNREG Reference Voltage Line Regulation (Note 4); VIN = 4V to 38V 0.002 0.02 %/V

VLOADREG Output Voltage Load Regulation (Note 4)

Measured in Servo Loop;

DITH Voltage = 1.2V to 0.7V

l0.01 0.1 %

Measured in Servo Loop;

DITH Voltage = 1.2V to 2V

l–0.01 –0.1 %

gm1,2,3 Transconductance Amplifier gm(Note 4); ITH1,2,3 = 1.2V;

Sink/Source 5µA 2 mmho

The l denotes the speciﬁcations which apply over the speciﬁed operating

junction temperature range, otherwise speciﬁcations are at TA = 25°C. VBIAS = 12V, VRUN1,2,3 = 5V, EXTVCC = 0V unless otherwise

noted. (Note 2)

LEAD FREE FINISH TAPE AND REEL PART MARKING* PACKAGE DESCRIPTION TEMPERATURE RANGE

LTC3859AEFE#PBF LTC3859AEFE#TRPBF LTC3859AFE 38-Lead Plastic TSSOP –40°C to 125°C

LTC3859AIFE#PBF LTC3859AIFE#TRPBF LTC3859AFE 38-Lead Plastic TSSOP –40°C to 125°C

LTC3859AHFE#PBF LTC3859AHFE#TRPBF LTC3859AFE 38-Lead Plastic TSSOP –40°C to 150°C

LTC3859AMPFE#PBF LTC3859AMPFE#TRPBF LTC3859AFE 38-Lead Plastic TSSOP –55°C to 150°C

LTC3859AEUHF#PBF LTC3859AEUHF#TRPBF 3859A 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C

LTC3859AIUHF#PBF LTC3859AIUHF#TRPBF 3859A 38-Lead (5mm × 7mm) Plastic QFN –40°C to 125°C

LTC3859AHUHF#PBF LTC3859AHUHF#TRPBF 3859A 38-Lead (5mm × 7mm) Plastic QFN –40°C to 150°C

LTC3859AMPUHF#PBF LTC3859AMPUHF#TRPBF 3859A 38-Lead (5mm × 7mm) Plastic QFN –55°C to 150°C

Consult LTC Marketing for parts speciﬁed with wider operating temperature ranges. *The temperature grade is identiﬁed by a label on the shipping container.

For more information on lead free part marking, go to: http://www.linear.com/leadfree/

For more information on tape and reel speciﬁcations, go to: http://www.linear.com/tapeandreel/

LTC3859A

3859af

elecTrical characTerisTics

The l denotes the speciﬁcations which apply over the speciﬁed operating

junction temperature range, otherwise speciﬁcations are at TA = 25°C. VBIAS = 12V, VRUN1,2,3 = 5V, EXTVCC = 0V unless otherwise

noted. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

IQInput DC Supply Current (Note 5)

Pulse-Skipping or

Forced Continuous Mode

(One Channel On)

RUN1 = 5V and RUN2,3 = 0V or

RUN2 = 5V and RUN1,3 = 0V or

RUN3 = 5V and RUN1,2 = 0V

VFB1, 2 ON = 0.83V (No Load)

VFB3 = 1.25V

1.5 mA

Pulse-Skipping or

Forced Continuous Mode

(All Channels On)

RUN1,2,3 = 5V,

VFB1,2 = 0.83V (No Load)

VFB3 = 1.25V

3 mA

Sleep Mode

(One Channel On, Buck) RUN1 = 5V and RUN2,3 = 0V or

RUN2 = 5V and RUN1,3 = 0V

VFB,ON = 0.83V (No Load)

55 80 µA

Sleep Mode

(One Channel On, Boost) RUN3 = 5V and RUN1,2 = 0V

VFB3 = 1.25V 55 80 µA

Sleep Mode

(Buck and Boost Channel On) RUN1 = 5V and RUN2 = 0V or

RUN2 = 5V and RUN1 = 0V

RUN3 = 5V

VFB1,2 = 0.83V (No Load)

VFB3 = 1.25V

65 100 µA

Sleep Mode

(All Three Channels On) RUN1,2,3 = 5V,

VFB1,2 = 0.83V (No Load)

VFB3 = 1.25V

80 120 µA

Shutdown RUN1,2,3 = 0V 14 30 µA

UVLO Undervoltage Lockout INTVCC Ramping Up l4.15 4.5 V

INTVCC Ramping Down l3.5 3.8 4.0 V

VOVL1,2 Buck Feedback Overvoltage Protection Measured at VFB1,2 Relative to

Regulated VFB1,2

7 10 13 %

ISENSE1,2+ SENSE+ Pin Current Bucks (Channels 1 and 2) ±1 µA

ISENSE3+ SENSE+ Pin Current Boost (Channel 3) 170 µA

ISENSE1,2– SENSE– Pin Current Bucks (Channels 1 and 2)

VOUT1,2 < VINTVCC – 0.5V

VOUT1,2 > VINTVCC + 0.5V

700

±2

µA

ISENSE3– SENSE– Pin Current Boost (Channel 3)

VSENSE3+, VSENSE3– = 12V ±1 µA

DFMAX,TG Maximum Duty Factor for TG Bucks (Channels 1,2) in Dropout, FREQ = 0V

Boost (Channel 3) in Overvoltage 98 99

100 %

DFMAX,BG Maximum Duty Factor for BG Bucks (Channels 1,2) in Overvoltage

Boost (Channel 3) 100

96 %

ITRACK/SS1,2 Soft-Start Charge Current VTRACK/SS1,2 = 0V 0.7 1.0 1.4 µA

ISS3 Soft-Start Charge Current VSS3 = 0V 0.7 1.0 1.4 µA

VRUN1 ON

VRUN2,3 ON RUN1 Pin Threshold

RUN2,3 Pin Threshold VRUN1 Rising

VRUN2,3 Rising

1.19

1.23 1.25

1.28 1.31

1.33 V

VRUN1,2,3 Hyst RUN Pin Hysteresis 80 mV

VSENSE1,2,3(MAX) Maximum Current Sense Threshold VFB1,2 = 0.7V, VSENSE1,2– = 3.3V

VFB1,2,3 = 1.1V, VSENSE3+ = 12V

l43 50 57 mV

VSENSE3(CM) SENSE3 Pins Common Mode Range

(BOOST Converter Input Supply Voltage) 2.5 38 V

LTC3859A

3859af

elecTrical characTerisTics

The l denotes the speciﬁcations which apply over the speciﬁed operating

junction temperature range, otherwise speciﬁcations are at TA = 25°C. VBIAS = 12V, VRUN1,2,3 = 5V, EXTVCC = 0V unless otherwise

noted. (Note 2)

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

Gate Driver

TG1,2 Pull-Up On-Resistance

Pull-Down On-Resistance 2.5

1.5 Ω

Ω

BG1,2 Pull-Up On-Resistance

Pull-Down On-Resistance 2.4

1.1 Ω

Ω

TG3 Pull-Up On-Resistance

Pull-Down On-Resistance 1.2

1.0 Ω

Ω

BG3 Pull-Up On-Resistance

Pull-Down On-Resistance 1.2

1.0 Ω

Ω

TG1,2,3 tr

TG1,2,3 tf

TG Transition Time:

Rise Time

Fall Time

(Note 6)

CLOAD = 3300pF

BG1,2,3 tr

BG1,2,3 tf

BG Transition Time:

Rise Time

Fall Time

(Note 6)

CLOAD = 3300pF

TG/BG t1D Top Gate Off to Bottom Gate On Delay

Synchronous Switch-On Delay Time CLOAD = 3300pF Each Driver Bucks (Channels 1, 2)

Boost (Channel 3) 30

70 ns

BG/TG t1D Bottom Gate Off to Top Gate On Delay

Top Switch-On Delay Time CLOAD = 3300pF Each Driver Bucks (Channels 1, 2)

Boost (Channel 3) 30

70 ns

tON(MIN)1,2 Buck Minimum On-Time (Note 7) 95 ns

tON(MIN)3 Boost Minimum On-Time (Note 7) 120 ns

INTVCC Linear Regulator

VINTVCCVBIAS Internal VCC Voltage 6V < VBIAS < 38V, VEXTVCC = 0V, IINTVCC = 0mA 5.0 5.4 5.6 V

VLDOVBIAS INTVCC Load Regulation ICC = 0mA to 50mA, VEXTVCC = 0V 0.7 2 %

VINTVCCEXT Internal VCC Voltage 6V < VEXTVCC < 13V, IINTVCC = 0mA 5.0 5.4 5.6 V

VLDOEXT INTVCC Load Regulation ICC = 0mA to 50mA, VEXTVCC = 8.5V 0.7 2 %

VEXTVCC EXTVCC Switchover Voltage EXTVCC Ramping Positive 4.5 4.7 V

VLDOHYS EXTVCC Hysteresis 200 mV

Oscillator and Phase-Locked Loop

f25k Programmable Frequency RFREQ = 25k; PLLIN/MODE = DC Voltage 115 kHz

f65k Programmable Frequency RFREQ = 65k; PLLIN/MODE = DC Voltage 375 440 505 kHz

f105k Programmable Frequency RFREQ = 105k; PLLIN/MODE = DC Voltage 835 kHz

fLOW Low Fixed Frequency VFREQ = 0V PLLIN/MODE = DC Voltage 320 350 380 kHz

fHIGH High Fixed Frequency VFREQ = INTVCC; PLLIN/MODE = DC Voltage 485 535 585 kHz

fSYNC Synchronizable Frequency PLLIN/MODE = External Clock l75 850 kHz

PGOOD1 Output

VPGL1 PGOOD1 Voltage Low IPGOOD1 = 2mA 0.2 0.4 V

IPGOOD1 PGOOD1 Leakage Current VPGOOD1 = 5V ±1 µA

VPG1 PGOOD1 Trip Level VFB1 with Respect to Set Regulated Voltage

VFB1 Ramping Negative

–13

–10

–7

Hysteresis 2.5 %

VFB1 Ramping Positive 7 10 13 %

Hysteresis 2.5 %

LTC3859A

3859af

Note 1: Stresses beyond those listed under Absolute Maximum Ratings

may cause permanent damage to the device. Exposure to any Absolute

Maximum Rating condition for extended periods may affect device

reliability and lifetime.

Note 2: The LTC3859A is tested under pulsed load conditions such that

TJ ≈ TA. The LTC3859AE is guaranteed to meet performance speciﬁcations

from 0°C to 85°C. Speciﬁcations over the –40°C to 125°C operating

junction temperature range are assured by design, characterization and

correlation with statistical process controls. The LTC3859AI is guaranteed

over the –40°C to 125°C operating junction temperature range, the

LTC3859AH is guaranteed over the –40°C to 150°C operating junction

temperature range and the LTC3859AMP is tested and guaranteed over

the –55°C to 150°C operating junction temperature range. High junction

temperatures degrade operating lifetimes; operating lifetime is derated for

junction temperatures greater than 125°C. Note that the maximum ambient

temperature consistent with these speciﬁcations is determined by speciﬁc

operating conditions in conjunction with board layout, the rated package

thermal impedance and other environmental factors. TJ is calculated from

the ambient temperature TA and power dissipation PD according to the

following formula: TJ = TA + (PD • qJA), where qJA = 34°C/W for the QFN

package and qJA = 25°C/W for the TSSOP package.

Note 3: This IC includes overtermperature protection that is intended to

protect the device during momentary overload conditions. The maximum

rated junction temperature will be exceeded when this protection is active.

Continuous operation above the speciﬁed absolute maximum operating

junction temperature may impair device reliability or permanently damage

the device.

Note 4: The LTC3859A is tested in a feedback loop that servos VITH1,2,3

to a speciﬁed voltage and measures the resultant VFB. The speciﬁcation at

85°C is not tested in production and is assured by design, characterization

and correlation to production testing at other temperatures (125°C for the

LTC3859AE/LTC3859AI, 150°C for the LTC3859AH/LTC3859AMP). For the

LTC3859AMP, the speciﬁcation at –40°C is not tested in production and is

assured by design, characterization and correlation to production testing

at –55°C.

Note 5: Dynamic supply current is higher due to the gate charge being

delivered at the switching frequency. See the Applications Information

section.

Note 6: Rise and fall times are measured using 10% and 90% levels. Delay

times are measured using 50% levels.

Note 7: The minimum on-time condition is speciﬁed for an inductor

peak-to-peak ripple current ≥ 40% of IMAX (See the Minimum On-Time

Considerations in the Applications Information section).

elecTrical characTerisTics

SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS

TPG1 Delay For Reporting a Fault 20 µs

OV3 Boost Overvoltage Indicator Output

VOV3L OV3 Voltage Low IOV3 = 2mA 0.2 0.4 V

IOV3 OV3 Leakage Current VOV3 = 5V ±1 µA

VOV OV3 Trip Level VFB With Respect to Set Regulated Voltage 6 10 13 %

Hysteresis 1.5 %

BOOST3 Charge Pump

IBST3 BOOST3 Charge Pump Available Output

Current VBOOST3 = 16V; VSW3 = 12V;

Forced Continuous Mode 65 µA

The l denotes the speciﬁcations which apply over the speciﬁed operating

junction temperature range, otherwise speciﬁcations are at TA = 25°C. VBIAS = 12V, VRUN1,2,3 = 5V, EXTVCC = 0V unless otherwise

noted. (Note 2)

LTC3859A

3859af

Typical perForMance characTerisTics

Load Step (Buck)

Burst Mode Operation

Load Step (Buck)

Forced Continuous Mode

Load Step (Buck)

Pulse-Skipping Mode

Inductor Current at Light Load

(Buck) Soft Start-Up

Buck Regulated Feedback Voltage

vs Temperature

Efﬁciency and Power Loss

vs Output Current (Buck)

Efﬁciency

vs Output Current (Buck) Efﬁciency vs Input Voltage (Buck)

OUTPUT CURRENT (A)

0.0001

EFFICIENCY (%)

POWER LOSS (mW)

100

10000

100

1000

0.1

1 100.01

3859A G01

0.10.001

FIGURE 12 CIRCUIT

VIN = 10V, VOUT = 5V

FCM EFFICIENCY

PULSE-SKIPPING

EFFICIENCY

BURST LOSS

BURST EFFICIENCY

FCM LOSS

PULSE-SKIPPING

LOSS

OUTPUT CURRENT (A)

0.0001

EFFICIENCY (%)

100

01 100.01

3859A G02

0.10.001

VIN = 10V

VIN = 20V

FIGURE 12 CIRCUIT

VOUT = 5V

INPUT VOLTAGE (V)

EFFICIENCY (%)

100

92 20 25 30 35 4010

3859A G03

155

FIGURE 12 CIRCUIT

VOUT = 5V

ILOAD = 4A

50µs/DIV

VOUT

100mV/DIV

AC-COUPLED

2A//DIV

VIN = 12V

VOUT = 5V

FIGURE 12 CIRCUIT

3859A G04 50µs/DIV

VOUT

100mV/DIV

AC-COUPLED

2A//DIV

VIN = 12V

VOUT = 5V

FIGURE 12 CIRCUIT

3859A G05 50µs/DIV

VOUT

100mV/DIV

AC-COUPLED

2A//DIV

VIN = 12V

VOUT = 5V

FIGURE 12 CIRCUIT

3859A G06

2µs/DIV

FORCED

CONTINUOUS

MODE

Burst Mode

OPERATION

1A/DIV

PULSE-

SKIPPING

MODE

VIN = 10V

VOUT = 5V

ILOAD = 1mA

FIGURE 12 CIRCUIT

3859A G07 20ms/DIV

VOUT2

2V/DIV

VOUT1

2V/DIV

3859A G08

FIGURE 12 CIRCUIT

TEMPERATURE (°C)

–75

REGULATED FEEDBACK VOLTAGE (mV)

808

806

802

798

794

804

800

796

792 0 25 50 75 150125100–50

3859A G09

–25

LTC3859A

3859af

Typical perForMance characTerisTics

Load Step (Boost)

Burst Mode Operation

Load Step (Boost)

Pulse-Skipping Mode

Load Step (Boost)

Forced Continuous Mode

Inductor Current at Light Load

(Boost) Soft Start-Up (Boost)

Boost Regulated Feedback

Voltage vs Temperature

Efﬁciency and Power Loss

vs Output Current (Boost)

Efﬁciency

vs Output Current (Boost) Efﬁciency vs Input Voltage (Boost)

OUTPUT CURRENT (A)

0.0001

EFFICIENCY (%)

POWER LOSS (mW)

100

10000

100

1000

0.1

1 100.01

3859A G10

0.10.001

FIGURE 12 CIRCUIT

VIN = 5V, VOUT = 10V, VBIAS = VIN

FCM EFFICIENCY

PULSE-SKIPPING

EFFICIENCY

BURST LOSS

BURST

EFFICIENCY

FCM LOSS

PULSE-SKIPPING

LOSS

OUTPUT CURRENT (A)

0.0001

EFFICIENCY (%)

100

01 100.01

3859A G11

0.10.001

VIN = 5V

FIGURE 12 CIRCUIT

VBIAS = VIN

VOUT = 10V

VIN = 8V

INPUT VOLTAGE (V)

EFFICIENCY (%)

100

90 6 7 8 9 1043

3859A G12

FIGURE 12 CIRCUIT

VBIAS = VIN

VOUT = 10V

ILOAD = 2A

200µs/DIV

VOUT

100mV/

DIV

AC-

COUPLED

5A/DIV

3859A G13

VOUT = 10V

VIN = 5V

FIGURE 12 CIRCUIT

200µs/DIV

VOUT

100mV/DIV

AC-COUPLED

5A/DIV

3859A G14

VOUT = 10V

VIN = 5V

FIGURE 12 CIRCUIT

200µs/DIV

VOUT

100mV/DIV

AC-COUPLED

5A/DIV

3859A G15

VOUT = 10V

VIN = 5V

FIGURE 12 CIRCUIT

2µs/DIV

FORCED

CONTINUOUS

MODE

Burst Mode

OPERATION

5A/DIV

PULSE-

SKIPPING

MODE

3859A G16

VOUT = 10V

VIN = 7V

ILOAD = 1mA

FIGURE 12 CIRCUIT

20ms/DIV

VOUT3

2V/DIV

GND

3859A G17

VIN = 5V

FIGURE 12 CIRCUIT

TEMPERATURE (°C)

–75

REGULATED FEEDBACK VOLTAGE (V)

1.212

1.209

1.203

1.191

1.194

1.197

1.206

1.200

1.188 0 25 50 75 150120100–50

3859A G18

–25

LTC3859A

3859af

Typical perForMance characTerisTics

SENSE Pins Total Input Current

vs VSENSE Voltage

Buck SENSE– Pin Input Bias

Current vs Temperature

Boost SENSE Pin Total Input

Current vs Temperature

Maximum Current Sense

Threshold vs Duty Cycle

Maximum Current Sense

Threshold vs ITH Voltage

TRACK/SS Pull-Up Current

vs Temperature

INTVCC Line Regulation

INTVCC and EXTVCC

vs Load Current

EXTVCC Switchover and INTVCC

Voltages vs Temperature

INPUT VOLTAGE (V)

INTVCC VOLTAGE (V)

5.5

5.4

5.2

5.3

5.1

5.0 15 20 25 30 35 405

3859A G19

LOAD CURRENT (mA)

INTVCC VOLTAGE (V)

5.6

5.2

5.4

4.6

4.8

5.0

4.4

4.2

4.0 60 80 10020

3859A G20

EXTVCC = 0V

EXTVCC = 5V

EXTVCC = 8.5V

VBIAS = 12V

TEMPERATURE (°C)

–75

EXTVCC AND INTVCC VOLTAGE (V)

6.0

5.8

5.4

5.2

4.4

4.2

4.6

4.8

5.6

5.0

4.0 0 25 50 75 150125100–50

3859A G21

–25

INTVCC

EXTVCC RISING

EXTVCC FALLING

VSENSE COMMON MODE VOLTAGE (V)

SENSE CURRENT (µA)

800

700

400

500

300

100

200

600

015 20 25 30 35 405

3859A G22

SENSE1, 2 PINS

SENSE3 PIN

TEMPERATURE (°C)

–75

SENSE CURRENT (µA)

900

700

800

400

500

300

100

200

600

00 25 50 75 100 125 150–50

3859A G23

–25

VOUT < INTVCC – 0.5V

VOUT > INTVCC + 0.5V

TEMPERATURE (°C)

–75

SENSE CURRENT (µA)

200

160

180

100

120

140

00 25 50 75 100 125 150–50

3859A G24

–25

SENSE3+ PIN

SENSE3– PIN

VIN = 12V

DUTY CYCLE (%)

MAXIMUM CURRENT SENSE VOLTAGE (mV)

050 60 70 80 90 10010

3859A G25

20 30 40

BOOST

BUCK

ITH (V)

MAXIMUM CURRENT SENSE VOLTAGE (mV)

–10

–20

–30 1 1.2 1.40.2

3859A G26

0.4 0.6 0.8

Burst Mode OPERATION

PULSE-SKIPPING

FORCED CONTINUOUS

TEMPERATURE (°C)

–75

TRACK/SS CURRENT (µA)

1.20

1.15

1.05

1.00

0.85

0.90

1.10

0.95

0.80 0 25 50 75 125100 150–50

3859A G27

–25

LTC3859A

3859af

Typical perForMance characTerisTics

Buck Foldback Current Limit

Oscillator Frequency

vs Temperature

Undervoltage Lockout Threshold

vs Temperature

Shutdown (RUN) Threshold

vs Temperature

Charge Pump Charging Current

vs Operating Frequency

Charge Pump Charging Current

vs Switch Voltage

Shutdown Current vs Temperature

Shutdown Current

vs Input Voltage Quiescent Current vs Temperature

TEMPERATURE (°C)

–75

SHUTDOWN CURRENT (µA)

80 25 50 75 100 125 150–50

3859A G28

–25

VBIAS = 12V

VBIAS INPUT VOLTAGE (V)

SHUTDOWN CURRENT (µA)

020 25 30 35 4010

3859A G29

TEMPERATURE (°C)

–75

QUIESCENT CURRENT (µA)

100

40 0 25 50 75 100 125 150–50

3859A G30

–25

ONE CHANNEL ON

ALL CHANNELS ON

VBIAS = 12V

FEEDBACK VOLTAGE (mV)

MAXIMUM CURRENT SENSE VOLTAGE (mV)

0300 400 500 600 700 800100

3859A G31

200

TEMPERATURE (°C)

–75

FREQUENCY (kHz)

600

550

500

350

400

450

300 0 25 50 75 100 125 150–50

3859A G32

–25

FREQ = INTVCC

FREQ = GND

TEMPERATURE (°C)

–75

INTVCC VOLTAGE (V)

4.4

4.3

4.2

3.6

3.8

4.0

3.4

3.5

3.7

3.9

4.1

0 25 50 75 100 125 150–50

3859A G33

–25

RISING

FALLING

TEMPERATURE (°C)

–75

RUN PIN VOLTAGE (V)

1.40

1.35

1.30

1.20

1.00

1.15

1.10

1.05

1.25

0 25 50 75 100 125 150–50

3859A G34

–25

RUN1 RISING

RUN1 FALLING

RUN2,3 FALLING

RUN2,3 RISING

OPERATING FREQUENCY (kHz)

100

CHARGE PUMP CHARGING CURRENT (µA)

100

400 500 600 700 800200

3859A G35

300

–55°C

25°C

150°C

VBOOST3 = 16V

VSW3 = 12V

SWITCH VOLTAGE (V)

CHARGE PUMP CHARGING CURRENT (µA)

100

20 25 30 35 4010

3859A G36

FREQ = 0V

FREQ = INTVCC

VBOOST3 – VSW3 = 4V

LTC3859A

3859af

pin FuncTions

FREQ (Pin 1/Pin 5): The Frequency Control Pin for the

Internal VCO. Connecting the pin to GND forces the VCO

to a ﬁxed low frequency of 350kHz. Connecting the pin

to INTVCC forces the VCO to a ﬁxed high frequency of

535kHz. Other frequencies between 50kHz and 900kHz

can be programmed using a resistor between FREQ and

GND. The resistor and an internal 20µA source current

create a voltage used by the internal oscillator to set the

frequency.

PLLIN/MODE (Pin 2/Pin 6): External Synchronization

Input to Phase Detector and Forced Continuous Mode

Input. When an external clock is applied to this pin, the

phase-locked loop will force the rising TG1 signal to be

synchronized with the rising edge of the external clock,

and the regulators operate in forced continuous mode.

When not synchronizing to an external clock, this input,

which acts on all three controllers, determines how the

LTC3859AA operates at light loads. Pulling this pin to

ground selects Burst Mode operation. An internal 100k

resistor to ground also invokes Burst Mode operation

when the pin is ﬂoated. Tying this pin to INTVCC forces

continuous inductor current operation. Tying this pin to

a voltage greater than 1.2V and less than INTVCC – 1.3V

selects pulse-skipping operation. This can be done by

connecting a 100k resistor from this pin to INTVCC.

SGND (Pin 8/Pin 12): Small Signal Ground common to

all three controllers, must be routed separately from high

current grounds to the common (–) terminals of the CIN

capacitors.

RUN1, RUN2, RUN3 (Pins 9, 10, 11/Pins 13, 14, 15):

Digital Run Control Inputs for Each Controller. Forcing

RUN1 below 1.17V and RUN2/RUN3 below 1.20V shuts

down that controller. Forcing all of these pins below 0.7V

shuts down the entire LTC3859A, reducing quiescent cur-

rent to approximately 14µA.

OV3 (Pin 17/Pin 21): Overvoltage Open-Drain Logic

Output for the Boost Regulator. OV3 is pulled to ground

when the voltage on the VFB3 pin is under 110% of its set

point, and becomes high impedance when VFB3 goes over

110% of its set point.

INTVCC (Pin 22/Pin 26): Output of the Internal Linear Low

Dropout Regulator. The driver and control circuits are pow-

ered from this voltage source. Must be decoupled to PGND

with a minimum of 4.7µF ceramic or tantalum capacitor.

EXTVCC (Pin 23/Pin 27): External Power Input to an

Internal LDO Connected to INTVCC. This LDO supplies

INTVCC power, bypassing the internal LDO powered from

VBIAS whenever EXTVCC is higher than 4.7V. See EXTVCC

Connection in the Applications Information section. Do

not ﬂoat or exceed 14V on this pin.

VBIAS (Pin 24/Pin 28): Main Bias Input Supply Pin. A

bypass capacitor should be tied between this pin and the

SGND pin.

BG1, BG2, BG3 (Pins 29, 21, 25/Pins 33, 25, 29): High

Current Gate Drives for Bottom (Synchronous) N-Channel

MOSFETs. Voltage swing at these pins is from ground to

INTVCC.

BOOST1, BOOST2, BOOST3 (Pins 30, 20, 26/Pins 34,

24, 30): Bootstrapped Supplies to the Top Side Floating

Drivers. Capacitors are connected between the BOOST and

SW pins and Schottky diodes are tied between the BOOST

and INTVCC pins. Voltage swing at the BOOST pins is from

INTVCC to (VIN + INTVCC).

SW1, SW2, SW3 (Pins 31, 19, 28/Pins 35, 23, 32):

Switch Node Connections to Inductors.

TG1, TG2, TG3 (Pins 32, 18, 27/Pins 36, 22, 31): High

Current Gate Drives for Top N-Channel MOSFETs. These

are the outputs of ﬂoating drivers with a voltage swing

equal to INTVCC superimposed on the switch node volt-

age SW.

PGOOD1 (Pin 33/Pin 37): Open-Drain Logic Output.

PGOOD1 is pulled to ground when the voltage on the VFB1

pin is not within ±10% of its set point.

(QFN/TSSOP)

LTC3859A

3859af

pin FuncTions

TRACK/SS1, TRACK/SS2, SS3 (Pins 34, 16, 3/Pins 38,

20, 7): External Tracking and Soft-Start Input. For the buck

channels, the LTC3859A regulates the VFB1,2 voltage to the

smaller of 0.8V, or the voltage on the TRACK/SS1,2 pin.

For the boost channel, the LTC3859A regulates the VFB3

voltage to the smaller of 1.2V, or the voltage on the SS3

pin. An internal 1µA pull-up current source is connected

to this pin. A capacitor to ground at this pin sets the ramp

time to ﬁnal regulated output voltage. Alternatively, a re-

sistor divider on another voltage supply connected to the

TRACK/SS pins of the buck channels allow the LTC3859A

buck outputs to track the other supply during start-up.

ITH1, ITH2, ITH3 (Pins 35, 15, 7/Pins 1, 19, 11): Error

Ampliﬁer Outputs and Switching Regulator Compensation

Points. Each associated channel’s current comparator trip

point increases with this control voltage.

VFB1, VFB2, VFB3 (Pins 36, 14, 6/Pins 2, 18, 10): Receives

the remotely sensed feedback voltage for each controller

from an external resistive divider across the output.

SENSE1+, SENSE2+, SENSE3+ (Pins 37, 13, 4/Pins 3, 17, 8):

The (+) Input to the Differential Current Comparators.

The ITH pin voltage and controlled offsets between the

SENSE– and SENSE+ pins in conjunction with RSENSE set the

current trip threshold. For the boost channel, the SENSE3+

pin supplies current to the current comparator.

SENSE1–, SENSE2–, SENSE3– (Pins 38, 12, 5/Pins 4,

16, 9): The (–) Input to the Differential Current Compara-

tors. When SENSE1,2– for the buck channels is greater

than INTVCC, then SENSE1,2– pin supplies current to the

current comparator.

PGND (Exposed Pad Pin 39): Driver Power Ground. Con-

nects to the sources of bottom N-channel MOSFETs and the

(–) terminal(s) of CIN. The exposed pad must be soldered

to the PCB for rated electrical and thermal performance.

(QFN/TSSOP)

LTC3859A

3859af

FuncTional DiagraM

3859A BD

SWITCHING

LOGIC

INTVCC VIN1,2

BOOST

PGND

SENSE+

SENSE–

CIN

COUT

INTVCC

LRSENSE

TOP

BOT

DROPOUT

DET

S Q

BOT

TOPON

SHDN

–

SLEEP

–

ICMP IR

2.8V

0.65V

SLOPE COMP VFB

ITH

3mV

0.80V

TRACK/SS

0.88V

–

TRACK/SS

CC2 RC

RUN

CSS

FOLDBACK

SHDN

RST

2(VFB)

SHDN

6µA CH1

0.5µA CH2

11V

PFD

VCO

CLP

CLK2

CLK1

SYNC

DET

20µA

100k

LDO

–

4.7V

5.4V 5.4V

INTVCC

SGND

EXTVCC

VBIAS

FREQ

PGOOD1

–

0.88V

0.72V

VFB1

BUCK CHANNELS 1 AND 2

1µA

VOUT1,2

6.8V

LTC3859A

3859af

FuncTional DiagraM

3859A BD

SWITCHING

LOGIC

INTVCC VOUT3

BOOST3

TG3

SW3

BG3

PGND

SENSE3+

SENSE3–

COUT

CIN

INTVCC

LRSENSE

TOP

BOT

S Q

BOTON

SHDN

–

SLEEP

–

ICMP IR

2.8V

0.7V

SLOPE COMP

VFB3

ITH3

2mV

1.2V

SS3

1.32V

–

SS3

CC2 RC

RUN3

CSS

SHDN SNSLO

0.5µA

11V

–

SNSLO

CLK1

PLLIN/MODE

–

VFB3

1.32V

OV3 0.425V

BOOST CHANNEL 3

1µA

VIN3

LTC3859A

3859af

operaTion

Main Control Loop

The LTC3859A uses a constant frequency, current mode

step-down architecture. The two buck controllers, chan-

nels 1 and 2, operate 180 degrees out of phase with each

other. The boost controller, channel 3, operates in phase

with channel 1. During normal operation, the external

top MOSFET for the buck channels (the external bottom

MOSFET for the boost channel) is turned on when the

clock for that channel sets the RS latch, and is turned off

when the main current comparator, ICMP, resets the RS

latch. The peak inductor current at which ICMP trips and

resets the latch is controlled by the voltage on the ITH pin,

which is the output of the error ampliﬁer EA. The error

ampliﬁer compares the output voltage feedback signal at

the VFB pin, (which is generated with an external resistor

divider connected across the output voltage, VOUT, to

ground) to the internal 0.800V reference voltage for the

bucks (1.2V reference voltage for the boost). When the

load current increases, it causes a slight decrease in VFB

relative to the reference, which causes the EA to increase

the ITH voltage until the average inductor current matches

the new load current.

After the top MOSFET for the bucks (the bottom MOSFET

for the boost) is turned off each cycle, the bottom MOSFET

is turned on (the top MOSFET for the boost) until either

the inductor current starts to reverse, as indicated by the

current comparator IR, or the beginning of the next clock

cycle.

INTVCC/EXTVCC Power

Power for the top and bottom MOSFET drivers and most

other internal circuitry is derived from the INTVCC pin.

When the EXTVCC pin is left open or tied to a voltage less

than 4.7V, the VBIAS LDO (low dropout linear regulator)

supplies 5.4V from VBIAS to INTVCC. If EXTVCC is taken

above 4.7V, the VBIAS LDO is turned off and an EXTVCC

LDO is turned on. Once enabled, the EXTVCC LDO supplies

5.4V from EXTVCC to INTVCC. Using the EXTVCC pin allows

the INTVCC power to be derived from a high efﬁciency

external source such as one of the LTC3859A switching

regulator outputs.

Each top MOSFET driver is biased from the ﬂoating

bootstrap capacitor CB, which normally recharges during

each cycle through an external diode when the switch

voltage goes low.

For buck channels 1 and 2, if the buck’s input voltage

decreases to a voltage close to its output, the loop may

enter dropout and attempt to turn on the top MOSFET

continuously. The dropout detector detects this and forces

the top MOSFET off for about one twelfth of the clock

period every tenth cycle to allow CB to recharge.

Shutdown and Start-Up (RUN1, RUN2, RUN3 and

TRACK/SS1, TRACK/SS2, SS3 Pins)

The three channels of the LTC3859A can be independently

shut down using the RUN1, RUN2 and RUN3 pins. Pulling

RUN1 below 1.17V and RUN2/RUN3 below 1.20V shuts

down the main control loop for that channel. Pulling all

three pins below 0.7V disables all controllers and most

internal circuits, including the INTVCC LDOs. In this state,

the LTC3859A draws only 14µA of quiescent current.

Releasing a RUN pin allows a small internal current to pull

up the pin to enable that controller. The RUN1 pin has a

6µA pull-up current while the RUN2 and RUN3 pins have

a smaller 0.5µA. The 6µA current on RUN1 is designed

to be large enough so that the RUN1 pin can be safely

ﬂoated (to always enable the controller) without worry

of condensation or other small board leakage pulling the

pin down. This is ideal for always-on applications where

one or more controllers are enabled continuously and

never shut down.

Each RUN pin may also be externally pulled up or driven

directly by logic. When driving a RUN pin with a low

impedance source, do not exceed the absolute maximum

rating of 8V. Each RUN pin has an internal 11V voltage

clamp that allows the RUN pin to be connected through

a resistor to a higher voltage (for example, VBIAS), so

long as the maximum current in the RUN pin does not

exceed 100µA.

The start-up of each channel’s output voltage VOUT is

controlled by the voltage on the TRACK/SS pin (TRACK/SS1

for channel 1, TRACK/SS2 for channel 2, SS3 for channel 3).

When the voltage on the TRACK/SS pin is less than the

(Refer to Functional Diagram)

LTC3859A

3859af

operaTion

0.8V internal reference for the bucks and the 1.2V internal

reference for the boost, the LTC3859A regulates the VFB

voltage to the TRACK/SS pin voltage instead of the cor-

responding reference voltage. This allows the TRACK/SS

pin to be used to program a soft-start by connecting an

external capacitor from the TRACK/SS pin to SGND. An

internal 1µA pull-up current charges this capacitor creating

a voltage ramp on the TRACK/SS pin. As the TRACK/SS

voltage rises linearly from 0V to 0.8V/1.2V (and beyond

up to INTVCC), the output voltage VOUT rises smoothly

from zero to its ﬁnal value.

Alternatively the TRACK/SS pins for buck channels 1 and 2

can be used to cause the start-up of VOUT to track that of

another supply. Typically, this requires connecting to the

TRACK/SS pin an external resistor divider from the other sup-

ply to ground (see the Applications Information section).

Light Load Current Operation (Burst Mode Operation,

Pulse-Skipping, or Continuous Conduction)

(PLLIN/MODE Pin)

The LTC3859A can be enabled to enter high efﬁciency

Burst Mode operation, constant frequency pulse-skipping

mode or forced continuous conduction mode at low load

currents. To select Burst Mode operation, tie the PLLIN/

MODE pin to ground. To select forced continuous opera-

tion, tie the PLLIN/MODE pin to INTVCC. To select pulse-

skipping mode, tie the PLLIN/MODE pin to a DC voltage

greater than 1.2V and less than INTVCC – 1.3V.

When a controller is enabled for Burst Mode operation, the

minimum peak current in the inductor is set to approxi-

mately 25% of the maximum sense voltage (30% for the

boost) even though the voltage on the ITH pin indicates a

lower value. If the average inductor current is higher than

the load current, the error ampliﬁer EA will decrease the

voltage on the ITH pin. When the ITH voltage drops below

0.425V, the internal sleep signal goes high (enabling sleep

mode) and both external MOSFETs are turned off. The ITH

pin is then disconnected from the output of the EA and

parked at 0.450V.

In sleep mode, much of the internal circuitry is turned off,

reducing the quiescent current that the LTC3859A draws.

If one channel is in sleep mode and the other two are

shut down, the LTC3859A draws only 55µA of quiescent

current. If two channels are in sleep mode and the other

shut down, it draws only 65µA of quiescent current. If all

three controllers are enabled in sleep mode, the LTC3859A

draws only 80µA of quiescent. In sleep mode, the load

current is supplied by the output capacitor. As the output

voltage decreases, the EA’s output begins to rise. When the

output voltage drops enough, the ITH pin is reconnected

to the output of the EA, the sleep signal goes low, and the

controller resumes normal operation by turning on the top

external MOSFET on the next cycle of the internal oscillator.

When a controller is enabled for Burst Mode operation,

the inductor current is not allowed to reverse. The reverse

current comparator (IR) turns off the bottom external

MOSFET (the top external MOSFET for the boost) just

before the inductor current reaches zero, preventing it

from reversing and going negative. Thus, the controller

operates in discontinuous operation.

In forced continuous operation or clocked by an external

clock source to use the phase-locked loop (see the Fre-

quency Selection and Phase-Locked Loop section), the

inductor current is allowed to reverse at light loads or

under large transient conditions. The peak inductor cur-

rent is determined by the voltage on the ITH pin, just as

in normal operation. In this mode, the efﬁciency at light

loads is lower than in Burst Mode operation. However,

continuous operation has the advantage of lower output

voltage ripple and less interference to audio circuitry. In

forced continuous mode, the output ripple is independent

of load current.

When the PLLIN/MODE pin is connected for pulse-skipping

mode, the LTC3859A operates in PWM pulse-skipping

mode at light loads. In this mode, constant frequency

operation is maintained down to approximately 1% of

designed maximum output current. At very light loads, the

current comparator ICMP may remain tripped for several

cycles and force the external top MOSFET to stay off for

the same number of cycles (i.e., skipping pulses). The

inductor current is not allowed to reverse (discontinuous

operation). This mode, like forced continuous operation,

exhibits low output ripple as well as low audio noise and

reduced RF interference as compared to Burst Mode

operation. It provides higher low current efﬁciency than

forced continuous mode, but not nearly as high as Burst

Mode operation.

LTC3859A

3859af

operaTion

Frequency Selection and Phase-Locked Loop

(FREQ and PLLIN/MODE Pins)

The selection of switching frequency is a tradeoff between

efﬁciency and component size. Low frequency opera-

tion increases efﬁciency by reducing MOSFET switching

losses, but requires larger inductance and/or capacitance

to maintain low output ripple voltage.

The switching frequency of the LTC3859A’s controllers

can be selected using the FREQ pin.

If the PLLIN/MODE pin is not being driven by an external

clock source, the FREQ pin can be tied to SGND, tied to

INTVCC, or programmed through an external resistor. Tying

FREQ to SGND selects 350kHz while tying FREQ to INTVCC

selects 535kHz. Placing a resistor between FREQ and

SGND allows the frequency to be programmed between

50kHz and 900kHz.

A phase-locked loop (PLL) is available on the LTC3859A

to synchronize the internal oscillator to an external clock

source that is connected to the PLLIN/MODE pin. The

LTC3859A’s phase detector adjusts the voltage (through

an internal lowpass ﬁlter) of the VCO input to align the

turn-on of controller 1’s external top MOSFET to the ris-

ing edge of the synchronizing signal. Thus, the turn-on

of controller 2’s external top MOSFET is 180 degrees out

of phase to the rising edge of the external clock source.

The VCO input voltage is pre-biased to the operating

frequency set by the FREQ pin before the external clock

is applied. If prebiased near the external clock frequency,

the PLL loop only needs to make slight changes to the

VCO input in order to synchronize the rising edge of the

external clock’s to the rising edge of TG1. The ability to

pre-bias the loop ﬁlter allows the PLL to lock in rapidly

without deviating far from the desired frequency.

The typical capture range of the LTC3859A’s phase-locked

loop is from approximately 55kHz to 1MHz, with a guar-

antee over all manufacturing variations to be between

75kHz and 850kHz. In other words, the LTC3859A’s PLL

is guaranteed to lock to an external clock source whose

frequency is between 75kHz and 850kHz.

The typical input clock thresholds on the PLLIN/MODE

pin are 1.6V (rising) and 1.2V (falling).

Boost Controller Operation When VIN > VOUT

When the input voltage to the boost channel rises above

its regulated VOUT voltage, the controller can behave

differently depending on the mode, inductor current and

VIN voltage. In forced continuous mode, the loop works

to keep the top MOSFET on continuously once VIN rises

above VOUT. An internal charge pump delivers current to

the boost capacitor from the BOOST3 pin to maintain a

sufﬁciently high TG voltage. (The amount of current the

charge pump can deliver is characterized by two curves

in the Typical Performance Characteristics section.)

In pulse-skipping mode, if VIN is between 100% and

110% of the regulated VOUT voltage, TG3 turns on if the

inductor current rises above approximately 3% of the

programmed ILIM current. If the part is programmed in

Burst Mode operation under this same VIN window, then

TG3 turns on at the same threshold current as long as

the chip is awake (one of the buck channels is awake and

switching). If both buck channels are asleep or shut down

in this VIN window, then TG3 will remain off regardless of

the inductor current.

If VIN rises above 110% of the regulated VOUT voltage in

any mode, the controller turns on TG3 regardless of the

inductor current. In Burst Mode operation, however, the

internal charge pump turns off if the entire chip is asleep

(the two buck channels are asleep or shut down). With

the charge pump off, there would be nothing to prevent

the boost capacitor from discharging, resulting in an

insufﬁcient TG voltage needed to keep the top MOSFET

completely on. The charge pump turns back on when the

chip wakes up, and it remains on as long as one of the

buck channels is actively switching.

Boost Controller at Low SENSE Pin Common Voltage

The current comparator of the boost controller is powered

directly from the SENSE3+ pin and can operate to voltages

as low as 2.5V. Since this is lower than the VBIAS UVLO of

the chip, VBIAS can be connected to the output of the boost

controller, as illustrated in the typical application circuit

in Figure 12. This allows the boost controller to handle

input voltage transients down to 2.5V while maintaining

output voltage regulation. If the SENSE3+ rises back

above 2.5V, the SS3 pin will be released initiating a new

soft-start sequence.

LTC3859A

3859af

Buck Controller Output Overvoltage Protection

The two buck channels have an overvoltage comparator

that guards against transient overshoots as well as other

more serious conditions that may overvoltage their outputs.

When the VFB1,2 pin rises by more than 10% above its

regulation point of 0.800V, the top MOSFET is turned off

and the bottom MOSFET is turned on until the overvoltage

condition is cleared.

Channel 1 Power Good (PGOOD1)

Channel 1 has a PGOOD1 pin that is connected to an open

drain of an internal N-channel MOSFET. The MOSFET

turns on and pulls the PGOOD1 pin low when the VFB1 pin

voltage is not within ±10% of the 0.8V reference voltage

for the buck channel. The PGOOD1 pin is also pulled low

when the RUN1 pin is low (shut down). When the VFB1

pin voltage is within the ±10% requirement, the MOSFET

is turned off and the pin is allowed to be pulled up by an

external resistor to a source no greater than 6V.

Boost Overvoltage Indicator (OV3)

The OV3 pin is an overvoltage indicator that signals

whether the output voltage of the channel 3 boost control-

ler goes over its programmed regulated voltage. The pin

is connected to an open drain of an internal N-channel

MOSFET. The MOSFET turns on and pulls the OV3 pin low

when the VFB3 pin voltage is less than 110% of the 1.2V

reference voltage for the boost channel. The OV3 pin is

also pulled low when the RUN3 pin is low (shut down).

When the VFB3 pin voltage goes higher than 110% of the

1.2V reference, the MOSFET is turned off and the pin is

allowed to be pulled up by an external resistor to a source

no greater than 6V.

Buck Foldback Current

When the buck output voltage falls to less than 70% of

its nominal level, foldback current limiting is activated,

progressively lowering the peak current limit in proportion

to the severity of the overcurrent or short-circuit condition.

Foldback current limiting is disabled during the soft-start

interval (as long as the VFB voltage is keeping up with

the TRACK/SS1,2 voltage). There is no foldback current

limiting for the boost channel.

THEORY AND BENEFITS OF 2-PHASE OPERATION

Why the need for 2-phase operation? Up until the 2-phase

family, constant-frequency dual switching regulators

operated both channels in phase (i.e., single-phase

operation). This means that both switches turned on at

the same time, causing current pulses of up to twice the

amplitude of those for one regulator to be drawn from the

input capacitor and battery. These large amplitude current

pulses increased the total RMS current ﬂowing from the

input capacitor, requiring the use of more expensive input

capacitors and increasing both EMI and losses in the input

capacitor and battery.

With 2-phase operation, the two buck controllers of the

LTC3859A are operated 180 degrees out of phase. This

effectively interleaves the current pulses drawn by the

switches, greatly reducing the overlap time where they add

together. The result is a signiﬁcant reduction in total RMS

input current, which in turn allows less expensive input

capacitors to be used, reduces shielding requirements for

EMI and improves real world operating efﬁciency.

operaTion

LTC3859A

3859af

operaTion

Figure 1 compares the input waveforms for a representative

single-phase dual switching regulator to the 2-phase dual

buck controllers of the LTC3859A. An actual measure-

ment of the RMS input current under these conditions

shows that 2-phase operation dropped the input current

from 2.53ARMS to 1.55ARMS. While this is an impressive

reduction in itself, remember that the power losses are

proportional to IRMS2, meaning that the actual power wasted

is reduced by a factor of 2.66. The reduced input ripple

voltage also means less power is lost in the input power

path, which could include batteries, switches, trace/con-

nector resistances and protection circuitry. Improvements

in both conducted and radiated EMI also directly accrue

as a result of the reduced RMS input current and voltage.

Of course, the improvement afforded by 2-phase opera-

tion is a function of the dual switching regulator’s relative

duty cycles which, in turn, are dependent upon the input

voltage VIN (Duty Cycle = VOUT/VIN). Figure 2 shows how

the RMS input current varies for single-phase and 2-phase

operation for 3.3V and 5V regulators over a wide input

voltage range.

Figure 1. Input Waveforms Comparing Single-Phase (a) and 2-Phase (b) Operation for Dual Switching

Regulators Converting 12V to 5V and 3.3V at 3A Each. The Reduced Input Ripple with the 2-Phase Regulator

Allows Less Expensive Input Capacitors, Reduces Shielding Requirements for EMI and Improves Efﬁciency

Figure 2. RMS Input Current Comparison

(a) (b)

It can readily be seen that the advantages of 2-phase op-

eration are not just limited to a narrow operating range,

for most applications is that 2-phase operation will reduce

the input capacitor requirement to that for just one channel

operating at maximum current and 50% duty cycle.

The schematic on the ﬁrst page is a basic LTC3859A ap-

plication circuit. External component selection is driven

by the load requirement, and begins with the selection of

RSENSE and the inductor value. Next, the power MOSFETs

are selected. Finally, CIN and COUT are selected.

INPUT VOLTAGE (V)

INPUT RMS CURRENT (A)

3.0

2.5

2.0

1.5

1.0

0.5

010 20 30 40

3859A F02

SINGLE PHASE

DUAL CONTROLLER

2-PHASE

DUAL CONTROLLER

VO1 = 5V/3A

VO2 = 3.3V/3A

IIN(MEAS) = 2.53ARMS IIN(MEAS) = 1.55ARMS 3859A F01b3859A F01a

5V SWITCH

20V/DIV

3.3V SWITCH

20V/DIV

INPUT CURRENT

5A/DIV

INPUT VOLTAGE

500mV/DIV

LTC3859A

3859af

Figure 3. Sense Lines Placement with Inductor or Sense Resistor

applicaTions inForMaTion

The Typical Application on the ﬁrst page is a basic LTC3859A

application circuit. LTC3859A can be conﬁgured to use

either DCR (inductor resistance) sensing or low value

resistor sensing. The choice between the two current

sensing schemes is largely a design trade-off between

cost, power consumption, and accuracy. DCR sensing

is becoming popular because it saves expensive current

sensing resistors and is more power efﬁcient, especially

in high current applications. However, current sensing

resistors provide the most accurate current limits for the

controller. Other external component selection is driven

by the load requirement, and begins with the selection of

RSENSE (if RSENSE is used) and inductor value. Next, the

power MOSFETs and Schottky diodes are selected. Finally,

input and output capacitors are selected.

SENSE+ and SENSE– Pins

The SENSE+ and SENSE– pins are the inputs to the current

comparators.

Buck Controllers

(SENSE1+/SENSE1–,SENSE2+/SENSE2–):

The common mode voltage range on these pins is 0V

to 28V (absolute maximum), enabling the LTC3859A to

regulate buck output voltages up to a nominal 24V (al-

lowing margin for tolerances and transients). The SENSE+

pin is high impedance over the full common mode range,

drawing at most ±1µA. This high impedance allows the

current comparators to be used in inductor DCR sensing.

The impedance of the SENSE– pin changes depending on

the common mode voltage. When SENSE– is less than

INTVCC–0.5V, a small current of less than 1µA ﬂows out

of the pin. When SENSE– is above INTVCC+0.5V, a higher

current (≈700µA) ﬂows into the pin. Between INTVCC–0.5V

and INTVCC+0.5V, the current transitions from the smaller

current to the higher current.

Boost Controller

(SENSE3+/SENSE3–): The common

mode input range for these pins is 2.5V to 38V, allowing

the boost converter to operate from inputs over this full

range. The SENSE3+ pin also provides power to the cur-

rent comparator and draws about 170µA during normal

operation (when not shut down or asleep in Burst Mode

operation). There is a small bias current of less than 1µA

that ﬂows out of the SENSE3– pin. This high impedance

on the SENSE3– pin allows the current comparator to be

used in inductor DCR sensing.

Filter components mutual to the sense lines should be

placed close to the LTC3859A, and the sense lines should

run close together to a Kelvin connection underneath the

current sense element (shown in Figure 3). Sensing cur-

rent elsewhere can effectively add parasitic inductance

and capacitance to the current sense element, degrading

the information at the sense terminals and making the

programmed current limit unpredictable. If DCR sensing

is used (Figure 4b), sense resistor R1 should be placed

close to the switching node, to prevent noise from coupling

into sensitive small-signal nodes.

Low Value Resistor Current Sensing

A typical sensing circuit using a discrete resistor is shown

in Figure 4a. RSENSE is chosen based on the required

output current.

The current comparators have a maximum threshold

VSENSE(MAX) of 50mV. The current comparator threshold

sets the peak of the inductor current, yielding a maximum

average output current, IMAX, equal to the peak value less

half the peak-to-peak ripple current, DIL. To calculate the

sense resistor value, use the equation:

RSENSE =VSENSE(MAX)

IMAX +DIL

When using the buck controllers in very low dropout

conditions, the maximum output current level will be

reduced due to the internal compensation required to

meet stability criterion for buck regulators operating at

greater than 50% duty factor. A curve is provided in the

Typical Performance Characteristics section to estimate

this reduction in peak output current level depending upon

the operating duty factor.

3859A F03

TO SENSE FILTER

NEXT TO THE CONTROLLER

INDUCTOR OR RSENSE

CURRENT FLOW

LTC3859A

3859af

applicaTions inForMaTion

Inductor DCR Sensing

For applications requiring the highest possible efﬁciency at

high load currents, the LTC3859A is capable of sensing the

voltage drop across the inductor DCR, as shown in Figure 4b.

The DCR of the inductor represents the small amount of

DC winding resistance of the copper, which can be less

than 1mΩ for today’s low value, high current inductors.

In a high current application requiring such an inductor,

conduction loss through a sense resistor would cost several

points of efﬁciency compared to DCR sensing.

If the external R1||R2 • C1 time constant is chosen to be

exactly equal to the L/DCR time constant, the voltage drop

across the external capacitor is equal to the drop across

the inductor DCR multiplied by R2/(R1 + R2). R2 scales the

voltage across the sense terminals for applications where

the DCR is greater than the target sense resistor value.

To properly dimension the external ﬁlter components, the

DCR of the inductor must be known. It can be measured

using a good RLC meter, but the DCR tolerance is not

always the same and varies with temperature; consult the

manufacturers’ data sheets for detailed information.

Using the inductor ripple current value from the Inductor

Value Calculation section, the target sense resistor value

is:

R(EQUIV) =

SENSE(MAX)

IMAX +DIL

To ensure that the application will deliver full load cur-

rent over the full operating temperature range, determine

RSENSE(EQUIV), keeping in mind that the maximum current

sense threshold (VSENSE(MAX)) for the LTC3859A is ﬁxed

at 50mV.

Next, determine the DCR of the inductor. Where provided,

use the manufacturer’s maximum value, usually given at

20°C. Increase this value to account for the temperature

coefﬁcient of resistance, which is approximately 0.4%/°C.

A conservative value for TL(MAX) is 100°C.

To scale the maximum inductor DCR to the desired sense

resistor value, use the divider ratio:

RD=RSENSE(EQUIV)

DCRMAX atTL(MAX)

C1 is usually selected to be in the range of 0.1µF to 0.47µF.

This forces R1||R2 to around 2k, reducing error that might

have been caused by the SENSE+ pin’s ±1µA current.

The equivalent resistance R1||R2 is scaled to the room

temperature inductance and maximum DCR:



R1R2 =L

(DCR at 20°C) •C1

The sense resistor values are:



R1=R1R2

; R2 =R1•RD

1−RD

4b. Using the Inductor DCR to Sense Current

4a. Using a Resistor to Sense Current

Figure 4. Current Sensing Methods

3859A F04a

LTC3859A

INTVCC

BOOST

SENSE1,2+

(SENSE3–)

SENSE1, 2–

(SENSE3+)

SGND

VIN1,2

(VOUT3)

VOUT1,2

(VIN3)

RSENSE

CAP

PLACED NEAR SENSE PINS

3859A F04b

LTC3859A

INTVCC

BOOST

SENSE1, 2+

(SENSE3–)

SENSE1, 2–

(SENSE3+)

SGND

VIN1,2

(VOUT3)

VOUT1,2

(VIN3)

C1* R2

*PLACE C1 NEAR SENSE PINS RSENSE(EQ) = DCR(R2/(R1+R2))

L DCR

INDUCTOR

(R1||R2) • C1 = L/DCR

LTC3859A

3859af

applicaTions inForMaTion

The maximum power loss in R1 is related to duty cycle. For

the buck controllers, the maximum power loss will occur

in continuous mode at the maximum input voltage:

PLOSS R1=(VIN(MAX) −VOUT)•VOUT

For the boost controller, the maximum power loss in R1

will occur in continuous mode at VIN = 1/2•VOUT:

PLOSS R1=(VOUT(MAX)

−

VIN)•VIN

Ensure that R1 has a power rating higher than this value.

If high efﬁciency is necessary at light loads, consider this

power loss when deciding whether to use DCR sensing or

sense resistors. Light load power loss can be modestly

higher with a DCR network than with a sense resistor, due

to the extra switching losses incurred through R1. However,

DCR sensing eliminates a sense resistor, reduces conduc-

tion losses and provides higher efﬁciency at heavy loads.

Peak efﬁciency is about the same with either method.

Inductor Value Calculation

The operating frequency and inductor selection are inter-

related in that higher operating frequencies allow the use

of smaller inductor and capacitor values. So why would

anyone ever choose to operate at lower frequencies with

larger components? The answer is efﬁciency. A higher

frequency generally results in lower efﬁciency because

of MOSFET gate charge losses. In addition to this basic

trade-off, the effect of inductor value on ripple current and

low current operation must also be considered.

The inductor value has a direct effect on ripple current.

The inductor ripple current DIL decreases with higher

inductance or frequency. For the buck controllers, DIL

increases with higher VIN:

DIL=1

(f)(L) VOUT 1−VOUT

VIN











For the boost controller, the inductor ripple current DIL

increases with higher VOUT:

DIL=1

(f)(L) VIN 1−VIN

VOUT













Accepting larger values of DIL allows the use of low

inductances, but results in higher output voltage ripple

and greater core losses. A reasonable starting point for

setting ripple current is DIL = 0.3(IMAX). The maximum

DIL occurs at the maximum input voltage for the bucks

and VIN = 1/2•VOUT for the boost.

The inductor value also has secondary effects. The tran-

sition to Burst Mode operation begins when the average

inductor current required results in a peak current below

25% of the current limit (30% for the boost) determined

by RSENSE. Lower inductor values (higher DIL) will cause

this to occur at lower load currents, which can cause a dip

in efﬁciency in the upper range of low current operation. In

Burst Mode operation, lower inductance values will cause

the burst frequency to decrease.

Inductor Core Selection

Once the value for L is known, the type of inductor must

be selected. High efﬁciency converters generally cannot

afford the core loss found in low cost powdered iron cores,

forcing the use of more expensive ferrite or molypermalloy

cores. Actual core loss is independent of core size for a

ﬁxed inductor value, but it is very dependent on inductance

selected. As inductance increases, core losses go down.

Unfortunately, increased inductance requires more turns

of wire and therefore copper losses will increase.

Ferrite designs have very low core loss and are preferred

at high switching frequencies, so design goals can con-

centrate on copper loss and preventing saturation. Ferrite

core material saturates “hard,” which means that induc-

tance collapses abruptly when the peak design current is

exceeded. This results in an abrupt increase in inductor

ripple current and consequent output voltage ripple. Do

not allow the core to saturate!

LTC3859A

3859af

applicaTions inForMaTion

Power MOSFET and Schottky Diode

(Optional) Selection

Two external power MOSFETs must be selected for each

controller in the LTC3859A: one N-channel MOSFET for the

top switch (main switch for the buck, synchronous for the

boost), and one N-channel MOSFET for the bottom switch

(main switch for the boost, synchronous for the buck).

The peak-to-peak drive levels are set by the INTVCC voltage.

This voltage is typically 5.4V during start-up (see EXTVCC

Pin Connection). Consequently, logic-level threshold

MOSFETs must be used in most applications. Pay close

attention to the BVDSS speciﬁcation for the MOSFETs as

well; many of the logic level MOSFETs are limited to 30V

or less.

Selection criteria for the power MOSFETs include the

on-resistance RDS(ON), Miller capacitance CMILLER, input

voltage and maximum output current. Miller capacitance,

CMILLER, can be approximated from the gate charge curve

usually provided on the MOSFET manufacturers’ data

sheet. CMILLER is equal to the increase in gate charge

along the horizontal axis while the curve is approximately

ﬂat divided by the speciﬁed change in VDS. This result is

then multiplied by the ratio of the application applied VDS

to the gate charge curve speciﬁed VDS. When the IC is

operating in continuous mode the duty cycles for the top

and bottom MOSFETs are given by:

Buck Main Switch Duty Cycle = VOUT

VIN

Buck Sync Switch Duty Cycle = VIN −VOUT

VIN

Boost Main Switch Duty Cycle =VOUT −VIN

VOUT

Boost Sync Switch Duty Cycle =VIN

VOUT

The MOSFET power dissipations at maximum output

current are given by:

PMAIN_BUCK =VOUT

VIN

IOUT(MAX)

( )

21+ δ

( )

RDS(ON) +

(VIN)2IOUT(MAX)









(RDR)(CMILLER )•

VINTVCC −VTHMIN

VTHMIN









(f)

PSYNC _BUCK =VIN −VOUT

VIN

IOUT(MAX)

( )

21+ δ

( )

RDS(ON)

PMAIN_BOOST =VOUT −VIN

( )

VOUT

VIN

2IOUT(MAX)

( )

2•

1+ δ

( )

RDS(ON) +V2

OUT

VIN













IOUT(MAX)









•

RDR

( )

CMILLER

( )

•1

VINTVCC −VTHMIN

VTHMIN









(f)

PSYNC _BOOST =VIN

VOUT

IOUT(MAX)

( )

21+ δ

( )

RDS(ON)

where z is the temperature dependency of RDS(ON) and

RDR (approximately 2Ω) is the effective driver resistance

at the MOSFET’s Miller threshold voltage. VTHMIN is the

typical MOSFET minimum threshold voltage.

Both MOSFETs have I2R losses while the main N-channel

equations for the buck and boost controllers include an

additional term for transition losses, which are highest at

high input voltages for the bucks and low input voltages for

the boost. For VIN < 20V (high VIN for the boost) the high

current efﬁciency generally improves with larger MOSFETs,

while for VIN > 20V (low VIN for the boost) the transition

losses rapidly increase to the point that the use of a higher

RDS(ON) device with lower CMILLER actually provides higher

LTC3859A

3859af

applicaTions inForMaTion

efﬁciency. The synchronous MOSFET losses for the buck

controllers are greatest at high input voltage when the top

switch duty factor is low or during a short-circuit when the

synchronous switch is on close to 100% of the period. The

synchronous MOSFET losses for the boost controller are

greatest when the input voltage approaches the output volt-

age or during an overvoltage event when the synchronous

switch is on 100% of the period.

The term (1+ z) is generally given for a MOSFET in the

form of a normalized RDS(ON) vs Temperature curve, but

z = 0.005/°C can be used as an approximation for low

voltage MOSFETs.

The optional Schottky diodes D4, D5, and D6 shown in

Figure 13 conduct during the dead-time between the

conduction of the two power MOSFETs. This prevents

the body diode of the synchronous MOSFET from turning

on, storing charge during the dead-time and requiring a

reverse recovery period that could cost as much as 3%

in efﬁciency at high VIN. A 1A to 3A Schottky is generally

a good compromise for both regions of operation due to

the relatively small average current. Larger diodes result

in additional transition losses due to their larger junction

capacitance.

Boost CIN, COUT Selection

The input ripple current in a boost converter is relatively

low (compared with the output ripple current), because

this current is continuous. The boost input capacitor CIN

voltage rating should comfortably exceed the maximum

input voltage. Although ceramic capacitors can be relatively

tolerant of overvoltage conditions, aluminum electrolytic

capacitors are not. Be sure to characterize the input voltage

for any possible overvoltage transients that could apply

excess stress to the input capacitors.

The value of CIN is a function of the source impedance, and

in general, the higher the source impedance, the higher the

required input capacitance. The required amount of input

capacitance is also greatly affected by the duty cycle. High

output current applications that also experience high duty

cycles can place great demands on the input supply, both

in terms of DC current and ripple current.

In a boost converter, the output has a discontinuous current,

so COUT must be capable of reducing the output voltage

ripple. The effects of ESR (equivalent series resistance) and

the bulk capacitance must be considered when choosing

the right capacitor for a given output ripple voltage. The

steady ripple due to charging and discharging the bulk

capacitance is given by:

Ripple =IOUT(MAX) •VOUT −VIN(MIN)

( )

COUT •VOUT •fV

where COUT is the output ﬁlter capacitor.

The steady ripple due to the voltage drop across the ESR

is given by:

DVESR = IL(MAX) • ESR

Multiple capacitors placed in parallel may be needed to

meet the ESR and RMS current handling requirements.

Dry tantalum, special polymer, aluminum electrolytic and

ceramic capacitors are all available in surface mount

packages. Ceramic capacitors have excellent low ESR

characteristics but can have a high voltage coefﬁcient.

Capacitors are now available with low ESR and high ripple

current ratings such as OS-CON and POSCAP.

Buck CIN, COUT Selection

The selection of CIN for the two buck controllers is simpliﬁed

by the 2-phase architecture and its impact on the worst-

case RMS current drawn through the input network (bat-

tery/fuse/capacitor). It can be shown that the worst-case

capacitor RMS current occurs when only one controller

is operating. The controller with the highest (VOUT)(IOUT)

product needs to be used in the formula shown in Equa-

tion (1) to determine the maximum RMS capacitor current

requirement. Increasing the output current drawn from

the other controller will actually decrease the input RMS

ripple current from its maximum value. The out-of-phase

technique typically reduces the input capacitor’s RMS

ripple current by a factor of 30% to 70% when compared

to a single phase power supply solution.

LTC3859A

3859af

applicaTions inForMaTion

In continuous mode, the source current of the top MOSFET

is a square wave of duty cycle (VOUT)/(VIN). To prevent

large voltage transients, a low ESR capacitor sized for the

maximum RMS current of one channel must be used. The

maximum RMS capacitor current is given by:

CIN Required IRMS ≈IMAX

VOUT

( )

VIN −VOUT

( )





1/2

(1)

This formula has a maximum at VIN = 2VOUT, where IRMS

= IOUT/2. This simple worst-case condition is commonly

used for design because even signiﬁcant deviations do not

offer much relief. Note that capacitor manufacturers’ ripple

current ratings are often based on only 2000 hours of life.

This makes it advisable to further derate the capacitor, or

to choose a capacitor rated at a higher temperature than

required. Several capacitors may be paralleled to meet

size or height requirements in the design. Due to the high

operating frequency of the LTC3859A, ceramic capacitors

can also be used for CIN. Always consult the manufacturer

if there is any question.

The beneﬁt of the LTC3859A 2-phase operation can be cal-

culated by using Equation (1) for the higher power controller

and then calculating the loss that would have resulted if

both controller channels switched on at the same time.

The total RMS power lost is lower when both controllers

are operating due to the reduced overlap of current pulses

required through the input capacitor’s ESR. This is why

the input capacitor’s requirement calculated above for the

worst-case controller is adequate for the dual controller

design. Also, the input protection fuse resistance, battery

resistance, and PC board trace resistance losses are also

reduced due to the reduced peak currents in a 2-phase

system. The overall beneﬁt of a multiphase design will

only be fully realized when the source impedance of the

power supply/battery is included in the efﬁciency testing.

The drains of the top MOSFETs should be placed within

1cm of each other and share a common CIN (s). Separat-

ing the drains and CIN may produce undesirable voltage

and current resonances at VIN.

A small (0.1µF to 1µF) bypass capacitor between the chip

VIN pin and ground, placed close to the LTC3859A, is also

suggested. A small (1Ω to 10Ω) resistor placed between

CIN (C1) and the VIN pin provides further isolation between

the two channels.

The selection of COUT is driven by the effective series

resistance (ESR). Typically, once the ESR requirement

is satisﬁed, the capacitance is adequate for ﬁltering. The

output ripple (DVOUT) is approximated by:

DVOUT ≈ DILESR+1

8fCOUT













where f is the operating frequency, COUT is the output

capacitance and DIL is the ripple current in the inductor.

The output ripple is highest at maximum input voltage

since DIL increases with input voltage.

Setting Output Voltage

The LTC3859A output voltages are each set by an external

feedback resistor divider carefully placed across the output,

as shown in Figure 5. The regulated output voltages are

determined by:

VOUT, BUCK =0.8V 1+RB













VOUT, BOOST =1.2V 1+RB











To improve the frequency response, a feedforward ca-

pacitor, CFF, may be used. Great care should be taken to

route the VFB line away from noise sources, such as the

inductor or the SW line.

Figure 5. Setting Output Voltage

3859A F05

1/3 LTC3859A

VFB

RBCFF

VOUT

LTC3859A

3859af

applicaTions inForMaTion

Tracking and Soft-Start

(TRACK/SS1, TRACK/SS2, SS3 Pins)

The start-up of each VOUT is controlled by the voltage on

the respective TRACK/SS pin (TRACK/SS1 for channel 1,

TRACK/SS2 for channel 2, SS3 for channel 3). When the

voltage on the TRACK/SS pin is less than the internal

0.8V reference (1.2V reference for the boost channel), the

LTC3859A regulates the VFB pin voltage to the voltage on the

TRACK/SS pin instead of the internal reference. Likewise,

the TRACK/SS pin for the buck channels can be used to

program an external soft-start function or to allow VOUT

to track another supply during start-up.

Soft-start is enabled by simply connecting a capacitor

from the TRACK/SS pin to ground, as shown in Figure 6.

An internal 1µA current source charges the capacitor,

providing a linear ramping voltage at the TRACK/SS pin.

The LTC3859A will regulate the VFB pin (and hence VOUT)

according to the voltage on the TRACK/SS pin, allowing

VOUT to rise smoothly from 0V to its ﬁnal regulated value.

The total soft-start time will be approximately:

tSS _BUCK =CSS •

0.8V

1µA

tSS _BOOST =CSS •1.2V

1µA

Alternatively, the TRACK/SS1 and TRACK/SS2 pins for the

two buck controllers can be used to track two (or more) sup-

plies during start-up, as shown qualitatively in Figures 7a

and 7b. To do this, a resistor divider should be connected

from the master supply (VX) to the TRACK/SS pin of the

slave supply (VOUT), as shown in Figure 8. During start-up

VOUT will track VX according to the ratio set by the resis-

tor divider:

VOUT

=RA

RTRACKA

•RTRACKA +RTRACKB

RA+RB

For coincident tracking (VOUT = VX during start-up),

RA = RTRACKA

RB = RTRACKB

7a. Coincident Tracking

7b. Radiometric Tracking

Figure 7. Two Different Modes of Output Voltage Tracking

Figure 8. Using the TRACK/SS Pin for Tracking

3859A F07a

VX(MASTER)

VOUT(SLAVE)

OUTPUT (VOUT)

TIME

3859A F07b

VX(MASTER)

VOUT(SLAVE)

OUTPUT (VOUT)

TIME

3859A F08

LTC3859A

VFB1,2

TRACK/SS1,2

VOUT

RTRACKB

RTRACKA

Figure 6. Using the TRACK/SS Pin to Program Soft-Start

3859A F06

1/3 LTC3859A

TRACK/SS

SGND

CSS

LTC3859A

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applicaTions inForMaTion

INTVCC Regulators

The LTC3859A features two separate internal P-channel

low dropout linear regulators (LDO) that supply power

at the INTVCC pin from either the VBIAS supply pin or the

EXTVCC pin depending on the connection of the EXTVCC

pin. INTVCC powers the gate drivers and much of the

LTC3859A’s internal circuitry. The VBIAS LDO and the

EXTVCC LDO regulate INTVCC to 5.4V. Each of these must

be bypassed to ground with a minimum of 4.7µF ceramic

capacitor. No matter what type of bulk capacitor is used, an

additional 1µF ceramic capacitor placed directly adjacent

to the INTVCC and PGND IC pins is highly recommended.

Good bypassing is needed to supply the high transient

currents required by the MOSFET gate drivers and to

prevent interaction between the channels.

High input voltage applications in which large MOSFETs

are being driven at high frequencies may cause the maxi-

mum junction temperature rating for the LTC3859A to be

exceeded. The INTVCC current, which is dominated by the

gate charge current, may be supplied by either the VBIAS

LDO or the EXTVCC LDO. When the voltage on the EXTVCC

pin is less than 4.7V, the VBIAS LDO is enabled. Power dis-

sipation for the IC in this case is highest and is equal to

VBIAS • I

INTVCC. The gate charge current is dependent

on operating frequency as discussed in the Efﬁciency

Considerations section. The junction temperature can be

estimated by using the equations given in Note 2 of the

Electrical Characteristics. For example, the LTC3859A

INTVCC current is limited to less than 40mA from a 40V

supply when not using the EXTVCC supply at a 70°C ambi-

ent temperature in the QFN package:

TJ = 70°C + (40mA)(40V)(34°C/W) = 125°C

To prevent the maximum junction temperature from being

exceeded, the input supply current must be checked while

operating in continuous conduction mode (PLLIN/MODE

= INTVCC) at maximum VIN.

When the voltage applied to EXTVCC rises above 4.7V, the

VBIAS LDO is turned off and the EXTVCC LDO is enabled.

The EXTVCC LDO remains on as long as the voltage applied

to EXTVCC remains above 4.5V. The EXTVCC LDO attempts

to regulate the INTVCC voltage to 5.4V, so while EXTVCC

is less than 5.4V, the LDO is in dropout and the INTVCC

voltage is approximately equal to EXTVCC. When EXTVCC

is greater than 5.4V, up to an absolute maximum of 14V,

INTVCC is regulated to 5.4V.

Using the EXTVCC LDO allows the MOSFET driver and

control power to be derived from one of the LTC3859A’s

switching regulator outputs (4.7V ≤ VOUT ≤ 14V) dur-

ing normal operation and from the VBIAS LDO when the

output is out of regulation (e.g., startup, short-circuit). If

more current is required through the EXTVCC LDO than

is speciﬁed, an external Schottky diode can be added

between the EXTVCC and INTVCC pins. In this case, do

not apply more than 6V to the EXTVCC pin and make sure

than EXTVCC ≤ VBIAS.

Signiﬁcant efﬁciency and thermal gains can be realized

by powering INTVCC from the buck output, since the VIN

current resulting from the driver and control currents will

be scaled by a factor of (Duty Cycle)/(Switcher Efﬁciency).

For 5V to 14V regulator outputs, this means connecting

the EXTVCC pin directly to VOUT. Tying the EXTVCC pin to

a 8.5V supply reduces the junction temperature in the

previous example from 125°C to:

TJ = 70°C + (40mA)(8.5V)(34°C/W) = 82°C

However, for 3.3V and other low voltage outputs, addi-

tional circuitry is required to derive INTVCC power from

the output.

LTC3859A

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applicaTions inForMaTion

The following list summarizes the four possible connec-

tions for EXTVCC:

1. EXTVCC grounded. This will cause INTVCC to be powered

from the internal 5.4V regulator resulting in an efﬁciency

penalty of up to 10% at high input voltages.

2. EXTVCC connected directly to the output voltage of one

of the buck regulators. This is the normal connection

for a 5V to 14V regulator and provides the highest ef-

ﬁciency.

3. EXTVCC connected to an external supply. If an external

supply is available in the 5V to 14V range, it may be

used to power EXTVCC providing it is compatible with the

MOSFET gate drive requirements. Ensure that EXTVCC

< VIN.

4. EXTVCC connected to an output-derived boost network

off one of the buck regulators. For 3.3V and other low

voltage buck regulators, efﬁciency gains can still be

realized by connecting EXTVCC to an output-derived

voltage that has been boosted to greater than 4.7V. This

can be done with the capacitive charge pump shown in

Figure 9. Ensure that EXTVCC < VIN.

Figure 9. Capacitive Charge Pump for EXTVCC

3859A F09

LTC3859A

PGND

RSENSE

MTOP

MBOT

EXTVCC

BAT85 BAT85

VIN1,2

BAT85

VOUT1,2

LTC3859A

3859af

applicaTions inForMaTion

Topside MOSFET Driver Supply (CB, DB)

External bootstrap capacitors CB connected to the BOOST

pins supply the gate drive voltages for the topside MOSFETs.

Capacitor CB in the Functional Diagram is charged though

external diode DB from INTVCC when the SW pin is low.

When one of the topside MOSFETs is to be turned on, the

driver places the CB voltage across the gate-source of the

desired MOSFET. This enhances the MOSFET and turns

on the topside switch. The switch node voltage, SW, rises

to VIN for the buck channels (VOUT for the boost channel)

and the BOOST pin follows. With the topside MOSFET

on, the boost voltage is above the input supply: VBOOST

= VIN + VINTVCC (VBOOST = VOUT + VINTVCC for the boost

controller). The value of the boost capacitor CB needs to

be 100 times that of the total input capacitance of the

topside MOSFET(s). The reverse breakdown of the external

Schottky diode must be greater than VIN(MAX) for the buck

channels and VOUT(MAX) for the boost channel.

The external diode DB can be a Schottky diode or silicon

diode, but in either case it should have low leakage and fast

recovery. Pay close attention to the reverse leakage at high

temperatures where it generally increases substantially.

The topside MOSFET driver for the boost channel includes

an internal charge pump that delivers current to the

bootstrap capacitor from the BOOST3 pin. This charge

current maintains the bias voltage required to keep the

top MOSFET on continuously during dropout/overvolt-

age conditions. The Schottky/silicon diode selected for

the boost topside driver should have a reverse leakage

less than the available output current the charge pump

can supply. Curves displaying the available charge pump

current under different operating conditions can be found

in the Typical Performance Characteristics section.

A leaky diode DB in the boost converter can not only

prevent the top MOSFET from fully turning on but it can

also completely discharge the bootstrap capacitor CB and

create a current path from the input voltage to the BOOST3

pin to INTVCC. This can cause INTVCC to rise if the diode

leakage exceeds the current consumption on INTVCC. This

is particularly a concern in Burst Mode operation where

the load on INTVCC can be very small. There is an internal

voltage clamp on INTVCC that prevents the INTVCC voltage

from running away, but this clamp should be regarded as a

failsafe only. The external Schottky or silicon diode should

be carefully chosen such that INTVCC never gets charged

up much higher than its normal regulation voltage.

Care should also be taken when choosing the external

diode DB for the buck converters. A leaky diode not only

increases the quiescent current of the buck converter, but

it can also cause a similar leakage path to INTVCC from

VOUT for applications with output voltages greater than

the INTVCC voltage (~5.4V).

Figure 10. Relationship Between Oscillator

Frequency and Resistor Value at the FREQ Pin

FREQ PIN RESISTOR (kΩ)

FREQUENCY (kHz)

600

800

1000

35 45 5525

3859A F10

400

200

500

700

900

300

100

065 75 85 95 105 115 125

LTC3859A

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applicaTions inForMaTion

Fault Conditions: Buck Current Limit and Current

Foldback

The LTC3859A includes current foldback for the buck

channels to help limit load current when the output is

shorted to ground. If the buck output falls below 70% of

its nominal output level, then the maximum sense volt-

age is progressively lowered from 100% to 40% of its

maximum selected value. Under short-circuit conditions

with very low duty cycles, the buck channel will begin

cycle skipping in order to limit the short-circuit current.

In this situation the bottom MOSFET will be dissipating

most of the power but less than in normal operation. The

short-circuit ripple current is determined by the minimum

on-time tON(MIN) of the LTC3859A (≈95ns), the input volt-

age and inductor value:

DIL(SC) = tON(MIN) (VIN/L)

The resulting average short-circuit current is:

ISC =40% •ILIM(MAX) −

2DIL(SC)

Fault Conditions: Buck Overvoltage Protection

(Crowbar)

The overvoltage crowbar is designed to blow a system

input fuse when the output voltage of the one of the buck

regulators rises much higher than nominal levels. The

crowbar causes huge currents to ﬂow, that blow the fuse

to protect against a shorted top MOSFET if the short oc-

curs while the controller is operating.

A comparator monitors the buck output for overvoltage

conditions. The comparator detects faults greater than

10% above the nominal output voltage. When this condi-

tion is sensed, the top MOSFET of the buck controller is

turned off and the bottom MOSFET is turned on until the

overvoltage condition is cleared. The bottom MOSFET

remains on continuously for as long as the overvoltage

condition persists; if VOUT returns to a safe level, normal

operation automatically resumes.

A shorted top MOSFET for the buck channel will result in

a high current condition which will open the system fuse.

The switching regulator will regulate properly with a leaky

top MOSFET by altering the duty cycle to accommodate

the leakage.

Fault Conditions: Over Temperature Protection

At higher temperatures, or in cases where the internal

power dissipation causes excessive self heating on chip

(such as INTVCC short to ground), the over temperature

shutdown circuitry will shut down the LTC3859A. When

the junction temperature exceeds approximately 170°C,

the over temperature circuitry disables the INTVCC LDO,

causing the INTVCC supply to collapse and effectively

shutting down the entire LTC3859A chip. Once the junc-

tion temperature drops back to approximately 155°C, the

INTVCC LDO turns back on. Long term overstress (TJ >

125°C) should be avoided as it can degrade the perfor-

mance or shorten the life of the part.

Phase-Locked Loop and Frequency Synchronization

The LTC3859A has an internal phase-locked loop (PLL)

comprised of a phase frequency detector, a lowpass ﬁlter,

and a voltage-controlled oscillator (VCO). This allows the

turn-on of the top MOSFET of controller 1 to be locked to

the rising edge of an external clock signal applied to the

PLLIN/MODE pin. The turn-on of controller 2’s top MOSFET

is thus 180 degrees out of phase with the external clock.

The phase detector is an edge sensitive digital type that

provides zero degrees phase shift between the external

and internal oscillators. This type of phase detector does

not exhibit false lock to harmonics of the external clock.

If the external clock frequency is greater than the internal

oscillator’s frequency, fOSC, then current is sourced continu-

ously from the phase detector output, pulling up the VCO

input. When the external clock frequency is less than fOSC,

current is sunk continuously, pulling down the VCO input.

LTC3859A

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applicaTions inForMaTion

If the external and internal frequencies are the same but

exhibit a phase difference, the current sources turn on for

an amount of time corresponding to the phase difference.

The voltage at the VCO input is adjusted until the phase

and frequency of the internal and external oscillators are

identical. At the stable operating point, the phase detector

output is high impedance and the internal ﬁlter capacitor,

CLP, holds the voltage at the VCO input.

Note that the LTC3859A can only be synchronized to an

external clock whose frequency is within range of the

LTC3859A’s internal VCO, which is nominally 55kHz to

1MHz. This is guaranteed to be between 75kHz and 850kHz.

Typically, the external clock (on PLLIN/MODE pin) input high

threshold is 1.6V, while the input low threshold is 1.2V.

Rapid phase-locking can be achieved by using the FREQ pin

to set a free-running frequency near the desired synchro-

nization frequency. The VCO’s input voltage is prebiased

at a frequency correspond to the frequency set by the

FREQ pin. Once prebiased, the PLL only needs to adjust

the frequency slightly to achieve phase-lock and synchro-

nization. Although it is not required that the free-running

frequency be near external clock frequency, doing so will

prevent the operating frequency from passing through a

large range of frequencies as the PLL locks.

Table 1 summarizes the different states in which the FREQ

pin can be used.

Table 1

FREQ PIN PLLIN/MODE PIN FREQUENCY

0V DC Voltage 350kHz

INTVCC DC Voltage 535kHz

Resistor to SGND DC Voltage 50kHz to 900kHz

Any of the Above External Clock Phase-Locked to

External Clock

Minimum On-Time Considerations

Minimum on-time tON(MIN) is the smallest time duration

that the LTC3859A is capable of turning on the top MOSFET

(bottom MOSFET for the boost controller). It is determined

by internal timing delays and the gate charge required to

turn on the top MOSFET. Low duty cycle applications may

approach this minimum on-time limit and care should be

taken to ensure that

tON(MIN)_BUCK <

OUT

VIN(f)

tON(MIN)_BOOST <VOUT −VIN

VOUT(f)

If the duty cycle falls below what can be accommodated

by the minimum on-time, the controller will begin to skip

cycles. The output voltage will continue to be regulated,

but the ripple voltage and current will increase.

The minimum on-time for the LTC3859A is approximately

95ns for the bucks and 120ns for the boost. However, as

the peak sense voltage decreases the minimum on-time

gradually increases up to about 130ns. This is of particu-

lar concern in forced continuous applications with low

ripple current at light loads. If the duty cycle drops below

the minimum on-time limit in this situation, a signiﬁcant

amount of cycle skipping can occur with correspondingly

larger current and voltage ripple.

LTC3859A

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applicaTions inForMaTion

Efﬁciency Considerations

The percent efﬁciency of a switching regulator is equal to

the output power divided by the input power times 100%.

It is often useful to analyze individual losses to determine

what is limiting the efﬁciency and which change would

produce the most improvement. Percent efﬁciency can

be expressed as:

%Efﬁciency = 100% – (L1 + L2 + L3 + ...)

where L1, L2, etc. are the individual losses as a percent-

age of input power.

Although all dissipative elements in the circuit produce

losses, four main sources usually account for most of the

losses in LTC3859A circuits: 1) IC VIN current, 2) INTVCC

regulator current, 3) I2R losses, 4) Topside MOSFET

transition losses.

1. The VIN current is the DC supply current given in the

Electrical Characteristics table, which excludes MOSFET

driver and control currents. VIN current typically results

in a small (<0.1%) loss.

2. INTVCC current is the sum of the MOSFET driver and

control currents. The MOSFET driver current results

from switching the gate capacitance of the power

MOSFETs. Each time a MOSFET gate is switched from

low to high to low again, a packet of charge, dQ, moves

from INTVCC to ground. The resulting dQ/dt is a current

out of INTVCC that is typically much larger than the

control circuit current. In continuous mode, IGATECHG

= f(QT + QB), where QT and QB are the gate charges of

the topside and bottom side MOSFETs.

Supplying INTVCC from an output-derived source power

through EXTVCC will scale the VIN current required

for the driver and control circuits by a factor of (Duty

Cycle)/(Efﬁciency). For example, in a 20V to 5V applica-

tion, 10mA of INTVCC current results in approximately

2.5mA of VIN current. This reduces the mid-current loss

from 10% or more (if the driver was powered directly

from VIN) to only a few percent.

3. I2R losses are predicted from the DC resistances of the

fuse (if used), MOSFET, inductor, current sense resis-

tor, and input and output capacitor ESR. In continuous

mode the average output current ﬂows through L and

RSENSE, but is “chopped” between the topside MOSFET

and the synchronous MOSFET. If the two MOSFETs have

approximately the same RDS(ON), then the resistance

of one MOSFET can simply be summed with the resis-

tances of L, RSENSE and ESR to obtain I2R losses. For

example, if each RDS(ON) = 30mΩ, RL = 50mΩ, RSENSE

= 10mΩ and RESR = 40mΩ (sum of both input and

output capacitance losses), then the total resistance

is 130mΩ. This results in losses ranging from 3% to

13% as the output current increases from 1A to 5A for

a 5V output, or a 4% to 20% loss for a 3.3V output.

Efﬁciency varies as the inverse square of VOUT for the

same external components and output power level. The

combined effects of increasingly lower output voltages

and higher currents required by high performance digital

systems is not doubling but quadrupling the importance

of loss terms in the switching regulator system!

4. Transition losses apply only to the top MOSFET(s) (bot-

tom MOSFET for the boost), and become signiﬁcant only

when operating at high input voltages (typically 15V or

greater). Transition losses can be estimated from:

Transition Loss = (1.7)VIN2 • IO(MAX) • CRSS • f

Other hidden losses such as copper trace and internal

battery resistances can account for an additional 5%

to 10% efﬁciency degradation in portable systems. It is

very important to include these “system” level losses

during the design phase. The internal battery and fuse

resistance losses can be minimized by making sure that

CIN has adequate charge storage and very low ESR at

the switching frequency. A 25W supply will typically

require a minimum of 20µF to 40µF of capacitance

having a maximum of 20mΩ to 50mΩ of ESR. The

LTC3859A 2-phase architecture typically halves this

input capacitance requirement over competing solu-

tions. Other losses including Schottky conduction losses

during dead-time and inductor core losses generally

account for less than 2% total additional loss.

LTC3859A

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applicaTions inForMaTion

Checking Transient Response

The regulator loop response can be checked by looking at

the load current transient response. Switching regulators

take several cycles to respond to a step in DC (resistive)

load current. When a load step occurs, VOUT shifts by an

amount equal to DILOAD(ESR), where ESR is the effective

series resistance of COUT. DILOAD also begins to charge or

discharge COUT generating the feedback error signal that

forces the regulator to adapt to the current change and

return VOUT to its steady-state value. During this recovery

time VOUT can be monitored for excessive overshoot or

ringing, which would indicate a stability problem. OPTI-

LOOP compensation allows the transient response to be

optimized over a wide range of output capacitance and

ESR values. The availability of the ITH pin not only allows

optimization of control loop behavior, but it also provides

a DC coupled and AC ﬁltered closed loop response test

point. The DC step, rise time and settling at this test

point truly reﬂects the closed loop response. Assuming a

predominantly second order system, phase margin and/

or damping factor can be estimated using the percentage

of overshoot seen at this pin. The bandwidth can also be

estimated by examining the rise time at the pin. The ITH

external components shown in Figure 16 will provide an

adequate starting point for most applications.

The ITH series RC-CC ﬁlter sets the dominant pole-zero

loop compensation. The values can be modiﬁed slightly

(from 0.5 to 2 times their suggested values) to optimize

transient response once the ﬁnal PC layout is done and

the particular output capacitor type and value have been

determined. The output capacitors need to be selected

because the various types and values determine the loop

gain and phase. An output current pulse of 20% to 80%

of full-load current having a rise time of 1µs to 10µs will

produce output voltage and ITH pin waveforms that will

give a sense of the overall loop stability without breaking

the feedback loop.

Placing a power MOSFET directly across the output

capacitor and driving the gate with an appropriate signal

generator is a practical way to produce a realistic load step

condition. The initial output voltage step resulting from

the step change in output current may not be within the

bandwidth of the feedback loop, so this signal cannot be

used to determine phase margin. This is why it is better to

look at the ITH pin signal which is in the feedback loop and

is the ﬁltered and compensated control loop response.

The gain of the loop will be increased by increasing

RC and the bandwidth of the loop will be increased by

decreasing CC. If RC is increased by the same factor

that CC is decreased, the zero frequency will be kept the

same, thereby keeping the phase shift the same in the

most critical frequency range of the feedback loop. The

output voltage settling behavior is related to the stability

of the closed-loop system and will demonstrate the actual

overall supply performance.

A second, more severe transient is caused by switching

in loads with large (>1µF) supply bypass capacitors. The

discharged bypass capacitors are effectively put in parallel

with COUT, causing a rapid drop in VOUT. No regulator can

alter its delivery of current quickly enough to prevent this

sudden step change in output voltage if the load switch

resistance is low and it is driven quickly. If the ratio of

CLOAD to COUT is greater than 1:50, the switch rise time

should be controlled so that the load rise time is limited

to approximately 25 • CLOAD. Thus a 10µF capacitor would

require a 250µs rise time, limiting the charging current

to about 200mA.

LTC3859A

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applicaTions inForMaTion

Buck Design Example

As a design example for one of the buck channels channel,

assume VIN = 12V(NOMINAL), VIN = 22V(MAX), VOUT = 3.3V,

IMAX = 6A, VSENSE(MAX) = 50mV, and f = 350kHz.

The inductance value is chosen ﬁrst based on a 30% ripple

current assumption. The highest value of ripple current

occurs at the maximum input voltage. Tie the FREQ pin

to GND, generating 350kHz operation. The minimum

inductance for 30% ripple current is:

DIL=VOUT

(f)(L) 1−VOUT

VIN(NOMINAL)













A 3.9µH inductor will produce 29% ripple current. The

peak inductor current will be the maximum DC value plus

one half the ripple current, or 6.88A. Increasing the ripple

current will also help ensure that the minimum on-time

of 95ns is not violated. The minimum on-time occurs at

maximum VIN:

tON(MIN) =

OUT

VIN(MAX)(f) =3.3V

22V(350kHz) =429ns

The RSENSE resistor value can be calculated by using the

minimum value for the maximum current sense threshold

(43mV):

RSENSE ≤43mV

6.88A

=0.006Ω

Choosing 1% resistors: RA = 25k and RB = 80.6k yields

an output voltage of 3.33V.

The power dissipation on the top side MOSFET can be easily

estimated. Choosing a Fairchild FDS6982S dual MOSFET

results in: RDS(ON) = 0.035Ω/0.022Ω, CMILLER = 215pF. At

maximum input voltage with T(estimated) = 50°C:

PMAIN =3.3V

22V (6A)21+(0.005)(50°C−25°C)

{ }

(0.035Ω)+(22V)265A

2(2.5Ω)(215pF) •

5V −2.3V +1

2.3V











(350kHz) =433mW

A short-circuit to ground will result in a folded back

current of:

ISC =20mV

0.006Ω−1

95ns(22V)

3.9µH











=3.07A

with a typical value of RDS(ON) and z = (0.005/°C)(25°C)

= 0.125. The resulting power dissipated in the bottom

MOSFET is:

PSYNC =(2.23A)2(1.125)(0.022Ω)=233mW

which is less than under full-load conditions.

The input capacitor to the buck regulator CIN is chosen

for an RMS current rating of at least 3A at temperature

assuming only this channel is on. COUT is chosen with an

ESR of 0.02Ω for low output ripple. The output ripple in

continuous mode will be highest at the maximum input volt-

age. The output voltage ripple due to ESR is approximately:

VORIPPLE = RESR (DIL) = 0.02Ω(1.75A) = 35mVP-P

LTC3859A

3859af

PC Board Layout Checklist

When laying out the printed circuit board, the following

checklist should be used to ensure proper operation of

the IC. These items are also illustrated graphically in the

layout diagram of Figure 11. Figure 12 illustrates the current

waveforms present in the various branches of the 2-phase

synchronous buck regulators operating in the continuous

mode. Check the following in your layout:

1. Are the top N-channel MOSFETs MTOP1 and MTOP2

located within 1cm of each other with a common drain

connection at CIN? Do not attempt to split the input

decoupling for the two channels as it can cause a large

resonant loop.

2. Are the signal and power grounds kept separate? The

combined IC signal ground pin and the ground return

of CINTVCC must return to the combined COUT (–) ter-

minals. The path formed by the top N-channel MOSFET,

Schottky diode and the CIN capacitor should have short

leads and PC trace lengths. The output capacitor (–)

terminals should be connected as close as possible

to the (–) terminals of the input capacitor by placing

the capacitors next to each other and away from the

Schottky loop described above.

3. Do the LTC3859A VFB pins’ resistive dividers connect to

the (+) terminals of COUT? The resistive divider must be

connected between the (+) terminal of COUT and signal

ground. The feedback resistor connections should not

be along the high current input feeds from the input

capacitor(s).

4. Are the SENSE– and SENSE+ leads routed together with

minimum PC trace spacing? The ﬁlter capacitor between

SENSE+ and SENSE– should be as close as possible

to the IC. Ensure accurate current sensing with Kelvin

connections at the sense resistor.

5. Is the INTVCC decoupling capacitor connected close

to the IC, between the INTVCC and the power ground

pins? This capacitor carries the MOSFET drivers’ cur-

rent peaks. An additional 1µF ceramic capacitor placed

immediately next to the INTVCC and PGND pins can help

improve noise performance substantially.

6. Keep the switching nodes (SW1, SW2, SW3), top gate

nodes (TG1, TG2, TG3), and boost nodes (BOOST1,

BOOST2, BOOST3) away from sensitive small-signal

nodes, especially from the opposites channel’s voltage

and current sensing feedback pins. All of these nodes

have very large and fast moving signals and therefore

should be kept on the output side of the LTC3859A and

occupy minimum PC trace area.

7. Use a modiﬁed star ground technique: a low impedance,

large copper area central grounding point on the same

side of the PC board as the input and output capacitors

with tie-ins for the bottom of the INTVCC decoupling

capacitor, the bottom of the voltage feedback resistive

divider and the SGND pin of the IC.

applicaTions inForMaTion

LTC3859A

3859af

PC Board Layout Debugging

Start with one controller on at a time. It is helpful to use

a DC-50MHz current probe to monitor the current in the

inductor while testing the circuit. Monitor the output switch-

ing node (SW pin) to synchronize the oscilloscope to the

internal oscillator and probe the actual output voltage as

well. Check for proper performance over the operating

voltage and current range expected in the application.

The frequency of operation should be maintained over the

input voltage range down to dropout and until the output

load drops below the low current operation threshold—

typically 25% of the maximum designed current level in

Burst Mode operation.

The duty cycle percentage should be maintained from cycle

to cycle in a well-designed, low noise PCB implementation.

Variation in the duty cycle at a subharmonic rate can sug-

gest noise pickup at the current or voltage sensing inputs

or inadequate loop compensation. Overcompensation of

the loop can be used to tame a poor PC layout if regulator

bandwidth optimization is not required. Only after each

controller is checked for its individual performance should

both controllers be turned on at the same time. A particularly

difﬁcult region of operation is when one controller channel

is nearing its current comparator trip point when the other

channel is turning on its top MOSFET. This occurs around

50% duty cycle on either channel due to the phasing of

the internal clocks and may cause minor duty cycle jitter.

Reduce VIN from its nominal level to verify operation of

the regulator in dropout. Check the operation of the un-

dervoltage lockout circuit by further lowering VIN while

monitoring the outputs to verify operation.

Investigate whether any problems exist only at higher out-

put currents or only at higher input voltages. If problems

coincide with high input voltages and low output currents,

look for capacitive coupling between the BOOST, SW, TG,

and possibly BG connections and the sensitive voltage

and current pins. The capacitor placed across the current

sensing pins needs to be placed immediately adjacent to

the pins of the IC. This capacitor helps to minimize the

effects of differential noise injection due to high frequency

capacitive coupling. If problems are encountered with

high current output loading at lower input voltages, look

for inductive coupling between CIN, Schottky and the top

MOSFET components to the sensitive current and voltage

sensing traces. In addition, investigate common ground

path voltage pickup between these components and the

SGND pin of the IC.

An embarrassing problem, which can be missed in an

otherwise properly working switching regulator, results

when the current sensing leads are hooked up backwards.

The output voltage under this improper hookup will still

be maintained but the advantages of current mode control

will not be realized. Compensation of the voltage loop will

be much more sensitive to component selection. This

behavior can be investigated by temporarily shorting out

the current sensing resistor—don’t worry, the regulator

will still maintain control of the output voltage.

applicaTions inForMaTion

LTC3859A

3859af

applicaTions inForMaTion

Figure 11. Branch Current Waveforms for Bucks

RL1

SW1 RSENSE1 VOUT1

COUT1

VIN

CIN

RIN

RL2

BOLD LINES INDICATE

HIGH SWITCHING

CURRENT. KEEP LINES

TO A MINIMUM LENGTH.

SW2

3859A F11

RSENSE2 VOUT2

COUT2

LTC3859A

3859af

Typical applicaTions

Figure 12. High Efﬁciency Wide Input Range Dual 5V/8.5V Converter

3859A F12

LTC3859A

SENSE1–

SENSE1+

PGOOD1

TG1

SW1

BOOST1

BG1

VBIAS

PGND

INTVCC

TG2

BOOST2

SW2

BG2

SENSE2+

SENSE2–

TG3

SW3

BOOST3

BG3

SENSE3–

SENSE3+

VFB1

ITH1

TRACK/SS1

FREQ

PLLIN/MODE

SGND

RUN1

RUN2

RUN3

VFB2

ITH2

TRACK/SS2

VFB3

ITH3

SS3

1nF

100k

CB1

0.1µF

CBIAS

10µF

CINT1

4.7µF

1nF

MTOP1

MBOT1

10µF L1

4.9µH RSENSE1

6mΩ

COUT1

220µF

VOUT1

MTOP2

MBOT2

10µF

6.5µH RSENSE2

8mΩ

COUT2

68µF

VOUT2

8.5V

CB2

0.1µF

MTOP3

MBOT3

1.2µH RSENSE2

2mΩ

1nF

CB3

0.1µF

CIN

220µF

VIN

2.5V TO 38V

(START-UP ABOVE 5V)

* VOUT3 IS 10V WHEN VIN < 10V,

FOLLOWS VIN WHEN VIN > 10V

COUT3

220µF

RB1

357k

OPT

VOUT1

RA1

68.1k

RB2

649k

10pF

VOUT2

RA2

68.1k

CITH1A

100pF

CITH1

1500pF

RITH1

15k

CITH2A

68pF

CITH2

2.2nF

CSS2

0.1µF

RITH2

15k

RB3

499k

OPT

VOUT3

RA3

68.1k

CITH3A

820pF

CITH3

0.01µF

CSS3

0.1µF

RITH3

3.6k

CSS1

0.1µF

MTOP1, MTOP2: BSZ097NO4LS

MBOT1, MBOT2: BSZ097NO4LS

MTOP3: BSC027NO4LS

MBOT3: BSCO1BN04LS

L1: WÜRTH 744314490

L2: WÜRTH 744314650

L3: WÜRTH 744325120

COUT1: SANYO 6TPB220ML

COUT2: SANYO 10TPC68M

CIN, COUT3: SANYO 50CE220LX

D1, D2: CMDH-4E

D3: BAS140W

VOUT3

10V*

OV3

EXTVCC

VOUT1

LTC3859A

3859af

Typical applicaTions

Figure 13. High Efﬁciency Wide Input Range Dual 12V/3.3V Converter

3859A F13

LTC3859A

SENSE1–

SENSE1+

PGOOD1

TG1

SW1

BOOST1

BG1

VBIAS

PGND

INTVCC

TG2

BOOST2

SW2

BG2

SENSE2+

SENSE2–

TG3

SW3

BOOST3

BG3

SENSE3–

SENSE3+

VFB1

ITH1

TRACK/SS1

FREQ

PLLIN/MODE

SGND

RUN1

RUN2

RUN3

VFB2

ITH2

TRACK/SS2

VFB3

ITH3

SS3

1nF

100k

CB1

0.1µF

CBIAS

10µF

CINT1

4.7µF

1nF

MTOP1

MBOT1

10µF L1

8.8µH RSENSE1

9mΩ

COUT1

47µF

VOUT1

12V

MTOP2

MBOT2

10µF

3.2µH RSENSE2

6mΩ

COUT2

150µF

VOUT2

3.3V

CB2

0.1µF

MTOP3

MBOT3

1.2µH RSENSE2

2mΩ

1nF

CB3

0.1µF

CIN

220µF

VIN

2.5V TO 38V

(START-UP ABOVE 5V)

* VOUT3 IS 15V WHEN VIN < 15V,

FOLLOWS VIN WHEN VIN > 15V

COUT3

220µF

RB1

475k

33pF

VOUT1

RA1

34k

RB2

215k

15pF

VOUT2

RA2

68.1k

CITH1A

100pF

CITH1

680pF

RITH1

10k

CITH2A

150pF

CITH2

820pF

CSS2

0.1µF

RITH2

15k

RB3

787k

OPT

VOUT3

RA3

68.1k

CITH3A

820pF

INTVCC

CITH3

0.01µF

CSS3

0.1µF

RITH3

3.6k

CSS1

0.1µF

MTOP1, MTOP2: VISHAY Si7848DP

MBOT1, MBOT2: VISHAY Si7848DP

MTOP3: BSC027NO4LS

MBOT3: BSCO1BN04LS

L1: SUMIDA CDEP105-8R8M

L2: SUMIDA CDEP105-3R2M

L3: WÜRTH 744325120

COUT1: KEMET T525D476MO16E035

COUT2: SANYO 4TPE150M

CIN, COUT3: SANYO 50CE220LX

D1, D2: CMDH-4E

D3: BAS140W

VOUT3

15V*

OV3

100k

EXTVCC

LTC3859A

3859af

Typical applicaTions

Figure 14. High Efﬁciency Triple 24V/1V/1.2V Converter from 12V VIN

3859A F14

LTC3859A

SENSE1–

SENSE1+

PGOOD1

TG1

SW1

BOOST1

BG1

VBIAS

PGND

INTVCC

TG2

BOOST2

SW2

BG2

SENSE2+

SENSE2–

TG3

SW3

BOOST3

BG3

SENSE3–

SENSE3+

VFB1

ITH1

TRACK/SS1

FREQ

PLLIN/MODE

SGND

RUN1

RUN2

RUN3

VFB2

ITH2

TRACK/SS2

VFB3

ITH3

SS3

1nF

100k

CB1

0.1µF

CBIAS

10µF

CINT1

4.7µF

1nF

MTOP1

MBOT1

10µF L1

0.47µH RSENSE1

3.5mΩ

COUT1

220µF

×2

VOUT1

MTOP2

MBOT2

10µF

0.47µH RSENSE2

3.5mΩ

COUT2

220µF

×2

VOUT2

1.2V

CB2

0.1µF

MTOP3

MBOT3

3.3µH RSENSE2

4mΩ

1nF

CB3

0.1µF CIN

220µF

COUT3

220µF

RB1

28.7k

56pF

VOUT1

RA1

115k

RB2

57.6k

56pF

VOUT2

RA2

115k

CITH1A

200pF

CITH1

1000pF

RITH1

3.93k

CITH2A

200pF

CITH2

1000pF

CSS2

0.01µF

RITH2

3.93k

RB3

232k

OPT

VOUT3

RA3

12.1k

CITH3A

220pF

CITH3

15nF

CSS3

0.01µF

RITH3

8.66k

CSS1

0.01µF

MTOP1, MTOP2: RENESAS RJK0305

MBOT1, MBOT2: RENESAS RJK0328

MTOP3, MBOT3: RENESAS HAT2169H

L1, L2: SUMIDA CDEP105-0R4

L3: PULSE PA1494.362NL

COUT1, COUT2: SANYO 2R5TPE220M

CIN, COUT3: SANYO 50CE220AX

D1, D2: CMDH-4E

D3: BAS140W

VOUT3

24V

VIN

12V

OV3

EXTVCC

LTC3859A

3859af

Typical applicaTions

Figure 15. High Efﬁciency 1.2V/3.3V Step-Down Converter with 10.5V SEPIC Converter

3859A F15

LTC3859A

SENSE1–

SENSE1+

PGOOD1

TG1

SW1

BOOST1

BG1

VBIAS

PGND

INTVCC

TG2

BOOST2

SW2

BG2

SENSE2+

SENSE2–

TG3

SW3

BOOST3

BG3

SENSE3–

SENSE3+

VFB1

ITH1

TRACK/SS1

FREQ

PLLIN/MODE

SGND

RUN1

RUN2

RUN3

VFB2

ITH2

TRACK/SS2

VFB3

ITH3

SS3

1nF

100k

CB1

0.1µF

CBIAS

10µF

CINT1

4.7µF

1nF

MTOP1

MBOT1

10µF L1

2.2µH RSENSE1

9mΩ

COUT1

220µF

VOUT1

1.2V

MTOP2

MBOT2

10µF

6.5µH RSENSE2

9mΩ

COUT2

220µF

VOUT2

3.3V

CB2

0.1µF

MBOT3 L3

10µH

RSENSE2

9mΩ

1nF

10µF

50V

CIN

220µF

COUT3

270µF

RB1

57.6k

VOUT1

RA1

115k

RB2

357k

VOUT2

RA2

115k

CITH1A

100pF

CITH1

2.2nF

RITH1

5.6k

CITH2A

100pF

CITH2

3.3nF

CSS2

0.1µF

RITH2

9.1k

RB3

887k

VOUT3

RA3

115k

CITH3A

10pF

CITH3

100nF

CSS3

0.1µF

RITH3

13k

CSS1

0.1µF

MTOP1, MTOP2: BSZ097NO4LS

MBOT1, MBOT2: BSZ097NO4LS

MBOT3: BSZ097NO4L

L1: WURTH 744311220

L2: WURTH 744314650

L3: COOPER BUSSMANN DRQ125-100

COUT1: SANYO 2R5TPE220MAFB

COUT2: SANYO 4TPE220MAZB

COUT3: SANYO SVPC270M

CIN: SANYO 50CE220LX

D1, D2: CMDH-4E

D3: DIODES INC B360A-13-F

VOUT3

10.5V

1.2A

VIN

5.8V TO 34V

••

OV3

EXTVCC

LTC3859A

3859af

package DescripTion

FE Package

38-Lead Plastic TSSOP (4.4mm)

(Reference LTC DWG # 05-08-1772 Rev C)

Exposed Pad Variation AA

4.75

(.187) REF

FE38 (AA) TSSOP REV C 0910

0.09 – 0.20

(.0035 – .0079)

0° – 8°

0.25

REF

0.50 – 0.75

(.020 – .030)

4.30 – 4.50*

(.169 – .177)

119

REF

9.60 – 9.80*

(.378 – .386)

1.20

(.047)

MAX

0.05 – 0.15

(.002 – .006)

0.50

(.0196)

BSC 0.17 – 0.27

(.0067 – .0106)

TYP

RECOMMENDED SOLDER PAD LAYOUT

0.315 ±0.05

0.50 BSC

4.50 REF

6.60 ±0.10

1.05 ±0.10

4.75 REF

2.74 REF

2.74

(.108)

MILLIMETERS

(INCHES) *DIMENSIONS DO NOT INCLUDE MOLD FLASH. MOLD FLASH

SHALL NOT EXCEED 0.150mm (.006") PER SIDE

NOTE:

1. CONTROLLING DIMENSION: MILLIMETERS

2. DIMENSIONS ARE IN

3. DRAWING NOT TO SCALE

SEE NOTE 4

4. RECOMMENDED MINIMUM PCB METAL SIZE

FOR EXPOSED PAD ATTACHMENT

6.40

(.252)

BSC

LTC3859A

3859af

Information furnished by Linear Technology Corporation is believed to be accurate and reliable.

However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-

tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.

package DescripTion

UHF Package

38-Lead Plastic QFN (5mm × 7mm)

(Reference LTC DWG # 05-08-1701 Rev C)

5.00 ± 0.10

NOTE:

1. DRAWING CONFORMS TO JEDEC PACKAGE

OUTLINE M0-220 VARIATION WHKD

2. DRAWING NOT TO SCALE

3. ALL DIMENSIONS ARE IN MILLIMETERS

PIN 1

TOP MARK

(SEE NOTE 6)

BOTTOM VIEW—EXPOSED PAD

5.50 REF 5.15 ± 0.10

7.00 ± 0.10

0.75 ± 0.05

R = 0.125

TYP R = 0.10

TYP

0.25 ± 0.05

(UH) QFN REF C 1107

0.50 BSC

0.200 REF

0.00 – 0.05

RECOMMENDED SOLDER PAD LAYOUT

APPLY SOLDER MASK TO AREAS THAT ARE NOT SOLDERED

3.00 REF

3.15 ± 0.10

0.40 ±0.10

0.70 ± 0.05

0.50 BSC

5.5 REF

3.00 REF 3.15 ± 0.05

4.10 ± 0.05

5.50 ± 0.05 5.15 ± 0.05

6.10 ± 0.05

7.50 ± 0.05

0.25 ± 0.05

PACKAGE

OUTLINE

4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE

MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.20mm ON ANY SIDE

5. EXPOSED PAD SHALL BE SOLDER PLATED

6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION

ON THE TOP AND BOTTOM OF PACKAGE

PIN 1 NOTCH

R = 0.30 TYP OR

0.35 × 45° CHAMFER

LTC3859A

3859af

Linear Technology Corporation

1630 McCarthy Blvd., Milpitas, CA 95035-7417

(408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com

LT 0811 • PRINTED IN USA

relaTeD parTs

PART NUMBER DESCRIPTION COMMENTS

LTC3857/LTC3857-1

LTC3858/LTC3858-1 Low IQ, Dual Output 2-Phase Synchronous Step-Down

DC/DC Controllers with 99% Duty Cycle Phase-Lockable Fixed Frequency 50kHz to 900kHz,

4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 24V, IQ = 50µA/170µA

LTC3890/LTC3890-1 60V, Low IQ, Dual 2-Phase Synchronous Step-Down

DC/DC Controller Phase-Lockable Fixed Frequency 50kHz to 900kHz,

4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ 24V, IQ = 50µA

LTC3789 4-Switch High Efﬁciency Buck-Boost Controller 4V ≤ VIN ≤ 38V, 0.8V ≤ VOUT ≤ 38V, SSOP-28, 4mm × 5mm QFN-28

LTC3834/LTC3834-1

LTC3835/LTC3835-1 Low IQ, Synchronous Step-Down DC/DC Controller with

99% Duty Cycle Phase-Lockable Fixed Frequency 140kHz to 650kHz,

4V ≤ VIN ≤ 36V, 0.8V ≤ VOUT ≤ 10V, IQ = 30µA/80µA

LTC3891 60V, Low IQ, Synchronous Step-Down DC/DC Controller

with 99% Duty Cycle PLL Fixed Frequency 50kHz to 900kHz, 4V ≤ VIN ≤ 60V,

0.8V ≤ VOUT ≤ 24V, TSSOP-20E, 3mm × 4mm QFN-20

LTC3824 Low IQ, High Voltage DC/DC Controller, 100% Duty Cycle Selectable Fixed 200kHz to 600kHz Operating Frequency,

4V ≤ VIN ≤ 60V, 0.8V ≤ VOUT ≤ VIN , IQ = 40µA, MSOP-10E

Typical applicaTion

High Efﬁciency Wide Input Range Dual 3.3V/8.5V Converter

3859A TA02

LTC3859A

SENSE1–

SENSE1+

PGOOD1

TG1

SW1

BOOST1

BG1

VBIAS

PGND

INTVCC

TG2

BOOST2

SW2

BG2

SENSE2+

SENSE2–

TG3

SW3

BOOST3

BG3

SENSE3–

SENSE3+

VFB1

ITH1

TRACK/SS1

FREQ

PLLIN/MODE

SGND

RUN1

RUN2

RUN3

VFB2

ITH2

TRACK/SS2

VFB3

ITH3

SS3

1nF

100k

CB1

0.1µF

CBIAS

10µF

CINT1

4.7µF

1nF

MTOP1

MBOT1

10µF L1

3.2µH RSENSE1

6mΩ

COUT1

150µF

VOUT1

3.3V

MTOP2

MBOT2

10µF

6.5µH RSENSE2

8mΩ

COUT2

68µF

VOUT2

8.5V

CB2

0.1µF

MTOP3

MBOT3

1.2µH RSENSE2

2mΩ

1nF

CB3

0.1µF

CIN

220µF

VIN

2.5V TO 38V

(START-UP ABOVE 5V)

* VOUT3 IS 10V WHEN VIN < 10V,

FOLLOWS VIN WHEN VIN > 10V

COUT3

220µF

RB1

215k

15pF

VOUT1

RA1

68.1k

RB2

649k

10pF

VOUT2

RA2

68.1k

CITH1A

150pF

CITH1

820pF

RITH1

15k

CITH2A

68pF

CITH2

2.2nF

CSS2

0.1µF

RITH2

15k

RB3

499k

OPT

VOUT3

VOUT2

RA3

68.1k

CITH3A

820pF

CITH3

0.01µF

CSS3

0.1µF

RITH3

3.6k

CSS1

0.1µF

MTOP1, MTOP2: VISHAY Si7848DP

MBOT1, MBOT2: BSZ097NO4LS

MTOP3: BSC027NO4LS

MBOT3: BSCO1BN04LS

L1: SUMIDA CDEP105-3R2M

L2: WÜRTH 744314650

L3: WÜRTH 744325120

COUT1: SANYO 6TPB220ML

COUT2: SANYO 4TPE150M

CIN, COUT3: SANYO 50CE220LX

D1, D2: CMDH-4E

D3: BAS140W

VOUT3

10V*

OV3

EXTVCC