SL2610/IG/LH1P - Zarlink Semiconductor, Inc.

Features

• Single chip mixer/oscillator PLL combination for

multi band tuner for DTT applications

• Each mixer oscillator band optimized for wide

dynamic range

• RF input stages allow for either single-ended or

differential drive

• PLL frequency synthesizer designed for low

phase noise performance

• Broadband output level detect with onset adjust

• PLL frequency synthesizer compatible with

standard digital terrestrial offsets

• Four integrated switching ports

•I

2C fast mode compliant

• ESD protection (Normal ESD handling

procedures should be observed)

Applications

• Terrestrial digital receiver systems

• Terrestrial analogue receiver systems

• Cable receiver systems

• Data communications systems

Figure 1 - Pin Allocation Diagram

LH40

PORT P3

VccRF

HI INPUT

PORT P2

PORT P1

MID INPUT

SL2610

LOLOWOP

LOLOWOPB

LOMIDOP

VccLO

LOHIIP

LOHIOP

LOHIOPB

LOHIIPB

VccLO

MID INPUTB

VccRF

LO INPUT

IFOPB

IFOP

AGCBIAS

VCCIF

IFIPB

IFIP

ADD

CONVOP

CONVOPB

VccDIG

LO INPUTB

VccRF

AGCOUT

PORT P0

CHARGE PUMP

XTAL CAP

DRIVE

XTAL

SDA

SCL

LOMIDOPB

HI INPUTB

VEE

(PACKAGE

PADDLE)

Figure 2 - SL2610 Block Diagram

CONVOP

BAND

MID

BAND

CONVOP

IFIP

IFIPB

IFOP

IFOPB

AGC BIA

AGC OUT

BAND

MID

BAND

I2C

Interface

Port

Interface

REF

DIVIDER

PORT P0

PORT P1

PORT P2

PORT P3

PROG

DIVIDER

CHARGE

PUMP

DRIVE

XTAL

XTALCAP

SDA SCL ADD

SELECT

February 2003

Ordering Information

SL2610/IG/LH1S (tubes)

SL2610/IG/LH1T (tape & reel)

-40oC to 85oC

SL2610

Wide Dynamic Range Image Reject MOPLL

Data Sheet

SL2610 Data Sheet

Description

The SL2610 is a mixer oscillator intended primarily for application in all band tuners, where it performs image

reject downconversion of the RF channel to a standard 36MHz or 44MHz IF.

Each band consists of a low noise preamplifier/mixer and local oscillator with an external varactor tuned tank.

The band outputs share a common low impedance SAWF driver stage.

Frequency selection is controlled by the on-board I2C bus frequency synthesizer. This block also controls four

general purpose switching ports for selecting the prefilter/AGC stages.

The SL2610 has high intermodulation intercept performance so offering high signal to spurious performance in

the presence of higher amplitude interferers or in the presence of a wide bandwidth composite input signal.

An output broadband level detect circuit is included for control of the tuner front end AGC.

Quick Reference Data

Characteristics Units

Frequency range: LOW band 50-500 MHz

MID band 50-500 MHz

HIGH band 200-900 MHz

Conversion gain * 32 ± 2dB

Noise figure 13 dB

Typical Image Reject 35 dB

P1dB input referred, Converter section only 106 dBuV

IP3 input referred, Converter section only 14 dBm

IP2 input referred, Converter section only 48 dBm

LO phase noise (free running) @ 10kHz offset -90 dBc/Hz

@ 100kHz offset -110 dBc/Hz

PLL phase noise -158 dBc/Hz

Maximum composite output amplitude 3 dBm

* Assuming 2 dB shaping filter loss in external IF path.

Data Sheet SL2610

Figure 3 - SL2610 Evaluation Board Schematic

SL2610 Data Sheet

Figure 4 - SL2610 Evaluation Board Layout (Top)

Figure 5 - SL2610 Evaluation Board Layout (Bottom)

Data Sheet SL2610
5
1.0 Functional Description
The SL2610 is a multi band RF mixer oscillator with image reject and on-board frequency synthesizer. It is
intended primarily for application in all band terrestrial tuners and requires a minimum external component
count. It contains all elements required for RF downconversion to a standard IF with the exception of external
VCO tank circuits. 
The pin allocation is contained in Figure 1 and the block diagram in Figure 2.
1.1 Mixer/oscillator section
In normal application the RF input is interfaced to the selected mixer oscillator preamplifier through the tuner
prefilter and AGC stages. The mixer input is arranged such that the signal can be coupled either differentially or
single-ended, and achieves the specified minimum performance in both configurations. Band input impedances
and NF are contained in Figure 11 and Figure 12 respectively. The converter two tone input spectra are
contained in Figure 13 and Figure 14.
The preamplifier output then feeds the mixer stage where the required channel is image reject downconverted
to the IF frequency. The local oscillator frequency for the downconversion is obtained from the on board local
oscillator, which uses an external varactor tuned tank. Typical VCO applications are contained in Figures 8, 9,
and 10. 
The output of the mixer is then fed to the converter output driver which presents a matched 200 Ω differential
load to an external IF shaping filter.
The output of the shaping filter is then coupled into the IFAMP stage, which provides further gain and offers a
50 Ω output impedance to interface direct with the tuner SAW filter.
The SL2610 contains a broadband level detect circuit whose output can be used to control the tuner AGC. The
target level of the AGC detector is controlled by the voltage applied to the AGCBIAS pin. The characteristic of
the target level is given in Figure 18.
1.2 PLL Frequency Synthesizer
The PLL frequency synthesizer section contains all the elements necessary, with the exception of a frequency
reference and loop filter, to control a varicap tuned local oscillator, so forming a complete PLL frequency
synthesised source. The device allows for operation with a high comparison frequency and is fabricated in high
speed logic, which enables the generation of a loop with good phase noise performance. It can also be
operated with comparison frequencies appropriate for frequency offsets as required in digital terrestrial (DTT)
receivers. 
The LO signal is multiplexed from the selected oscillator section to an internal preamplifier which provides gain
and reverse isolation from the divider signals. The output of the preamplifier interfaces direct with the 15-bit
fully programmable divider which is of MN+A architecture, where the dual modulus prescaler is 16/17, the A
counter is 4-bits and the M counter is 11 bits.
The output of the programmable divider is fed to the phase comparator where it is compared in both phase and
frequency domain with the comparison frequency. This frequency is derived either from the on-board crystal
controlled oscillator or from an external reference source. In both cases the reference frequency is divided
down to the comparison frequency by the reference divider which is programmable into 1 of 29 ratios as
detailed in Table 1.
The output of the phase detector feeds a charge pump and loop amplifier section which when used with an
external loop filter integrates the current pulses into the varactor line voltage. 
The programmable divider output Fpd, divided by two and the reference divider output Fcomp, can be switched
to port P0 by programming the device into test mode. The test modes are described in Table 5.

SL2610 Data Sheet

2.0 Programming

The SL2610 is controlled by an I2C data bus and is compatible with both standard and fast mode formats.

Data and Clock are fed in on the SDA and SCL lines respectively as defined by I2C bus format. The synthesizer

can either accept data (write mode), or send data (read mode). The LSB of the address byte (R/W) sets the

device into write mode if it is low, and read mode if it is high. Tables 2 and 3 illustrate the format of the data. The

device can be programmed to respond to several addresses, which enables the use of more than one

synthesizer in an I2C bus system (Tables 2 and 3). Table 4 shows how the address is selected by applying a

voltage to the ‘ADD’ input. When the device receives a valid address byte, it pulls the SDA line low during the

acknowledge period and during following acknowledge periods after further data bytes are received. When the

device is programmed into read mode, the controller accepting the data must pull the SDA line low during all

status byte acknowledge periods to read another status byte. If the controller fails to pull the SDA line low

during this period the device generates an internal STOP condition which inhibits further reading.

2.1 Write mode

With reference to Table 2, bytes 2 and 3 contain frequency information bits 214-20 inclusive. Byte 4 controls the

reference divider ratio bits R4-R0 (Table 1), and the charge pump setting bits C1-C0 (Table 6). Byte 5 controls

the IF select (Table 8), the band select function bits BS1-BS0 (Table 7), the switching ports P3-P0 and the test

modes (Table 5).

After reception and acknowledgement of a correct address (byte 1), the first bit of the following byte determines

whether the byte is interpreted as a byte 2 or 4, a logic '0' indicating byte 2, and a logic '1' indicating byte 4.

Having interpreted this byte as either byte 2 or 4 the following data byte will be interpreted as byte 3 or 5

respectively. Having received two complete data bytes, additional data bytes can be entered, where byte

interpretation follows the same procedure, without re-addressing the device. This procedure continues until a

STOP condition is received. The STOP condition can be generated after any data byte, if however it occurs

during a byte transmission, the previous byte data is retained. To facilitate smooth fine tuning, the frequency

data bytes are only accepted by the device after all 15 bits of frequency data have been received, or after the

generation of a STOP condition.

2.2 Read mode

When the device is in read mode, the status byte read from the device takes the form shown Table 3.

Bit 1 (POR) is the power-on reset indicator, and this is set to a logic '1' if the Vcc supply to the device has

dropped below 3V (at 25oC), e.g. when the device is initially turned ON. The POR is reset to '0' when the read

sequence is terminated by a STOP command. When POR is set high this indicates that the programmed

information may have been corrupted and the device reset to power up condition.

Bit 2 (FL) indicates whether the device is phase locked, a logic '1' is present if the device is locked, and a logic

'0' if the device is unlocked.

Data Sheet SL2610

2.3 Programmable features

Synthesiser

programmable divider

Function as described above.

Reference programmable

divider

Function as described above.

Band selection The required mixer oscillator band and RF input is selected by bits BS1-BS0,

within data byte 5, as defined in Table 7.

IF selection The centre of the image reject passband is selected by IF as defined in Table 8.

Charge pump current The charge pump current can be programmed by bits C1-C0 within data byte 4, as

defined in Table 6.

Ports P3-P0 These are configured as NPN open collector buffers and programmed by bits P3-

P0.

Logic ‘1’ = on.

Logic ‘0’ = off (high impedance); default on power up.

In test modes, when TE=1, ports P3-P0 respond according to T2-T0 respectively,

and previously transmitted data is lost.

Test mode The test modes are invoked by setting bits T2–T0 as described in Table 5.

SL2610 Data Sheet

Table 1 - Reference Division Ratio

R4 R3 R2 R1 R0 Ratio

00000 2

00001 4

00010 8

00011 16

00100 32

00101 64

00110 128

00111 256

01000not allowed

01001 5

01010 10

01011 20

01100 40

01101 80

01110 160

01111 320

10000not allowed

10001 6

10010 12

10011 24

10100 48

10101 96

10110 192

10111 384

11000not allowed

11001 7

11010 14

11011 28

11100 56

11101 112

11110 224

11111 448

Data Sheet SL2610

Table 2 - Write Data Format (MSB is transmitted first)

Table 3 - Read Data Format (MSB is transmitted first)

A : Acknowledge bit

MA1,MA0 : Variable address bits (see Table 4)

214-20: Programmable division ratio control bits

R4-R0 : Reference division ratio select (see Table 1)

C1,C0 : Charge pump current select (see Table 6)

BS1-BS0 : Band select bits (see Table 7)

IF : IF passband select (see Table 8)

TE : Test mode enable

T2-T0 : Test mode control bits when TE=1 (see Table 5)

P3-P0 : P3-P0 port output states

POR : Power on reset indicator

FL : Phase lock flag

MSB LSB

Address 1 1 0 0 0MA1MA00AByte 1

Programmable

divider

14 213 212 211 210 2928AByte 2

Programmable

divider

2726252423222120AByte 3

Control data 1 C1C0R4R3R2R1R0AByte 4

Control data IF BS1 BS0 TE P3/T2 P2/T1 P1/T0 P0 A Byte 5

MSB LSB

Address 11000MA1MA01AByte 1

Status Byte POR FL 0 0 0 0 0 0 A Byte 2

SL2610 Data Sheet

# Programmed by connecting a 30 kΩ resistor between pin and Vcc

Table 4 - Address Selection

Table 5 - Test Modes

* crystal and selected local oscillator need signals to enable charge pump test modes and to toggle status

byte bit FL

X -’don’t care’

MA1 MA0 Address Input Voltage Level

0 0 0-0.1Vcc

0 1 Open circuit

1 0 0.4Vvcc – 0.6 Vcc #

1 1 0.9 Vcc - Vcc

TE T2 T1 T0 Test Mode Description

0 X X X Normal operation

1 0 0 0 Normal operation

1 0 0 1 Charge pump sink *

Status byte FL set to logic ‘0’

1 0 1 0 Charge pump source *

Status byte FL set to logic ‘0’

1 0 1 1 Charge pump disabled *

Status byte FL set to logic ‘1’

1 1 0 0 Normal operation and Port P0 = Fpd/2

1 1 0 1 Charge pump sink *

Status byte FL set to logic ‘0’

Port P0 = Fcomp

1 1 1 0 Charge pump source *

Status byte FL set to logic ‘0’

Port P0 = Fcomp

1 1 1 1 Charge pump disabled *

Status byte FL set to logic ‘1’

Port P0 = Fcomp

Data Sheet SL2610

Table 6 - Charge pump current

Table 7 - Band select

C1 C0 Current in µA

min typ max

00+

85 +130 +175

01+190 +280 +370

10+420 +600 +780

11+930 +1300 +1670

BS1 BS0 Band Selected

0 0 LO Band

01 MID Band

1 0 HI band

1 1 HI band

IF input Centre of Image Reject Passband Passband

Bandwidth

0 57 MHz 6 MHz

0 44 MHz 6 MHz

1 36 MHz 8 MHz

Table 8 - IF SELECT function

SL2610 Data Sheet

Figure 6 - Crystal Oscillator Application

Figure 7 - Ifamp Output Load Condition for Test Purposes

Figure 8 - LO Band VCO Application

XTALCAP

XTAL

39 pF

18 pF

SL2610

to 50 Ω load

SL2610

IFOP

IFOPB

5:1

C2 L1

4K7

1u5H

100pF

BB640 VT

7pF

R16

120nH

20R

LOLOWOP LOLOWOPB

Data Sheet SL2610

Figure 9 - Mid Band VCO Application

Figure 10 - HI Band VCO Application

L3 36nH

C10

7pF

82nH

4K7

100pF

BB640

LOMIDOP LOMIDOPB

C15

10R

L5 22nH

C16

100pF D3

BB555 5pF R19

C14

C13

C12C11

2p2 2p2 2p2 2p2

R17

10R

R18

10R

4K7

R5 1K

8.2nH

LOHIIP LOHIOP LOHIOPB LOHIIPB

SL2610 Data Sheet

Figure 11 - LO, MID and HI Band Input Impedance

Figure 12 - Low, Mid and Hi Band Noise Figure versus Frequency

CH1 S 11 1 U FS

START 50.000 000 MHz STOP 900.000 000 MHz

DEV1 VCC=4.7V

Cor

PRm

12 Mar 2002 15:10:11

1_: 152.31 -12.117 145.94 pF

90.000 000 MHz

2_: 150.74

-34.063

220 MHz

3_: 133.48

-62.813

500 MHz

4_: 111.79

-86.926

900 MHz

10.5

11.5

12.5

0 100 200 300 400 500 600 700 800 900 1000

LO Frequency (MHz)

Noise Figure (dB)

Data Sheet SL2610

Figure 13 - Converter third order two tone intermodulation test condition spectrum, input

referred, all bands

Figure 14 - Second order two tone intermodulation test condition spectrum, input referred

-14 dBm

-56 dBm

(6 MHz)

f1-df f1 f2 f2+df

Incident power from 50Ω source

IIM3; -42dBc

-14 dBm

-54 dBm

f2-f1 f1 f2

Incident power from 50Ω source

IIM2; -40dBc

SL2610 Data Sheet

Figure 15 - Converter Output Impedance (Single Ended)

Figure 16 - IFAMP Input Impedance

CH1 S

11 1 U FS

START 32.000 000 MHz STOP 60.000 000 MHz

DEV4 5.3V

PRm

26 Nov 2002 13:38:57

3_: 101.43 -8.0313 347.67 pF

57.000 000 MHz

1_: 102.92

-5.043

36 MHz

2_: 102.48

-6.4883

44 MHz

CH1 S

11 1 U FS

START 30.000 000 MHz STOP 60.000 000 MHz

Avg

PRm

27 Nov 2002 09:17:33

1_: 173.88 11.094 49.045 nH

36.000 000 MHz

2_: 178.89

10.016

44 MHz

3_: 185.77

04.922

57 MHz

Data Sheet SL2610

Figure 17 - IFAMP Output Impedance (Single Ended)

Figure 18 - Typical AGC Output Level Set versus AGCBIAS Voltage

CH1 S

11 1 U FS

START 30.000 000 MHz STOP 60.000 000 MHz

PRm

27 Nov 2002 08:59:45

1_: 58.967 8.8438 39.098 nH

36.000 000 MHz

2_: 59.295

11.096

44 MHz

3_: 60.443

14.813

57 MHz

-25

-20

-15

-10

-5

0123456

AGCBIAS Voltage (V)

Output Level (dBm)

SL2610 Data Sheet
18
Electrical Characteristics
Test conditions (unless otherwise stated)
Tamb = -40oC to 85oC, Vee= 0V, Vcc=Vcca=Vccd = 5V +5%
These characteristics are guaranteed by either production test or design. They apply within the specified
ambient temperature and supply voltage unless otherwise stated.
Characteristic pin min typ max units conditions
Supply current 163 196 mA All switching ports off.
LO or MID BAND 
ENABLED
Input frequency range 50 500 MHz
Input impedance See Figure 11 and refer to Note 8.
Input Noise Figure 13 dB Tamb=27oC, see Figure 12, refer to Note 2, 
no correction for external filtering.
Converter gain 10
8.5
14
12.5
dB
dB
At 36MHz and 44MHz IF frequency.
At 57MHz IF frequency.
Conversion gain from 50 Ω single ended 
source to differential 
200 Ω load, refer to Note 3.
Conversion gain to IFAMP 
output
28
25
36
33
dB
dB
At 36MHz and 44MHz IF frequency.
At 57MHz IF frequency.
Conversion gain from 50 Ω single ended 
source to 50 Ω single-ended load with 
output transformer as in Figure 7, see Notes 
2 and 3.
Gain variation within 
channel
0.4 1 dB Channel bandwidth 8 MHz within operating 
frequency range, see note (2), excluding 
interstage shaping filter ripple.
Converter input referred 
IP2
26 dBm See Figure 14 and refer to Notes 4 and 6. 
Assuming ideal power match.
Converter input referred 
IM2
-40 dBc See Figure 14 and refer to Notes 4 and 6.
Converter input referred 
IP3
7 dBm See Figure 13 and refer to Notes 4 and 6. 
Assuming ideal power match.
Converter input referred 
IM3
-42 dBc See Figure 13 and refer to Notes 4 and 6.
Input referred P1dB 101 dBµV
Local oscillator operation 
range
50 550 MHz Refer to Note 7.
Local oscillator tuning 
range
68
200
225
465
MHz
MHz
With application as in Figure 8.
With application as in Figure 9.

Data Sheet SL2610
19
Characteristic Pin Min Typ Max Units Conditions
LO phase noise, SSB 
@ 1 kHz offset 
@ 10 kHz offset
@ 100 kHz offset
-55
-86
-109
dBc/Hz
dBc/Hz
dBc/Hz
With application as in Figure 8 and 
Figure 9 outside of PLL loop 
bandwidth.
LO temperature stability
80 kHz/oC
Application as in Figure 8 and Figure 
9. 
No temperature compensation.
LO turn on drift
100 kHz
Application as in Figure 8 and Figure 
9, frequency drift over 15 minute 
period from turn on at a fixed ambient 
temperature.
No temperature compensation.
LO to RF input leakage 60 dBµV Application as in Figures 8 and 9.
LO Vcc stability 0.5 MHz/V
LO spurs due to RF 
pulling
-52 dBc See Note 5.
HI BAND ENABLED
Input frequency range 200 870 MHz
Input impedance See Figure 11 and refer to Note 8.
Input Noise Figure 13.5 dB Tamb=27oC, see Figure 12, refer to 
Note 2, no correction for external 
filtering.
Converter gain 10
8.5
14
12.5
dB
dB
At 36MHz and 44MHz IF frequency.
At 57MHz IF frequency.
Conversion gain from 50 Ω single 
ended source to differential 
200 Ω load, refer to Note 3.
Conversion gain to 
IFAMP output
28
25
36
33
dB
dB
At 36MHz and 44MHz IF frequency.
At 57MHz IF frequency.
Conversion gain from 50 Ω single 
ended source to 50 Ω single-ended 
load with output transformer as in 
Figure 7, see Notes 2 and 3.
Gain variation within 
channel
0.4 1 dB Channel bandwidth 8 MHz within 
operating frequency range, see Note 
3, excluding interstage shaping filter 
ripple.
Converter input referred 
IP2
26 dBm See Figure 14 and refer to Notes 4 
and 6. Assuming ideal power match.

SL2610 Data Sheet
20
Characteristic Pin Min Typ Max Units Conditions
Converter input referred IM2 -40 dBc See Figure 14 and refer to Notes 4 and 
6.
Converter input referred IP3 7 dBm See Figure 13 and refer to Notes 4 and 
6. Assuming ideal power match.
Converter input referred IM3 -42 dBc See Figure 13 and refer to Notes 4 and 
6.
Input referred P1dB 101 dBµV
Local oscillator operation 
range
200 1000 MHz Refer to Note 7.
Local oscillator tuning range 440 950 MHz With application as in 
Figure 10.
LO phase noise, SSB 
@ 1 kHz offset 
@ 10 kHz offset
@ 100 kHz offset
-55
-86
-109
dBc/Hz
dBc/Hz
dBc/Hz
With application as in Figure 10, 
outside of PLL loop bandwidth.
LO temperature stability
110 kHz/oC
Application as in Figure 10.
No temperature compensation.
LO turn on drift
100 kHz
Application as in Figure 10, frequency 
drift over 15 minute period from turn on 
at a fixed ambient temperature.
No temperature compensation.
LO to RF input leakage 60 dBµV Application as in Figure 10.
LO Vcc stability 0.5 MHz/V
LO spurs due to RF pulling -52 dBc See Note 5.
All Bands
Converter output impedance 200 ΩDifferential, see Figure 15.
Image rejection 25
29
25
30
35
30
dB
dB
dB
At 36 MHz IF frequency, IF bit = 1.
At 44 MHz IF frequency, IF bit = 0.
At 57 MHz IF frequency, IF bit = 0.
See Table 8.
Tamb  =  0 oC to +85oC.
Tank Schematics and layouts as in 
recommended application. See 
Figures , 4 and 5.
Isolation between band inputs -60 dBc Level of desired signal converted to IF 
output through disabled band relative 
to signal converted through enabled 
band.
Composite output amplitude 3 dBm

Data Sheet SL2610

Characteristic Pin Min Typ Max Units Conditions

IFAMP

Input frequency range 32 60 MHz

Input impedance 200 ΩDifferential, see Figure 16.

Gain 20

18.5

22.5

At 36MHz and 44MHz IF frequency.

At 57MHz IF frequency.

Voltage conversion gain from 200 Ω

differential source to differential load

as contained in Figure 7, see Note 3.

Output impedance 100 ΩDifferential, see Figure 17.

Output limiting 3

2.7

Vp-p

At 36MHz and 44MHz IF fequency.

At 57MHz IF frequency.

Differential into load as in Figure 7.

IFAMP OPIP3 135 dBµV Two output tones at 2 MHz

separation at 104 dBuV into load as

in Figure 7, see Note 2.

IFAMP OPIM3 -62 dBc Two output tones at 2 MHz

separation at 104 dBuV into load as

in Figure 7, see Note 2.

AGCBIAS Leakage

current

28 -100

-50

100

µA

Vee ≤ Vagc1 ≤ Vcc

1.5V ≤ Vagc1 ≤ 3.5V

AGCOUT voltage range 13 0.5 3 V Max load current 20 µA.

AGC output level set See Figure 18.

Supply rejection -52 dBc Spurs introduced on converted

output relative to desired signal by a

supply ripple voltage of 10 mV p-p in

the range 1 kHz to 100 kHz

(including external supply

decoupling).

Synthesiser

SDA, SCL

Input high voltage

Input low voltage

Input current

Leakage current

Hysterysis

19, 20

-10

0.4

5.5

1.5

µA

Input voltage =Vee to Vcc

Input voltage = Vee to 5.5V, Vcc=Vee

SDA output voltage 19 0.4

0.6

Isink = 3 mA

Isink = 6 mA

SCL clock rate 20 400 kHz

SL2610 Data Sheet

Notes

1 All power levels are referred to 50 Ω, and 0 dBm = 107 dBµV.

2 Total system with final load as in Figure 7, including an interstage IF shaping filter with IL of 2 dB and

characteristic impedance of 200 Ω differential.

3 The specified gain is determined by the following formula;

Gs = Gm + Vtr where Gs = gain as specified

Gm = gain as measured with specified load conditions

Vtr = voltage transformation ratio of transformer as in Figure 7

4 Two input tones within RF operating range at -14 dBm from 50Ω single ended source with 200 Ω differential output load. DC output

current must be shunted to Vcc through suitable inductor, i.e. 10µH.

5 Modulation spurs introduced on local oscillator through injection locking of the local oscillator by an

undesired RF carrier.

Desired carrier at 80 dBµV, undesired carrier at 90 dBµV at an offset frequency of fd plus 42+fc MHz,

where fd is desired carrier frequency, fc is US chrominance sub carrier and 42 equals 7 channel spacings.

6 All intermodulation specifications are measured with a single-ended input.

7 Operation range is defined as the region over which the oscillator presents a negative impedance.

8 Target to achieve 6 dB minimum S11.

Characteristic Pin Min Typ Max Units Conditions

Charge pump output

current

16 See Table 6.

Vpin16 = 2V

Charge pump output

leakage

16 +3+10 nA Vpin16 = 2V

Charge pump drive

output current

15 0.5 mA Vpin15 = 0.7V

Crystal frequency 17,

4 16 MHz Application as in Figure 6.

Recommended crystal

series resonance

10 200 Ω4 MHz parallel resonant crystal.

External reference input

frequency

17,

4 20 MHz Sinewave coupled through 10nF

blocking capacitor.

External reference drive

level

18 0.2 0.5 Vpp Sinewave coupled through 10nF

blocking capacitor.

Phase detector

comparison frequency

.03125 0.25 MHz

Equivalent phase noise

at phase detector

-158

With 4 MHz crystal, SSB, within loop

bandwidth.

With Fcomp = 125 kHz

RF division ratio 240 32767

Reference division ratio See Table 1.

Switching ports P0-P3

sink current

leakage current

1, 5,

6, 14 10

µA

Vport = 0.7V

Vport = Vcc

Address select

Input high current

Input low current

-0.5

See Table 4.

Vin=Vcc

Vin=Vee

Data Sheet SL2610

Absolute Maximum Ratings

All voltages are referred to Vee at 0V

Characteristic min max units conditions

Supply voltage -0.3 6 V

RF input voltage 117 dBµV Transient condition only.

All I/O port DC offsets -0.3 Vcc+0.3 V

Total port current 20 mA

Storage temperature -55 150 oC

Junction temperature 125 oC Power applied.

Package thermal resistance, chip

to ambient

27 oC/W Package paddle soldered to ground.

Power consumption at 5.25V 1 W

ESD protection 1 kV Mil-std 883B method 3015 cat1

SL2610 Data Sheet

Figure 19 - Input and Output Interface Circuits (RF section)

VCC

50Ω29 IFOP

50Ω

IFOPB

AGCOUT

VCC

1nF

3, 7, 10

External

to Chip

Typical

133-j62Ω

@ 500MHz

(see Figure 10)

LOW, MID, HI, RF Input

20K

AGC Out

CONVOPB

22 CONVOP

100Ω100Ω

VCC

1.38K

95Ω

IFIP

IFIPB

Converter Output

IF Input

IF Output

LOHIOP

33 LOHIOPB

400

Ω

400

Ω

LOHIIP

bias

LOHIPB

500

Ω

LOHI Input & Output

LOLOWOP

LOMIDOP

Vbias

LOLOW and LOMID Outputs

LOLOWOPB

LOMIDOPB

2.4V

VCC

AGCBIAS

AGCBIAS Input

4, 8, 11

IPB

VCC

40K

Data Sheet SL2610

Figure 20 - Input and Output Interface Circuits (PLL section)

200µA

XTALCAP

XTAL

Vccd

220

15 DRIVE

Vccd

PUMP

500K

Vccd

SCL/SDA

ACK

*On SDA only

Vccd

120K

40K

ADD

P0, P1, P2, P3

Reference oscillator

SDA/SCL (pins 19 and 20)

Output Ports (pins 1, 5, 6, 14)

ADD input

Loop amplifier

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