© 2008 Microchip Technology Inc. DS21811E-page 1
MCP6281/1R/2/3/4/5
Features
• Gain Bandwidth Product: 5 MHz (typical)
• Supply Current: IQ = 450 µA (typical)
• Supply Voltage: 2.2V to 6.0V
• Rail-to-Rail Input/Outp ut
• Extended Temperature Range: -40°C to +125°C
• Available in Single, Dual, and Quad Packages
• Single with CS (MCP6283)
• Dual with CS (MCP6285)
Applications
• Automotive
• Portable Equipment
• Photodiode Amplifier
• Analog Filters
• Notebooks and PDAs
• Battery-Powered Systems
Design Aids
• SPICE Macro Models
• FilterLab® Software
• Mindi™ Circui t Designer & Simulator
• MAPS (Microchip Advanced Part Selector)
• Analog Demonstration and Evaluation Boards
• Application Notes
Description
The Microchip Technology Inc. MCP6281/1R/2/3/4/5
family of operat ional amplifi ers (op amps) provide wi de
bandwidth for the current. Th is family has a 5 MHz Gain
Bandwidth Product (GBWP) and a 65° phase margin.
This family also operates from a single supply voltage
as low as 2.2V , while drawing 450 µA (typical) quiescent
current. Additionally, the MCP6281/1R/2/3/4/5 supports
rail-to-rail input and outp ut swing, with a comm on mode
input voltage range of V
DD
+300mV to V
SS
– 300 mV.
This family of operational amplifiers is designed with
Microchip’s advanced CMOS process.
The MCP6285 has a Chip Select (CS) input for dual op
amps in an 8-pin package. This device is manufactured
by cascading the two op amps (the output of op amp A
connected to the non-inverting input of op amp B). The
CS input puts the device in Low-power mode.
The MCP6281/1R/2/3/4/5 family operates over the
Extended Temperature Range of -40°C to +125°C. It
also has a power supply range of 2.2V to 6.0V.
Package Types
VIN_
MCP6281
VDD
1
2
3
4
8
7
6
5
-
+
NC
NC
NC
VIN+
VSS
MCP6282
PDIP, SOIC, MSOP
MCP6284
1
2
3
4
14
13
12
11
-+-
+
10
9
8
5
6
7
+
--
+
PDIP, SOIC, TSSOP
1
2
3
4
8
7
6
5
-
+-
+
VOUT
MCP6283
1
2
3
4
8
7
6
5
-
+
VINA_
VINA+
VSS
VOUTA
VOUTB
VDD
VINB_
VINB+
VSS
VIN+
VIN_
NC CS
VDD
VOUT
NC
VOUTA
VINA_
VINA+
VDD VSS
VOUTB
VINB_
VINB+
VOUTC
VINC_
VINC+
VOUTD
VIND_
VIND+
PDIP, SOIC, MSOP
PDIP, SOIC, MSOP MCP6285
PDIP, SOIC, MSOP
1
2
3
4
8
7
6
5
+-
VINA_
VINA+
VSS
VOUTA/VINB+
VOUTB
VDD
VINB_
CS
-+
MCP6281
SOT-23-5
4
1
2
3-
+
5VDD
VIN–
VOUT
VSS
VIN+
MCP6281R
SOT-23-5
4
1
2
3-
+
5VSS
VIN–
VOUT
VDD
VIN+
MCP6283
SOT-23-6
4
1
2
3-
+
6
5
VSS
VIN+
VOUT CS
VDD
VIN_
450 µA, 5 MHz Rail-to-Rail Op Amp
MCP6281/1R/2/3/4/5
DS21811E-page 2 © 2008 Microchip Technology Inc.
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD –V
SS ........................................................................7.0V
Current at Input Pins ....................................................±2 mA
Analog Inputs (VIN+, VIN–) ††........ VSS –1.0VtoV
DD +1.0V
All Other Inputs and Outputs ......... VSS – 0.3V to VDD +0.3V
Difference Input Voltage ...................................... |VDD –V
SS|
Output Short Circuit Current .................................Continuous
Current at Output and Supply Pins ............................±30 mA
Storage Temperature....................................–65°C to +150°C
Maximum Junction Temperature (TJ)..........................+150°C
ESD Protection On All Pins (HBM; MM).............. ≥ 4 kV; 400V
† Notice: Stresses above those listed under “Absolute
Maximum Ratings” may cause permanent damage to the
device. This is a stress rating only and functional operation of
the device at those or any other conditions above those
indicated in the operational listings of this specification is not
implied. Exposure to maximum rating conditions for extended
periods may affect device reliability.
†† See Section 4.1.2 “Input Voltage and Current Limits”.
DC ELECTRICAL SPECIFICATIONS
Electrical Characteristics: Unless otherwise indicated, TA = +25 C, VDD = +2.2V to +5.5V, VSS =GND, V
OUT ≈VDD/2,
VCM = VDD/2, VL = VDD/2, RL = 10 kΩ to VL and CS is tied low. (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
Input Offset
Input Offset Voltage VOS -3.0 — +3.0 mV VCM = VSS (Note 1)
Input Offset Voltage
(Extended Temperature) VOS -5.0 — +5.0 mV TA= -40°C to +125°C,
VCM = VSS (Note 1)
Input Offset Temperature Drift ΔVOS/ΔTA—±1.7—µV/°CT
A= -40°C to +125°C,
VCM = VSS (Note 1)
Power Supply Rejection Ratio PSRR 70 90 — dB VCM = VSS (Note 1)
Input Bias, Input Offset Current and Impedance
Input Bias Current IB— ±1.0 — pA Note 2
At Temperature IB— 50 200 pA TA= +85°C (Note 2)
At Temperature IB—2 5nAT
A= +125°C (Note 2)
Input Offset Current IOS — ±1.0 — pA Note 3
Common Mode Input Impedance ZCM —10
13||6 — Ω||pF Note 3
Differential Input Impedance ZDIFF —10
13||3 — Ω||pF Note 3
Common Mode (Note 4)
Common Mode Input Range VCMR VSS − 0.3 — VDD + 0.3 V
Common Mode Rejection Ratio CMRR 70 85 — dB VCM = -0.3V to 2.5V, VDD = 5V
Common Mode Rejection Ratio CMRR 65 80 — dB VCM = -0.3V to 5.3V, VDD = 5V
Open-Loop Gain
DC Open-Loop Gain (Large Signal) AOL 90 110 — dB VOUT = 0.2V to VDD – 0.2V,
VCM =V
SS (Note 1)
Output
Maximum Output Voltage Swing VOL, VOH VSS + 15 — VDD – 15 mV 0.5V input overdrive
Output Short Circuit Current ISC —±25—mA
Power Supply
Supply Voltage VDD 2.2 — 6.0 V (Note 5)
Quiescent Current per Amplifier IQ300 450 570 µA IO = 0
Note 1: The MCP6285’s VCM for op amp B (pins VOUTA/VINB+ and VINB–) is VSS + 100 mV.
2: The current at the MCP6285’s VINB– pin is specified by IB only.
3: This specification does not apply to the MCP6285’s VOUTA/VINB+ pin.
4: The MCP6285’s VINB– pin (op amp B) has a common mode range (VCMR) of VSS + 100 mV to VDD – 100 mV.
The MCP6285’s VOUTA/VINB+ pin (op amp B) has a voltage range specified by VOH and VOL.
5: All parts with date codes November 2007 and later have been screened to ensure operation at VDD = 6.0V. However,
the other minimum and maximum specifications are measured at 2.4V and/or 5.5V.
© 2008 Microchip Technology Inc. DS21811E-page 3
MCP6281/1R/2/3/4/5
AC ELECTRICAL SPECIFICATIONS
MCP6283/MCP6285 CHIP SELECT (CS) SPECIFICATIONS
FIGURE 1-1: Timing Diagram for the Chip
Select (CS) pin on the MCP6283 and MCP6285.
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VOUT ≈VDD/2,
VCM = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low. (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
AC Response
Gain Bandwidth Product GBWP — 5.0 — MHz
Phase Margin at Unity-Gain PM — 65 — ° G = +1 V/V
Slew Rate SR — 2.5 — V/µs
Noise
Input Noise Voltage Eni —5.2—µV
P-P f = 0.1 Hz to 10 Hz
Input Noise Voltage Density eni —16—nV/√Hz f = 1 kHz
Input Noise Current Density ini —3—fA/√Hz f = 1 kHz
Electrical Characteristics: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +5.5V, VSS = GND, VOUT ≈VDD/2,
VCM = VDD/2, VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low. (refer to Figure 1-2 and Figure 1-3).
Parameters Sym Min Typ Max Units Conditions
CS Low Specifications
CS Logic Threshold, Low VIL VSS —0.2V
DD V
CS Input Current, Low ICSL —0.01—µACS = VSS
CS High Specifications
CS Logic Threshold, High VIH 0.8 VDD —V
DD V
CS Input Current, High ICSH —0.7 2µACS = VDD
GND Current per Amplifier ISS —-0.7—µACS = VDD
Amplifier Output Leakage — — 0.01 — µA CS = VDD
Dynamic Specifications (Note 1)
CS Low to Valid Amplifier
Output, Turn-on Time tON —410µsCS Low ≤ 0.2 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.9 VDD/2,
VDD = 5.0V
CS High to Amplifier Output High-Z tOFF —0.01— µsCS High ≥ 0.8 VDD, G = +1 V/V,
VIN = VDD/2, VOUT = 0.1 VDD/2
Hysteresis VHYST —0.6—VV
DD = 5V
Note 1: The input condition (VIN) specified applies to both op amp A and B of the MCP6285. The dynamic specification is tested
at the output of op amp B (VOUTB).
VIL
Hi-Z
tON
VIH
CS
tOFF
VOUT
-0.7 µA
Hi-Z
ISS
ICS
0.7 µA 0.7 µA
-0.7 µA
-450 µA
10 nA
(typical)
(typical) (typical) (typical)
(typical)
(typical)
MCP6281/1R/2/3/4/5
DS21811E-page 4 © 2008 Microchip Technology Inc.
TEMPERATURE SPECIFICATIONS
1.1 Test Circuits
The test circuits used for the DC and AC tests are
shown in Figure 1-2 and Figure 1-2. The bypass
capacitors are laid out according to the rules discussed
in Section 4.6 “Supply Bypass”.
FIGURE 1-2: AC and DC Test Circuit for
Most Non-Inverting Gain Conditions.
FIGURE 1-3: AC and DC Test Circuit for
Most Inverting Gain Conditions.
Electrical Characteristics: Unless otherwise indicated, VDD = +2.2V to +5.5V and VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Operating Temperature Range TA-40 — +125 °C Note
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 5L-SOT-23 θJA — 256 — °C/W
Thermal Resistance, 6L-SOT-23 θJA — 230 — °C/W
Thermal Resistance, 8L-PDIP θJA —85—°C/W
Thermal Resistance, 8L-SOIC θJA — 163 — °C/W
Thermal Resistance, 8L-MSOP θJA — 206 — °C/W
Thermal Resistance, 14L-PDIP θJA —70 —°C/W
Thermal Resistance, 14L-SOIC θJA —120 —°C/W
Thermal Resistance, 14L-TSSOP θJA —100 —°C/W
Note: The Junction Temperature (TJ) must not exceed the Absolute Maximum specification of +150°C.
VDD
MCP628X
RGRF
RNVOUT
VIN
VDD/2
1µF
CLRL
VL
0.1 µF
VDD
MCP628X
RGRF
RNVOUT
VDD/2
VIN
1µF
CLRL
VL
0.1 µF
© 2008 Microchip Technology Inc. DS21811E-page 5
MCP6281/1R/2/3/4/5
2.0 TYPICAL PERFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
FIGURE 2-1: Input Offset Voltage.
FIGURE 2-2: Input Bias Curren t at
TA=+85 °C.
FIGURE 2-3: Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 2.2V.
FIGURE 2-4: Input Offset Voltage Drift.
FIGURE 2-5: Input Bias Current at
TA= +125 °C.
FIGURE 2-6: Input Offset Voltage vs.
Common Mode Input Voltage at VDD = 5.5V.
Note: The graphs and tables provided following this note are a statistical summary based on a limited number of
samples and are provide d for informational purposes only. The performance characteristics listed here in
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified pow er supply range) and therefore outside the warranted range.
0%
2%
4%
6%
8%
10%
12%
14%
-2.8
-2.4
-2.0
-1.6
-1.2
-0.8
-0.4
0.0
0.4
0.8
1.2
1.6
2.0
2.4
2.8
Input Offset Voltage (mV)
Percentage of Occurrences
832 Samples
VCM = VSS
0%
5%
10%
15%
20%
25%
0 102030405060708090100
Input Bias Current (pA)
Percentage of Occurrences
210 Samples
TA = +85°C
-100
-50
0
50
100
150
200
250
300
-0.5 0.0 0.5 1.0 1.5 2.0 2.5
Common Mode In put Voltage (V)
Input Offset Voltage (µ V)
VDD = 2.2V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0%
5%
10%
15%
20%
25%
30%
-10-8-6-4-20246810
Input Offset Voltage Drift (µV/°C)
Percentage of Occurrences
832 Samples
VCM = VSS
TA = -40°C to +125°C
0%
5%
10%
15%
20%
25%
30%
35%
0
200
400
800
1200
1600
2000
2400
2800
3200
3600
Input Bias Current (pA)
Percentage of Occurrences
210 Samples
TA = +125°C
-100
-50
0
50
100
150
200
250
300
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
Common Mode Input Voltage (V)
Input Offset Voltage (µV)
VDD = 5.5V
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
MCP6281/1R/2/3/4/5
DS21811E-page 6 © 2008 Microchip Technology Inc.
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
FIGURE 2-7: Input Offset Voltage vs.
Output Voltage.
FIGURE 2-8: CMRR, PSRR vs.
Frequency.
FIGURE 2-9: Input Bias, Offset Currents
vs. Common Mode Input Voltage at TA=+85°C.
FIGURE 2-10: Input Bias, Input Offset
Currents vs. Ambient Temperature.
FIGURE 2-11: CMRR, PSRR vs. Ambient
Temperature.
FIGURE 2-12: Input Bias, Offset Currents
vs. Common Mode Input V olt age at TA= +125°C.
-100
-50
0
50
100
150
200
250
300
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Output Voltage (V)
Input Offset Voltage (µV)
VDD = 2.2V
VCM = VSS
Representative Part
VDD = 5.5V
20
30
40
50
60
70
80
90
100
110
1.E+00 1.E +01 1.E+0 2 1.E+03 1.E +04 1.E+05 1. E+06
Frequency (H z)
CMRR, PSRR (dB)
1 10k 100k 1M10010 1k
PSRR+
PSRR- CMRR
-25
-15
-5
5
15
25
35
45
55
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode Input Voltage (V)
Input Bias, Offset Currents
(pA)
TA = +85°C
VDD = 5.5V
Input Bias Current
Input Offset Current
1
10
100
1,000
10,000
25 35 45 55 65 75 85 95 105 115 125
Ambient Temperature (°C)
Input Bias, Offset Currents
(pA)
Input Bias Current
Input Offset Current
VCM = VDD
VDD = 5.5V
60
70
80
90
100
110
120
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
PSRR, CMRR (dB)
PSRR
VCM = VSS
CMRR
-1.0
-0.5
0.0
0.5
1.0
1.5
2.0
2.5
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Common Mode In put Voltage (V)
Input Bias, Offset Currents
(nA)
TA = +125°C
VDD = 5.5V
Input Bias Current
Input Offset Current
© 2008 Microchip Technology Inc. DS21811E-page 7
MCP6281/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
FIGURE 2-13: Quiescent Current vs.
Power Supply Voltage.
FIGURE 2-14: Open-Loop Gain, Phase vs.
Frequency.
FIGURE 2-15: Maximum Output Voltage
Swing vs. Frequency.
FIGURE 2-16: Output Voltage Headroom
vs. Output Current Magnitude.
FIGURE 2-17: Gain Bandwidth Product,
Phase Margin vs. Ambient Temperature.
FIGURE 2-18: Slew Rate vs. Ambient
Temperature.
0
100
200
300
400
500
600
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
5.
5
Power Supply Voltage (V)
Quiescent Current
(µA/amplifier)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
-20
0
20
40
60
80
100
120
1.E-01
1.E+00
1.E+01
1.E+02
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
1.E+08
Frequency (Hz)
Open-Loop Gain (dB)
-210
-180
-150
-120
-90
-60
-30
0
Open-Loop Phase (°)
Gain
Phase
0.1 1 10 100 1k 10k 100k 1M 10M 100M
0.1
1
10
1.E+03
1.E+04
1.E+05
1.E+06
1.E+07
Frequency (Hz)
Maximum Output Vol tage
Swing (VP-P)
VDD = 2.2V
1k 10k 100k 1M
VDD = 5.5V
10M
1
10
100
1000
0.01 0.1 1 10
Output Current Magnitude (mA)
Ouput Voltage Headroom (mV)
VOL - VSS
VDD - VOH
0
1
2
3
4
5
6
-50-250 255075100125
Ambient Temperature (°C)
Gain Bandwidth Product
(MHz)
60
65
70
75
80
85
90
Phase Margin (°)
Gain Bandwidth Product
VDD = 5.5V
VDD = 2.2V
VDD = 2.2V
VDD = 5.5V
Phase Margin
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
-50 -25 0 25 50 75 100 125
Ambient Temperature (°C)
Slew Rate (V/µs)
Rising Edge, VDD = 2.2V
Rising Edge, VDD = 5.5V
Falling Edge, VDD = 5.5V
Falling Edge, VDD = 2.2V
MCP6281/1R/2/3/4/5
DS21811E-page 8 © 2008 Microchip Technology Inc.
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
FIGURE 2-19: Input Noise Voltage Density
vs. Frequency.
FIGURE 2-20: Output Short Circ uit Current
vs. Power Supply Voltage.
FIGURE 2-21: Quiescent Current vs.
Chip Select (CS) Voltage at VDD = 2.2V
(MCP6283 and MCP6285 only).
FIGURE 2-22: Input Noise Voltage Density
vs. Common Mode Input Voltage at 1 kHz.
FIGURE 2-23: Channel-to-Channel
Separation vs. Frequency (MCP6282 and
MCP6284 only).
FIGURE 2-24: Quiescent Current vs.
Chip Select (CS) Voltage at VDD = 5.5V
(MCP6283 and MCP6285 only).
10
100
1,000
1.E-01 1.E+00 1.E+01 1.E+02 1.E+03 1.E+04 1.E+05 1.E+06
Frequency (Hz)
Input Noise Voltage Density
(nV/√Hz)
0.1 10010 1k 100k10k 1M1
0
5
10
15
20
25
30
35
0.00.51.01.52.02.53.03.54.04.55.05.5
Power Supply Voltage (V)
Ouptut Short Circuit Current
(mA)
TA = +125°C
TA = +85°C
TA = +25°C
TA = -40°C
0
50
100
150
200
250
300
350
400
450
500
0.0 0.2 0.4 0.6 0.8 1.0 1.2 1.4 1.6 1.8 2.0 2.2
Chip Select Voltage (V)
Quiescent Current
(µA/Amplifier)
Hysteresis
Op-Amp shuts off here
Op-Amp turns on here
VDD = 2.2V
CS swept
high to low CS swept
low to high
0
5
10
15
20
25
30
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
Common Mode Input Voltage (V)
Input Noise Voltage Density
(nV/√Hz)
f = 1 kHz
VDD = 5.0V
100
110
120
130
140
1 10 100
Frequency (kHz)
Channel-to-Channel Separation
(dB)
0
100
200
300
400
500
600
700
800
900
1000
0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5
Chip Select V o ltage (V)
Quiescent Current
(µA/Amplifier)
Hysteresis
Op Amp toggles On/Off here
VDD = 5.5V
CS swept
low to high
CS swept
high to low
© 2008 Microchip Technology Inc. DS21811E-page 9
MCP6281/1R/2/3/4/5
TYPICAL PERFORMANCE CURVES (CONTINUED)
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
FIGURE 2-25: Large-Signal, Non-inverting
Pulse Response.
FIGURE 2-26: Small-Signal, Non-inverting
Pulse Response.
FIGURE 2-27: Chip Select (CS) to
Amplifier Output Response Time at VDD = 2.2V
(MCP6283 and MCP6285 only).
FIGURE 2-28: Large-Signal, Inverting
Pulse Response.
FIGURE 2-29: Small-Signal, Inverting
Pulse Response.
FIGURE 2-30: Chip Select (CS) to
Amplifier Output Response Time at VDD = 5.5V
(MCP6283 and MCP6285 only).
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.E+00 2.E-06 4.E-06 6.E-06 8.E-06 1.E-05 1.E-05 1.E-05 2.E-05 2.E-05 2.E-05
Time (2 µs/div)
Output Voltage (V)
G = +1V/V
VDD = 5.0V
Time (500 ns/div)
Output Voltage (10 mV/div)
G = +1V/V
0.0
0.5
1.0
1.5
2.0
2.5
0.0E+00 5.0E-06 1.0E-05 1.5E-05 2.0E-05 2.5E-05 3.0E-05 3.5E-05 4.0E-05 4.5E-05 5.0E-05
Time (5 µs/div)
Chip Select, Output Voltages
(V)
VOUT Output On
Output High-Z
VDD = 2.2V
G = +1V/V
VIN = VSS
CS Voltage
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
0.E+00 2.E-06 4. E-06 6.E- 06 8.E-06 1. E-05 1.E-05 1.E- 05 2.E-05 2. E-05 2.E- 05
Time (2 µs/div)
Output Voltage (V)
G = -1V/V
VDD = 5.0V
Time (500 ns/div)
Output Voltage (10 mV/div)
G = -1V/V
0.0
0.5
1.0
1.5
2.0
2.5
3.0
3.5
4.0
4.5
5.0
5.5
6.0
0.E+00 5.E-06 1.E-05 2.E-05 2.E-05 3.E-05 3.E-05 4.E-05 4.E-05 5.E-05 5.E-05
Time (5 µs/div)
Chip Select, Output Voltages
(V)
VOUT
Output OnOutput High-Z
VDD = 5.5V
G = +1V/V
VIN = VSS
CS Voltage
MCP6281/1R/2/3/4/5
DS21811E-page 10 © 2008 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = +2.2V to +6.0V, VSS = GND, VCM = VDD/2, VOUT ≈VDD/2,
VL = VDD/2, RL = 10 kΩ to VL, CL = 60 pF and CS is tied low.
FIGURE 2-31: Measured Input Current vs.
Input Voltage (below VSS). FIGURE 2-32: The MCP6281/1R/2/3/4/5
Show No Phase Reversal.
1.E-12
1.E-11
1.E-10
1.E-09
1.E-08
1.E-07
1.E-06
1.E-05
1.E-04
1.E-03
1.E-02
-1.0 -0.9 -0.8 -0.7 -0.6 -0.5 -0.4 -0.3 -0.2 -0.1 0.0
Input Voltage (V)
Input Current Magnitude (A)
+125°C
+85°C
+25°C
-40°C
10m
1m
100µ
10µ
1µ
100n
10n
1n
100p
10p
1p
-1
0
1
2
3
4
5
6
-15 -14 -13 -12 -11 -10 -9 -8 -7 -6 -5
Time (1 ms/div)
Input, Output Voltage (V)
VDD = 5.0V
G = +2 V/V
VIN VOUT
© 2008 Microchip Technology Inc. DS21811E-page 11
MCP6281/1R/2/3/4/5
3.0 PIN DESCRIPTIONS
Description s of the pi ns are listed in Table 3-1 (single op amps) and Table 3-2 (d ual and quad op amps).
TABLE 3-1: PIN FUNCTION TABLE FOR SINGLE OP AMPS
TABLE 3-2: PIN FUNCTION TABLE FOR DUAL AND QUAD OP AMPS
3.1 Analog Outputs
The output pins are low-impedance voltage sources.
3.2 Analog Inputs
The non-inverting and inverting inputs are high-
impedance CMOS inputs with low bias currents.
3.3 MCP6285’s VOUTA/VINB+ Pin
For the MCP6285 only, the output of op amp A is
connected directly to the non-inverting input of
op amp B; this is the VOUTA/VINB+ pin. This connection
makes it possible to provide a Chip Select pin for duals
in 8-pin packages.
3.4 Chip Select Digital Input (CS)
This is a CMOS, Schmitt-triggered input that places the
part into a low-power mode of operation.
3.5 Power Supply Pins
The positive power supply (VDD) is 2.2V to 6.0V higher
than the negative power supply (VSS). For normal
operation, the other pins are between VSS and VDD.
Typically, these parts are used in a single (positive)
supply configuration. In this case, VSS is connected to
ground and VDD is connected to the supply. VDD will
need bypass capacitors.
MCP6281 MCP6281R MCP6283 Symbol Description
PDIP, SOIC,
MSOP SOT-23-5 SOT-23-5 PDIP, SOIC,
MSOP SOT-23-6
611 6 1V
OUT Analog Output
244 2 4V
IN– Inver ting Input
333 3 3V
IN+ Non-inverting Input
752 7 6V
DD Positive Power Supply
425 4 2V
SS Negative Power Supply
——— 8 5CS
Chip Select
1,5,8 — — 1,5 — NC No Internal Connection
MCP6282 MCP6284 MCP6285 Symbol Description
PDIP, SOIC, MSOP PDIP, SOIC, TSSOP PDIP, SOIC, MSOP
11—V
OUTA Analog Out pu t (o p amp A)
222V
INA– Inverting Input (op amp A)
333V
INA+ Non-inverting Input (op amp A)
848V
DD Positive Power Supply
55—V
INB+ Non-inverting Input (op amp B)
666V
INB– Inverting Input (op amp B)
777V
OUTB Analog Output (op amp B)
—8—V
OUTC Analog Output (o p amp C)
—9—V
INC– Inverting Input (op amp C)
—10—V
INC+ Non-inverting Input (op amp C)
4114V
SS Negative Power Supply
—12—V
IND+ Non-inverting Input (op amp D)
—13—V
IND– Inverting Input (op amp D)
—14—V
OUTD Analog Output (o p amp D)
—— 1V
OUTA/
VINB+Analog Output (op amp A)/Non-
inverting Input (op amp B)
—— 5CS
Chip Select
MCP6281/1R/2/3/4/5
DS21811E-page 12 © 2008 Microchip Technology Inc.
4.0 APPLICATION INFORMATION
The MCP6281/1R/2/3/4/5 family of op amps is manu-
factured using Microchip's state-of-the-art CMOS
process. This family is specifically designed for low-
cost, low-power and general purpose applications.
The low supply voltage, low quiescent current and
wide bandwidth makes the MCP6281/1R/2/3/4/5 ideal
for battery-powered applications.
4.1 Rail-to-Rail Inputs
4.1.1 PHASE REVERSAL
The MCP6281/1R/2/3/4/5 op amp is designed to
prevent phase reversal when the input pins exceed the
supply voltages. Figure 2-32 shows the input voltage
exceeding the supply voltage without any phase
reversal.
4.1.2 INPUT VOLTAGE AND CURRENT
LIMITS
The ESD protection on the inputs can be depicted as
shown in Figure 4-1. This structure was chosen to
protect the input transistors, and to minimize input bias
current (IB). The input ESD diodes clamp the inputs
when they try to go more than one diode drop below
VSS. They also clamp any voltages that go too far
above VDD; their breakdown voltage is high enough to
allow normal operation, and low enough to bypass
quick ESD events within the specified limits.
FIGURE 4-1: Simplified Analog Input ESD
Structures.
In order to prevent damage and/or improper operation
of these op amps, the circuit they are in must li mit the
currents and voltages at the VIN+ and VIN– pins (see
Absolute Maximum Ratings † at the beginning of
Section 1.0 “Electr ical Characteristics” ). Figure 4-2
shows the recommended approach to protecting these
inputs. The internal ESD diodes prevent the input pins
(VIN+ and VIN–) from going too far below ground, and
the resistors R1 and R2 limit the possible current drawn
out of the input pins. Diodes D1 and D2 prevent the
input pins (VIN+ and VIN–) from going too far above
VDD, and dump any currents onto VDD. When
implemented as shown, resistors R1 and R2 also limit
the current through D1 and D2.
FIGURE 4-2: Protecting the Analog
Inputs.
It is also possible to connect the diodes to the left of
resistors R1 and R2. In this case, current through the
diodes D1 and D2 needs to be limited by some other
mechanism. The resistors then serve as in-rush current
limiters; the DC current into the input pins (VIN+ and
VIN–) should be very small.
A significant amount of current can flow out of the
inputs when the common mode voltage (VCM) is below
ground (VSS); see Figure 2-31. Applications that are
high impedance may need to limit the usable voltage
range.
4.1.3 NORMAL OPERATION
The input stage of the MCP6281/1R/2/3/4/5 op amps
use two differential CMOS input stages in p arallel. One
operates at low common mode input voltage (VCM),
while the other operates at high VCM. WIth this
topology, the device operates with VCM up to 0.3V
above VDD and 0.3V below VSS.
There is a transition in input behavior as VCM is
changed. It occurs when VCM is n ear VDD –1.2V (see
Figure 2-3 and Figure 2-6). For the best distortion
performance with non-inverting gains, avoid these
regions of operation.
Bond
Pad
Bond
Pad
Bond
Pad
VDD
VIN+
VSS
Input
Stage Bond
Pad VIN–
V1
MCP628X
R1
VDD
D1
R1>VSS – (minimum expected V1)
2mA
R2>VSS – (minimum expected V2)
2mA
V2R2
D2
R3
© 2008 Microchip Technology Inc. DS21811E-page 13
MCP6281/1R/2/3/4/5
4.2 Rail-to-Rail Output
The output voltage range of the MCP6281/1R/2/3/4/5
op amp is VDD –15mV (min.) and V
SS +15mV (max.)
when RL=10kΩ is connected to VDD/2 and
VDD = 5.5 V. Refer to Figure 2-16 for more information.
4.3 Capacitive Loads
Driving large capacitive loads can cause stability
problems for voltage feedback op amps. As the load
capacitance increases, the feedback loop’s phase
margin decreases and the closed-loop bandwidth is
reduced. This produce s gain peaking in the frequency
response, with overshoot and ringing in the step
response. A unity-gain buffer (G = +1) is the most
sensitive to capacitive loads, though all gains show the
same general behavior.
When driving large capacitive loads with these op
amps (e.g., > 100 pF when G = +1), a small series
resistor at the output (RISO in Figure 4-3) improves the
feedback loop’s phase margin (stability) by making the
output load resistive at higher frequencies. The
bandwidth will generally be lower than the bandwidth
with no capacitive load.
FIGURE 4-3: Output Resistor, RISO
stabilizes large capacitive loads.
Figure 4-4 gives recommended RISO values for differ-
ent capacitive loads and gains. The x-axis is the
normalized load capacitance (CL/GN), where GN is the
circuit's noise gain. For non-inverting gains, GN and the
Signal Gain are equal. For inverting gains, GN is
1+|Signal Gain| (e.g., -1 V/V gives GN = +2 V/V).
FIGURE 4-4: Recommended RISO Values
for Capacitive Loads.
After selecting RISO for your circuit, double-check the
resulting frequency response peaking and step
response overshoot. Modify RISO's value until the
response is reasonable . Bench evaluation and simula-
tions with the MCP6281/1R/2/3/4/5 SPICE macro
model are helpful.
4.4 MCP628X Chip Select (CS)
The MCP6283 and MCP6285 are single and dual op
amps with Chip Select (CS), respectively. When CS is
pulled high, the supply current drops to 0.7 µA (typical)
and flows through the CS pin to VSS. When this hap-
pens, the amplifier output is put into a high-impedance
state. By pulling CS low, the amplifier is ena bled. The
CS pin has an internal 5 MΩ (typical) pull-down resistor
connected to VSS, so it will go low if the CS pin is left
floating. Figure 1-1 shows the output voltage and
supply current response to a CS pulse.
4.5 Cascaded Dual Op Amps
(MCP6285)
The MCP6285 is a dual op amp with Chip Select (CS).
The Chip Select in put is avai lable on wha t would be the
non-inverting input of a standard dual op amp (pin 5).
This pin is available because the output of op amp A
connects to the non-inverting input of op amp B, as
shown in Figure 4-5. The Chip Sele ct input, which can
be connected to a microcontroller I/O line, puts the
device in Low-power mode. Refer to Section 4.4
“MCP628X Chip Select (CS)”.
FIGURE 4-5: Cascaded Gain Amplifier.
The output of op amp A is loaded by the input imped-
ance of op amp B, which is typically 1013Ω||6pF, as
specified in the DC specification table (Refer to
Section 4.3 “Capacitive Loads” for further details
regarding capacitive loads).
The common mode input range of these op amps is
specified in the data sheet as VSS – 300 mV and
VDD + 300 mV. However, since the output of op amp A
is limited to VOL and VOH (20 mV from the rails with a
10 kΩ load), the non-inverting input range of op amp B
is limited to the common mode input range of
VSS + 20 mV and VDD –20mV.
VIN
RISO VOUT
CL
–
+
MCP628X
10
100
1,000
10 100 1,000 10,000
Normalized Load Capacitance; CL / GN (pF)
Recommended RISO (:)
GN = 1 V/V
GN = 2 V/V
GNt 4 V/V
AB
CS
2
3
5
6
7
VINA+
VOUTB
MCP6285
1
VINA–
VOUTA/VINB+VINB–
MCP6281/1R/2/3/4/5
DS21811E-page 14 © 2008 Microchip Technology Inc.
4.6 Supply Bypass
With this family of operational amplifiers, the power
supply pin (VDD for single-supply) shou ld have a local
bypass capacitor (i.e., 0.01 µF to 0.1 µF) within 2 mm
for good, high-frequency performance. It al so needs a
bulk capacitor (i.e., 1 µF or larger) within 100 mm to
provide large, slow currents. This bulk capacitor can be
shared with nearby analog parts.
4.7 Unused Op Amps
An unused op amp in a quad package (MCP6284)
should be configured as shown in Figure 4-6. These
circuits prevent the output from toggling and causing
crosstalk. Circuits A sets the op amp at its minimum
noise gain. The resistor divider produces any desired
reference voltage within the output voltage range of the
op amp; the op amp buffers that reference voltage.
Circuit B uses the minimum number of components
and operates as a comparator, but it may draw more
current.
FIGURE 4-6: Unused Op Amps.
4.8 PCB Surface Leakage
In applications where low input bias current is critical,
Printed Circuit Board (PCB) surface-leakage effects
need to be considered. Surface leakage is caused by
humidity, dust or other contamination on the board.
Under low humidity conditions, a typical resistance
between nearby traces is 1012Ω. A 5V difference would
cause 5 pA of current to flow, which is greater than the
MCP6281/1R/2/3/4/5 family’s bias current at +25°C
(1 pA, typical).
The easiest way to reduce surface leaka ge is to use a
guard ring around sensitive pins (or traces). The guard
ring is biased at the same voltage as the sensitive pin.
An example of this type of layout is shown in
Figure 4-7.
FIGURE 4-7: Example Guard Ring Layout
for Inverting Gain.
1. For Inverting Gain and Transimpedance
Amplifiers (convert current to voltage, such as
photo detect ors):
a. Connect the guard ring to the non-inverting
input pin (VIN+). This biases th e guard ring
to the same reference voltage as the op
amp (e.g., VDD/2 or ground).
b. Connect the inverting pin (VIN–) to the input
with a wire that does not touch the PCB
surface.
2. Non-inverting Gain and Unity-Gain Buffer:
a. Connect the non-inverting pi n (VIN+) to the
input with a wire that does not touch the
PCB surface.
b. Connect the guard ring to the inverting input
pin (VIN–). This biases the guard ring to the
common mode input voltage.
VDD
VDD
¼ MCP6284 (A) ¼ MCP6284 (B)
R1
R2
VDD
VREF
VREF VDD R2
R1R2
+
------------------
⋅=
Guard Rin g
VSS
VIN–V
IN+
© 2008 Microchip Technology Inc. DS21811E-page 15
MCP6281/1R/2/3/4/5
4.9 Application Circuits
4.9.1 SALLEN-KEY HIGH-PASS FILTER
The MCP6281/1R/2/3/4/5 op amps can be used in
active-filter applications. Figure 4-8 shows a second-
order Sallen-Key high-pass filter with a gain of 1. The
output bias voltage is set by the VDD/2 reference, which
can be changed to any voltage within the output voltage
range.
FIGURE 4-8: Sallen-Key High-Pass Filter.
This filter, and others, can be designed using
Microchip’s Design Aids; see Section 5.2 “FilterLab®
Software” and Section 5.3 “Mindi™ Circuit
Designer & Sim ulator”.
4.9.2 INVERTING MILLER INTEGRATOR
Analog integrators are used in filters, control loops and
measurement circuits. Figure 4-9 shows the most
common implementation, the inverting Miller integrator .
The non-inverting input is at VDD/2 so that the op amp
properly biases up. The switch (SW) is used to zero the
output in some applications. Other applications use a
feedback loop to keep the output within its linear range
of operation.
FIGURE 4-9: Miller Integrator.
4.9.3 CASCADED OP AMP
APPLICATIONS
The MCP6285 provides the flexibility of Low-power
mode for dual op amps in an 8-pin package. The
MCP6285 eliminates the added cost and space in
battery-powered applications by using two single op
amps with Chip Select lines or a 10-pin device with one
Chip Select line for both op amps. Since the two op
amps are internally cascaded, this device cannot be
used in circuits that require active or passive elements
between the two op amps. However, there are several
applications where this op amp configuration with
Chip Select line becomes suitable. The circuits below
show possible applications for this device.
4.9.3.1 Load Isolation
With the cascaded op amp configuration, op amp B can
be used to isolate the load from op amp A. In app lica-
tions where op amp A is driving capacitive or low resis-
tance loads in the feedback loop (such as an integrator
circuit or filter circuit), the op amp may not have
sufficient source current to drive the load. In this case,
op amp B can be used as a buffer.
FIGURE 4-10: Isolatin g th e Lo ad with a
Buffer.
4.9.3.2 Cascaded Gain
Figure 4-11 shows a cascaded gain circuit configura-
tion with Chip Select. Op amps A and B are configured
in a non-inverting amplifier configuration. In this
configuration, it is important to note that the input offset
voltage of op amp A is amplified by the gain of
op amp A and B, as shown below:
Therefore, it is recommended to set most of the gain
with op amp A and use op amp B with relatively small
gain (e.g., a unity-gain buffer).
MCP6281
VOUT
VIN
VDD/2
RC
VOUT
VIN =1
sRC
SW
+
–
AB
MCP6285
CS
VOUTB
Load
VOUT VINGAGBVOSAGAGBVOSBGB
++=
Where:
GA= op amp A gain
GB= op amp B gain
VOSA = op amp A input offset voltage
VOSB = op amp B input offset voltage
MCP6281/1R/2/3/4/5
DS21811E-page 16 © 2008 Microchip Technology Inc.
FIGURE 4-11: Cascaded Gain Circuit
Configuration.
4.9.3.3 Difference Amplifier
Figure 4-12 shows op amp A configured as a difference
amplifier with Chip Select. In this configuration, it is
recommended to use well-matched resistors (e.g.,
0.1%) to increase the Common Mode Rejection Ratio
(CMRR). Op amp B can be used to provide additional
gain and isolate the load from the difference amplifier.
FIGURE 4-12: Difference Amplifier Circuit.
4.9.3.4 Buffered Non-inverting Integrator
Figure 4-13 shows a lossy non-inverting integrator that
is buffered and has a Chip Select input. Op amp A is
configured as a non-inverting integrator. In this config-
uration, matching the impedance at each input is
recommended. RF is used to provide a feedback loop
at frequencies << 1/(2πR1C1) and makes this a lossy
integrat or (it has a fini te gain at DC) . Op amp B is used
to isolate the load from the integrator.
FIGURE 4-13: Buffered Non-inverting
Integrator with Chip Select.
4.9.3.5 Inverting Integrator with Active
Compensation and Chip Select
Figure 4-14 uses an active compensator (op amp B) to
compensate for the non-ideal op amp characteristics
introduced at higher frequencies. This circuit uses
op amp B as a u nity-gain buffer to isolate the integration
capacitor C1 from op amp A and drives the capacitor
with low-impedance source. Since both op amps are
matched very well, they provide a higher quality
integrator.
FIGURE 4-14: Integrator Circuit with Active
Compensation.
4.9.3.6 Second-Order MFB Low-Pass Filter
with an Extra Pole-Zero Pair
Figure 4-15 is a second-order multiple feedback low-
pass filter with Chip Select. Use the FilterLab® software
from Microchip to determine the R and C values for the
op amp A’s second-order filter. Op amp B can be used
to add a pole-zero pair using C3, R6, and R7.
AB
CS
R4R3R2R1
VIN
VOUT
MCP6285
AB
CS
R2R1
VIN2
VIN1 R2
R1
VOUT
R4R3
MCP6285
AB
CS
RF
C1
R2C2
R1
VIN
VOUT
MCP6285
R1C1R2RF
||
()C2
=
A
CS
B
VIN
VOUT
R1C1
MCP6285
© 2008 Microchip Technology Inc. DS21811E-page 17
MCP6281/1R/2/3/4/5
FIGURE 4-15: Second-Order Multiple
Feedback Low-Pass Filter with an Extra
Pole-Zero Pair.
4.9.3.7 Second-Or der Sallen-Key Low-Pass
Filter with an Extra Pole-Zero Pair
Figure 4-16 is a second-order Sallen-Key low-pass
filter with Chip Select. Use the FilterLab® software from
Microchip to determine the R and C values for the op
amp A’s second-order filter. Op amp B can be used to
add a pole-zero pair using C3, R5 and R6.
FIGURE 4-16: Second-Order Sallen-Key
Low-Pass Filter with an Extra Pole-Zero Pair and
Chip Select.
4.9.3.8 Capacitorless Second-Order
Low-Pass filter with Chip Select
The low-pass filter shown in Figure 4-17 does not
require external capacitors and uses only three exter-
nal resistors; the op amp's GBWP sets the corner
frequency. R1 and R2 are used to set the circuit gain
and R3 is used to set the Q. To avoid gain peaking in
the frequency response, Q needs to be low (lower
values need to be selected for R3). Note that the ampli-
fier bandwidth varies greatly over temperature and
process. However, this configuration provides a low-
cost solution for applications with high bandwidth
requirements.
FIGURE 4-17: Capacitorless Second-Or der
Low-Pass Filter with Chip Select.
AB
CS
R1
C1
R5
VIN VOUT
C2R4
R3R2
R6C3
MCP6285
R7
AB
CS
R2
C1
R1
VIN
VOUT
R4R3
C2
C3R5
MCP6285
R6
AB
CS
VREF
VIN
VOUT
R2R1
R3
MCP6285
MCP6281/1R/2/3/4/5
DS21811E-page 18 © 2008 Microchip Technology Inc.
5.0 DESIGN AIDS
Microchip provides the basic design tools needed for
the MCP6281/1R/2/3/4/5 family of op amps.
5.1 SPICE Macro Model
The latest SPICE macro model for the MCP6281/1R/2/
3/4/5 op amps is available on the Microchip web site at
www.microchip.com. This model is intended to be an
initial design tool that works well in the op amp’s linear
region of operation over the temperature range. See
the model file for information on its capabilities.
Bench testing is a very important part of any design and
cannot be replaced with simulations. Also, simulation
results using this macro model need to be validated by
comparing them to the data sheet specifications and
characteristic curves.
5.2 FilterLab® Software
Microchip’s FilterLab® software is an innovative
software tool that simplifies analog active filter (using
op amps) design. Available at no cost from the
Microchip web site at www.microchip.com/filte rlab, the
FilterLab d esign tool provides fu ll schematic diagrams
of the filter circuit with component values. It also
outputs the filter circuit in SPICE format, which can b e
used with the macro model to simulate actual filter
performance.
5.3 Mindi™ Circuit Designer &
Simulator
Microchip’s Mindi™ Circuit Designer & Simulator aids
in the design of various circuits useful for active filter,
amplifier and power-management applications. It is a
free online circuit designer & simulator available from
the Microchip web site at www.microchip.com/mindi.
This interactive circuit designer & simulator enables
designers to quickly generate circuit diagrams, simu-
late circuits. Circuits developed using the Mindi Circuit
Designer & Simulator can be downloaded to a personal
computer or workstation.
5.4 MAPS (Microchip Advanced Part
Selector)
MAPS is a software tool that helps semiconductor
professionals efficiently identify Microchip devices that
fit a particular design requirement. Available at no cost
from the Microchip web site at www.microchip.com/
maps, the MAPS is an overall selection tool for
Microchip’s product portfolio that includes Analog,
Memory, MCUs and DSCs. Using this tool you can
define a filter to sort features for a parametric search of
devices and export side-by-side technical comparison
reports. Helpful links are also provided for Data sheets,
Purchase, and Sampling of Microchip parts.
5.5 Analog Demonstration and
Evaluation Boards
Microchip offers a broad spectrum of Analog Demon-
stration and Evaluation Boards that are designed to
help you achieve faster time to market. For a complete
listing of these boards and their corresponding user ’s
guides and technical information, visit the Microchip
web site at www.microchip.com/analogtools.
Two of our boards that are especially useful are:
•P/N SOIC8EV: 8-Pin SOIC/MSOP/TSSOP/DIP
Evaluation Board
•P/N SOIC14EV: 14-Pin SOIC/TSSOP/DIP
Evaluation Board
5.6 Application Notes
The following Microchip Application Notes are avail-
able on the Microchip web site at www.microchip. com/
appnotes and are recommended a s supplemental ref-
erence resources.
ADN003: “Select the Right Operational Amplifier for
your Filtering Circuits”, DS21821
AN722: “Operational Amplifier Topologies and DC
Specifications”, DS00722
AN723: “Operational Amplifier AC Specifications and
Applications”, DS00723
AN884: “Driving Capacitive Loads With Op Amps”,
DS00884
AN990: “Analog Sensor Conditioning Circuits – An
Overview”, DS00990
These application notes and others are listed in the
design guide:
“Signal Chain Design Guide”, DS21825
© 2008 Microchip Technology Inc. DS21811E-page 19
MCP6281/1R/2/3/4/5
6.0 PACKAGING INFORMATION
6.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
MCP6281
E/P256
0722
8-Lead MSOP
XXXXXX
YWWNNN
6281E
722256
5-Lead SOT-23 (MCP6281 and MCP628 1R)Example:
XXNN CH25
Device Code
MCP6281 CHNN
MCP6281R EUNN
Note: Applies to 5-Lead SOT-23.
6-Lead SOT-23 (MCP6283)Example:
XXNN CL25
Example:
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (las t 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanumeric traceability code
Pb-free JEDEC designator for Matte Tin (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the event the full Microchip part number cannot be marked on one line, it will
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
MCP6281
E/P 256
0722
3
e
OR
MCP6281/1R/2/3/4/5
DS21811E-page 20 © 2008 Microchip Technology Inc.
Package Marking Information (Continued)
14-Lead PDIP (300 mil) (MCP6284) Example:
14-Lead TSSOP (MCP6284) Example:
14-Lead SOIC (150 mil) (MCP6284) Example:
XXXXXXXXXXXXXX
XXXXXXXXXXXXXX
YYWWNNN
XXXXXXXXXX
YYWWNNN
XXXXXX
YYWW
NNN
MCP6284-E/P
0722256
6284EST
0437
256
XXXXXXXXXX MCP6284ESL
0722256
8-Lead SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP6281
E/SN0722
256
MCP6281E
SN 0722
256
OR
3
e
MCP6284
0722256
E/P
3
e
OR
MCP6284
0722256
E/SL^^
OR
3
e
© 2008 Microchip Technology Inc. DS21811E-page 21
MCP6281/1R/2/3/4/5
5-Lead Plastic Small Outl ine Transis tor (OT) [SOT-23]
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mo ld flash or protrusions shall not exceed 0.127 mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 5
Lead Pitch e 0.95 BSC
Outside Lead Pitch e1 1.90 BSC
Overall Height A 0.90 – 1.45
Molded Package Thickness A2 0.89 – 1.30
Standoff A1 0.00 – 0.15
Overall Width E 2.20 – 3.20
Molded Package Width E1 1.30 – 1.80
Overall Length D 2.70 – 3.10
Foot Length L 0.10 – 0 .60
Footprint L1 0.35 – 0.80
Foot Angle φ0° – 30°
Lead Thickness c 0.08 – 0.26
Lead Width b 0.20 – 0.51
φ
N
b
E
E1
D
123
e
e1
A
A1
A2 c
L
L1
Microchip Technology Drawing C04-091B
MCP6281/1R/2/3/4/5
DS21811E-page 22 © 2008 Microchip Technology Inc.
6-Lead Plastic Small Outl ine Transis tor (CH) [SOT-23]
Notes:
1. Dimensions D and E1 do not include mold flash or protrusions. Mo ld flash or protrusions shall not exceed 0.127 mm per side.
2. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 6
Pitch e 0.95 BSC
Outside Lead Pitch e1 1.90 BSC
Overall Height A 0.90 – 1.45
Molded Package Thickness A2 0.89 – 1.30
Standoff A1 0.00 – 0.15
Overall Width E 2.20 – 3.20
Molded Package Width E1 1.30 – 1.80
Overall Length D 2.70 – 3.10
Foot Length L 0.10 – 0 .60
Footprint L1 0.35 – 0.80
Foot Angle φ0° – 30°
Lead Thickness c 0.08 – 0.26
Lead Width b 0.20 – 0.51
b
E
4
N
E1
PIN 1 ID BY
LASER MARK
D
123
e
e1
A
A1
A2 c
L
L1
φ
Microchip Technology Drawing C04-028B
© 2008 Microchip Technology Inc. DS21811E-page 23
MCP6281/1R/2/3/4/5
8-Lead Plastic Micro Small Outline Package (MS) [MSOP]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Ref erence Dimension, usually without tolerance, for inform ation purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 0.65 BSC
Overall Height A – – 1.10
Molded Package Thickness A2 0.75 0.85 0.95
Standoff A1 0.00 – 0.15
Overall Width E 4.90 BSC
Molded Package Width E1 3.00 BSC
Overall Length D 3.00 BSC
Foot Length L 0.40 0.60 0.80
Footprint L1 0.95 REF
Foot Angle φ0° – 8°
Lead Thickness c 0.08 – 0. 23
Lead Width b 0.22 – 0.40
D
N
E
E1
NOTE 1
12
e
b
A
A1
A2
c
L1 L
φ
Microchip Technology Drawing C04-111B
MCP6281/1R/2/3/4/5
DS21811E-page 24 © 2008 Microchip Technology Inc.
8-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e .100 BSC
Top to Seating Plane A – – .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 – –
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .348 .365 .400
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .040 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB – – .430
N
E1
NOTE 1
D
12
3
A
A1
A2
L
b1
b
e
E
eB
c
Microchip Technology Drawing C04-018B
© 2008 Microchip Technology Inc. DS21811E-page 25
MCP6281/1R/2/3/4/5
14-Lead Plastic Dual In-Line (P) – 300 mil Body [PDIP]
Notes:
1. Pin 1 visual index feature may vary, but must be located with the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed .010" per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units INCHES
Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e .100 BSC
Top to Seating Plane A – – .210
Molded Package Thickness A2 .115 .130 .195
Base to Seating Plane A1 .015 – –
Shoulder to Shoulder Width E .290 .310 .325
Molded Package Width E1 .240 .250 .280
Overall Length D .735 .750 .775
Tip to Seating Plane L .115 .130 .150
Lead Thickness c .008 .010 .015
Upper Lead Width b1 .045 .060 .070
Lower Lead Width b .014 .018 .022
Overall Row Spacing § eB – – .430
N
E1
D
NOTE 1
123
E
c
eB
A2
L
A
A1
b1
be
Microchip Technology Drawing C04-005B
MCP6281/1R/2/3/4/5
DS21811E-page 26 © 2008 Microchip Technology Inc.
8-Lead Plastic Small Outline (SN) – Narrow, 3.90 mm Body [SOIC]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Ref erence Dimension, usually without tolerance, for inform ation purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 8
Pitch e 1.27 BSC
Overall Height A – – 1.75
Molded Package Thickness A2 1.25 – –
Standoff §A1 0.10 – 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 4.90 BSC
Chamfer (optional) h 0.25 – 0.50
Foot Length L 0.40 – 1.27
Footprint L1 1.04 REF
Foot Angle φ0° – 8°
Lead Thickness c 0.17 – 0. 25
Lead Width b 0.31 – 0.51
Mold Draft Angle Top α5° – 15°
Mold Draft Angle Bottom β5° – 15°
D
N
e
E
E1
NOTE 1
12 3
b
A
A1
A2
L
L1
c
h
h
φ
β
α
Microchip Technology Drawing C04-057B
© 2008 Microchip Technology Inc. DS21811E-page 27
MCP6281/1R/2/3/4/5
/HDG3ODVWLF6PDOO2XWOLQH61±1DUURZPP%RG\>62,&@
1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW
KWWSZZZPLFURFKLSFRPSDFNDJLQJ
MCP6281/1R/2/3/4/5
DS21811E-page 28 © 2008 Microchip Technology Inc.
14-Lead Plastic Small Outline (SL) – Narrow, 3.90 mm Body [SOIC]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. § Significant Characteristic.
3. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
4. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Ref erence Dimension, usually without tolerance, for inform ation purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e 1.27 BSC
Overall Height A – – 1.75
Molded Package Thickness A2 1.25 – –
Standoff § A1 0.10 – 0.25
Overall Width E 6.00 BSC
Molded Package Width E1 3.90 BSC
Overall Length D 8.65 BSC
Chamfer (optional) h 0.25 – 0.50
Foot Length L 0.40 – 1.27
Footprint L1 1.04 REF
Foot Angle φ0° – 8°
Lead Thickness c 0.17 – 0. 25
Lead Width b 0.31 – 0.51
Mold Draft Angle Top α5° – 15°
Mold Draft Angle Bottom β5° – 15°
NOTE 1
N
D
E
E1
123
b
e
A
A1
A2
L
L1
c
h
hα
β
φ
Microchip Technology Drawing C04-065B
© 2008 Microchip Technology Inc. DS21811E-page 29
MCP6281/1R/2/3/4/5
14-Lead Plastic Thin Shrink Small Outline (ST) – 4.4 mm Body [TSSOP]
Notes:
1. Pin 1 visual index feature may vary, but must be located within the hatched area.
2. Dimensions D and E1 do not include mold flash or protrusions. Mold flash or protrusions shall not exceed 0.15 mm per side.
3. Dimensioning and tolerancing per ASME Y14.5M.
BSC: Basic Dimension. Theoretically exact value shown without tolerances.
REF: Ref erence Dimens ion, usually without tolerance, for information purposes only.
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
Units MILLIMETERS
Dimension Limits MIN NOM MAX
Number of Pins N 14
Pitch e 0.65 BSC
Overall Height A – – 1.20
Molded Package Thickness A2 0.80 1.00 1.05
Standoff A1 0.05 – 0.15
Overall Width E 6.40 BSC
Molded Package Width E1 4.30 4.40 4.50
Molded Package Length D 4.90 5.00 5.10
Foot Length L 0.45 0.60 0.75
Footprint L1 1.00 REF
Foot Angle φ0° – 8°
Lead Thickness c 0.09 – 0. 20
Lead Width b 0.19 – 0.30
NOTE 1
D
N
E
E1
12
e
b
c
A
A1
A2
L1 L
φ
Microchip Technology Drawing C04-087B
MCP6281/1R/2/3/4/5
DS21811E-page 30 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS21811E-page 31
MCP6281/1R/2/3/4/5
APPENDIX A: REVISION HISTORY
Revision E (February 2008)
The following is the list of modificatio ns:
1. Updated notes to Section 1.0 “Electrical Char-
acteristics”.
2. Increased absolute maximum voltage range of
input pins. Increased maximum operating
supply voltage (VDD).
3. Added Section 1.1 “Test Circuits”.
4. Added Figure 2-32.
5. Updated Table 3-1 and Table 3-2 in Section 3.0
“Pin Descriptions”.
6. Added Section 4.1.1 “Phase Reversal”,
Section 4.1.2 “Input Voltage and Current
Limits”, and Section 4.1.3 “Normal Opera-
tion”.
7. Added Section 4.7 “Unused Op Amps”.
8. Updated Section 5.0 “Design AIDS”.
9. Updated package outline drawings in
Section 6.0 “Packaging Information”.
Revision D (December 2004)
The following is the list of modificatio ns:
1. Added SOT-23-5 packages for the MCP6281
and MCP6281R single op amps.
2. Added SOT-23-6 package for the MCP6283
single op amp.
3. Added Section 3.0 “Pin Descriptions”.
4. Corrected application circuits
(Section 4.9 “Application Circuits”).
5. Added SOT-23-5 and SOT-23-6 packages and
corrected package marking information
(Section 6.0 “Packaging Information”).
6. Added Appendix A: Revision History.
Revision C (June 2004)
The following is the list of modificatio ns:
1. Undocumented changes.
Revision B (October 2003)
The following is the list of modificatio ns:
1. Undocumented changes.
Revision A (June 2003)
• Original data sheet release .
MCP6281/1R/2/3/4/5
DS21811E-page 32 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS21811E-page 33
MCP6281/1R/2/3/4/5
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
Device: MCP6281: Single Op Amp
MCP6281T: Single Op Amp
(Tape and Reel)
(SOIC, MSOP, SOT-23-5)
MCP6281RT: Single Op Amp
(Tape and Reel) (SOT-23-5)
MCP6282: Dual Op Amp
MCP6282T: Dual Op Amp
(Tape and Reel) (SOIC, MSOP)
MCP6283: Single Op Amp with CS
MCP6283T: Single Op Amp with CS
(Tape and Reel)
(SOIC, MSOP, SOT-23-6)
MCP6284: Quad Op Amp
MCP6284T: Quad Op Amp
(Tape and Reel) (SOIC, TSSOP)
MCP6285: Dual Op Amp with CS
MCP6285T: Dual Op Amp with CS
(Tape and Reel) (SOIC, MSOP)
Temperature Range: E = -40°C to +125°C
Package: CH = Plastic Small Outline Transistor (SOT-23), 6-lead
(MCP6283 only)
MS = Plastic MSOP, 8-lead
P = Plastic DIP (300 mil body), 8-lead, 14-lead
OT = Plastic Small Outline Transistor (SOT-23), 5-lead
(MCP6281, MCP6281R only)
SL = Plastic SOIC (3.90 mm body), 14-lead
SN = Plastic SOI C , (3.90 mm body), 8-lead
ST = Plastic TSSOP (4.4 mm body), 14-lead
PART NO. X/XX
PackageTemperature
Range
Device
Examples:
a) MCP6281-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6281-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6281-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6281T-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23 package.
e) MCP6281RT-E/OT: Tape and Reel,
Extended Temperature,
5LD SOT-23 package.
a) MCP6282-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6282-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6282-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6282T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
a) MCP6283-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6283-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6283-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6283T-E/CH: Tape and Reel,
Extended Temperature,
6LD SOT-23 package.
a) MCP6284-E/P: Extended Temperature,
14LD PDIP package.
b) MCP6284T-E/SL: Tape and Reel,
Extended Temperature,
14LD SOIC package.
c) MCP6284-E/SL: Extended Temperature,
14LD SOIC package.
d) MCP6284-E/ST: Extended Temperature,
14LD TSSOP package.
a) MCP6285-E/SN: Extended Temperature,
8LD SOIC package.
b) MCP6285-E/MS: Extended Temperature,
8LD MSOP package.
c) MCP6285-E/P: Extended Temperature,
8LD PDIP package.
d) MCP6285T-E/SN: Tape and Reel,
Extended Temperature,
8LD SOIC package.
–
MCP6281/1R/2/3/4/5
DS21811E-page 34 © 2008 Microchip Technology Inc.
NOTES:
© 2008 Microchip Technology Inc. DS21811E-page 35
Information contained in this publication regarding device
applications and the like is provided only for your convenience
and may be superseded by updates. It is your responsibility to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defen d, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, Accuron,
dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro,
PICST ART, PRO MA TE, rfPIC and SmartShunt are registered
trademarks of Microchip Technology Incorporated in the
U.S.A. and other countries.
FilterLab, Linear Active Thermistor, MXDEV, MXLAB,
SEEV AL, SmartSensor and The Embedded Control Solutions
Company are registered trademarks of Microchip Technology
Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONITOR, FanSense, In-Circuit Serial
Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB
Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM,
PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo,
PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total
Endurance, UNI/O, WiperLock and ZENA are trademarks of
Microchip Technology Incorporated in the U.S.A. and other
countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2008, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in their particular Microchip Data Sheet.
• Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Dat a
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of the ir code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digit al Millennium Copyright Act. If such acts
allow unauthorized access to you r software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:200 2 certif ication for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperi pherals, nonvola tile memo ry and
analog product s. In addition, Microchip ’s quality system for the design
and manufacture of development systems is ISO 9001:2000 certified.
DS21811E-page 36 © 2008 Microchip Technology Inc.
AMERICAS
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Tel: 480-792-7200
Fax: 480-792-7277
Technical Support:
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Fax: 86-10-8528-2104
China - Chengdu
Tel: 86-28-8665-5511
Fax: 86-28-8665-7889
China - Hong Kong SAR
Tel: 852-2401-1200
Fax: 852-2401-3431
China - Nanjing
Tel: 86-25-8473-2460
Fax: 86-25-8473-2470
China - Qingdao
Tel: 86-532-8502-7355
Fax: 86-532-8502-7205
China - Shanghai
Tel: 86-21-5407-5533
Fax: 86-21-5407-5066
China - Shenyang
Tel: 86-24-2334-2829
Fax: 86-24-2334-2393
China - Shenzhen
Tel: 86-755-8203-2660
Fax: 86-755-8203-1760
China - Wuhan
Tel: 86-27-5980-5300
Fax: 86-27-5980-5118
China - Xiamen
Tel: 86-592-2388138
Fax: 86-592-2388130
China - Xian
Tel: 86-29-8833-7252
Fax: 86-29-8833-7256
China - Zhuhai
Tel: 86-756-3210040
Fax: 86-756-3210049
ASIA/PACIFIC
India - Bangalore
Tel: 91-80-4182-8400
Fax: 91-80-4182-8422
India - New Delhi
Tel: 91-11-4160-8631
Fax: 91-11-4160-8632
India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-572-9526
Fax: 886-3-572-6459
Taiwan - Kaohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangkok
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Copenhagen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53-63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-144-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08-91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
WORLDWIDE SALES AND SERVICE
01/02/08