LM5005MHX/NOPB - NATIONAL SEMICONDUCTOR

Output Current (A)

Efficiency ()

0 0.5 1 1.5 2 2.5

100

D001

VIN = 12 V

VIN = 24 V

VIN = 36 V

VIN = 48 V

VIN = 60 V

VIN = 75 V

VIN

LM5005

VOUT

AGND

COMP

VIN

SYNC

SD LF

RC1

CC1

CC2

RFB1

RFB2

PGND

VCC

17,18

13,14

3,4

CSS

CIN

COUT

optional

CVCC

IS 15,16

CRAMP

RAMP

CBST

OUT 12

BST 20

PRE 19

optional

SYNC

Product

Folder

Sample &

Buy

Technical

Documents

Tools &

Software

Support &

Community

An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LM5005

SNVS397E –SEPTEMBER 2005–REVISED NOVEMBER 2016

LM5005 75-V, 2.5-A Step-Down Switching Regulator With Wide Input Voltage Range

1 Features

1• High-Efficiency DC-DC Buck Converter

– Wide Input Voltage Range From 7 V to 75 V

– Adjustable Output Voltage as Low as 1.225 V

– Output Current as High as 2.5 A

– Junction Temperature Range –40°C to 125°C

• Integrated 75-V, 160-mΩBuck MOSFET

• Meets EN55022 and CISPR 22 EMI Standards

• ±1.5% Feedback Voltage Accuracy

• Emulated Peak Current-Mode Control

– Ultra-Fast Line and Load Transient Response

• Switching Frequency From 50 kHz to 500 kHz

• Master or Slave Frequency Synchronization Input

• 80-ns Minimum PWM ON Time For Low VOUT

• Monotonic Start-up into Prebiased Output

• Internal High-Voltage VCC Bias Supply Regulator

• Auxiliary Bias Supply Option to VCC

• Configurable Soft Start With Tracking

• Precision Standby and Shutdown Input

– Programmable Input UVLO With Hysteresis

• Remote Shutdown and Standby Control

• Cycle-by-Cycle Overcurrent Protection

• VCC and Gate Drive UVLO Protection

• Thermal Shutdown Protection With Hysteresis

• Thermally-Enhanced 20-Pin HTSSOP Package

2 Applications

• High-Efficiency Point-of-Load Regulators

• Telecommunications Infrastructure

• Factory Automation and Control

SPACER

3 Description

The LM5005 high-voltage buck converter features all

of the functions necessary to implement an efficient

high-voltage switching regulator with a minimum

number of external components. This easy-to-use

converter operates over an input voltage range from

7 V to 75 V and delivers a maximum output current of

2.5 A. The control loop architecture is based upon

current-mode control using an emulated current ramp

for high noise immunity. Current-mode control

provides inherent line feed-forward, cycle-by-cycle

overcurrent protection and straightforward loop

compensation. The use of an emulated control ramp

reduces noise sensitivity of the PWM circuit, allowing

reliable control of small duty cycles necessary in high

input voltage applications.

The switching frequency is resistor-programmable

from 50 kHz to 500 kHz. To reduce EMI, an oscillator

synchronization pin allows multiple LM5005

regulators to self-synchronize or be synchronized to

an external clock signal. Additional protection

features include configurable soft start, external

power supply tracking, thermal shutdown with

automatic recovery, and remote shutdown capability.

The LM5005 is available in an 20-pin HTSSOP

package with an exposed pad that is soldered to the

PCB to achieve a low junction-to-board thermal

impedance. To create a custom regulator design, use

the LM5005 with WEBENCH®Power Designer.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (NOM)

LM5005 HTSSOP (20) 6.50 mm × 4.40 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Application Circuit Typical Efficiency, VOUT =5V

LM5005

SNVS397E –SEPTEMBER 2005–REVISED NOVEMBER 2016

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 5

6.1 Absolute Maximum Ratings ...................................... 5

6.2 ESD Ratings.............................................................. 5

6.3 Recommended Operating Conditions....................... 5

6.4 Thermal Information.................................................. 5

6.5 Electrical Characteristics........................................... 6

6.6 Switching Characteristics.......................................... 7

6.7 Typical Characteristics.............................................. 7

7 Detailed Description.............................................. 9

7.1 Overview................................................................... 9

7.2 Functional Block Diagram......................................... 9

7.3 Feature Description................................................... 9

7.4 Device Functional Modes ....................................... 14

8 Application and Implementation ........................ 15

8.1 Application Information............................................ 15

8.2 Typical Application.................................................. 17

9 Power Supply Recommendations...................... 26

10 Layout................................................................... 26

10.1 Layout Guidelines ................................................. 26

10.2 Layout Example .................................................... 29

11 Device and Documentation Support................. 31

11.1 Third-Party Products Disclaimer ........................... 31

11.2 Device Support .................................................... 31

11.3 Documentation Support ........................................ 31

11.4 Receiving Notification of Documentation Updates 31

11.5 Community Resources.......................................... 32

11.6 Trademarks........................................................... 32

11.7 Electrostatic Discharge Caution............................ 32

11.8 Glossary................................................................ 32

12 Mechanical, Packaging, and Orderable

Information........................................................... 32

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision D (March 2013) to Revision E Page

• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation

section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and

Mechanical, Packaging, and Orderable Information section.................................................................................................. 1

• Deleted Simplified Application Schematic image ................................................................................................................... 1

• Added Typical Application Circuit image................................................................................................................................ 1

• Changed Junction to Ambient, RθJA, value in the Thermal Information table From: 40 To: 35.2........................................... 5

• Changed Junction to Case, RθJC(bot), value in the Thermal Information table From: 4 To: 1.2............................................... 5

• Changed Efficiency vs IOUT and VIN graph.............................................................................................................................. 7

• Deleted RRAMP to VCC for VOUT > 7.5V figure........................................................................................................................ 13

• Added Connection of External Ramp Resistor to VCC when VOUT > 7.5 V figure............................................................. 13

Changes from Revision C (March 2013) to Revision D Page

• Changed layout of National Semiconductor Data Sheet to TI format .................................................................................... 1

1VCC 20 BST

2SD 19 PRE

3VIN 18 SW

4VIN 17 SW

5SYNC 16 IS

6COMP 15 IS

7FB 14 PGND

8RT 13 PGND

9RAMP 12 OUT

10AGND 11 SS

Not to scale

Exposed Pad

LM5005

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5 Pin Configuration and Functions

PWP Package

20-Pin HTSSOP

Top View

(1) G = Ground, I = Input, O = Output, P = Power

Pin Functions

PIN TYPE(1) DESCRIPTION

NO. NAME

1 VCC I Output of the bias regulator. VCC tracks VIN up to 9 V. Beyond 9 V, VCC is regulated to 7 V. A 0.1-µF to

1-µF ceramic decoupling capacitor is required. An external voltage (7.5 V to 14 V) can be applied to this

pin to reduce internal power dissipation.

2 SD I

Shutdown or UVLO input. If the SD pin voltage is below 0.7 V, the regulator is in a low power state. If the

SD pin voltage is between 0.7 V and 1.225 V, the regulator is in standby mode. If the SD pin voltage is

above 1.225 V, the regulator is operational. Use an external voltage divider to set a line undervoltage

shutdown threshold. If the SD pin is left open circuit, a 5-µA pullup current source configures the regulator

as fully operational.

3, 4 VIN P Input supply voltage, nominal operating range: 7 V to 75 V.

5 SYNC I/O Oscillator synchronization input or output. The internal oscillator can be synchronized to an external clock

with an external pulldown device. Multiple LM5005 regulators can be synchronized together by connection

of their SYNC pins.

6 COMP O Output of the internal error amplifier, the loop compensation network must be connected between this pin

and the FB pin.

7 FB I Feedback signal from the regulated output. This pin is connected to the inverting input of the internal error

amplifier. The regulation threshold is 1.225 V.

8 RT I Internal oscillator frequency set input. The internal oscillator is set with a single resistor connected between

RT and AGND pins. The recommended switching frequency range is 50 kHz to 500 kHz.

9 RAMP I Ramp control signal. An external capacitor connected between RAMP and AGND pins sets the ramp slope

used for emulated peak current-mode control. Recommended capacitance range is 50 pF to 2 nF.

10 AGND G Analog ground. Internal reference for the regulator control functions.

11 SS I Soft-start. An external capacitor and an internal 10-µA current source set the ramp rate for the rise of the

error amplifier's reference. The SS pin is held low during standby, VCC UVLO and thermal shutdown.

12 OUT I Output voltage connection. Connect directly to the regulated output voltage.

13, 14 PGND G Power ground. Low-side reference for the integrated PRE switch and the IS current sense resistor.

15, 16 IS P Current sense. Current measurement connection for the freewheeling Schottky diode. An internal sense

resistor and a sample-and-hold circuit sense the diode current near the conclusion of the off-time. This

current measurement provides the DC level of the emulated current ramp.

17, 18 SW P Switching node. The source terminal of the internal buck switch. Connect the SW pin to the external

Schottky diode and to the buck inductor.

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SNVS397E –SEPTEMBER 2005–REVISED NOVEMBER 2016

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Pin Functions (continued)

PIN TYPE(1) DESCRIPTION

NO. NAME

19 PRE P Precharge assist for the bootstrap capacitor. Connect this open-drain output to the SW pins to aid charging

the bootstrap capacitor during light-load conditions or in applications where the output may be precharged

before the LM5005 is enabled. An internal precharge MOSFET is turned on for 250 ns each cycle just prior

to the on-time interval of the buck switch.

20 BST P Boost input for bootstrap capacitor. Connect an external capacitor between the BST and SW pins. A 22-nF

ceramic capacitor is recommended. The capacitor is charged from VCC through an internal bootstrap

diode during the off-time of the buck switch when the SW-node voltage is low.

— EP P Exposed pad. Exposed metal pad on the underside of the device. Connect this pad to the PCB ground

plane to assist with heat spreading.

LM5005

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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings

only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended

Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.

(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/Distributors for availability and

specifications.

6 Specifications

6.1 Absolute Maximum Ratings

Over operating free-air temperature range (unless otherwise noted)(1)(2)

MIN MAX UNIT

VIN to GND 76 V

BST to GND 90 V

PRE to GND 76 V

SW to GND (steady state) –1.5 76 V

BST to VCC 76 V

VCC to GND 14 V

BST to SW 14 V

OUT to GND Limited to VVIN V

SD, SYNC, SS, FB to GND 7 V

Junction temperature, TJ–40 150 °C

Storage temperature, Tstg –65 150 °C

(1) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.

(2) JEDEC document JEP157 states that 250-V CDM allows safe manufacturing with a standard ESD control process.

6.2 ESD Ratings VALUE UNIT

V(ESD) Electrostatic

discharge Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(1) ±2000 V

Charged-device model (CDM), per JEDEC specification JESD22-C101(2) ±750

(1) Recommended Operating Conditions are conditions under which operation of the device is intended to be functional. For ensured

specifications and test conditions, see the Electrical Characteristics.

6.3 Recommended Operating Conditions

Over operating free-air temperature range (unless otherwise noted)(1)

MIN MAX UNIT

VIN Input voltage 7 75 V

IOUT Output current 0 2.5 A

TJOperating junction temperature –40 125 °C

(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application

report.

6.4 Thermal Information

THERMAL METRIC(1) LM5005

UNITPWP (HTSSOP)

20 PINS

RθJA Junction-to-ambient thermal resistance 35.2 °C/W

RθJC(top) Junction-to-case (top) thermal resistance 17.8 °C/W

RθJB Junction-to-board thermal resistance 15.5 °C/W

ψJT Junction-to-top characterization parameter 0.4 °C/W

ψJB Junction-to-board characterization parameter 15.3 °C/W

RθJC(bot) Junction-to-case (bottom) thermal resistance 1.2 °C/W

LM5005

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(1) The junction temperature (TJin °C) is calculated from the ambient temperature (TAin °C) and power dissipation (PDin Watts) as follows:

TJ= TA+ (PD× RθJA) where RθJA (in °C/W) is the package thermal impedance provided in Thermal Information.

(2) Minimum and maximum limits are 100% production tested at 25°C. Limits over the operating temperature range are ensured through

correlation using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

6.5 Electrical Characteristics

Typical values correspond to TJ= 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature

range. VIN = 48 V and RT= 32.4 kΩ(unless otherwise noted).(1)

PARAMETER TEST CONDITIONS MIN(2) TYP MAX(2) UNIT

START-UP REGULATOR

VVCC-REG VCC regulator output 6.85 7.15 7.45 V

VVCC-EXT VCC LDO mode turnoff 9 V

IVCC-CL VCC current limit VVCC = 0 V 20 mA

VCC SUPPLY

VVCC-UV VCC UVLO threshold VVCC increasing 5.95 6.35 6.75 V

VVCC-HYS VCC undervoltage hysteresis 1 V

IVCC Bias current, IIN VFB = 1.3 V 5 mA

ISD Shutdown current, IIN VSD = 0 V 60 100 µA

SHUTDOWN THRESHOLDS

VSD-TH Shutdown threshold 0.5 0.7 0.9 V

VSD-HYS Shutdown hysteresis 0.1 V

VSBY-TH Standby threshold 1.18 1.225 1.27 V

VSBY-HYS Standby hysteresis 0.1 V

ISD SD pullup current source 5 µA

BUCK SWITCH

RDS-ON Buck switch, RDS(on) 160 320 mΩ

VBST-UV BOOST UVLO 3.8 V

VBST-UV-HYS BOOST UVLO hysteresis 0.56 V

RPRE Precharge switch, RDS(on) 75 Ω

CURRENT LIMIT

ICL Cycle-by-cycle current limit RAMP = 0 V 3 3.5 4.25 A

TCL-DLY Cycle-by-cycle current limit delay RAMP = 2.5 V 100 ns

SOFT-START

ISS SS current source 7 10 13 µA

OSCILLATOR

FSW1 Switching frequency 1 180 200 220 kHz

FSW2 Switching frequency 2 RT= 11 kΩ425 485 525 kHz

RSYNC-SRC SYNC source impedance 10 kΩ

RSYNC-SINK SYNC sink impedance 160 Ω

VSYNC-FALL SYNC threshold (falling) 1.4 V

FSYNC-MAX SYNC frequency 550 kHz

TSYNC-MIN SYNC pulse width minimum 15 ns

RAMP GENERATOR

IRAMP1 Ramp current 1 VIN = 60 V, VOUT = 10 V 234 275 316 µA

IRAMP2 Ramp current 2 VIN = 10 V, VOUT = 10 V 20 25 30 µA

PWM COMPARATOR

VCOMP-OFS COMP to PWM comparator offset 0.7 V

RT (k:)

OSCILLATOR FREQUENCY (kHz)

1 10 100 1000

100

1000

TEMPERATURE (oC)

NORMALIZED OSCILLATOR FREQUENCY

-50 -25 0 25 50 75 100 125

0.990

0.995

1.000

1.005

1.010

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Electrical Characteristics (continued)

Typical values correspond to TJ= 25°C. Minimum and maximum limits apply over the –40°C to 125°C junction temperature

range. VIN = 48 V and RT= 32.4 kΩ(unless otherwise noted).(1)

PARAMETER TEST CONDITIONS MIN(2) TYP MAX(2) UNIT

ERROR AMPLIFIER

VFB Feedback voltage VFB = VCOMP 1.207 1.225 1.243 V

IFB-BIAS FB bias current 10 nA

AOL DC gain 70 dB

ICOMP COMP sink and source current 3 mA

FBW Unity gain bandwidth 3 MHz

THERMAL SHUTDOWN

TSD Thermal shutdown threshold 165 °C

TSD-HYS Thermal shutdown hysteresis 25 °C

6.6 Switching Characteristics

Over operating free-air temperature range (unless otherwise noted).

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

TON-MIN Minimum controllable PWM on-time 80 ns

TOFF-MIN Forced PWM off-time 500 ns

TPRE Precharge switch on-time 275 ns

6.7 Typical Characteristics

Unless otherwise specified, VIN = 48 V and VOUT = 5 V (see Typical Application for circuit designs).

Figure 1. Oscillator Frequency vs RT

FOSC = 200 kHz

Figure 2. Oscillator Frequency

vs Temperature

Output Current (A)

Efficiency ()

0 0.5 1 1.5 2 2.5

100

D001

VIN = 12 V

VIN = 24 V

VIN = 36 V

VIN = 48 V

VIN = 60 V

VIN = 75 V

0 2 4 6 8 10

VCC (V)

VIN (V)

Ramp Up

Ramp Down

PHASE (°)

10k 100k 1M 10M 100M

FREQUENCY (Hz)

-30

-20

-10

GAIN (dB)

-135

-90

-45

135

180

225

GAIN

PHASE

TEMPERATURE (oC)

NORMALIZED SOFTSTART CURRENT

-50 -25 0 25 50 75 100 125

0.90

0.95

1.00

1.05

1.10

04 16 20 24

ICC (mA)

VCC (V)

812

LM5005

SNVS397E –SEPTEMBER 2005–REVISED NOVEMBER 2016

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Product Folder Links: LM5005

Typical Characteristics (continued)

Unless otherwise specified, VIN = 48 V and VOUT = 5 V (see Typical Application for circuit designs).

Figure 3. Soft-Start Current vs Temperature

VIN = 12 V

Figure 4. VCC vs ICC

RL= 7 kΩ

Figure 5. VCC vs VIN

AVCL = 101

Figure 6. Error Amplifier Gain and Phase

Figure 7. LM5005 Evaluation Board Efficiency vs IOUT and VIN

VIN

BST

AGND

CLK

PRE

3, 4

5 8 912

13, 14

LM5005

SHUTDOWN

STANDBY

REGULATOR

SYNC

OSCILLATOR

RAMP OUT

PGND

CLK

COMP

ERROR

AMP

20.5k:

CRAMP

330pF

10:

COUT2

22PF

COUT1

150PF

RFB2

1.65k:

RFB1

5.11k:

33 PH

CBST

22nF

CVCC

0.47PF

CSHD6-100C

15, 16

17, 18

THERMAL

SHUTDOWN

UVLO

CLK

DIS

VCC

LEVEL

SHIFT

DRIVER

1.225V

0.7V

RC1

49.9k:

CC1

10nF

CC2

open

RUV2

N/A

CUV

N/A CSS

10nF

CIN2

2.2PF

CIN1

2.2PF

RUV1

N/A

VIN = 7V to 75V VIN

1.75V

PWM

C_LIMIT

10 PA

5 PA

VIN

TRACK

SAMPLE

and

HOLD

0.5V/A

RAMP GENERATOR

IRAMP = 5 PA u (VIN ± VOUT)

+ 25 PA

VOUT = 5V

LM5005

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SNVS397E –SEPTEMBER 2005–REVISED NOVEMBER 2016

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7 Detailed Description

7.1 Overview

The LM5005 high-voltage switching regulator features all of the functions necessary to implement an efficient

high-voltage buck regulator using a minimum of external components. This easy-to-use regulator integrates a

75-V N-channel buck switch with an output current capability of 2.5 A. The regulator control method is based on

current mode control using an emulated current ramp. Peak current mode control provides inherent line feed-

forward, cycle-by-cycle current limiting and simple loop compensation. The use of an emulated control ramp

reduces noise sensitivity of the pulse-width modulation circuit, allowing reliable processing of small duty cycles

necessary in high input voltage applications. The operating frequency is user programmable from 50 kHz to

500 kHz. An oscillator synchronization pin allows multiple LM5005 regulators to self-synchronize or be

synchronized to an external clock. The output voltage can be set at or above 1.225 V. Fault protection features

include cycle-by-cycle current limiting, thermal shutdown and remote shutdown capability. The device is available

in the 20-pin HTSSOP package featuring an exposed pad to aid thermal dissipation.

The LM5005's functional block diagram and typical application are shown in the following section. The LM5005

can be applied in numerous applications to efficiently step down from an unregulated input voltage. The device is

well suited for telecom, industrial, and automotive power bus voltage ranges.

7.2 Functional Block Diagram

7.3 Feature Description

7.3.1 High-Voltage Start-Up Regulator

The LM5005 contains a dual-mode internal high-voltage start-up regulator that provides the VCC bias supply for

the PWM controller and bootstrap MOSFET gate driver. The VIN pins can be connected directly to the input

voltage, as high as 75 V. For input voltages below 9 V, a low dropout switch connects VCC directly to VIN. In this

supply range, VCC is approximately equal to VIN. For input voltages greater than 9 V, the low dropout switch is

disabled and the VCC regulator is enabled to maintain VCC at approximately 7 V. The wide operating range of

7 V to 75 V is achieved through the use of this dual-mode regulator.

TSW

7407

R k 4.3

F kHz

: 

ª º

¬ ¼ ª º

¬ ¼

VIN

VCC

Internal Enable Signal

6.3V

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Feature Description (continued)

The output of the VCC regulator is current limited to 20 mA. Upon power up, the regulator sources current into

the capacitor connected to the VCC pin. When the voltage at the VCC pin exceeds the VCC UVLO threshold of

6.3 V and the SD pin is greater than 1.225 V, a soft-start sequence begins. Switching continues until VCC falls

below 5.3 V or the SD pin falls below 1.125 V.

An auxiliary supply voltage can be applied to the VCC pin to reduce the IC power dissipation. If the auxiliary

voltage is greater than 7.3 V, the internal regulator essentially shuts off, reducing the IC power dissipation. The

VCC regulator series pass transistor includes a diode between VCC and VIN that must not be forward biased in

normal operation. Therefore the auxiliary VCC voltage must never exceed the VIN voltage.

Take extra care in high-voltage applications to ensure the VIN and PRE pin voltages do not exceed their

absolute maximum voltage ratings of 76 V. During line or load transients, voltage ringing on the input bus that

exceeds the Absolute Maximum Ratings can damage the IC. Careful PC board layout and the use of quality

input bypass capacitors placed close to the VIN and PGND pins are essential. See Layout Guidelines for more

detail.

Figure 8. VIN and VCC Sequencing

7.3.2 Shutdown and Standby

The LM5005 contains a dual-level shutdown (SD) circuit. When the SD pin voltage is below 0.7 V, the regulator

is in a low-current shutdown mode. When the SD pin voltage is greater than 0.7 V but less than 1.225 V, the

regulator is in standby mode. In standby mode the VCC regulator is active but MOSFET switching is disabled.

When the SD pin voltage exceeds 1.225 V, switching is enabled and normal operation begins. An internal 5-µA

pullup current source configures the regulator to be fully operational if the SD pin is left open.

An external voltage divider from VIN to GND can be used to set the operational input range of the regulator. The

divider must be designed such that the voltage at the SD pin is greater than 1.225 V when VIN is in the desired

operating range. The internal 5-µA pullup current source must be included in calculations of the external set-point

divider. Hysteresis of 0.1 V is included for both the shutdown and standby thresholds. The voltage at the SD pin

must never exceed 7 V. When using an external divider, it may be necessary to clamp the SD pin to limit its

voltage at high input voltage conditions.

7.3.3 Oscillator and Synchronization Capability

The LM5005 oscillator frequency is set by a single external resistor designated RTconnected between the RT

and AGND pins. Place the RTresistor close to the LM5005's RT and AGND pins. Calculate the resistance of RT

from Equation 1 to set a desired switching frequency, FSW.

(1)

SYNC

10k

DEADTIME

ONE-SHOT

2.5V

I = f (RT)

SYNC

LM5005

Up to Five

Total Devices

LM5005

SYNC

Texas Instruments Incorporated

SYNC

AGND

LM5005

CLK

SYNC

500 ns

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Feature Description (continued)

The SYNC pin can be used to synchronize the internal oscillator to an external clock. The external clock signal

must be of higher frequency than the free-running frequency of the LM5005 set by the RTresistor. A clock circuit

with an open-drain output as shown in Figure 9 is the recommended interface to the SYNC pin. The clock pulse

duration must be greater than 15 ns.

Figure 9. External Clock Synchronization Figure 10. Self-Synchronization of Multiple

LM5005 Regulators

Multiple LM5005 devices can be synchronized together simply by connecting the SYNC pins together. In this

configuration all of the devices are synchronized to the highest frequency device. The diagram in Figure 11

illustrates the SYNC input/output features of the LM5005. The internal oscillator circuit drives the SYNC pin with

a strong pulldown and weak pullup inverter. When the SYNC pin is pulled low either by the internal oscillator or

an external clock, the ramp cycle of the oscillator is terminated and a new oscillator cycle begins. Thus, if the

SYNC pins of several LM5005 IC's are connected together, the IC with the highest internal clock frequency pulls

the connected SYNC pins low first and terminates the oscillator ramp cycles of the other IC’s. The LM5005 with

the highest programmed clock frequency serves as the master and controls the switching frequency of all the

devices with lower oscillator frequency.

Figure 11. Simplified Oscillator Block Diagram and SYNC I/O Circuit

RAMP F

C L 10

 

RAMP IN OUT

I 5$ 9 9 $ ˜  

Sample and

Hold DC Level

0.5V/A

RAMP

TON

tON

CRAMP

(5P x (VIN ± VOUT) + 25P) x

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7.3.4 Error Amplifier and PWM Comparator

The internal high-gain error amplifier generates an error signal proportional to the difference between the

regulated output voltage and an internal precision reference of 1.225 V. The output of the error amplifier is at the

COMP pin, allowing the user to connect loop compensation components, generally a type-II network, from

COMP to FB as illustrated in the Functional Block Diagram. This network creates a pole at unity frequency, a

zero, and a noise-attenuating high-frequency pole. The PWM comparator compares the emulated current sense

signal from the RAMP generator to the error amplifier's output voltage at the COMP pin.

7.3.5 RAMP Generator

The ramp signal used in the pulse width modulator for current-mode control is typically derived directly from the

buck switch current. This switch current corresponds to the positive slope portion of the output inductor current.

Using this signal for the PWM ramp simplifies the control loop transfer function to a single pole response and

provides inherent input voltage feedforward compensation. The disadvantage of using the buck switch current

signal for PWM control is the large leading-edge spike due to circuit parasitics that must be filtered or blanked.

Also, the current measurement may introduce significant propagation delays. The filtering, blanking time and

propagation delay limit the minimum achievable pulse-width. In applications where the input voltage may be

relatively large in comparison to the output voltage, controlling small pulse-widths and duty cycles is necessary

for regulation. The LM5005 uses a unique ramp generator, which does not actually measure the buck switch

current but rather reconstructs the current signal. Reconstructing or emulating the inductor current provides a

ramp signal to the PWM comparator that is free of leading-edge spikes and measurement or filtering delays. The

current reconstruction is comprised of two elements: a sample-and-hold DC level and an emulated current ramp.

Figure 12. Emulated Current-Sense Ramp Waveform

The sample-and-hold DC level illustrated in Figure 12 is derived from a measurement of the current flowing in the

freewheeling Schottky diode. Connect the freewheeling diode's anode terminal to the LM5005's IS pin. The diode

current flows through an internal current sense resistor between the IS and PGND pins. The voltage level across

the sense resistor is sampled and held just prior to the onset of the next conduction interval of the buck switch.

The diode current sensing and sample-and-hold provide the DC level for the reconstructed current signal. The

positive slope inductor current ramp is emulated by an internal voltage-controlled current source and an external

capacitor connected between the RAMP and AGND pins. The ramp current source that emulates the inductor

current is a function of the input and output voltages given by Equation 2.

(2)

Proper selection of the RAMP capacitor depends upon the selected output inductance. Select the capacitance of

CRAMP using Equation 3.

where

• LFis the output inductance in Henrys (3)

LM5005

AGND

VCC

CVCC RRAMP

CRAMP

RAMP

LM5005

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With this value, the scale factor of the emulated current ramp is approximately equal to the scale factor of the DC

level sample-and-hold (0.5 V/A). Place the CRAMP capacitor close to the LM5005's RAMP and AGND pins.

For duty cycles greater than 50%, peak current-mode control circuits are subject to subharmonic oscillation.

Subharmonic oscillation is normally characterized by observing alternating wide and narrow pulses of the switch-

node voltage waveform. Adding a fixed-slope voltage ramp (slope compensation) to the current sense signal

prevents this oscillation. The 25 µA of offset current provided from the emulated current source adds some fixed

slope to the ramp signal. In some high output voltage and high duty cycle applications, additional slope may be

required. In these applications, add a pullup resistor between the VCC and RAMP pins to increase the ramp

slope compensation.

For VOUT > 7.5 V, calculate the optimal slope current with Equation 4.

IOS = VOUT × 5 µA/V (4)

For example, at VOUT = 10 V, IOS = 50 µA.

Install a resistor from the RAMP pin to VCC using Equation 5.

RRAMP = VVCC / (IOS – 25 µA) (5)

Figure 13. Connection of External Ramp Resistor to VCC when VOUT > 7.5 V

7.3.6 Current Limit

The LM5005 contains a unique current monitoring scheme for control and overcurrent protection. When set

correctly, the emulated current sense signal provides a signal that is proportional to the buck switch current with

a scale factor of 0.5 V/A. The emulated ramp signal is applied to the current limit comparator. If the emulated

ramp signal exceeds 1.75 V (3.5 A), the present cycle is terminated (cycle-by-cycle current limiting). In

applications with small output inductance and high input voltage, the switch current may overshoot due to the

propagation delay of the current limit comparator. If an overshoot must occur, the diode current sampling circuit

detects the excess inductor current during the off-time of the buck switch. If the sample-and-hold DC level

exceeds the 1.75-V current limit threshold, the buck switch is disabled and skip pulses until the diode current

sampling circuit detects that the inductor current has decayed below the current limit threshold. This approach

prevents current runaway conditions due to propagation delays or inductor saturation, because the inductor

current is forced to decay following any current overshoot.

7.3.7 Soft-Start Capability

The soft-start feature prevents inrush current impacting the LM5005 regulator and the input supply when power is

first applied. Output voltage soft-start is achieved by slowly ramping up the target regulation voltage when the

device is first enabled or powered up. The internal soft-start current source of 10 µA gradually increases the

voltage of an external soft-start capacitor connected to the SS pin. The soft-start capacitor voltage is connected

to the noninverting input of the error amplifier. Various sequencing and tracking schemes can be implemented

using external circuits that limit or clamp the voltage level of the SS pin.

 

OUT

BOUNDARY F SW

V 1 D

I2 2 L F

˜ 

˜ ˜

LM5005

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In the event a fault is detected, including overtemperature, VCC UVLO or shutdown, the soft-start capacitor is

discharged. When the fault condition is no longer present, a new soft-start sequence commences.

7.3.8 MOSFET Gate Driver

The LM5005 integrates an N-channel high-side MOSFET and associated floating high-voltage gate driver. This

gate driver circuit works in conjunction with an internal bootstrap diode and an external bootstrap capacitor. A

22-nF ceramic capacitor, connected with short traces between the BST and SW pins, is recommended. During

the off time of the buck switch, the SW voltage is approximately –0.5 V and the bootstrap capacitor is charged

from VCC through the internal bootstrap diode. When operating at a high PWM duty cycle, the buck switch is

forced off each cycle for 500 ns to ensure that the bootstrap capacitor is recharged.

Under light-load conditions or when the output voltage is precharged, the SW voltage may not remain low during

the off-time of the buck switch. If the inductor current falls to zero and the SW voltage rises, the bootstrap

capacitor may not have sufficient voltage to operate the buck switch gate driver. For these applications, connect

the PRE pin to the SW pins to precharge the bootstrap capacitor. The internal precharge MOSFET and diode

connected between the PRE and PGND pins turns on each cycle for 250 ns just prior to the onset of a new

switching cycle. If the SW pin is at a normal negative voltage level (continuous conduction mode), then no

current flows through the precharge MOSFET and diode.

7.4 Device Functional Modes

7.4.1 Shutdown Mode

The SD pin provides ON and OFF control for the LM5005. When VSD is below approximately 0.6 V, the device is

in shutdown mode. Both the internal LDO and the switching regulator are off. The quiescent current in shutdown

mode drops to 60 µA at VIN = 48 V. The LM5005 also employs VCC bias rail undervoltage protection. If the VCC

bias supply voltage is below its UV threshold, the regulator remains off.

7.4.2 Standby Mode

The bias supply subregulator has a lower enable threshold than the regulator itself. When VSD is above 0.6 V

and below the standby threshold (1.225 V typically), the VCC supply is on and regulating. Switching action and

output voltage regulation are not enabled until VSD rises above the standby threshold.

7.4.3 Light-Load Operation

The LM5005 maintains high efficiency when operating at light loads. Whenever the load current is reduced to a

level less than half the peak-to-peak inductor ripple current, the device enters discontinuous conduction mode

(DCM). Calculate the critical conduction boundary using Equation 6.

(6)

When the inductor current reaches zero, the SW node becomes high impedance. Resonant ringing occurs at SW

as a result of the LC tank circuit formed by the buck inductor and the parasitic capacitance at the SW node. At

light loads, typically below 100 mA, several pulses may be skipped in between switching cycles, effectively

reducing the switching frequency and further improving light-load efficiency.

7.4.4 Thermal Shutdown Protection

Internal thermal shutdown circuitry is provided to protect the regulator in the event that the maximum junction

temperature is exceeded. When activated, typically at 165°C, the regulator is forced into a low power reset state,

disabling the output driver and the bias regulator. This feature is provided to prevent catastrophic failures from

accidental device overheating.

LM5005 VOUT

SW LF

PGND

COUT

CVCC

CBST

BST

PRE

DVCC

RBST

VCC

LM5005 VOUT

PGND

COUT

CVCC

CBST

BST

PRE

DVCC

RBST

VCC

LM5005

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

8.1.1 Reducing Bias Power Dissipation

The LM5005 is a wide input voltage range buck regulator with a maximum output current of 2.5 A. In general,

buck regulators operating at high input voltage can dissipate a significant amount of bias power. The VCC

regulator must step-down the input voltage to a nominal VCC level of 7 V. A large voltage drop across the VCC

regulator implies a large power dissipation in the LM5005. There are several techniques that can significantly

reduce this bias regulator power dissipation.

Figure 14 and Figure 15 depict two methods to bias the IC from the output voltage. In each case the internal

VCC regulator is used to initially bias the VCC rail. After the output voltage is established, the voltage at VCC is

raised above the nominal 7-V regulation level, which effectively disables the internal VCC regulator. The voltage

applied to the VCC pin must never exceed 14 V. The voltage at the VCC pin must not exceed the input voltage,

VIN.

Figure 14. VCC Bias From the Output Voltage for 8 V < VOUT < 14 V

Figure 15. VCC Bias Using an Additional Winding on the Buck Inductor

UV2 UV1 IN(on) UV1

1.225V

R R V 1.225V 5$ 5

  ˜

IN(off) IN(on)

UV1

1.225V

V V

1.125V

R5$

˜ 

VIN

5A

1.225V

Shutdown/Standby

Comparator

RUV1

RUV2

LM5005

1.125V

LM5005

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Application Information (continued)

Given the increased gate drive capability with a higher VCC voltage, use a resistor RBST of 5 Ωto 10 Ωin series

with the bootstrap capacitor to reduce the turnon speed of the power MOSFET and curtail SW node voltage

overshoot and ringing.

8.1.2 Input Voltage UVLO Protection

The SD input supports adjustable input voltage undervoltage lockout (UVLO) with hysteresis for application

specific power-up and power-down requirements. SD connects to a comparator-based input referenced to a

1.225-V bandgap voltage with 100-mV hysteresis. An external logic signal can be used to drive the SD input to

toggle the output ON and OFF and for system sequencing or protection.

Figure 16. Programmable Input Voltage UVLO With Hysteresis

If the SD pin is not used, it can be left open circuit as it is pulled high by an internal 5-µA current source. This

allows self-start-up of the LM5005 when VCC is within its valid operating range above its UVLO threshold.

However, many applications benefit from using a resistor divider RUV1 and RUV2 as shown in Figure 16 to

establish a precision input voltage UVLO level.

Given VIN(on) and VIN(off) as the input voltage turnon and turnoff thresholds, respectively, select the UVLO

resistors using Equation 7 and Equation 8.

(7)

(8)

An optional capacitor CUV in parallel with RUV2 provides filtering for the divider. If the input UVLO level is set at a

low input voltage, it is possible that the maximum SD pin voltage of 7 V could be exceeded at the higher end of

the input voltage operating range. In this case, use a small 6.2-V Zener diode clamp from SD to AGND such that

the maximum SD operating voltage is never exceeded.

LM5005

VOUT = 5V

AGND

COMP

VIN

SYNC

RC1

CC1

CC2

RFB1

RFB2

PGND

VCC

17,18

13,14

3,4

CSS

CIN1

COUT2

optional

CVCC

IS 15,16

CRAMP

RAMP

CBST

OUT 12

BST 20

PRE 19

RUV1

RUV2 CS

SYNC

CUV

20.5k:

0.47PF

330pF 10nF

2.2PF

10nF 49.9k:

22nF

22PF

33PH

330pF

5.11k:

1.65k:

10:

N/A

VIN = 7V to 75V

COUT1

150PF

N/A

CIN2

16V

6.3V

CDSH6-100C

100V

LM5005

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8.2 Typical Application

The following design procedure assists with component selection for the LM5005. Alternately, the WEBENCH®

Design Tool is available to generate a complete design. With access to a comprehensive component database,

this online tool uses an iterative design procedure to create an optimized design, allowing the user to experiment

with various design options.

The schematic diagram of a 5-V, 2.5-A regulator with an input voltage range is 7 V to 75 V is given in Figure 17.

The free-running switching frequency (with the SYNC pin open circuit) is 300 kHz. In terms of control loop

performance, the target loop crossover frequency is 20 kHz with a phase margin in excess of 55°.

Figure 17. LM5005 Circuit Schematic

8.2.1 Design Requirements

An example of the step-by-step procedure to generate power stage and compensation component values using

the typical application setup of Figure 17 is given below.

The circuit shown in Figure 17 is configured for the following specifications:

• VIN =7Vto75V

• VOUT =5V

• IOUT(max) = 2.5 A

• FSW = 300 kHz

• Minimum load current for CCM = 250 mA

• Line and load regulation less than 1% and 0.1%, respectively

The Bill of Materials for this design is listed in Table 1.

8.2.2 Detailed Design Procedure

8.2.2.1 Frequency Set Resistor (RT)

Resistor RTsets the switching frequency. Generally, higher frequency applications are smaller but have higher

losses. A switching frequency of 300 kHz is selected in this example as a reasonable compromise for small

solution size and high efficiency. Calculate the resistance of RTfor a 300-kHz switching frequency with

Equation 9.

RAMP F

C pF 10 L + ˜

ª º ª º

¬ ¼ ¬ ¼

 

OUT IN(max) OUT

FL SW IN(max)

V V V 5V 75V 5V

L 31+

I F V 0.5A 300kHz 75V

˜  ˜ 

' ˜ ˜ ˜ ˜

IPEAK

Inductor Current

0 A

IVALLEY

IOUT

SSW

TSW

7407

R k 4.3

F kHz

: 

ª º

¬ ¼ ª º

¬ ¼

LM5005

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Typical Application (continued)

(9)

Choose the nearest standard resistor value of 20.5 kΩfor RT.

8.2.2.2 Inductor (LF)

The inductance is determined based on the switching frequency, load current, inductor ripple current, and the

minimum and maximum input voltages designated VIN(min) and VIN(max), respectively.

Figure 18. Inductor Current Waveform

To keep the converter operating in CCM, the maximum inductor ripple current ΔILmust be less than twice the

minimum load current, or 0.5-A peak-to-peak. Using this value of ripple current, calculate the inductance using

Equation 10.

(10)

Use the nearest standard value of 33 µH. An alternative method is to choose an inductance that gives an

inductor ripple current of 30% to 50% of the rated full load current at the nominal input voltage.

Note that the inductor must be rated for the peak inductor current, denoted as IPEAK in Figure 18, to prevent

saturation. During normal loading conditions, the peak inductor current corresponds to maximum load current

plus half the maximum peak-to-peak ripple current. The peak inductor current during an overload condition is

limited to 3.5 A nominal (4.25 A maximum). The selected inductor in this design example (see Table 1) has a

conservative 6.2-A saturation current rating. The saturation current is defined by this inductor manufacturer as

the current required for the inductance to reduce by 30% at 20°C.

8.2.2.3 Ramp Capacitor (CRAMP)

With the inductor selected, calculate the value of CRAMP necessary for the emulation ramp circuit using

Equation 11.

(11)

With LFselected as 33 µH, the recommended CRAMP is 330 pF. Use a capacitor with NP0 or C0G dielectric.

8.2.2.4 Output Capacitors (COUT)

The output capacitor filters the inductor ripple current and provides a source of charge for transient load

conditions. A wide range of output capacitors may be used with the LM5005 that provide various advantages.

The best performance is typically obtained using ceramic or polymer electrolytic type components. Typical trade-

offs are that the ceramic capacitor provides extremely low ESR to reduce the output ripple voltage and noise

spikes, while electrolytic capacitors provide a large bulk capacitance in a small volume for transient loading

conditions.

When selecting an output capacitor, the two performance characteristics to consider are the output voltage ripple

and load transient response. Approximate the output voltage ripple with Equation 12.

 

F OUT STEP

DROOP OUT STEP ESR OUT IN OUT

L I

V I R C V V



˜ '

' ˜  ˜ 

OUT L ESR SW OUT

V I R 8 F C

§ ·

' '  ¨ ¸

˜ ˜

LM5005

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Typical Application (continued)

where

•ΔVOUT is the peak-to-peak output voltage ripple

• RESR is the effective series resistance (ESR) of the output capacitor

• FSW is the switching frequency

• COUT is the effective output capacitance (12)

The amount of output voltage ripple is application specific. A general recommendation is to keep the output ripple

less than 1% of the rated output voltage.

Bear in mind that ceramic capacitors are sometimes preferred because they have low ESR. However, depending

on package and voltage rating of the capacitor, the effective in-circuit capacitance can drop significantly with

applied voltage. The output capacitor selection also affects the output voltage droop during a load transient. The

peak deviation of the output voltage during a load transient is dependent on many factors. An approximation of

the transient dip ignoring loop bandwidth is obtained using Equation 13:

where

• COUT is the minimum required output capacitance

• LFis the buck filter inductance

• VDROOP is the output voltage deviation ignoring loop bandwidth considerations

•ΔIOUT-STEP is the load step change

• RESR is the output capacitor ESR

• VIN is the input voltage

• VOUT is the output voltage setpoint (13)

A 22-µF, 16-V ceramic capacitor with X7R dielectric and 1210 footprint and a 150-µF, 6.3-V polymer electrolytic

capacitor are selected here based on a review of each capacitor's tolerance and voltage coefficient to meet

output ripple specification. The ceramic capacitor provides ultra-low ESR to reduce the output ripple voltage and

noise spikes, while the electrolytic capacitor provides a large bulk capacitance in a small volume for transient

loading conditions.

8.2.2.5 Schottky Diode (DF)

A Schottky type freewheeling diode is required for all LM5005 applications. Select the diode's reverse breakdown

rating for the maximum VIN plus some safety margin. Ultra-fast diodes are not recommended and may result in

damage to the regulator due to reverse recovery current transients. The near ideal reverse recovery

characteristics and low forward voltage drop of a Schottky diode are particularly important diode characteristics

for high input voltage and low output voltage applications common to the LM5005.

The reverse recovery characteristic determines how long the current surge lasts each cycle when the buck

switch is turned on. The benign reverse recovery characteristics of a Schottky diode minimizes the peak

instantaneous power in the buck switch occurring during turnon each cycle, and the resulting switching losses of

the buck switch are significantly reduced.

The diode's forward voltage drop has a significant impact on the conversion efficiency, especially for applications

with a low output voltage. Rated current for diodes vary widely from various manufactures. The worst case is to

assume a short-circuit load condition. In this case the diode conducts the output current almost continuously. For

the LM5005 this current can be as high as 3.5 A. Assuming a worst-case 1-V drop across the diode, the

maximum diode power dissipation can be as high as 3.5 W. For this design example, a 100-V, 6-A Schottky in a

DPAK package is selected.

OUT

FB1 FB2

V 1.225V

R R

1.225V



SS SS

C nF 8.16 t ms ˜

ª º ª º

¬ ¼ ¬ ¼

SS SS SS

SS REF

t I t 10$

CV 1.225V

˜ ˜

LM5005

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Typical Application (continued)

8.2.2.6 Input Capacitors (CIN)

The regulator supply voltage has a large source impedance at the switching frequency. Good quality input

capacitors are necessary to limit the ripple voltage at the VIN pin while supplying most of the switch current

during the on-time. When the buck switch turns on, the current into the VIN pins steps to the lower peak of the

inductor current waveform, ramps up to the peak value, then drops to zero at turnoff. The average current into

VIN during the on-time is the load current. The input capacitance must be selected for RMS current rating and

minimum ripple voltage. A good approximation for the required ripple current rating necessary is IRMS > IOUT / 2.

Select ceramic capacitors with a low ESR for the input filter. To allow for capacitor tolerances and voltage

derating effects, two 2.2-µF, 100-V ceramic capacitors are used. If step input voltage transients are expected

near the maximum rating of the LM5005, a careful evaluation of ringing and possible spikes at the VIN pin id

required. An additional damping network, snubber circuit or input voltage clamp may be required in these cases.

8.2.2.7 VCC Capacitor (CVCC)

The capacitor at the VCC pin provides noise filtering and stability for the VCC regulator. The recommended value

of CVCC is 0.47 µF and must be a low-ESR ceramic capacitor of X7R dielectric rated for at least 16 V.

8.2.2.8 Bootstrap Capacitor (CBST)

The bootstrap capacitor connected between the BST and SW pins supplies the gate current to charge the buck

switch gate at turnon. The recommended value of CBST is 22 nF. Choose a low ESR ceramic capacitor with X7R

dielectric rated for at least 16 V.

8.2.2.9 Soft Start Capacitor (CSS)

The capacitor connected to the SS pin determines the soft-start time, or the time for the reference voltage and

the output voltage to reach their final regulated values. If tSS is the required soft-start time, calculate the soft-start

capacitance using Equation 14 or more simply with Equation 15.

(14)

(15)

Choose a CSS of 10 nF corresponding to a soft-start time of 1.2 ms for this application.

8.2.2.10 Feedback Resistors (RFB1 and RFB2)

Resistors RFB1 and RFB2 establish the output voltage setpoint. Based on a selected value for the lower feedback

resistor RFB2, calculate the upper feedback resistor RFB1 from Equation 16.

(16)

In general, a good starting point for RFB2 is in the range of 1 kΩto 10 kΩ. Resistances of 5.11 kΩand 1.65 kΩ

are selected for RFB1 and RFB2 (respectively) to achieve a 5-V output setpoint for this design example.

8.2.2.11 RC Snubber (RSand CS)

A snubber network across the power diode reduces ringing and spikes at the switching node. Excessive ringing

and spikes can cause erratic operation and couple spikes and noise to the output. Ultimately, excessive spikes

beyond the rating of the LM5005 or the freewheeling diode can damage these devices. Selecting the values for

the snubber is best accomplished through empirical methods. First, make sure the lead lengths for the snubber

connections are short. For the current levels typical of the LM5005 converter, a snubber resistance RSbetween

2Ωand 10 Ωis adequate. Increasing the value of the snubber capacitor results in more damping but higher

losses. Select a minimum value of CSthat provides adequate damping of the SW voltage waveform at full load

(see PCB Layout for EMI Reduction for more details).

REF LEVEL

0.000 dB

0.0 deg

100 1k

START 50.000 Hz 10k

STOP 50 000.000 Hz

/DIV

10.000 dB

45.000 deg

GAIN

PHASE

p(MOD) LOAD OUT

f2 R C

˜ ˜

MOD-DC m(MOD) LOAD LOAD

GAIN G R 2 R ˜ ˜

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Typical Application (continued)

8.2.2.12 Compensation Components (RC1, CC1, CC2)

These components configure the error amplifier gain characteristics to accomplish a stable overall loop gain. One

advantage of current-mode control is the ability to close the loop with only two feedback components, RC1 and

CC1. The overall loop gain is the product of the modulator gain and the error amplifier gain. The DC modulator

gain of the LM5005 is calculated with Equation 17.

(17)

The dominant low-frequency pole of the modulator is determined by the load resistance, RLOAD, and the output

capacitance, COUT. Calculate the corner frequency of this pole with Equation 18.

(18)

For RLOAD = 5 Ωand COUT = 177 µF, then fp(MOD) = 180 Hz

GAINMOD-DC = 2 A/V × 5 Ω= 10 = 20 dB

For this design example given RLOAD = 5 Ωand COUT = 177 µF, Figure 19 shows the experimentally measured

modulator gain versus frequency characteristic.

Figure 19. PWM Modulator Gain and Phase Plot

Components RC1 and CC1 configure the error amplifier as a Type-II configuration, giving a pole at the origin and a

zero at fZ=1/(2πRC1 CC1). The error amplifier zero cancels the modulator pole leaving a single pole response

at the crossover frequency of the loop gain. A single pole response at the crossover frequency yields a stable

loop with 90° of phase margin.

For the design example, select a target loop bandwidth (crossover frequency) of 20 kHz. Place the compensator

zero frequency, fZ, an order of magnitude less than the target crossover frequency. This constrains the product of

RC1 and CC1 for a desired compensation network zero frequency to be less than 2 kHz. Increasing RC1 while

proportionally decreasing CC1 increases the error amp gain. Conversely, decreasing RC1 while proportionally

increasing CC1, decreases the error amp gain. Select RC1 of 49.9 kΩand CC1 of 10 nF. These values configure

the compensation network zero at 320 Hz. The compensator gain at frequencies greater than fZis RC1 / RFB1,

which is approximately 20 dB.

REF LEVEL

0.000 dB

0.0 deg

100 1k

START 50.000 Hz 10k

STOP 50 000.000 Hz

/DIV

10.000 dB

45.000 deg

GAIN

PHASE

REF LEVEL

0.000 dB

0.0 deg

100 1k

START 50.000 Hz 10k

STOP 50 000.000 Hz

/DIV

10.000 dB

45.000 deg

GAIN

PHASE

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Typical Application (continued)

The compensator's bode plot is shown by Figure 20. The overall loop is predicted as the sum (in dB) of the

modulator gain and the compensator gain as shown in Figure 21.

Figure 20. Compensator Gain and Phase Plot Figure 21. Overall Loop Gain and Phase Plot

If a network analyzer is available, measure the modulator gain and configure the compensator gain for the

desired loop transfer function. If a network analyzer is not available, design the error amplifier's compensation

components using the guidelines provided. Perform step-load transient tests to verify acceptable performance.

The step load goal is minimum overshoot with a damped response. Add a capacitor CC2 to the compensation

network to decrease noise susceptibility of the error amplifier. The value of CC2 must be sufficiently small,

because the addition of this capacitor adds a pole in the compensator transfer function. This pole must be well

beyond the loop crossover frequency. A good approximation of the location of the pole added by CC2 is

Equation 19.

fp2 = fZ× CC1 / CC2 (19)

An alternative method to decrease the error amplifier noise susceptibility is to connect a capacitor from COMP to

AGND. When using this method, the capacitance of CC2 must not exceed 100 pF.

2 Ps/DIV

VOUT 10 mV/DIV

Output Current (A)

Efficiency ()

0 0.5 1 1.5 2 2.5

100

D001

VIN = 12 V

VIN = 24 V

VIN = 36 V

VIN = 48 V

VIN = 60 V

VIN = 75 V

LM5005

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(1) See Third-Party Products Disclaimer.

8.2.2.13 Bill of Materials

Table 1 lists the bill of materials for the design example.

Table 1. LM5005 Buck Regulator Bill of Materials(1), VOUT =5V,IOUT = 2.5 A

REF DES DESCRIPTION VENDOR PART NUMBER QUANTITY

CIN1, CIN2 CAPACITOR, CER, 2.2 µF, 100 V, X7R, 1210 TDK C3225X7R2A225M 2

COUT1 CAPACITOR, SP, 150 µF, 6.3 V, 12 mΩPanasonic EEFHE0J151R 1

COUT2 CAPACITOR, CER, 22 µF, 16 V, X7R, 1210 TDK C3225X7R1C226M 1

CSCAPACITOR, CER, 330 pF, 100 V, 0603 Kemet C0603C331G1GAC 1

CC1, CSS CAPACITOR, CER, 10 nF, 100 V, 0603 TDK C1608X7R2A103K 2

CBST CAPACITOR, CER, 22 nF, 100 V, 0603 TDK C1608X7R2A223K 1

CVCC CAPACITOR, CER, 0.47 µF, 16 V, 0604 TDK C1608X7R1C474M 1

CRAMP CAPACITOR, CER, 330 pF, 100 V, 0603 Kemet C0603C331G1GAC 1

DFDIODE, 100 V, 6 A, Schottky, DPAK Central Semi CSHD6-100C 1

DIODE, 100 V, 6 A, Schottky (alternative) IR 6CWQ10FN

LFINDUCTOR, 33 µH, ISAT 6.22 A, DCR 60 mΩCoiltronics/Eaton DR127-330-R 1

RTRESISTOR, 20.5 kΩ, 0603 Vishay Dale CRCW06032052F 1

RC1 RESISTOR, 49.9 kΩ, 0603 Vishay Dale CRCW06034992F 1

RFB1 RESISTOR, 5.11 kΩ, 0603 Vishay Dale CRCW06035111F 1

RFB2 RESISTOR, 1.65 kΩ, 0603 Vishay Dale CRCW06031651F 1

RSRESISTOR, 10 Ω, 1 W, 1206 Vishay Dale CRCW1206100J 1

U1Wide VIN Regulator, 75 V, 2.5 A Texas Instruments LM5005 1

8.2.3 Application Curves

Converter efficiency and performance waveforms are shown from Figure 22 to Figure 32. Unless indicated

otherwise, all waveforms are taken at VIN = 48 V.

Figure 22. Typical Efficiency vs Input Voltage

and Output Current, 5-V Output Figure 23. Output Voltage Ripple, 2.5-A Load

1 ms/DIV

IOUT 1 A/DIV

VOUT 1 V/DIV

VIN 10 V/DIV

1 ms/DIV

VOUT 1 V/DIV

VSD 1 V/DIV

1 ms/DIV

IOUT 1 A/DIV

VOUT 1 V/DIV

VSD 1 V/DIV

1 ms/DIV

IOUT 1 A/DIV

VOUT 1 V/DIV

VSD 1 V/DIV

1 Ps/DIV

VSW 10 V/DIV

1 Ps/DIV

VSW 10 V/DIV

LM5005

SNVS397E –SEPTEMBER 2005–REVISED NOVEMBER 2016

www.ti.com

Product Folder Links: LM5005

Figure 24. SW Node Voltage, 2.5-A Load Figure 25. SW Node Voltage, 0.1-A Load

Figure 26. Start-Up Using SD Pin, 2.5-A Resistive Load Figure 27. Shutdown Using SD Pin, 2.5-A Resistive Load

Figure 28. Start-Up Using SD Pin, Pre-biased Output Figure 29. Start-Up by Applying VIN, 2.5-A Resistive Load

1 Ps/DIV

VSW 10 V/DIV

VSYNC 1 V/DIV

20 ms/DIV

IOUT 1 A/DIV

VOUT 20 mV/DIV

VIN 10 V/DIV

1 ms/DIV

IOUT 1 A/DIV

VOUT 100 mV/DIV

1 ms/DIV

VOUT 100 mV/DIV

IOUT 1 A/DIV

LM5005

www.ti.com

SNVS397E –SEPTEMBER 2005–REVISED NOVEMBER 2016

Product Folder Links: LM5005

Figure 30. Load Transient Response, 0.1-A to 2.5-A Load Figure 31. Load Transient Response, 1.25-A to 2.5-A Load

Figure 32. Line Transient, 12 V to 60 V, 2.5-A Load Figure 33. SYNC IN Operation at 350 kHz

K˜

OUTOUT

IN VIV

LM5005

SNVS397E –SEPTEMBER 2005–REVISED NOVEMBER 2016

www.ti.com

Product Folder Links: LM5005

9 Power Supply Recommendations

The LM5005 converter is designed to operate from a wide input voltage range from 7 V to 75 V. The

characteristics of the input supply must be compatible with the Absolute Maximum Ratings and Recommended

Operating Conditions. In addition, the input supply must be capable of delivering the required input current to the

fully-loaded regulator. Estimate the average input current with Equation 20.

where

•ηis the efficiency (20)

If the converter is connected to an input supply through long wires or PCB traces with large impedance, special

care is required to achieve stable performance. The parasitic inductance and resistance of the input cables may

have an adverse affect on converter operation. The parasitic inductance in combination with the low ESR

ceramic input capacitors form an underdamped resonant circuit. This circuit can cause overvoltage transients at

VIN each time the input supply is cycled ON and OFF. The parasitic resistance causes the input voltage to dip

during a load transient. If the regulator is operating close to the minimum input voltage, this dip can cause false

UVLO fault triggering and a system reset. The best way to solve such issues is to reduce the distance from the

input supply to the regulator and use an aluminum or tantalum input capacitor in parallel with the ceramics. The

moderate ESR of the electrolytic capacitors helps to damp the input resonant circuit and reduce any voltage

overshoots. A capacitance in the range of 10 µF to 47 µF is usually sufficient to provide input damping and helps

to hold the input voltage steady during large load transients.

An EMI input filter is often used in front of the regulator that, unless carefully designed, can lead to instability as

well as some of the effects mentioned above. The user's guide Simple Success with Conducted EMI for DC-DC

Converters (SNVA489) provides helpful suggestions when designing an input filter for any switching regulator.

10 Layout

10.1 Layout Guidelines

PC board layout is an important and critical part of any DC-DC converter design. The performance of any

switching converter depends as much upon the layout of the PCB as the component selection. Poor layout

disrupts the performance of a switching converter and surrounding circuitry by contributing to EMI, ground

bounce, conduction loss in the traces, and thermal problems. Erroneous signals can reach the DC-DC converter,

possibly resulting in poor regulation or instability. There are several paths that conduct high slew-rate currents or

voltages that can interact with stray inductance or parasitic capacitance to generate noise and EMI or degrade

the power-supply performance.

The following guidelines serve to help users to design a PCB with the best power conversion performance,

thermal performance, and minimized generation of unwanted EMI.

1. In a buck regulator there are two critical current conduction loops. The first loop starts from the input

capacitors to the LM5005's VIN pins, to the SW pin, to the inductor and then out to the load. The second

loop starts from the output capacitors' return terminals, to the LM5005's PGND pins, to the IS pins, to the

freewheeling diode's anode, to the inductor and then out to the load. Minimizing the effective area of these

two loops reduces the stray inductance and minimizes noise and possible erratic operation.

2. Place the input capacitors close to the LM5005's VIN pins and exposed pad that is connected to PGND pins.

Place the inductor as close as possible to the SW pins and output capacitors. As described further in PCB

Layout for EMI Reduction, this placement serves to minimize the area of switching current loops and reduce

the resistive loss of the high current path. Ideally, use a ground plane on the top layer that connects the

PGND pins, the exposed pad of the device, and the return terminals of the input and output capacitors. For

more details, see the board layout detailed in LM5005 EVM user's guide AN-1748 LM5005 Evaluation Board

(SNVA298).

3. Minimize the copper area of the switch node. Route the two SW pins on a single top-layer plane to the

inductor terminal using a wide trace to minimize conduction loss. The inductor can be placed on the bottom

side of the PCB relative to the LM5005, but take care to avoid any coupling of the inductor's magnetic field to

sensitive feedback or compensation traces.

4. Use a solid ground plane on layer two of the PCB, particularly underneath the LM5005 and power stage

LM5005

www.ti.com

SNVS397E –SEPTEMBER 2005–REVISED NOVEMBER 2016

Product Folder Links: LM5005

Layout Guidelines (continued)

components. This plane functions as a noise shield and also as a heat dissipation path.

5. Make input and output power bus connections as wide and short as possible to reduce voltage drops on the

input and output of the converter and to improve efficiency. Use copper planes on top to connect the multiple

VIN pins and PGND pins together.

6. Provide enough PCB area for proper heat-sinking. As stated in Thermal Design, use enough copper area to

ensure a low RθJA commensurate with the maximum load current and ambient temperature. Make the top

and bottom PCB layers with two ounce copper thickness and no less than one ounce. Use an array of heat-

sinking vias to connect the exposed pad to the ground plane on the bottom PCB layer. If the PCB has

multiple copper layers as recommended, connect these thermal vias to the inner layer heat-spreading ground

planes.

7. Route the sense trace from the VOUT point of regulation to the feedback resistors away from the SW pins

and inductor to avoid contaminating this feedback signal with switching noise. This routing is most important

when high resistances are used to set the output voltage. Routing the feedback trace on a different layer

than the inductor and SW node trace is recommended such that a ground plane exists between the sense

trace and inductor or SW node polygon to provide further cancellation of EMI on the feedback trace.

8. If voltage accuracy at the load is important, ensure that the feedback voltage sense is made directly at the

load terminals. Doing so corrects for voltage drops in the PCB planes and traces and provides optimal output

voltage set-point accuracy and load regulation. Place the feedback resistor divider closer to the FB pin,

rather than close to the load, because the FB node is the input to the error amplifier and is thus noise

sensitive.

9. COMP is a also noise-sensitive node. Place the compensation components as close as possible to the FB

and COMP pins.

10. Place the components for RT, CSS, CRAMP and CVCC close to their respective pins. Connect all of the signal

components' ground return connections directly to the LM5005's AGND pin. Connect the AGND and PGND

pins together at the LM5005's exposed pad using the topside copper area covering the entire underside of

the device. Connect several vias within this underside copper area to the PCB's internal ground plane.

11. See Related Documentation for additional important guidelines.

10.1.1 PCB Layout for EMI Reduction

Radiated EMI generated by high slew-rate current edges relates to pulsating currents in switching converters.

The larger area covered by the path of a pulsing current, the more electromagnetic emission is generated. The

key to reducing radiated EMI is to identify the pulsing current path and minimize the area of that path.

The important high-frequency switching power loop (or hot loop) of the LM5005 power stage is denoted in blue in

Figure 34. The topological architecture of a buck converter means that particularly high di/dt current exists in this

loop as current commutates between the externally-connected Schottky diode and the integrated high-side

MOSFET during switching transitions. As such, it becomes mandatory to minimize this effective loop area, with

an eye to reducing the layout-induced parasitic or stray inductances that cause excessive SW voltage overshoot

and ringing, noise and ground bounce.

In general, MOSFET switching behavior and the consequences for waveform ringing, power dissipation, device

stress and EMI are correlated with the parasitic inductances of the power loop. It follows that the cumulative

benefits of reducing the switching loop area are increased reliability and robustness owing to lower power

MOSFET voltage and current stress, increased margin for input voltage transients, and easier EMI filtering

(particularly in the more challenging high-frequency band above 30 MHz).

J D JA A

T P T ˜ T 

 

D OUT F OUT OUT DCR

P P V I 1 D I R 1.5

§ ·

 K

˜  ˜ ˜   ˜ ˜

¨ ¸

VIN

VOUT

GND

LM5005

High-side

MOSFET

gate driver

CIN

COUT

PGND

High

frequency

power

loop

VIN

BST

RCS

VCC

CVCC

CBST

LM5005

SNVS397E –SEPTEMBER 2005–REVISED NOVEMBER 2016

www.ti.com

Product Folder Links: LM5005

Layout Guidelines (continued)

Figure 34. LM5005 Power Stage Circuit Switching Loops

High-frequency ceramic bypass capacitors at the input side provide the primary path for the high di/dt

components of the pulsing current. Position low-ESL ceramic bypass capacitors with low-inductance, short trace

routes to the VIN and PGND pins. Keep the SW trace connecting to the inductor as short as possible, and just

wide enough to carry the load current without excessive heating. Use short, thick traces or copper polygon pours

(shapes) for current conduction paths to minimize parasitic resistance. Place the output capacitors close to the

VOUT side of the inductor and route the return connection using GND plane copper back to the PGND pins and

the exposed pad of the LM5005.

10.1.2 Thermal Design

As with any power conversion device, the LM5005 dissipates internal power while operating. The effect of this

power dissipation is to raise the internal junction temperature of the LM5005 above ambient. The junction

temperature (TJ) is a function of the ambient temperature (TA), the power dissipation (PD) and the effective

thermal resistance of the device and PCB combination (RθJA). The maximum operating junction temperature for

the LM5005 is 125°C, thus establishing a limit on the maximum device power dissipation and therefore the load

current at high ambient temperatures. Equation 21 and Equation 22 show the relationships between these

parameters.

(21)

(22)

An approximation for the inductor power loss in Equation 21 includes a factor of 1.5 for the core losses. Also, if a

snubber is used, estimate its power loss by observation of the resistor voltage drop at both turnon and turnoff

switching transitions.

High ambient temperatures and large values of RθJA reduce the maximum available output current. If the junction

temperature exceeds 165°C, the LM5005 cycles in and out of thermal shutdown. Thermal shutdown may be a

sign of inadequate heat-sinking or excessive power dissipation. Improve PCB heat-sinking by using more thermal

vias, a larger board, or more heat-spreading layers within that board.

VIN

VOUT

GND

GND IS

Thermal vias under

LM5005 pad

Connect ceramic input

cap(s) close to VIN pin

Keep COMP network close

to COMP and FB pins

Place FB resistors close to FB pin

SYNC

Keep diode close

to SW and IS pins

Place boot cap close

to BST and SW pins

LM5005

www.ti.com

SNVS397E –SEPTEMBER 2005–REVISED NOVEMBER 2016

Product Folder Links: LM5005

Layout Guidelines (continued)

As stated in Semiconductor and IC Package Thermal Metrics (SPRA953), the values given in Thermal

Information are not always valid for design purposes to estimate the thermal performance of the application. The

values reported in this table are measured under a specific set of conditions that are seldom obtained in an

actual application. The effective RθJA is a critical parameter and depends on many factors (such as power

dissipation, air temperature, PCB area, copper heat-sink area, number of thermal vias under the package, air

flow, and adjacent component placement). The LM5005's exposed pad has a direct thermal connection to

PGND. This pad must be soldered directly to the PCB copper ground plane to provide an effective heat-sink and

proper electrical connection. Use the documents listed in Documentation Support as a guide for optimized

thermal PCB design and estimating RθJA for a given application environment.

10.1.3 Ground Plane Design

As mentioned previously, using one of the inner PCB layers as a solid ground plane is recommended. A ground

plane offers shielding for sensitive circuits and traces and also provides a quiet reference potential for the control

circuitry. Connect the PGND pins to the system ground plane using an array of vias under the LM5005's exposed

pad. Also connect the PGND pins directly to the return terminals of the input and output capacitors. The PGND

net contains noise at the switching frequency and can bounce because of load current variations. The power

traces for PGND, VIN, and SW can be restricted to one side of the ground plane. The other side of the ground

plane contains much less noise and is ideal for sensitive analog trace routes.

10.2 Layout Example

Figure 35. Component Side

GND VOUT

GNDVIN

SYNC

Texas Instruments

LM5005

SNVS397E –SEPTEMBER 2005–REVISED NOVEMBER 2016

www.ti.com

Product Folder Links: LM5005

Layout Example (continued)

Figure 36. Solder Side (Viewed From Top)

Figure 37. Silkscreen

LM5005

www.ti.com

SNVS397E –SEPTEMBER 2005–REVISED NOVEMBER 2016

Product Folder Links: LM5005

11 Device and Documentation Support

11.1 Third-Party Products Disclaimer

TI'S PUBLICATION OF INFORMATION REGARDING THIRD-PARTY PRODUCTS OR SERVICES DOES NOT

CONSTITUTE AN ENDORSEMENT REGARDING THE SUITABILITY OF SUCH PRODUCTS OR SERVICES

OR A WARRANTY, REPRESENTATION OR ENDORSEMENT OF SUCH PRODUCTS OR SERVICES, EITHER

ALONE OR IN COMBINATION WITH ANY TI PRODUCT OR SERVICE.

11.2 Device Support

11.2.1 Development Support

For development support see the following:

• For TI's reference design library, visit TI Designs

• For TI's WEBENCH Design Environments, visit WEBENCH®Design Center

11.3 Documentation Support

11.3.1 Related Documentation

For related documentation see the following:

•AN-1748 LM5005 Evaluation Board (SNVA298)

•Buck Regulator Topologies for Wide Input/Output Voltage Differentials (SNVA594)

• White Papers:

–Valuing Wide VIN, Low EMI Synchronous Buck Circuits for Cost-Effective, Demanding Applications

(SLYY104)

–Wide VIN Power Management ICs Simplify Design, Reduce BOM Cost, and Enhance Reliability

(SLYY037)

11.3.1.1 PCB Layout Resources

•AN-1149 Layout Guidelines for Switching Power Supplies (SNVA021)

•AN-1229 Simple Switcher PCB Layout Guidelines (SNVA054)

•Constructing Your Power Supply – Layout Considerations (SLUP230)

•Low Radiated EMI Layout Made SIMPLE with LM4360x and LM4600x (SNVA721)

•AN-2162 Simple Success With Conducted EMI From DC-DC Converters (SNVA489)

•Reduce Buck-Converter EMI and Voltage Stress by Minimizing Inductive Parasitics (SLYT682)

11.3.1.2 Thermal Design Resources

•AN-2020 Thermal Design By Insight, Not Hindsight (SNVA419)

•AN-1520 A Guide to Board Layout for Best Thermal Resistance for Exposed Pad Packages (SNVA183)

•Semiconductor and IC Package Thermal Metrics (SPRA953)

•Thermal Design Made Simple with LM43603 and LM43602 (SNVA719)

•PowerPAD™Thermally Enhanced Package (SLMA002)

•PowerPAD Made Easy (SLMA004)

•Using New Thermal Metrics (SBVA025)

11.4 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

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SNVS397E –SEPTEMBER 2005–REVISED NOVEMBER 2016

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Product Folder Links: LM5005

11.5 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

11.6 Trademarks

PowerPAD, E2E are trademarks of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

11.7 Electrostatic Discharge Caution

These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam

during storage or handling to prevent electrostatic damage to the MOS gates.

11.8 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

12 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead/Ball Finish

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LM5005MH NRND HTSSOP PWP 20 73 TBD Call TI Call TI -40 to 125 LM5005

LM5005MH/NOPB ACTIVE HTSSOP PWP 20 73 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LM5005

LM5005MHX/NOPB ACTIVE HTSSOP PWP 20 2500 Green (RoHS

& no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 LM5005

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish

value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

PACKAGE OPTION ADDENDUM

www.ti.com 6-Feb-2020

Addendum-Page 2

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LM5005MHX/NOPB HTSSOP PWP 20 2500 330.0 16.4 6.95 7.1 1.6 8.0 16.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Feb-2016

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LM5005MHX/NOPB HTSSOP PWP 20 2500 367.0 367.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Feb-2016

Pack Materials-Page 2

MECHANICAL DATA

PWP0020A

www.ti.com

MXA20A (Rev C)

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