DS26C31MQML
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SNOSAS2A OCTOBER 2010REVISED APRIL 2013
DS26C31MQML CMOS Quad TRI-STATE Differential Line Driver
Check for Samples: DS26C31MQML
1FEATURES DESCRIPTION
The DS26C31 is a quad differential line driver
2 TTL Input Compatible designed for digital data transmission over balanced
Outputs Will Not Load Line When VCC = 0V lines. The DS26C31 meets all the requirements of
Meets the Requirements of EIA Standard RS- EIA standard RS-422 while retaining the low power
422 characteristics of CMOS. The DS26C31 is compatible
with EIA standard RS-422; however, one exception in
Operation from Single 5V Supply test methodology is taken. This enables the
TRI-STATE Outputs for Connection to System construction of serial and terminal interfaces while
Buses maintaining minimal power consumption.
Low Quiescent Current The DS26C31 accepts TTL or CMOS input levels and
translates these to RS-422 output levels. This part
uses special output circuitry that enables the drivers
to power down without loading down the bus. This
device has enable and disable circuitry common to all
four drivers. The DS26C31 is pin compatible to the
AM26LS31 and the DS26LS31.
All inputs are protected against damage due to
electrostatic discharge by diodes to VCC and ground.
Connection Diagram
Figure 1. CDIP, CLGA Packages- Top View
See Package Numbers NFE0016A, NAD0016A
1Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
2All trademarks are the property of their respective owners.
PRODUCTION DATA information is current as of publication date. Copyright © 2010–2013, Texas Instruments Incorporated
Products conform to specifications per the terms of the Texas
Instruments standard warranty. Production processing does not
necessarily include testing of all parameters.
DS26C31MQML
SNOSAS2A OCTOBER 2010REVISED APRIL 2013
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Figure 2. 20-Lead LCCC Package- Top View
See Package Number NAJ0020A
Logic Diagram
Truth Table (1)
ENABLE ENABLE Input Non-Inverting Inverting
Output Output
L H X Z Z
All other L L H
combinations of H H L
enable inputs
(1) L = Low logic state
X = Irrelevant
H = High logic state
Z = TRI-STATE (high impedance)
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These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
Absolute Maximum Ratings(1)(2)
Supply Voltage (VCC)0.5V to 7.0V
DC Input Voltage (VI)1.5V to VCC +0.5V
DC Output Voltage (VO)0.5V to 7V
Clamp Diode Current (IIK, IOK) ±20 mA
DC Output Current, per pin (IO) ±150 mA
DC VCC or Gnd Current, per pin (ICC) ±150 mA
Storage Temperature Range (TStg)65°C TA+150°C
Lead Temperature (TL) Soldering, 4 sec. 260°C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is functional, but do not verify specific performance limits. For verified specifications and test conditions, see the
Electrical Characteristics. The verified specifications apply only for the test conditions listed. Some performance characteristics may
degrade when the device is not operated under the listed test conditions.
(2) Unless otherwise specified, all voltages are referenced to ground. All currents into device pins are positive, all currents out of device
pins are negative.
Operating Conditions Min Max Units
Supply Voltage (VCC) 4.50 5.50 V
DC Input or Output Voltage (VI, VO) 0 VCC V
Operating Temperature Range (TA)55 +125 °C
Quality Conformance Inspection
Table 1. Mil-Std-883, Method 5005 - Group A
Subgroup Description Temp °C
1 Static tests at +25
2 Static tests at +125
3 Static tests at -55
4 Dynamic tests at +25
5 Dynamic tests at +125
6 Dynamic tests at -55
7 Functional tests at +25
8A Functional tests at +125
8B Functional tests at -55
9 Switching tests at +25
10 Switching tests at +125
11 Switching tests at -55
12 Settling time at +25
13 Settling time at +125
14 Settling time at -55
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DS26C31M Electrical Characteristics DC Parameters Sub-
Parameter Test Conditions Notes Min Max Unit groups
VIH Logical "1" Input Voltage 2.0 V 1, 2, 3
VIL Logical "0" Input Voltage 0.8 V 1, 2, 3
VOH Logical "1" Output Voltage VI= VIH or VIL, 2.5 V 1, 2, 3
VCC = 4.5V, IO= -20mA
VOL Logical "0" Output Voltage VI= VIH or VIL, 0.5 V 1, 2, 3
IO= 20mA, VCC = 4.5V
VTDifferential Output Voltage RL= 100, VCC = 4.5V (1) 2.0 V 1, 2, 3
|VT||VT| Difference in Differential Output RL= 100, VCC = 4.5V (1) 0.4 V 1, 2, 3
VOS Common Mode Output Voltage RL= 100, VCC = 5.5V (1) 3.0 V 1, 2, 3
|VOSVOS | Diff in Common Mode Output RL= 100, VCC = 5.5V (1) 0.4 V 1, 2, 3
IIInput Current VI= VCC, Gnd, VIH, or VIL, ±1.0 µA 1, 2, 3
VCC = 5.5V
ICC Quiescent Power Supply Current IO= 0µA, VI= VCC or Gnd, (2) 500 µA 1, 2, 3
VCC = 5.5V
IO= 0µA, VI= 2.4V or 0.5V, (2) 2.1 mA 1, 2, 3
VCC = 5.5V
IOZ TRI-STATE Output Leakage VO= VCC or Gnd, Enable = VIL, ±5.0 µA 1, 2, 3
Current VCC = 5.5V, Enable = VIH
ISC Output Short Circuit Current VI= VCC or Gnd, VCC = 5.5V (1),(3) -30 -150 mA 1, 2, 3
IOff Output Leakage Current "Power VCC = 0V, VO= 6V 100 µA 1, 2, 3
Off" VCC = 0V, VO= 0V -100 µA 1, 2, 3
(1) See EIA Specification RS-422 for exact test conditions.
(2) Measured per input. All other inputs at VCC or GND.
(3) This is the current sourced when a high output is shorted to ground. Only one output at a time should be shorted.
DS26C31M Electrical Characteristics AC Parameters - Propagation Delay Time (see Figure 26)
The following conditions apply, unless otherwise specified. VCC = 5V, tR6ns, tF6ns Sub-
Parameter Test Conditions Notes Min Max Unit groups
tPLH Input to Output Prop Delay Figure 27 14 ns 9, 10, 11
tPHL Input to Output Prop Dalay Figure 27 14 ns 9, 10, 11
Skew (1) 3.0 ns 9, 10, 11
tTLH Output Rise Time Figure 29 14 ns 9, 10, 11
tTHL Output Fall Time Figure 29 14 ns 9, 10, 11
tPZH Output Enable Time Figure 28 22 ns 9, 10, 11
tPZL Output Enable Time Figure 28 28 ns 9, 10, 11
tPHZ Output Disable Time Figure 28 (2) 12 ns 9, 10, 11
tPLZ Output Disable Time Figure 28 (2) 14 ns 9, 10, 11
(1) Skew is defined as the difference in propagation delays between complimentary outputs at the 50% point.
(2) Output disable time is the delay from ENABLE or ENABLE being switched to the output transistors turning off.
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Typical Performance Characteristics
Differential Propagation Delay Differential Propagation Delay
vs Temperature vs Power Supply Voltage
Figure 3. Figure 4.
Differential Skew
vs
Differential Skew vs Power
Temperature Supply Voltage
Figure 5. Figure 6.
Differential Transition Time Differential Transition Time
vs Temperature vs Power Supply Voltage
Figure 7. Figure 8.
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Typical Performance Characteristics (continued)
Complementary Skew vs Complementary Skew vs
Temperature Power Supply Voltage
Figure 9. Figure 10.
Differential Output Voltage Differential Output Voltage
vs Output Current vs Output Current
Figure 11. Figure 12.
Output High Voltage vs Output High Voltage vs
Output High Current Output High Current
Figure 13. Figure 14.
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Typical Performance Characteristics (continued)
Output Low Voltage vs Output Low Voltage vs
Output Low Current Output Low Current
Figure 15. Figure 16.
Supply Current Output Low Voltage vs
vs Temperature Output Low Current
Figure 17. Figure 18.
Output Low Voltage vs Supply Current
Output Low Current vs Temperature
Figure 19. Figure 20.
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Typical Performance Characteristics (continued)
Supply Current vs No Load Supply Current
Power Supply Voltage vs Data Rate
Figure 21. Figure 22.
Loaded Supply Current Output Short Circuit Current
vs Data Rate vs Temperature
Figure 23. Figure 24.
Output Short Circuit Current
vs Power Supply Voltage
Figure 25.
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AC TEST CIRCUIT AND SWITCHING TIME WAVEFORMS
Note: C1 = C2 = C3 = 40 pF (Including Probe and Jig Capacitance), R1 = R2 = 50Ω, R3 = 500Ω.
Figure 26. AC Test Circuit
Figure 27. Propagation Delays
Figure 28. Enable and Disable Times
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Input pulse; f = 1 MHz, 50%; tr6 ns, tf6 ns
Figure 29. Differential Rise and Fall Times
TYPICAL APPLICATIONS
*RTis optional although highly recommended to reduce reflection.
Figure 30. Two-Wire Balanced System, RS-422
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REVISION HISTORY
Table 2. Revision History
Released Revision Section Changes
10/26/2010 A New Release, Corporate format 1 MDS data sheets converted into one Corp. data
sheet format. MNDS26C31M-X Rev 0B0 will be
archived.
Changes from Original (April 2013) to Revision A Page
Changed layout of National Data Sheet to TI format .......................................................................................................... 10
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PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2013
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish MSL Peak Temp
(3)
Op Temp (°C) Top-Side Markings
(4)
Samples
DS26C31ME/883 ACTIVE LCCC NAJ 20 50 TBD Call TI Call TI -55 to 125 DS26C31ME/
883 Q
5962-91639
01M2A ACO
01M2A >T
DS26C31MJ/883 ACTIVE CDIP NFE 16 25 TBD Call TI Call TI -55 to 125 DS26C31MJ/883
5962-9163901MEA Q
DS26C31MW/883 ACTIVE CFP NAD 16 19 TBD Call TI Call TI -55 to 125 DS26C31MW
/883 Q
5962-91639
01MFA ACO
01MFA >T
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) Eco Plan - The planned eco-friendly classification: Pb-Free (RoHS), Pb-Free (RoHS Exempt), or Green (RoHS & no Sb/Br) - please check http://www.ti.com/productcontent for the latest availability
information and additional product content details.
TBD: The Pb-Free/Green conversion plan has not been defined.
Pb-Free (RoHS): TI's terms "Lead-Free" or "Pb-Free" mean semiconductor products that are compatible with the current RoHS requirements for all 6 substances, including the requirement that
lead not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, TI Pb-Free products are suitable for use in specified lead-free processes.
Pb-Free (RoHS Exempt): This component has a RoHS exemption for either 1) lead-based flip-chip solder bumps used between the die and package, or 2) lead-based die adhesive used between
the die and leadframe. The component is otherwise considered Pb-Free (RoHS compatible) as defined above.
Green (RoHS & no Sb/Br): TI defines "Green" to mean Pb-Free (RoHS compatible), and free of Bromine (Br) and Antimony (Sb) based flame retardants (Br or Sb do not exceed 0.1% by weight
in homogeneous material)
(3) MSL, Peak Temp. -- The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) Multiple Top-Side Markings will be inside parentheses. Only one Top-Side Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a
continuation of the previous line and the two combined represent the entire Top-Side Marking for that device.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
PACKAGE OPTION ADDENDUM
www.ti.com 15-Apr-2013
Addendum-Page 2
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
MECHANICAL DATA
J0016A
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J16A (REV L)
NFE0016A
MECHANICAL DATA
NAJ0020A
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E20A (Rev F)
MECHANICAL DATA
NAD0016A
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W16A (Rev T)
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