1. General description
The 74HC237 is a h igh-speed Si-gate CMOS device and is pin comp atible with low-power
Schottky TTL (LSTTL). The 74HC237 is specified in compliance with JEDEC
standard no. 7A.
The 74HC237 is a 3-to-8 line decoder, demultiplexer with latches at the three address
inputs (An). The 74HC237 essentially combines the 3-to-8 decoder function with a 3-bit
storage latch. When the latch is enabled ( LE = LOW), the 74HC237 acts as a 3-to-8 active
LOW decoder. When the latch enable (LE) goes from LOW-to-HIGH, the l ast dat a present
at the inputs before this transition, is stored in the latches. Further address changes are
ignored as long as LE remains HIGH. The output enable input (E1 and E2) controls the
state of the outputs independent of the address inputs or latch operation. All outputs are
HIGH unless E1 is LOW and E2 is HIGH. The 74HC237 is ideally suited for implementing
non-overlapping de coders in 3-st ate systems and strobed (stored address) applications in
bus-oriented systems.
2. Features and benefits
Combines 3-to-8 decoder with 3-bit latch
Multiple input enable for easy expansion or independent controls
Active HIGH mutually exclusive outputs
Low-power dissipation
ESD protection:
HBM JESD22-A114F exceeds 2000 V
MM JESD22-A115 -A ex ce ed s 200 V
Multiple package options
Specified from 40 Cto+85C and from 40 Cto+125C
3. Ordering information
74HC237
3-to-8 line decoder, demultiplexer with address latches
Rev. 6 — 23 August 2012 Product data sheet
Table 1. Ordering information
Type number Package
Temperature ra nge Name Description Version
74HC237N 40 C to +125 C DIP16 plastic dual in-line package; 16 leads (300 mil) SOT38-4
74HC237D 40 C to +125 C SO16 plastic small outline package; 16 leads; body width
3.9 mm SOT109-1
74HC237DB 40 C to +125 C SSOP16 plastic shrink small outline package; 16 leads;
body width 5.3 mm SOT338-1
74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 23 August 2012 2 of 17
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
4. Functional diagram
Fig 1. Functional di agram
001aab871
Y0
Y1
Y2
3 T O 8
DECODER
INPUT
LATCHES
Y3
Y4
Y5
Y6
Y7 7
9
10
11
12
13
14
15
A0
A1
E1
E2
A2
LE
4
3
5
6
2
1
Fig 2. Logic symbol Fig 3. IEC logic symbol
001aab869
Y0
Y1
Y2
3 T O 8
DECODER
INPUT
LATCHES Y3
Y4
Y5
Y6
Y7 7
9
10
11
12
13
14
15
A0
A1
E1
E2
5
6
A2
LE
4
3
2
1
001aab870
0
1
2
3
4
5
6
77
9
10
11
12
13
14
15
C8
8D,1
8D,2
X/Y
EN
&
2
8D,4
3
5
6
1
4
0
1
2
3
4
5
6
77
9
10
11
12
13
14
15
C8
0
8D,G 0
7
DX
&
2
2
3
5
6
1
4
74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 23 August 2012 3 of 17
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
5. Pinning information
5.1 Pinning
Fig 4. Logic diag ram
001aab872
E1
E2
A0
A1
A2
LE
Y0
Y1
Y2
Y3
Y4
Y5
Y6
Y7
A0
A0
LELE
LATCH
A1
A1
LELE
LATCH
A2
A2
LELE
LATCH
Fig 5. Pin configuration DIP16 and SO16 Fig 6. Pin configuration SSOP16
74HC237
A0 VCC
A1 Y0
A2 Y1
LE Y2
E1 Y3
E2 Y4
Y7 Y5
GND Y6
001aab868
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
74HC237
A0 V
CC
A1 Y0
A2 Y1
LE Y2
E1 Y3
E2 Y4
Y7 Y5
GND Y6
001aan382
1
2
3
4
5
6
7
8
10
9
12
11
14
13
16
15
74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 23 August 2012 4 of 17
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
5.2 Pin description
6. Functional description
[1] H = HIGH voltage level; L = LOW voltage level; X = don’t care; Z = high-impedance OFF-state.
7. Limiting values
Table 2. Pin description
Symbol Pin Description
A0 to A2 1, 2, 3 data input
LE 4 latch enable input (active LOW)
E1 5 data enable input 1 (active LOW)
E2 6 data enable input 2 (active HIGH)
Y0 to Y7 15, 14, 13, 12, 11, 10, 9, 7 output
GND 8 ground (0 V)
VCC 16 supply voltage
Table 3: Function table
Enable Input Output
LE E1 E2 A0 A1 A2 Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
HLHXXXstable
XHXXXXLLLLLLLL
XXLXXXLLLLLLLL
LLHLLLHLLLLLLL
HLLLHLLLLLL
LHLLLHLLLLL
HHLLLLHLLLL
LLHLLLLHLLL
HLHLLLLLHLL
LHHLLLLLLHL
HHHLLLLLLLH
Table 4. L imiting values
In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Min Max Unit
VCC supply voltage 0.5 +7 V
IIK input clamping current VI < 0.5 V or VI>V
CC +0.5 V - 20 mA
IOK output clamping current VO<0.5 V or VO>V
CC +0.5V - 20 mA
IOoutput current VO = 0.5 V to (VCC +0.5V) - 25 mA
ICC supply current - +50 mA
IGND ground current - 50 mA
Tstg storage temperature 65 +150 C
Ptot total power dissipation DIP16 p ackage [1] - 750 mW
SO16 and SSOP16 packages [2] - 500 mW
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Product data sheet Rev. 6 — 23 August 2012 5 of 17
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
[1] For DIP16 package: Ptot derates linearly with 12 mW/K above 70 C.
[2] For SO16 package: Ptot derates linearly with 8 mW/K above 70 C.
For SSOP16 package: Ptot derates linearly with 5.5 mW/K above 60 C.
8. Recommended operating conditions
9. Static characteristics
Table 5. Recommended operating con ditions
Voltages are referenced to GND (ground = 0 V)
Symbol Parameter Conditions Min Typ Max Unit
VCC supply voltage 2.0 5.0 6.0 V
VIinput voltage 0 - VCC V
VOoutput voltage 0 - VCC V
Tamb ambient temperature 40 +25 +125 C
t/V input transition rise and fall rate VCC = 2.0 V - - 625 ns/V
VCC = 4.5 V - 1.67 139 ns/V
VCC = 6.0 V - - 83 ns/V
Table 6. Static characteristics
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to
+85 CTamb = 40 C to
+125 CUnit
Min Typ Max Min Max Min Max
VIH HIGH-level
input voltage VCC = 2.0 V 1.5 1.2 - 1.5 - 1.5 - V
VCC = 4.5 V 3.15 2.4 - 3.15 - 3.15 - V
VCC = 6.0 V 4.2 3.2 - 4.2 - 4.2 - V
VIL LOW-level
input voltage VCC = 2.0 V - 0.8 0.5 - 0.5 - 0.5 V
VCC = 4.5 V - 2.1 1.35 - 1.35 - 1.35 V
VCC = 6.0 V - 2.8 1.8 - 1.8 - 1.8 V
VOH HIGH-level
output voltage VI=V
IH or VIL
IO=20 A; VCC = 2.0 V 1.9 2.0 - 1.9 - 1.9 - V
IO=20 A; VCC = 4.5 V 4.4 4.5 - 4.4 - 4.4 - V
IO=20 A; VCC = 6.0 V 5.9 6.0 - 5.9 - 5.9 - V
IO=4.0 mA; VCC = 4.5 V 3.98 4.32 - 3.84 - 3.7 - V
IO=5.2 mA; VCC = 6.0 V 5.48 5.81 - 5.34 - 5.2 - V
VOL LOW-level
output voltage VI=V
IH or VIL
IO=20A; VCC = 2.0 V - 0 0.1 - 0.1 - 0.1 V
IO=20A; VCC = 4.5 V - 0 0.1 - 0.1 - 0.1 V
IO=20A; VCC = 6.0 V - 0 0.1 - 0.1 - 0.1 V
IO= 4.0 mA; VCC = 4.5 V - 0.15 0.26 - 0.33 - 0.4 V
IO= 5.2 mA; VCC = 6.0 V - 0.16 0.26 - 0.33 - 0.4 V
74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 23 August 2012 6 of 17
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
10. Dynamic characteristics
IIinput leakage
current VI=V
CC or GND;
VCC =6.0V --0.1 - 1.0 - 1.0 A
ICC supply current VI=V
CC or GND; IO=0A;
VCC =6.0V - - 8.0 - 80 - 160 A
CIinput
capacitance -3.5- - - - -pF
Table 6. Static characteristics …continued
At recommended operating conditions; voltages are referenced to GND (ground = 0 V).
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C to
+85 CTamb = 40 C to
+125 CUnit
Min Typ Max Min Max Min Max
Table 7. Dynamic characteristics
Voltages are referenced to GND (ground = 0 V); C L = 50 pF unless otherwise specified; for test circuit see Figure 10.
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C
to +85 CTamb = 40 C
to +125 CUnit
Min Typ Max Min Max Min Max
tpd propagation
delay An to Yn; see Figure 7 [1]
VCC = 2.0 V - 52 160 - 200 - 240 ns
VCC = 4.5 V - 19 32 - 40 - 48 ns
VCC =5V; C
L=15pF - 16 - - - - - ns
VCC = 6.0 V - 15 27 - 34 - 41 ns
LE to Yn; see Figure 7 [1]
VCC = 2.0 V - 61 190 - 240 - 285 ns
VCC = 4.5 V - 22 38 - 48 - 57 ns
VCC =5V; C
L=15pF - 19 - - - - - ns
VCC = 6.0 V - 18 32 - 41 - 48 ns
E1to Yn; see Figure 8 [1]
VCC = 2.0 V - 47 145 - 180 - 220 ns
VCC = 4.5 V - 17 29 - 36 - 44 ns
VCC =5V; C
L=15pF - 14 - - - - - ns
VCC = 6.0 V - 14 25 - 31 - 38 ns
E2 to Yn; see Figure 7 [1]
VCC = 2.0 V - 47 145 - 180 - 220 ns
VCC = 4.5 V - 17 29 - 36 - 44 ns
VCC =5V; C
L=15pF - 14 - - - - - ns
VCC = 6.0 V - 14 25 - 31 - 38 ns
tttransition
time Yn; see Figure 7 and
Figure 8 [2]
VCC = 2.0 V - 19 75 - 95 - 110 ns
VCC = 4.5 V - 7 15 - 19 - 22 ns
VCC = 6.0 V - 6 13 - 16 - 19 ns
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Product data sheet Rev. 6 — 23 August 2012 7 of 17
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
[1] tpd is the same as tPLH and tPHL.
[2] tt is the same as tTHL and tTLH.
[3] CPD is used to determine the dynamic power dissipation (PD in W).
PD=C
PD VCC2fiN+(CLVCC2fo) where:
fi = input frequency in MHz;
fo= output frequency in MHz;
CL= output load capacitance in pF;
VCC = supply voltage in V;
N = number of inputs switching;
(CLVCC2fo) = sum of outputs.
11. Waveforms
tWpulse width LE HIGH; see Figure 9
VCC = 2.0 V 50 11 - 65 - 75 - ns
VCC = 4.5 V 10 4 - 13 - 15 - ns
VCC = 6.0 V 9 3 - 11 - 13 - ns
tsu set-up time An to LE; see Figure 9
VCC = 2.0 V 50 6 - 65 - 75 - ns
VCC = 4.5 V 10 2 - 13 - 15 - ns
VCC = 6.0 V 9 2 - 11 - 13 - ns
thhold time An to LE; see Figure 9 -
VCC = 2.0 V 30 3 - 40 - 45 - ns
VCC = 4.5 V 6 1 - 8 - 9 - ns
VCC = 6.0 V 5 1 - 7 - 8 - ns
CPD power
dissipation
capacitance
CL=50pF;f=1 MHz;
VI=GNDtoV
CC
[3] -60- - - - -pF
Table 7. Dynamic characteristics …continued
Voltages are referenced to GND (ground = 0 V); C L = 50 pF unless otherwise specified; for test circuit see Figure 10.
Symbol Parameter Conditions Tamb = 25 C Tamb = 40 C
to +85 CTamb = 40 C
to +125 CUnit
Min Typ Max Min Max Min Max
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 7. Propagation delay input (An) and enable inputs (E2, LE) to output (Yn) and output transition time
001aab873
An, E2, LE
input
Yn output
VM
tPHL
tTHL tTLH
tPLH
VM
90 %90 %
10 %10 %
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Product data sheet Rev. 6 — 23 August 2012 8 of 17
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 8. Prop agation enable inputs (E1) to output (Yn) and output transition time
001aab874
E1 input
Yn output
V
M
t
PHL
t
THL
t
TLH
t
PLH
V
M
90 %90 %
10 %10 %
Measurement points are given in Table 8.
VOL and VOH are typical voltage output levels that occur with the output load.
Fig 9. The data input (An) to latch enable input (LE) set-up times, latch enable input (LE) to dat a input (An) hold
times and latch enable input (LE) pulse width
t
su
t
h
LE input
V
M
V
M
001aab875
t
h
t
su
t
W
An input
transparant transparantlatched latched
Table 8. Mea surement points
Type Input Output
VMVM
74HC237 0.5VCC 0.5VCC
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Product data sheet Rev. 6 — 23 August 2012 9 of 17
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
Test data is given in Table 9.
Definitions test circuit:
RT = Termination resistance should be equal to output impedance Zo of the pulse generator.
CL = Load capacitance including jig and probe capacitance.
RL = Load resistance.
S1 = Test selection switch.
Fig 10. Test circuit for measuring switching times
Table 9. Test data
Type Input Load Test
VItr, tfCL
74HC237 VCC 6.0 ns 15 pF, 50 pF tPLH, tPHL
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Product data sheet Rev. 6 — 23 August 2012 10 of 17
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
12. Application information
Fig 11. 6-to-64 line decod e r wi th input address storage
001aab876
16
237
outputs
to five
other
decoders
17 18 19 20 21 22 23
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
LE A2 A1 A0 E2 E1
8
237
outputs
9 10 11 12 13 14 15
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
LE A2 A1 A0 E2 E1
0
237
outputs
1 2 3 4 5 6 7
Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7
LE A2 A1 A0 E2 E1
0
237
123 4 5 6 7
Y0
X0
decoder enable
input
address
strobe
X1
X2
X3
X4
X5
Y1 Y2 Y3 Y4 Y5 Y6 Y7
LE A2 A1 A0 E2 E1
74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 23 August 2012 11 of 17
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
13. Package outline
Fig 12. Package outline SOT38-4 (DIP16)
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
SOT38-4 95-01-14
03-02-13
MH
c
(e )
1
ME
A
L
seating plane
A1
wM
b1
b2
e
D
A2
Z
16
1
9
8
E
pin 1 index
b
0 5 10 mm
scale
Note
1. Plastic or metal protrusions of 0.25 mm (0.01 inch) maximum per side are not included.
UNIT A
max. 12 b1(1) (1) (1)
b2cD E e M Z
H
L
mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
A
min. A
max. bmax.
w
ME
e1
1.73
1.30 0.53
0.38 0.36
0.23 19.50
18.55 6.48
6.20 3.60
3.05 0.2542.54 7.62 8.25
7.80 10.0
8.3 0.764.2 0.51 3.2
inches 0.068
0.051 0.021
0.015 0.014
0.009
1.25
0.85
0.049
0.033 0.77
0.73 0.26
0.24 0.14
0.12 0.010.1 0.3 0.32
0.31 0.39
0.33 0.030.17 0.02 0.13
DIP16: plastic dual in-line package; 16 leads (300 mil) SOT38-4
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Product data sheet Rev. 6 — 23 August 2012 12 of 17
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
Fig 13. Package outline SOT109-1 (SO16)
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
8
9
1
16
y
pin 1 index
UNIT A
max. A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm
inches
1.75 0.25
0.10 1.45
1.25 0.25 0.49
0.36 0.25
0.19 10.0
9.8 4.0
3.8 1.27 6.2
5.8 0.7
0.6 0.7
0.3 8
0
o
o
0.25 0.1
DIMENSIONS (inch dimensions are derived from the original mm dimensions)
Note
1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.
1.0
0.4
SOT109-1 99-12-27
03-02-19
076E07 MS-012
0.069 0.010
0.004 0.057
0.049 0.01 0.019
0.014 0.0100
0.0075 0.39
0.38 0.16
0.15 0.05
1.05
0.041
0.244
0.228 0.028
0.020 0.028
0.012
0.01
0.25
0.01 0.004
0.039
0.016
0 2.5 5 mm
scale
SO16: plastic small outline package; 16 leads; body width 3.9 mm SOT109-1
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Product data sheet Rev. 6 — 23 August 2012 13 of 17
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
Fig 14. Package outline SOT338-1 (SSOP16)
UNIT A1A2A3bpcD
(1) E(1) eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.25 0.38
0.25 0.20
0.09 6.4
6.0 5.4
5.2 0.65 1.25
7.9
7.6 1.03
0.63 0.9
0.7 1.00
0.55 8
0
o
o
0.130.2 0.1
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.
SOT338-1 99-12-27
03-02-19
(1)
wM
bp
D
HE
E
Z
e
c
vMA
X
A
y
18
16 9
θ
A
A1
A2
Lp
Q
detail X
L
(A )
3
MO-150
pin 1 index
0 2.5 5 mm
scale
SSOP16: plastic shrink small outline package; 16 leads; body width 5.3 mm SOT338-1
A
max.
2
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Product data sheet Rev. 6 — 23 August 2012 14 of 17
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
14. Abbreviations
15. Revision history
Table 10. Abbreviations
Acronym Description
CMOS Complementary Metal Oxide Semiconductor
DUT Device Under Test
ESD ElectroStatic Discharge
HBM Human Body Model
MM Machine Model
TTL Transistor-Transistor Logic
Table 11. Revision history
Document ID Release date Data sheet status Change notice Supersedes
74HC237 v.6 20120823 Product data sheet - 7 4HC237 v.5
Modifications: •Measurement points added to Figure 7 and Figure 8 (errata).
74HC237 v.5 20111209 Product data sheet - 74HC237 v.4
Modifications: •Legal pages updated.
74HC237 v.4 20110110 Product data sheet - 74HC237 v.3
74HC237 v.3 20041112 Product data sheet - 74HC_HCT237_CNV v.2
74HC_HCT237_CNV v.2 19970828 Product specification - 7 4HC_HCT237 v.1
74HC_HCT237 v.1 19901201 Product specification - -
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Product data sheet Rev. 6 — 23 August 2012 15 of 17
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
16. Legal information
16.1 Data sheet status
[1] Please consult the most recently issued document before initiating or completing a design.
[2] The term ‘short data sheet’ is explained in section “Definitions”.
[3] The product status of de vice(s) descr ibed in th is docume nt may have cha nged since this docume nt was publis hed and ma y dif fer in case of multiple devices. The latest product status
information is available on the Internet at URL http://www.nxp.com.
16.2 Definitions
Draft — The document is a draft version only. The content is still under
internal review and subject to formal approval, which may result in
modifications or additions. NXP Semiconductors does not give any
representations or warranties as to the accuracy or comple teness of
information included herein and shall have no liab ility for the consequences of
use of such information.
Short data sheet — A short data sheet is an extract from a full data sheet
with the same product type number(s) and tit le. A short data sh eet is intended
for quick reference only and shou ld not be rel ied u pon to cont ain det ailed and
full information. For detailed and full information see the relevant full data
sheet, which is available on request via the local NXP Semiconductors sales
office. In case of any inconsistency or conf lict with the short data sheet, the
full data sheet shall pre vail.
Product specificat ion — The information and data provided in a Product
data sheet shall define the specification of the product as agreed between
NXP Semiconductors and its customer, unless NXP Semiconductors and
customer have explicitly agreed otherwise in writing. In no event however,
shall an agreement be valid in which the NXP Semiconductors product is
deemed to off er functions and qualities beyond those described in the
Product data sheet.
16.3 Disclaimers
Limited warr a nty and liability — Information in this document is believed to
be accurate and reliable. However, NXP Semiconductors does not give any
representations or warranties, expressed or implied, as to the accuracy or
completeness of such information and shall have no liability for the
consequences of use of such information. NXP Se miconductors takes no
responsibility for the content in this document if provided by an inf ormation
source outside of NXP Semiconductors.
In no event shall NXP Semiconductors be liable for any indirect, incidenta l ,
punitive, special or consequ ential damages (including - wit hout limitatio n - lost
profits, lost savings, business interruption, costs related to the removal or
replacement of any products or rework charges) whether or not such
damages are based on tort (including negligence), warranty, breach of
contract or any other legal theory.
Notwithstanding any damages that customer might incur for any reason
whatsoever, NXP Semiconduct ors’ aggregate and cumulat ive liability toward s
customer for the products described herein shall be limited in accordance
with the Terms and conditions of commercial sale of NXP Semiconductors.
Right to make changes — NXP Semiconductors reserves the right to make
changes to information published in this document, including without
limitation specifications and product descripti ons, at any time and without
notice. This document supersedes and replaces all informa tion supplied prior
to the publication hereof .
Suitability for use — NXP Semiconductors products are not designed,
authorized or warranted to be suitable for use in life support, life-critical or
safety-critical systems or equipment, nor in applications where failure or
malfunction of an NXP Semiconductors product can reasonably be expected
to result in perso nal injury, death or severe property or environmental
damage. NXP Semiconductors and its suppliers accept no liability for
inclusion and/or use of NXP Semiconducto rs products in such equipment or
applications and ther efore such inclu sion and/or use is at the cu stomer’s own
risk.
Applications — Applications that are described herein for any of these
products are for illustrative purposes only. NXP Semiconductors makes no
representation or warranty tha t such application s will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and ope ration of their applications
and products using NXP Semiconductors product s, and NXP Semiconductors
accepts no liability for any assistance with applications or customer product
design. It is customer’s sole responsibility to determine whether the NXP
Semiconductors product is suit able and fit for the custome r’s applications and
products planned, as well as fo r the planned application and use of
customer’s third party customer(s). Customers should provide appropriate
design and operating safeguards to minimize the risks associate d with t heir
applications and products.
NXP Semiconductors does not accept any liabil ity related to any default,
damage, costs or problem which is based on any weakness or default in the
customer’s applications or products, or the application or use by customer’s
third party customer(s). Customer is responsible for doing all necessary
testing for th e customer’s applications and pro ducts using NXP
Semiconductors products in order to avoid a default of the applications and
the products or of the application or use by customer’s third party
customer(s). NXP does not accept any liability in this respect.
Limiting values — Stress above one or more limiting values (as defined in
the Absolute Maximum Ratings System of IEC 60134) will cause permanent
damage to the device. Limiting values are stress rating s only and (proper)
operation of the device at these or any other conditions above those given in
the Recommended operating conditions section (if present) or the
Characteristics sections of this document is not warranted. Constant or
repeated exposure to limiting values will permanent ly and irreversibly affect
the quality and reliability of the device.
Terms and conditions of commercial sale — NXP Semiconductors
products are sold subject to the general terms and conditions of commercial
sale, as published at http://www.nxp.com/profile/terms, unless otherwise
agreed in a valid written individua l agreement. In case an individual
agreement is concluded only the ter ms and conditions of the respective
agreement shall apply. NXP Semiconductors hereby expressly objects to
applying the customer’s general terms and conditions with regard to the
purchase of NXP Semiconductors products by customer.
No offer to sell or license — Nothing i n this document may be interpreted or
construed as an of fer t o sell product s that is open for accept ance or t he grant,
conveyance or implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Document status[1][2] Product status[3] Definition
Objective [short] data sheet Development This document contain s data from the objective specification for product development.
Preliminary [short] dat a sheet Qualification This document contains data from the preliminary specificat ion.
Product [short] dat a sheet Production This document contains the product specification.
74HC237 All information provided in this document is subject to legal disclaimers. © NXP B.V. 2012. All rights reserved.
Product data sheet Rev. 6 — 23 August 2012 16 of 17
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
Export control — This document as well as the item(s) described herein
may be subject to export control regulations. Export might require a prior
authorization from competent authorities.
Non-automotive qualified products — Unless this data sheet expressly
states that this specific NXP Semiconductors prod uct is automotive qualified,
the product is not suitable for automotive use. It i s neit her qua lified nor tested
in accordance with automotive testing or application requirements. NXP
Semiconductors accepts no liability for inclusion and/or use of
non-automotive qualified products in automotive equipment or applications.
In the event that customer uses the product for design-in and use in
automotive applications to automot ive specifications and standard s, customer
(a) shall use the product without NXP Semiconductors’ warranty of the
product for such automotive applications, use and specifications, and (b)
whenever customer uses the product for automotive applications beyond
NXP Semiconductors’ specifications such use shall be solely at customer’s
own risk, and (c) customer fully indemnifies NXP Semiconductors for any
liability, damages or failed product claims result ing from customer design an d
use of the product for automotive applications beyond NXP Semiconductors’
standard warranty and NXP Semiconductors’ product specifications.
Translations — A non-English (translated) version of a document is for
reference only. The English version shall prevail in case of any discrepancy
between the translated and English versions.
16.4 Trademarks
Notice: All referenced b rands, produc t names, service names and trademarks
are the property of their respect i ve ow ners.
17. Contact information
For more information, please visit: http://www.nxp.com
For sales office addresses, please send an email to: salesaddresses@nxp.com
NXP Semiconductors 74HC237
3-to-8 line decoder, demultiplexer with address latches
© NXP B.V. 2012. All rights reserved.
For more information, please visit: http://www.nxp.co m
For sales office addresses, please send an email to: salesaddresses@nxp.com
Date of release: 23 August 2012
Document identifier: 74HC237
Please be aware that important notices concerning this document and the product(s)
described herein, have been included in section ‘Legal information’.
18. Contents
1 General description. . . . . . . . . . . . . . . . . . . . . . 1
2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1
3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1
4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2
5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3
5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4
6 Functional description . . . . . . . . . . . . . . . . . . . 4
7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4
8 Recommended operating conditions. . . . . . . . 5
9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5
10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6
11 Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
12 Application information. . . . . . . . . . . . . . . . . . 10
13 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 11
14 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14
15 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14
16 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15
16.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15
16.2 Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15
16.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 16
17 Contact information. . . . . . . . . . . . . . . . . . . . . 16
18 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17