Fujitsu’s CS61, a 0.35µm (0.28µm Leff) standard cell
product, is based on the state-of-the-art Fujitsu CMOS
process technology–a process designed for high performance
and high integration. The cell-based design enables the
realization of “system-on-silicon”applications that include
the following:
• User-defined logic
• Sophisticated analog functions
• High-density memory
• Intelligent peripherals
• Cores (including µprocessors and µcontrollers)
The CS61 technology is based on an enhanced 3.3V process
that provides fast performance along with 3.3V power sav-
ings. The CS61 standard cell library is the most aggressive
library for implementing today’s optimal, high-performance
deep submicron systems-on-silicon. The CS61 supports
dense, high-clock frequency system-level designs that meet
the performance, integration, and power management
requirements of networking, telecommunication, electronic
data processing and digital video applications. The library
also supports the most popular third-party tools and data-
exchange file standards.
The core operates at 2V, 2.5V or 3.3V and also in between,
with I/Os operating at 3.3V, 5V and 5V tolerant, or any
combination of these. The core also supports voltages as
low as 1.0V for sensitive, ultra low-power applications.
The CS61 family supports both standard and staggered
I/O pad configurations at 70µm and 100µm pad pitches.
Interface options include low-swing, high-speed I/Os and
CS61 Series Standard Cell
0.28µm Leff
Features
▼
Description
▼
bus interface I/Os. In addition to the traditional QFP
packages, the CS61 family is available in Ball Grid Array
and Flip Chip packages.
CS61 offers a rich set of ADCs and DACs, digital and
analog PLLs, and high-speed RAMs and ROMs, as well
as a variety of other embedded functions.
Design Methodology
Fujitsu’s design methodology ensures first-silicon success by
integrating proprietary point tools with the most popular,
sign-off quality, industry-standard CAD tools. The follow-
ing are among these tools:
• Logic design rule checker
• Delay calculator
• Quasi three-dimensional parasitic extraction tool
Fujitsu’s clock-driven design methodology is devised for
low power and low skew. It identifies the best-suited clock
distribution strategy for a given design and predicts perfor-
mance in advance. Fujitsu supports hardware and software
co-simulation, emulation, and high-level floorplanning to
ease the power, timing and size estimation of the design.
This enables the designer to make effective architectural-
level decisions toward achieving optimal design solutions.
Fujitsu’s design methodology supports cycle-based simula-
tors and formal verification, as well as static timing analysis
and the more conventional VHDL and Verilog simulators.
Fujitsu’s design-for-test strategy includes boundary scan
(JTAG), full and partial scan, as well as a built-in self-test
for memory.
CS61
Dual Power Supply
(5.0V/3.3V)
High-Speed
Devices
T-LVTTL
P-CML
LVDS
SDRAM I/F
SSTL
GTL
ADC/DAC
3.3V
CMOS
AGP USBPCI
AGP Bus USB DevicesPCI Bus
5.0V
Tolerant
High-Speed
Interface
Analog
Interface
3.3V CMOS
3.3V Device
5.0V TTL
5.0V Device
CS61 I/O Interface Capabilities
• 0.28µm effective channel length
• Over 3 million gates
• 0.3µW/gate/MHz power dissipation @ 3.3V
• 3.3V, 5V, 5V tolerant I/O interfaces
• High-performance embedded SRAM
• Analog and digital PPLs
• Powerful mixed-signal offering
• Advanced packaging
• Proven design methodology and tool support
© 1998 Fujitsu Microelectronics, Inc.
All company and product names are trademarks or
registered trademarks of their respective owners.
Printed in the U.S.A. ASIC-FS-20691-7/98
CS61 Series (0.28µm Leff) Standard Cell
Applications
The CS61 series offers integration, performance and very
low-power consumption, in addition to cost-effective, high-
performance, area-optimized memories. High-performance
transmission and switching applications and power-sensitive
applications, such as mobile computing and mobile commu-
nications, can benefit from this technology.
Memory Macros
• SRAM Compiler: single and dual port (1 R/W, 1R),
up to 72K bits per block
• ROM Compiler: up to 512K bits per block
Phase Locked Loops
• Digital: 180 to 360 MHz
• Analog: 50 to 200 MHz
I/Os
• 5V, 3.3V and 5V tolerant
• Slew-rate controlled
• CMOS, TTL, PCML/PECL, LVDS, PCI, SSTL, USB,
GTL+
IPs and Mega Macros
To achieve the highest level of integration for our cus-
tomers, Fujitsu offers a rich set of intellectual properties
(IPs), either developed internally or acquired through
strategic relationships with IP providers.
Interface Functions
• PCI core
• 10/100 Ethernet MAC (under development)
• P1394 (under development)
• USB
High-Performance Functions
• MPEG2 (Q1 ’99)
• 16/64/256 QAM (Q1 ’99)
• QPSK (Q1 ’99)
ASIC Design Kit and EDA Support
Verifire VCS, Verilog-XL,
(VCS, Cadence Tools, Sign-off Simulation, Veritime,
Synopsys Synthesis) Verifault, Design Compiler (Synopsys)
Vhdlfire All vital compliance tools,
Sign-off Simulation, Design Time,
Design Compiler
Other EDA Tools Motive, Sunrise, HLD, DesignPower
PACKAGE AVAILABILITY
No. of Pins Frame Size
QFP Package (1.0, 0.8, 0.65 mm pitch)
64 F10
80 F10
100 F10
120 F10, E7/8/9/15/19/25/35/45
160 E7/8/9/15/19/25/35/45/59,
F20/30/40/50/60/70/80
Shrink QFP Package (0.5 mm pitch)
64 E7/8/9, F10
80 E7/8/9, F10
100 E9/15, F10
120 E7/8/9/15/19/25/35/45, F10
144 E7/8/9/15/19/25/35/45,
F20/30/40/50
176 E8/9/15/19/25/35/45,
F20/30/40/50
208 E9/15/19/25/35/45/59,
F20/30/40/50/60/70/80
240 E15/19/25/35/45/59,
F30/40/50/60/70
256 F40/50/60/70/80
304 F50/60/70/80
256 (0.4 mm) E19/25/35/45/59
Heatspreader QFP Package (0.5 mm pitch)
208 E9/15/19/25/35/45/59/71,
F20/30/40/50/60/70/80
240 E15/19/25/35/45/58/71,
F30/40/50/60/70/80
256 F40/50/60/70/80
304 E35/45/59/71, F50/60/70/80
256 (0.4 mm) E19/25/35/45/59/71
Ball Grid Array (1.27 mm pitch)
256 E15/19, F40/50
352 E25/35, F60/70
420 E35/45, F60/70
576 E45/59
672 E71
FUJITSU MICROELECTRONICS, INC.
Corporate Headquarters
3545 North First Street, San Jose, California 95134-1804
Tel: (800) 866-8608 Fax: (408) 922-9179
E-mail: fmicrc@fmi.fujitsu.com Internet: http://www.fujitsumicro.com
