1
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
REF0
REF0/
VREF0
FB
FB/
VREF2
RxS
REF1
REF1/
VREF1
1Q
1Q
2Q
2Q
3Q
3Q
4Q
4Q
PLL
5Q
5Q
QFB
QFB
PD FS LOCK
PE
PLL_EN
0
1
/N
DS1:0
3 3
REF_SEL
0
1
Divide
Select
1F2:1
Divide
Select
2F2:1
Divide
Select
3F2:1
Divide
Select
4F2:1
Divide
Select
5F2:1
TxS
Divide
Select
FBF2:1
OMODE
PLL
1sOE
2sOE
3sOE
4sOE
5sOE
AUGUST 2012
2012 Integrated Device Technology, Inc. DSC 5982/30c
INDUSTRIAL TEMPERATURE RANGE
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
FEATURES:
• 2.5 VDD
• 6 differential outputs
• Low skew: 100ps all outputs
• Selectable positive or negative edge synchronization
• Tolerant of spread spectrum input clock
• Synchronous output enable
• Selectable inputs
• Input frequency: 4.17MHz to 250MHz
• Output frequency: 12.5MHz to 250MHz
• 1.8V / 2.5V LVTTL: up to 250MHz
• HSTL / eHSTL: up to 250MHz
• Hot insertable and over-voltage tolerant inputs
• 3-level inputs for selectable interface
• 3-level inputs for feedback divide selection with multiply ratios
of(1-6, 8, 10, 12)
• Selectable HSTL, eHSTL, 1.8V/2.5V LVTTL, or LVEPECL input
interface
• Selectable differential or single-ended inputs and six differen-
tial outputs
• PLL bypass for DC testing
• External differential feedback, internal loop filter
• Low Jitter: <75ps cycle-to-cycle
• Power-down mode
• Lock indicator
• Available in BGA and VFQFPN package
FUNCTIONAL BLOCK DIAGRAM
IDT5T2110
NRND
2.5V ZERO DELAY PLL DIFFERENTIAL
CLOCK DRIVER TERACLOCK™
Not Recommended for New Designs
DESCRIPTION:
The IDT5T2110 is a 2.5V PLL differential clock driver intended for high
performance computing and data-communications applications. The
IDT5T2110 has six differential outputs in six banks, including a dedicated
differential feedback. The redundant input capability allows for a smooth
change over to a secondary clock source when the primary clock source
is absent.
The feedback bank allows divide-by-functionality from 1 to 12 through
the use of the DS[1:0] inputs. This provides the user with frequency
multiplication 1 to 12 without using divided outputs for feedback. Each output
bank also allows for a divide-by functionality of 2 or 4.
The 5T2110 features a user-selectable, single-ended or differential input to
six differential outputs. The differential clock driver also acts as a translator from
a differential HSTL, eHSTL, 1.8V/2.5V LVTTL, LVEPECL, or single-ended
1.8V/2.5V LVTTL input to HSTL, eHSTL, or 1.8V/2.5V LVTTL outputs.
Selectable interface is controlled by 3-level input signals that may be hard-wired
to appropriate high-mid-low levels. The differential outputs can be synchro-
nously enabled/disabled.
Furthermore, when PE is held high, all the outputs are synchronized with
the positive edge of the REF clock input. When PE is held low, all the outputs
are synchronized with the negative edge of REF.
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INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
PIN CONFIGURATION
BGA
TOP VIEW
A A
1F2VDD GND
1sOE 1Q1QGND 2Q2Q2sOE 2F2VDDQ
B B
VDDVDD 1F1GND GND 2F1VDD NC NC VDDQ VDDQ 3F2
C C
VDDOMODE VDD VDD GND GND GND GND VDDQ VDDQ 3sOE
D
E
F
G
H
J
K
L
M
D
E
F
G
H
J
K
L
M
12345678910 11 12
12
REF1
/VREF1
REF0
/VREF0
FB
/VREF2
PLL_
EN
GND
TxS
VDD
VDD
DS0
3456789
10 11 12
REF_
SEL
REF1
PD
RxS
LOCK
VDD
DS1
FB
REF0
NC
3F1
VDDQ
VDDQ
4F1
NC
3Q
3Q
VDDQ
VDDQ
4Q
4Q
FBF1GND GND 5F1
FS
FBF2
VDD
NC
VDD
VDD
PE
VDD
VDD VDD
VDD
VDD
VDD
VDD
VDD
VDD
NC
QFB QFB GND GND 5Q5Q
NC
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
GND
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
5sOE
VDDQ
VDDQ
5F2
4sOE
4F2
VDDQ
GND
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
VDDQ
3
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
PIN CONFIGURATION
VFQFPN
TOP VIEW
2
F
1
V
DDQ
V
DD
1
F
1
1
F
2
1
Q
1
sOE
V
DD
OMODE
68
67
66
65
64
63
62
61
60
59
V
DDQ
2
F
2
2
Q
2
sOE
V
DDQ
V
DDQ
2
Q
58
57
56
55
54
53
52
1
Q
20
21
22
23
24
25
26
27
V
DDQ
FS
FBF
2
QFB
FBF
1
V
DDQ
QFB
V
DD
18
19
DS
1
DS
0
28
29
30
31
32
33
34
5
Q
5
F
1
5
Q
5
sOE
5
F
2
V
DDQ
V
DDQ
3sOE
3F2
VDDQ
VDDQ
3Q
51
50
49
48
47
46
45
44
43
42
3Q
VDD
4F1
VDD
3F1
4Q
4Q
VDDQ
41
40
39
38
37
36
35
VDDQ
4F2
VDD
4sOE
REF_SEL
VDD
REF1
FB
REF1/VREF1
REF0
REF0/VREF0
2
3
4
5
6
7
1
PE
FB/VREF2 8
9
10
VDD
PD
PLL_EN
VDD
VDD
RxS
TxS
LOCK
12
13
14
15
16
17
11
GND
4
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
Symbol Description Max Unit
VDDQ, VDD Power Supply Voltage(2) –0.5 to +3.6 V
VIInput Voltage –0.5 to +3.6 V
VOOutput Voltage –0.5 to VDDQ +0.5 V
VREF Reference Voltage(3) –0.5 to +3.6 V
TJJunction Temperature 1 5 0 °C
TSTG Storage Temperature –65 to +165 °C
ABSOLUTE MAXIMUM RATINGS(1)
NOTES:
1 . Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause
permanent damage to the device. This is a stress rating only and functional operation
of the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect reliability.
2. VDDQ and VDD internally operate independently. No power sequencing requirements
need to be met.
3. Not to exceed 3.6V.
PIN DESCRIPTION
Symbol I/O Type Description
REF[1:0] I Adjustable(1) Clock input. REF[1:0] is the "true" side of the differential clock input. If operating in single-ended mode, REF[1:0] is the clock input.
REF[1:0]/ I Adjustable(1) Complementary clock input. REF[1:0]/VREF[1:0] is the "complementary" side of REF[1:0] if the input is in differential mode. If operating
VREF[1:0] in single-ended mode, REF[1:0]/VREF[1:0] is left floating. For single-ended operation in differential mode, REF[1:0]/VREF[1:0] should be set
to the desired toggle voltage for REF[1:0]:
2.5V LVTTL VREF = 1250mV (SSTL2 compatible)
1.8V LVTTL, eHSTL VREF = 900mV
HSTL VREF = 750mV
LVEPECL VREF = 1082mV
FB I Adjustable(1) Clock input. FB is the "true" side of the differential feedback clock input. If operating in single-ended mode, FB is the differential feedback
clock input.
FB/VREF2I Adjustable(1) Complementary feedback clock input. FB/VREF2 is the "complementary" side of FB if the input is in differential mode. If operating in single-
ended mode, FB/VREF2 is left floating. For single-ended operation in differential mode, FB/VREF2 should be set to the desired toggle voltage
for FB: 2.5V LVTTL VREF = 1250mV (SSTL2 compatible)
1.8V LVTTL, eHSTL VREF = 900mV
HSTL VREF = 750mV
LVEPECL VREF = 1082mV
NOTE:
1. Inputs are capable of translating the following interface standards. User can select between:
Single-ended 2.5V LVTTL levels
Single-ended 1.8V LVTTL levels
or
Differential 2.5V/1.8V LVTTL levels
Differential HSTL and eHSTL levels
Differential LVEPECL levels
Symbol Description Min. Typ. Max. Unit
TAAmbient Operating Temperature –40 +25 +85 °C
VDD(1) Internal Power Supply Voltage 2.3 2.5 2.7 V
HSTL Output Power Supply Voltage 1.4 1.5 1.6 V
VDDQ(1) Extended HSTL and 1.8V LVTTL Output Power Supply Voltage 1.65 1.8 1.95 V
2.5V LVTTL Output Power Supply Voltage VDD V
VTTermination Voltage VDDQ / 2 V
RECOMMENDED OPERATING RANGE
NOTE:
1. All power supplies should operate in tandem. If VDD or VDDQ is at maximum, then VDDQ or VDD (respectively) should be at maximum, and vice-versa.
NOTE:
1. Capacitance applies to all inputs except RxS, TxS, nF[2:1], FBF[2:1],and DS[1:0].
CAPACITANCE(TA = +25°C, f = 1MHz, VIN = 0V)
Parameter Description Min. Typ. Max. Unit
CIN Input Capacitance 2.5 3 3.5 pF
COUT Output Capacitance — 6.3 7 pF
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INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
PIN DESCRIPTION, CONTINUED
Symbol I/O Type Description
REF_SEL I LVTTL(1) Reference clock select. When LOW, selects REF0 and REF0/VREF0. When HIGH, selects REF1 and REF1/VREF1.
nsOE I LVTTL(1) Synchronous output enable. When nsOE is HIGH, nQ and nQ are synchronously stopped. OMODE selects whether the outputs are
gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/HIGH,
the nQ is stopped in a HIGH/LOW state, while the nQ is stopped at a LOW/HIGH state. When OMODE is LOW, the outputs are tri-
stated. Set nsOE LOW for normal operation.
QFB O Adjustable(2) Feedback clock output
QFB O Adjustable(2) Complementary feedback clock output
nQ O Adjustable(2) Clock outputs
nQ O Adjustable(2) Complementary clock outputs
RxS I 3-Level(3) Selects single-ended 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) REF clock input or differential (LOW) REF clock input
TxS I 3-Level(3) Sets the drive strength of the output drivers and feedback inputs to be 2.5V LVTTL (HIGH), 1.8V LVTTL (MID) or eHSTL/HSTL (LOW)
compatible. Used in conjuction with VDDQ to set the interface levels.
PE I LVTTL(1) Selectable positive or negative edge control. When LOW/HIGH the outputs are synchronized with the negative/positive edge of the reference
clock (has internal pull-up).
nF[2:1] I LVTTL(1) Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on each bank. (See Control Summary table.)
FBF[2:1] I LVTTL(1) Function select inputs for divide-by-2, divide-by-4, zero delay, or invert on the feedback bank (See Control Summary table)
FS I LVTTL(1) Selects appropriate oscillator circuit based on anticipated frequency range (See VCO Frequency Range Select table)
DS[1:0] I 3-Level(3) 3-level inputs for feedback input divider selection (See Divide Selection table)
PLL_EN I LVTTL(1) PLL enable/disable control. Set LOW for normal operation. When PLL_EN is HIGH, the PLL is disabled and REF[1:0] goes to all outputs.
PD I LVTTL(1) Power down control. When PD is LOW, the inputs are disabled and internal switching is stopped. OMODE selects whether the outputs
are gated LOW/HIGH or tri-stated. When OMODE is HIGH, PE determines the level at which the outputs stop. When PE is LOW/
HIGH, the nQ and QFB are stopped in a HIGH/LOW state, while the nQ and QFB are stopped in a LOW/HIGH state. When OMODE
is LOW, the outputs are tri-stated. Set PD HIGH for normal operation.
LOCK O LVTTL PLL lock indication signal. HIGH indicates lock. LOW indicates that the PLL is not locked and outputs may not be synchronized to the
inputs. The output will be 2.5V LVTTL. (For more information on application specific use of the LOCK pin, please see AN237.)
OMODE I LVTTL(1) Output disable control. Determines the outputs' disable state. Used in conjunction with nsOE and PD. (See Output Enable/Disable and
Powerdown tables.)
VDDQ PWR Power supply for output buffers. When using 2.5V LVTTL, VDDQ should be connected to VDD.
VDD PWR Power supply for phase locked loop, lock output, inputs, and other internal circuitry
GND PWR Ground
VCO FREQUENCY RANGE SELECT
FS(1) Min. Max. Unit
LOW 50 125 MHz
HIGH 100 250 MHz
NOTE:
1 . PE determines the level at which the outputs stop. When PE is LOW/HIGH, the nQ
is stopped in a HIGH/LOW state while the nQ is stopped at a LOW/HIGH state.
OUTPUT ENABLE/DISABLE
nsOE OMODE Output
L X Normal Operation
H L Tri-State
H H Gated(1)
NOTE:
1 . PE determines the level at which the outputs stop. When PE is LOW/HIGH, the nQ
and QFB are stopped in a HIGH/LOW state, while the nQ and QFB are stopped in a
LOW/HIGH state.
POWERDOWN
PD OMODE Output
H X Normal Operation
L L Tri-State
L H Gated(1)
NOTE:
1. The level to be set on FS is determined by the nominal operating frequency of the
VCO. The VCO frequency (FNOM) always appears at nQ and nQ outputs when they
are operated in their undivided modes. The frequency appearing at the REF[1:0] and
REF[1:0] /VREF[1:0] and FB and FB/VREF2 inputs will be FNOM when the QFB and QFB
are undivided and DS[1:0] = MM. The frequency of REF[1:0] and REF[1:0] /VREF[1:0]
and FB and FB/VREF2 inputs will be FNOM/2 or FNOM/4 when the part is configured for
frequency multiplication by using a divided QFB and QFB and setting DS[1:0] = MM.
Using the DS[1:0] inputs allows a different method for frequency multiplication (see
Divide Selection table).
NOTES:
1. Pins listed as LVTTL inputs will accept 2.5V signals under all conditions. If the output is operating at 1.8V or 1.5V, the LVTTL inputs will accept 1.8V LVTTL signals as well.
2. Outputs are user selectable to drive 2.5V, 1.8V LVTTL, eHSTL, or HSTL interface levels when used with the appropriate VDDQ voltage.
3. 3-level inputs are static inputs and must be tied to VDD or GND or left floating. These inputs are not hot-insertable or over voltage tolerant.
6
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
DIVIDE SELECTION TABLE
DS [1:0] Divide-by-n Permitted Output Divide-by-n connected to FB and FB/VREF2(1)
LL 2 1, 2
LM 3 1
LH 4 1, 2
ML 5 1, 2
MM 1 1, 2, 4
MH 6 1, 2
HL 8 1
HM 10 1
HH 12 1
NOTE:
1. Permissible output division ratios connected to FB and FB/VREF2. The frequencies of the REF[1:0] and REF[1:0]/VREF[1:0] inputs will be FNOM/N when the parts are configured for
frequency multiplication by using an undivided output for FB and FB/VREF2 and setting DS[1:0] to N (N = 1-6, 8, 10, 12).
EXTERNAL DIFFERENTIAL FEEDBACK
By providing a dedicated external differential feedback, the IDT5T2110
gives users flexibility with regard to divide selection. The FB and FB/
VREF2 signals are compared with the input REF[1:0] and REF[1:0]/VREF[1:0]
signals at the phase detector in order to drive the VCO. Phase differ-
ences cause the VCO of the PLL to adjust upwards or downwards
accordingly.
An internal loop filter moderates the response of the VCO to the
phase detector. The loop filter transfer function has been chosen to
provide minimal jitter (or frequency variation) while still providing accu-
rate responses to input frequency changes.
CONTROL SUMMARY TABLE FOR ALL
OUTPUTS
nF2/FBF2nF1/FBF1Output Skew
L L Divide by 2
L H Zero Delay
H L Inverted
H H Divide by 4
7
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
INPUT/OUTPUT SELECTION(1)
Input Output
2.5V LVTTL SE 2.5V LVTTL
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
2.5V LVTTL SE 1.8V LVTTL
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
Input Output
2.5V LVTTL SE eHSTL
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
2.5V LVTTL SE HSTL
1.8V LVTTL SE
2.5V LVTTL DSE
1.8V LVTTL DSE
LVEPECL DSE
eHSTL DSE
HSTL DSE
2.5V LVTTL DIF
1.8V LVTTL DIF
LVEPECL DIF
eHSTL DIF
HSTL DIF
NOTE:
1. The INPUT/OUTPUT SELECTION Table describes the total possible combinations of input and output interfaces. Single-Ended (SE) inputs in a single-ended mode require the
REF[1:0]/VREF[1:0] and FB/VREF2 pins to be left floating. Differential Single-Ended (DSE) is for single-ended operation in differential mode, requiring V REF[1:0] and VREF2. Differential
(DIF) inputs are used only in differential mode.
NOTE:
1. These inputs are normally wired to VDD, GND, or left floating. Internal termination resistors bias unconnected inputs to VDD/2. If these inputs are switched dynamically after powerup,
the function and timing of the outputs may be glitched, and the PLL may require additional tLOCK time before all datasheet limits are achieved.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol Parameter Test Conditions Min. Max Unit
VIHH Input HIGH Voltage Level(1) 3-Level Inputs Only VDD – 0.4 — V
VIMM Input MID Voltage Level(1) 3-Level Inputs Only VDD/2 – 0.2 VDD/2 + 0.2 V
VILL Input LOW Voltage Level(1) 3-Level Inputs Only — 0.4 V
VIN = VDD HIGH Level — 200
I33-Level Input DC Current VIN = VDD/2 MID Level –50 +50 μA
(RxS, TxS, DS[1:0])VIN = GND LOW Level –200 —
IPU Input Pull-Up Current (PE) VDD = Max., VIN = GND –100 — μA
8
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
DC ELECTRICAL CHARACTERISTICS OVER OPERA TING RANGE FOR HSTL(1)
Symbol Parameter Test Conditions Min. Typ.(7) Max Unit
Input Characteristics
IIH Input HIGH Current VDD = 2.7V VI = VDDQ/GND — — ±5 μA
IIL Input LOW Current VDD = 2.7V VI = GND/VDDQ ——±5
VIK Clamp Diode Voltage VDD = 2.3V, IIN = -18mA — - 0.7 - 1.2 V
VIN DC Input Voltage - 0.3 +3.6 V
VDIF DC Differential Voltage(2,8) 0.2 — V
VCM DC Common Mode Input Voltage(3,8) 680 750 900 mV
VIH DC Input HIGH(4,5,8) VREF + 100 — mV
VIL DC Input LOW(4,6,8) —VREF - 100 mV
VREF Single-Ended Reference Voltage(4,8) — 750 — mV
Output Characteristics
VOH Output HIGH Voltage IOH = -8mA VDDQ - 0.4 — V
IOH = -100μAVDDQ - 0.1 —
VOL Output LOW Voltage IOL = 8mA — 0.4 V
IOL = 100μA — 0.1
VOX Qn/Qn and FB/FB Output Crossing Point VDDQ/2 - 150 VDDQ/2 VDDQ/2 + 150 mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.5V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
9
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
POWER SUPPL Y CHARACTERISTICS FOR HSTL OUTPUTS(1)
Symbol Parameter Test Conditions(2) Typ. Max Unit
IDDQ Quiescent VDD Power Supply Current(3) VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW, 15 25 mA
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
IDDQQ Quiescent VDDQ Power Supply Current(3) VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW, 0.7 50 μA
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
IDDPD Power Down Current VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH 0.8 3 mA
IDDD Dynamic VDD Power Supply VDD = Max., VDDQ = Max., CL = 0pF 13 20 μA/MHz
Current per Output
IDDDQ Dynamic VDDQ Power Supply VDD = Max., VDDQ = Max., CL = 0pF 16 25 μA/MHz
Current per Output
ITOT Total Power VDD Supply Current(4) VDDQ = 1.5V, FVCO = 100MHz, CL = 15pF 35 55 m A
VDDQ = 1.5V, FVCO = 250MHz, CL = 15pF 55 85
ITOTQ Total Power VDDQ Supply Current(4) VDDQ = 1.5V, FVCO = 100MHz, CL = 15pF 45 70 m A
VDDQ = 1.5V, FVCO = 250MHz, CL = 15pF 80 120
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3 . If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4 . FS = HIGH.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR HSTL
Symbol Parameter Value Units
VDIF Input Signal Swing(1) 1V
VXDifferential Input Signal Crossing Point(2) 750 mV
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR, tFInput Signal Edge Rate(4) 1 V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2 . A 750mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
10
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR eHSTL(1)
Symbol Parameter Test Conditions Min. Typ.(7) Max Unit
Input Characteristics
IIH Input HIGH Current VDD = 2.7V VI = VDDQ/GND — — ±5 μA
IIL Input LOW Current VDD = 2.7V VI = GND/VDDQ ——±5
VIK Clamp Diode Voltage VDD = 2.3V, IIN = -18mA — - 0.7 - 1.2 V
VIN DC Input Voltage - 0.3 +3.6 V
VDIF DC Differential Voltage(2,8) 0.2 — V
VCM DC Common Mode Input Voltage(3,8) 800 900 1000 mV
VIH DC Input HIGH(4,5,8) VREF + 100 — mV
VIL DC Input LOW(4,6,8) —VREF - 100 mV
VREF Single-Ended Reference Voltage(4,8) — 900 — mV
Output Characteristics
VOH Output HIGH Voltage IOH = -8mA VDDQ - 0.4 — V
IOH = -100μAVDDQ - 0.1 — V
VOL Output LOW Voltage IOL = 8mA — 0.4 V
IOL = 100μA — 0.1 V
VOX Qn/Qn and FB/FB Output Crossing Point VDDQ/2 - 150 VDDQ/2 VDDQ/2 + 150 mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation, in a differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
6. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
7. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
8. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
POWER SUPPL Y CHARACTERISTICS FOR eHSTL OUTPUTS(1)
Symbol Parameter Test Conditions(2) Typ. Max Unit
IDDQ Quiescent VDD Power Supply Current(3) VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW, 15 25 m A
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
IDDQQ Quiescent VDDQ Power Supply Current(3) VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW, 1.7 50 μA
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
IDDPD Power Down Current VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH 0.8 3 mA
IDDD Dynamic VDD Power Supply VDD = Max., VDDQ = Max., CL = 0pF 13 20 μA/MHz
Current per Output
IDDDQ Dynamic VDDQ Power Supply VDD = Max., VDDQ = Max., CL = 0pF 20 30 μA/MHz
Current per Output
ITOT Total Power VDD Supply Current(4) VDDQ = 1.8V, FVCO = 100MHz, CL = 15pF 35 55 mA
VDDQ = 1.8V, FVCO = 250MHz, CL = 15pF 55 85
ITOTQ Total Power VDDQ Supply Current(4) VDDQ = 1.8V, FVCO = 100MHz, CL = 15pF 50 75 m A
VDDQ = 1.8V, FVCO = 250MHz, CL = 15pF 115 175
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3 . If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4 . FS = HIGH
11
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR eHSTL
Symbol Parameter Value Units
VDIF Input Signal Swing(1) 1V
VXDifferential Input Signal Crossing Point(2) 900 mV
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR, tFInput Signal Edge Rate(4) 1 V/ns
NOTES:
1. The 1V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2 . A 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification under
actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR
LVEPECL(1)
Symbol Parameter Test Conditions Min. Typ.(2) Max Unit
Input Characteristics
IIH Input HIGH Current VDD = 2.7V VI = VDDQ/GND — — ±5 μA
IIL Input LOW Current VDD = 2.7V VI = GND/VDDQ ——±5
VIK Clamp Diode Voltage VDD = 2.3V, IIN = -18mA — - 0.7 - 1.2 V
VIN DC Input Voltage - 0.3 — 3.6 V
VCM DC Common Mode Input Voltage(3,5) 915 1082 1248 mV
VREF Single-Ended Reference Voltage(4,5) — 1082 — mV
VIH DC Input HIGH 1275 — 1620 mV
VIL DC Input LOW 5 55 — 8 7 5 mV
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. Typical values are at VDD = 2.5V, +25°C ambient.
3. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
4. For single-ended operation while in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
5. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
12
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR LVEPECL
Symbol Parameter Value Units
VDIF Input Signal Swing(1) 732 mV
VXDifferential Input Signal Crossing Point(2) 1082 mV
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR, tFInput Signal Edge Rate(4) 1 V/ns
NOTES:
1 . The 732mV peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC)
specification under actual use conditions.
2. A 1082mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 2.5V
LVTTL(1)
Symbol Parameter Test Conditions Min. Typ.(8) Max Unit
Input Characteristics
IIH Input HIGH Current VDD = 2.7V VI = VDDQ/GND — — ±5 μA
IIL Input LOW Current VDD = 2.7V VI = GND/VDDQ ——±5
VIK Clamp Diode Voltage VDD = 2.3V, IIN = -18mA — - 0.7 - 1.2 V
VIN DC Input Voltage - 0.3 +3.6 V
Single-Ended Inputs(2)
VIH DC Input HIGH 1.7 — V
VIL DC Input LOW — 0 .7 V
Differential Inputs
VDIF DC Differential Voltage(3,9) 0.2 — V
VCM DC Common Mode Input Voltage(4,9) 1150 1250 1350 mV
VIH DC Input HIGH(5,6,9) VREF + 100 — mV
VIL DC Input LOW(5,7,9) —VREF - 100 mV
VREF Single-Ended Reference Voltage(5,9) — 1250 — mV
Output Characteristics
VOH Output HIGH Voltage IOH = -12mA VDDQ - 0.4 — V
IOH = -100μAVDDQ - 0.1 — V
VOL Output LOW Voltage IOL = 12mA — 0.4 V
IOL = 100μA — 0.1 V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 2.5V LVTTL single-ended operation, the RxS pin is tied HIGH and REF[1:0]/VREF[1:0] is left floating. If TxS is HIGH, FB/VREF2 should be left floating.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5. For single-ended operation, in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0].
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = VDD, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
13
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 2.5V LVTTL
Symbol Parameter Value Units
VIH Input HIGH Voltage VDD V
VIL Input LOW Voltage 0V
VTHI Input Timing Measurement Reference Level(1) VDD/2 V
tR, tFInput Signal Edge Rate(2) 2 V/ns
NOTES:
1. A nominal 1.25V timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
2. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 2.5V LVTTL
Symbol Parameter Value Units
VDIF Input Signal Swing(1) VDD V
VXDifferential Input Signal Crossing Point(2) VDD/2 V
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR, tFInput Signal Edge Rate(4) 2.5 V/ns
NOTES:
1. A nominal 2.5V peak-to-peak input pulse level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VDIF
(AC) specification under actual use conditions.
2 . A nominal 1.25V crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 2.5V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
POWER SUPPL Y CHARACTERISTICS FOR 2.5V LVTTL OUTPUTS(1)
Symbol Parameter Test Conditions(2) Typ. Max Unit
IDDQ Quiescent VDD Power Supply Current(3) VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW, 15 25 mA
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
IDDQQ Quiescent VDDQ Power Supply Current(3) VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW, 12 50 μA
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
IDDPD Power Down Current VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH 0.5 3 mA
IDDD Dynamic VDD Power Supply VDD = Max., VDDQ = Max., CL = 0pF 15 25 μA/MHz
Current per Output
IDDDQ Dynamic VDDQ Power Supply VDD = Max., VDDQ = Max., CL = 0pF 30 40 μA/MHz
Current per Output
ITOT Total Power VDD Supply Current(4) VDDQ = 2.5V., FVCO = 100MHz, CL = 15pF 40 60 m A
VDDQ = 2.5V., FVCO = 250MHz, CL = 15pF 60 90
ITOTQ Total Power VDDQ Supply Current(4) VDDQ = 2.5V., FVCO = 100MHz, CL = 15pF 80 120 m A
VDDQ = 2.5V., FVCO = 250MHz, CL = 15pF 200 300
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3 . If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4 . FS = HIGH.
14
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR 1.8V
LVTTL(1)
Symbol Parameter Test Conditions Min. Typ.(8) Max Unit
Input Characteristics
IIH Input HIGH Current VDD = 2.7V VI = VDDQ/GND — — ±5 μA
IIL Input LOW Current VDD = 2.7V VI = GND/VDDQ ——±5
VIK Clamp Diode Voltage VDD = 2.3V, IIN = -18mA — - 0.7 - 1.2 V
VIN DC Input Voltage - 0.3 VDDQ + 0.3 V
Single-Ended Inputs(2)
VIH DC Input HIGH 1.073(10) —V
VIL DC Input LOW — 0.683(11) V
Differential Inputs
VDIF DC Differential Voltage(3,9) 0.2 — V
VCM DC Common Mode Input Voltage(4,9) 825 900 975 mV
VIH DC Input HIGH(5,6,9) VREF + 100 — mV
VIL DC Input LOW(5,7,9) —VREF - 100 mV
VREF Single-Ended Reference Voltage(5,9) — 900 — mV
Output Characteristics
VOH Output HIGH Voltage IOH = -6mA VDDQ - 0.4 — V
IOH = -100μAVDDQ - 0.1 — V
VOL Output LOW Voltage IOL = 6mA — 0.4 V
IOL = 100μA — 0.1 V
NOTES:
1. See RECOMMENDED OPERATING RANGE table.
2. For 1.8V LVTTL single-ended operation, the RxS pin is MID and REF[1:0]/VREF[1:0] is left floating. If TxS is MID, FB/VREF2 should be left floating.
3. VDIF specifies the minimum input differential voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level. Differential mode
only. The DC differential voltage must be maintained to guarantee retaining the existing HIGH or LOW input. The AC differential voltage must be achieved to guarantee switching
to a new state.
4. VCM specifies the maximum allowable range of (VTR + VCP) /2. Differential mode only.
5 . For single-ended operation in differential mode, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. The input is guaranteed to toggle within ±200mV of VREF[1:0] when VREF[1:0]
is constrained within +600mV and VDDI-600mV, where VDDI is the nominal 1.8V power supply of the device driving the REF[1:0] input. To guarantee switching in voltage range
specified in the JEDEC 1.8V LVTTL interface specification, VREF[1:0] must be maintained at 900mV with appropriate tolerances.
6. Voltage required to maintain a logic HIGH, single-ended operation in differential mode.
7. Voltage required to maintain a logic LOW, single-ended operation in differential mode.
8. Typical values are at VDD = 2.5V, VDDQ = 1.8V, +25°C ambient.
9. The reference clock input is capable of HSTL, eHSTL, LVEPECL, 1.8V or 2.5V LVTTL operation independent of the device output. (See Input/Output Selection table.)
10.This value is the worst case minimum VIH over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIH = 0.65 * VDD where VDD is 1.8V ± 0.15V.
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated
worst case value ( VIH = 0.65 * [1.8 - 0.15V]) rather than reference against a nominal 1.8V supply.
11.This value is the worst case maximum VIL over the specification range of the 1.8V power supply. The 1.8V LVTTL specification is VIL = 0.35 * VDD where VDD is 1.8V ± 0.15V.
However, the LVTTL translator is supplied by a 2.5V nominal supply on this part. To ensure compliance with the specification, the translator was designed to accept the calculated
worst case value ( VIL = 0.35 * [1.8 + 0.15V]) rather than reference against a nominal 1.8V supply.
15
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
SINGLE-ENDED INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol Parameter Value Units
VIH Input HIGH Voltage(1) VDDI V
VIL Input LOW Voltage 0V
VTHI Input Timing Measurement Reference Level(2) VDDI/2 mV
tR, tFInput Signal Edge Rate(3) 2 V/ns
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input.
2. A nominal 900mV timing measurement reference level is specified to allow constant, repeatable results in an automatic test equipment (ATE) environment.
3. The input signal edge rate of 2V/ns or greater is to be maintained in the 10% to 90% range of the input waveform.
DIFFERENTIAL INPUT AC TEST CONDITIONS FOR 1.8V LVTTL
Symbol Parameter Value Units
VDIF Input Signal Swing(1) VDDI V
VXDifferential Input Signal Crossing Point(2) VDDI/2 mV
VTHI Input Timing Measurement Reference Level(3) Crossing Point V
tR, tFInput Signal Edge Rate(4) 1.8 V/ns
NOTES:
1. VDDI is the nominal 1.8V supply (1.8V ± 0.15V) of the part or source driving the input. A nominal 1.8V peak-to-peak input pulse level is specified to allow consistent, repeatable
results in an automatic test equipment (ATE) environment. This device meets the VDIF (AC) specification under actual use conditions.
2 . A nominal 900mV crossing point level is specified to allow consistent, repeatable results in an automatic test equipment (ATE) environment. This device meets the VX specification
under actual use conditions.
3. In all cases, input waveform timing is marked at the differential cross-point of the input signals.
4. The input signal edge rate of 1.8V/ns or greater is to be maintained in the 20% to 80% range of the input waveform.
POWER SUPPL Y CHARACTERISTICS FOR 1.8V LVTTL OUTPUTS(1)
Symbol Parameter Test Conditions(2) Typ. Max Unit
IDDQ Quiescent VDD Power Supply Current(3) VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW, 15 25 mA
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
IDDQQ Quiescent VDDQ Power Supply Current(3) VDDQ = Max., REF = LOW, PD = HIGH, nSOE = LOW, 1.5 50 μA
PLL_EN = HIGH, DS[1:0] = MM, nF[2:1] = LH,
FBF[2:1] = LH, Outputs enabled, All outputs unloaded
IDDPD Power Down Current VDD = Max., PD = LOW, nSOE = LOW, PLL_EN = HIGH 0.5 3 mA
IDDD Dynamic VDD Power Supply VDD = Max., VDDQ = Max., CL = 0pF 16 25 μA/MHz
Current per Output
IDDDQ Dynamic VDDQ Power Supply VDD = Max., VDDQ = Max., CL = 0pF 22 30 μA/MHz
Current per Output
ITOT Total Power VDD Supply Current(4) VDDQ = 1.8V., FVCO = 100MHz, CL = 15pF 40 60 m A
VDDQ = 1.8V., FVCO = 250MHz, CL = 15pF 70 105
ITOTQ Total Power VDDQ Supply Current(4) VDDQ = 1.8V., FVCO = 100MHz, CL = 15pF 55 85 m A
VDDQ = 1.8V., FVCO = 250MHz, CL = 15pF 135 205
NOTES:
1. These power consumption characteristics are for all the valid input interfaces and cover the worst case input and output interface combinations.
2. The termination resistors are excluded from these measurements.
3 . If the differential input interface is used, the true input is held LOW and the complementary input is held HIGH.
4 . FS = HIGH.
16
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
AC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Symbol Parameter Min. Typ. Max Unit
FNOM VCO Frequency Range see VCO Frequency Range Select Table
tRPW Reference Clock Pulse Width HIGH or LOW 1 — — n s
tFPW Feedback Input Pulse Width HIGH or LOW 1 — — n s
tSK(O) Output Skew (Rise-Rise, Fall-Fall, Nominal)(1,2) — — 100 ps
tSK1(ω) Multiple Frequency Skew (Rise-Rise, Fall-Fall, Nominal-Divided, Divided-Divided)(1,2,3) — — 100 ps
tSK2(ω) Multiple Frequency Skew (Rise-Fall, Nominal-Divided, Divided-Divided)(1,2,3) — — 300 ps
tSK1(INV) Inverting Skew (Nominal-Inverted)(1,2) ——300 ps
tSK2(INV) Inverting Skew (Rise-Rise, Fall-Fall, Rise-Fall, Inverted-Divided)(1,2,3) — — 300 ps
tSK(PR) Process Skew(1,2,4) ——300 ps
t(φ) REF Input to FB Static Phase Offset(5) -100 — 100 ps
tODCV Output Duty Cycle Variation from 50%(11,12) 1.8V LVTTL -375 — 375 ps
2.5V LVTTL -275 — 275
tORISE Output Rise Time(6) HSTL / eHSTL / 1.8V LVTTL — — 1. 2 n s
2.5V LVTTL — — 1
tOFALL Output Fall Time(6) HSTL / eHSTL / 1.8V LVTTL — — 1. 2 n s
2.5V LVTTL — — 1
tLPower-up PLL Lock Time(7) —— 1ms
tL(ω) PLL Lock Time After Input Frequency Change(7) —— 1ms
tL(PD) PLL Lock Time After Asserting PD Pin(7) —— 1ms
tL(REFSEL1) PLL Lock Time After Change in REF_SEL(7,9) — — 100 μs
tL(REFSEL2) PLL Lock Time After Change in REF_SEL (REF1 and REF0 are different frequency)(7) —— 1ms
tJIT(CC) Cycle-to-Cycle Output Jitter (peak-to-peak)(2,8) —50 75 ps
tJIT(PER) Period Jitter (peak-to-peak)(2,8) ——75 ps
tJIT(HP) Half Period Jitter (peak-to-peak)(2,8,10) ——125 ps
tJIT(DUTY) Duty Cycle Jitter (peak-to-peak)(2,8) ——100 ps
VOX HSTL and eHSTL Differential True and Complementary Output Crossing Voltage Level VDDQ/2 - 150 VDDQ/2 VDDQ/2 + 150 mV
NOTES:
1. Skew is the time between the earliest and latest output transition among all outputs when all outputs are loaded with the specified load.
2. For differential LVTTL outputs, the measurement is made at VDDQ/2, where the true outputs are only compared with other true outputs and the complementary outputs are only
compared to other complementary outputs. For differential HSTL/eHSTL outputs, the measurement is made at the crossing point (VOX) of the true and complementary signals.
3. There are three classes of outputs: nominal (zero delay), inverted, and divided (divide-by-2 or divide-by-4 mode).
4. tSK(PR) is the output to corresponding output skew between any two devices operating under the same conditions (VDD and VDDQ, ambient temperature, air flow, etc.).
5. t(φ) is measured with REF and FB the same type of input, the same rise and fall times. For TxS/RxS = MID or HIGH, the measurement is taken from VTHI on REF to VTHI on
FB. For TxS/RxS = LOW, the measurement is taken from the crosspoint of REF/REF to the crosspoint of FB/FB. All outputs are set to zero delay, FB input divider is set to
divide-by-one, and FS = HIGH.
6. Output rise and fall times are measured between 20% to 80% of the actual output voltage swing.
7. tL, tL(ω), tL(REFSEL1), tL(REFSEL2), and tL(PD) are the times that are required before the synchronization is achieved. These specifications are valid only after VDD/VDDQ is stable and
within the normal operating limits. These parameters are measured from the application of a new signal at REF or FB, or after PD is (re)asserted until t(φ) is within specified
limits.
8. The jitter parameters are measured with all outputs selected for zero delay, FB input divider is set to divide-by-one, and FS = HIGH.
9. Both REF inputs must be the same frequency, but up to ±180° out of phase.
10. For HSTL/eHSTL outputs only.
11. For LVTTL outputs only.
12. tODCV is measured with all outputs selected for zero delay.
17
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
AC DIFFERENTIAL INPUT SPECIFICATIONS(1)
Symbol Parameter Min. Typ. Max Unit
t WReference/Feedback Input Clock Pulse Width HIGH or LOW (HSTL/eHSTL outputs)(2) 1——ns
Reference/Feedback Input Clock Pulse Width HIGH or LOW (2.5V / 1.8V LVTTL outputs)(2) 1——
HSTL/eHSTL/1.8V LVTTL/2.5V LVTTL
VDIF AC Differential Voltage(3) 400 — — mV
VIH AC Input HIGH(4,5) Vx + 200 — — mV
VIL AC Input LOW(4,6) — — Vx - 200 m V
LVEPECL
VDIF AC Differential Voltage(3) 400 — — mV
VIH AC Input HIGH(4) 1275 — — mV
VIL AC Input LOW(4) — — 875 mV
NOTES:
1. For differential input mode, RxS is tied to GND.
2 . Both differential input signals should not be driven to the same level simultaneously. The input will not change state until the inputs have crossed and the voltage range defined
by VDIF has been met or exceeded.
3. Differential mode only. VDIF specifies the minimum input voltage (VTR - VCP) required for switching where VTR is the "true" input level and VCP is the "complement" input level.
The AC differential voltage must be achieved to guarantee switching to a new state.
4. For single-ended operation, REF[1:0]/VREF[1:0] is tied to the DC voltage VREF[1:0]. Refer to each input interface's DC specification for the correct VREF[1:0] range.
5. Voltage required to switch to a logic HIGH, single-ended operation only.
6. Voltage required to switch to a logic LOW, single-ended operation only.
18
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
AC TIMING DIAGRAM(1)
NOTE:
1. The AC TIMING DIAGRAM applies to PE = VDD. For PE = GND, the negative edge of FB aligns with the negative edge of REF[1:0], divided outputs change on the negative
edge of REF[1:0], and the positive edges of the divide-by-2 and divide-by-4 signals align.
REF
FB
Q
OTHER Q
INVERTED Q
Q DIVIDED BY 2
Q DIVIDED BY 4
REF
FB
Q
OTHER Q
INVERTED Q
Q DIVIDED BY 2
Q DIVIDED BY 4
tFPWH tFPWL
tRPWH
tRPWL
tSK1(INV)
tSK2( ),
tSK2(INV)
tSK1( ),
tSK2(INV)
tSK1( )
tSK2( )
tSK2(INV)
tSK1(INV)
tSK(O)
tSK(O)
tODCV tODCV
19
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
FB
REF[1:0]
t(Ø)n t(Ø)n + 1
t(Ø) =
N
n = N
1t(Ø)n
REF[1:0]
FB
JITTER AND OFFSET TIMING WA VEFORMS
(N is a large number of samples)
Cycle-to-Cycle jitter
Static Phase Offset
nQ, QFB
tcycle n tcycle n + 1
nQ, QFB
tjit(cc) tcycle n tcycle n+1
=
NOTE:
1. Diagram for PE = H and TxS/RxS = L.
20
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
Period jitter
Half-Period jitter
Duty-Cycle Jitter
JITTER AND OFFSET TIMING WA VEFORMS
nQ, QFB
nQ, QFB
tW(MIN)
tW(MAX)
tJIT(DUTY) = tW(MAX) - tW(MIN)
tjit(per) =tcycle n 1
fo
nQ, QFB
nQ, QFB
tcycle n
1
fo
nQ, QFB
nQ, QFB
1
fo
tjit(hper) =thalf period n 1
2*fo
thalf period n thalf period n+1
nQ, QFB
nQ, QFB
nQ, QFB
nQ, QFB
21
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
TEST CIRCUITS AND CONDITIONS
Test Circuit for Differential Input(1)
VDD VDDQ
D.U.T.
Pulse
Generator
3 inch, ~50
Transmission Line
3 inch, ~50
Transmission Line
VIN
VIN
VDDI
R1
R2
VDDI
R1
R2
REF[1:0]
REF[1:0]
DIFFERENTIAL INPUT TEST CONDITIONS
Symbol VDD = 2.5V ± 0.2V Unit
R1 100 Ω
R2 100 Ω
VDDI VCM*2 V
HSTL: Crossing of REF[1:0] and REF[1:0]
eHSTL: Crossing of REF[1:0] and REF[1:0]
VTHI LVEPECL: Crossing of REF[1:0] and REF[1:0] V
1.8V LVTTL: VDDI/2
2.5V LVTTL: VDD/2
NOTE:
1. This input configuration is used for all input interfaces. For single-ended testing,
the REF[1:0] must be left floating. For testing single-ended in differential input
mode, the VIN should be floating.
22
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
Test Circuit for Differential Outputs
VDD VDDQ
D.U.T.
QFB
QFB
CL
VDDQ
R1
R2
VDDQ
R1
R2
CL
REF[1:0]
FB
FB
SW1
VDD VDDQ
D.U.T.
CL
VDDQ
R1
R2
nQ
FB
FB
QFB
QFB
REF[1:0]
nQ
CL
VDDQ
R1
R2
SW1
DIFFERENTIAL FEEDBACK TEST
CONDITIONS
Symbol VDD = 2.5V ± 0.2V Unit
VDDQ = Interface Specified
CL15 pF
R1 100 Ω
R2 100 Ω
VOX HSTL: Crossing of QFB and QFB V
eHSTL: Crossing of QFB and QFB
VTHO 1.8V LVTTL: VDDQ/2 V
2.5V LVTTL: VDDQ/2
SW1 TxS = MID or HIGH Open
TxS = LOW Closed
DIFFERENTIAL OUTPUT TEST
CONDITIONS
Symbol VDD = 2.5V ± 0.2V Unit
VDDQ = Interface Specified
CL15 pF
R1 100 Ω
R2 100 Ω
VOX HSTL: Crossing of nQ and nQ V
eHSTL: Crossing of nQ and nQ
VTHO 1.8V LVTTL: VDDQ/2 V
2.5V LVTTL: VDDQ/2
SW1 TxS = MID or HIGH Open
TxS = LOW Closed
Test Circuit for Differential Feedback
23
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
RECOMMENDED LANDING PATTERN
NL 68 pin
NOTE: All dimensions are in millimeters.
24
INDUSTRIAL TEMPERATURE RANGE
IDT5T2110
2.5V ZERO DELAY PLL DIFFERENTIAL CLOCK DRIVER TERACLOCK
ORDERING INFORMATION
IDT XXXXX XX
Package
Device Type
5T2110 2.5V Zero Delay PLL Differential Clock
Driver Teraclock
Package
X
-40°C to +85°C (Industrial)
I
Plastic Ball Grid Array
PBGA - Green
Thermally Enhanced Plastic Very Fine
Pitch Quad Flat No Lead Package
VFQFPN - Green
BB
BBG
NL
NLG
CORPORATE HEADQUARTERS for SALES: for Tech Support:
6024 Silver Creek Valley Road 800-345-7015 or 408-284-8200 clockhelp@idt.com
San Jose, CA 95138 fax: 408-284-2775
www.idt.com
