PIC24FJ256GB110 Family Data Sheet 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) (c) 2008 Microchip Technology Inc. Preliminary DS39897B Note the following details of the code protection feature on Microchip devices: * Microchip products meet the specification contained in their particular Microchip Data Sheet. * Microchip believes that its family of products is one of the most secure families of its kind on the market today, when used in the intended manner and under normal conditions. * There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip's Data Sheets. Most likely, the person doing so is engaged in theft of intellectual property. * Microchip is willing to work with the customer who is concerned about the integrity of their code. * Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not mean that we are guaranteeing the product as "unbreakable." Code protection is constantly evolving. We at Microchip are committed to continuously improving the code protection features of our products. Attempts to break Microchip's code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act. Information contained in this publication regarding device applications and the like is provided only for your convenience and may be superseded by updates. It is your responsibility to ensure that your application meets with your specifications. MICROCHIP MAKES NO REPRESENTATIONS OR WARRANTIES OF ANY KIND WHETHER EXPRESS OR IMPLIED, WRITTEN OR ORAL, STATUTORY OR OTHERWISE, RELATED TO THE INFORMATION, INCLUDING BUT NOT LIMITED TO ITS CONDITION, QUALITY, PERFORMANCE, MERCHANTABILITY OR FITNESS FOR PURPOSE. Microchip disclaims all liability arising from this information and its use. Use of Microchip devices in life support and/or safety applications is entirely at the buyer's risk, and the buyer agrees to defend, indemnify and hold harmless Microchip from any and all damages, claims, suits, or expenses resulting from such use. No licenses are conveyed, implicitly or otherwise, under any Microchip intellectual property rights. Trademarks The Microchip name and logo, the Microchip logo, Accuron, dsPIC, KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PICSTART, PRO MATE, rfPIC and SmartShunt are registered trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. FilterLab, Linear Active Thermistor, MXDEV, MXLAB, SEEVAL, SmartSensor and The Embedded Control Solutions Company are registered trademarks of Microchip Technology Incorporated in the U.S.A. Analog-for-the-Digital Age, Application Maestro, CodeGuard, dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN, ECONOMONITOR, FanSense, In-Circuit Serial Programming, ICSP, ICEPIC, Mindi, MiWi, MPASM, MPLAB Certified logo, MPLIB, MPLINK, mTouch, PICkit, PICDEM, PICDEM.net, PICtail, PIC32 logo, PowerCal, PowerInfo, PowerMate, PowerTool, REAL ICE, rfLAB, Select Mode, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. (c) 2008, Microchip Technology Incorporated, Printed in the U.S.A., All Rights Reserved. Printed on recycled paper. Microchip received ISO/TS-16949:2002 certification for its worldwide headquarters, design and wafer fabrication facilities in Chandler and Tempe, Arizona; Gresham, Oregon and design centers in California and India. The Company's quality system processes and procedures are for its PIC(R) MCUs and dsPIC(R) DSCs, KEELOQ(R) code hopping devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip's quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS39897B-page ii Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 64/80/100-Pin, 16-Bit Flash Microcontrollers with USB On-The-Go (OTG) Power Management: High-Performance CPU: * On-Chip 2.5V Voltage Regulator * Switch between Clock Sources in Real Time * Idle, Sleep and Doze modes with Fast Wake-up and Two-Speed Start-up * Run mode: 1 mA/MIPS, 2.0V Typical * Sleep mode Current Down to 100 nA Typical * Standby Current with 32 kHz Oscillator: 2.5 A, 2.0V typical * * * * * * * Modified Harvard Architecture Up to 16 MIPS Operation at 32 MHz 8 MHz Internal Oscillator 17-Bit x 17-Bit Single-Cycle Hardware Multiplier 32-Bit by 16-Bit Hardware Divider 16 x 16-Bit Working Register Array C Compiler Optimized Instruction Set Architecture with Flexible Addressing modes * Linear Program Memory Addressing, Up to 12 Mbytes * Linear Data Memory Addressing, Up to 64 Kbytes * Two Address Generation Units for Separate Read and Write Addressing of Data Memory Universal Serial Bus Features: Analog Features: USBOTG CTMU JTAG PMP/PSP Comparators I2CTM SPI UART w/IrDA(R) Compare/ PWM Output Capture Input Timers 16-Bit 10-Bit A/D (ch) * 10-Bit, Up to 16-Channel Analog-to-Digital (A/D) Converter at 500 ksps: - Conversions available in Sleep mode * Three Analog Comparators with Programmable Input/ Output Configuration * Charge Time Measurement Unit (CTMU) Remappable Peripherals Remappable Pins SRAM (Bytes) Program Memory (Bytes) Device Pins * USB v2.0 On-The-Go (OTG) Compliant * Dual Role Capable - can act as either Host or Peripheral * Low-Speed (1.5 Mb/s) and Full-Speed (12 Mb/s) USB Operation in Host mode * Full-Speed USB Operation in Device mode * High-Precision PLL for USB * Internal Voltage Boost Assist for USB Bus Voltage Generation * Interface for Off-Chip Charge Pump for USB Bus Voltage Generation * Supports up to 32 Endpoints (16 bidirectional): - USB Module can use any RAM location on the device as USB endpoint buffers * On-Chip USB Transceiver with On-Chip Voltage Regulator * Interface for Off-Chip USB Transceiver * Supports Control, Interrupt, Isochronous and Bulk Transfers * On-Chip Pull-up and Pull-Down Resistors PIC24FJ64GB106 64 64K 16K 29 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ128GB106 64 128K 16K 29 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ192GB106 64 192K 16K 29 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ256GB106 64 256K 16K 29 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ64GB108 80 64K 16K 40 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ128GB108 80 128K 16K 40 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ192GB108 80 192K 16K 40 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ256GB108 80 256K 16K 40 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ64GB110 100 64K 16K 44 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ128GB110 100 128K 16K 44 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ192GB110 100 192K 16K 44 5 9 9 4 3 3 16 3 Y Y Y Y PIC24FJ256GB110 100 256K 16K 44 5 9 9 4 3 3 16 3 Y Y Y Y (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 1 PIC24FJ256GB110 FAMILY Peripheral Features: Special Microcontroller Features: * Peripheral Pin Select: - Allows independent I/O mapping of many peripherals at run time - Continuous hardware integrity checking and safety interlocks prevent unintentional configuration changes - Up to 44 available pins (100-pin devices) * Three 3-Wire/4-Wire SPI modules (supports 4 Frame modes) with 8-Level FIFO Buffer * Three I2CTM modules support Multi-Master/Slave modes and 7-Bit/10-Bit Addressing * Four UART modules: - Supports RS-485, RS-232, LIN/J6202 protocols and IrDA(R) - On-chip hardware encoder/decoder for IrDA - Auto-wake-up and Auto-Baud Detect (ABD) - 4-level deep FIFO buffer * Five 16-Bit Timers/Counters with Programmable Prescaler * Nine 16-Bit Capture Inputs, each with a Dedicated Time Base * Nine 16-Bit Compare/PWM Outputs, each with a Dedicated Time Base * 8-Bit Parallel Master Port (PMP/PSP): - Up to 16 address pins - Programmable polarity on control lines * Hardware Real-Time Clock/Calendar (RTCC): - Provides clock, calendar and alarm functions * Programmable Cyclic Redundancy Check (CRC) Generator * Up to 5 External Interrupt Sources * * * * * * DS39897B-page 2 * * * * * * * * Operating Voltage Range of 2.0V to 3.6V Self-Reprogrammable under Software Control 5.5V Tolerant Input (digital pins only) Configurable Open-Drain Outputs on Digital I/O High-Current Sink/Source (18 mA/18 mA) on all I/O Selectable Power Management modes: - Sleep, Idle and Doze modes with fast wake-up Fail-Safe Clock Monitor Operation: - Detects clock failure and switches to on-chip, low-power RC oscillator On-Chip LDO Regulator Power-on Reset (POR), Power-up Timer (PWRT), Low-Voltage Detect (LVD) and Oscillator Start-up Timer (OST) Flexible Watchdog Timer (WDT) with On-Chip. Low-Power RC Oscillator for Reliable Operation In-Circuit Serial ProgrammingTM (ICSPTM) and In-Circuit Debug (ICD) via 2 Pins JTAG Boundary Scan and Programming Support Brown-out Reset (BOR) Flash Program Memory: - 10,000 erase/write cycle endurance (minimum) - 20-year data retention minimum - Selectable write protection boundary - Write protection option for Flash Configuration Words Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 64 63 62 61 60 59 58 57 56 55 54 53 52 51 50 49 PMD4/CN62/RE4 PMD3/CN61/RE3 PMD2/CN60/RE2 PMD1/CN59/RE1 PMD0/CN58/RE0 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 PMRD/RP20/CN14/RD5 PMWR/RP25/CN13/RD4 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 RP24/VCPCON/CN50/RD1 Pin Diagram (64-Pin TQFP) 48 1 2 3 4 5 6 7 8 9 10 11 12 47 46 45 PIC24FJXXXGB106 13 14 15 16 44 43 42 41 40 RPI37/SOSCO/C3INC/TICK/ CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 RP12/PMCS1/CN56/RD11 RP3/SCL1/PMCS2/CN55/RD10 RP4/DPLN/SDA1/CN54/RD9 RP2/DMLN/RTCC/CN53/RD8 VSS OSCO/CLKO/CN22/RC15 39 38 37 36 OSCI/CLKI/CN23/RC12 VDD D+/RG2 D-/RG3 35 34 33 VUSB VBUS RP16/USBID/CN71/RF3 Legend: TCK/PMA11/AN12/CTED2/CN30/RB12 TDI/PMA10/AN13/CTED1/CN31/RB13 CTPLS/RP14/PMA1/AN14/CN32/RB14 RP29/PMA0/AN15/REFO/CN12/RB15 PMA9/RP10/SDA2/CN17/RF4 PMA8/RP17/SCL2/CN18/RF5 PGEC2/AN6/RP6/CN24/RB6 PGED2/RCV/RP7/AN7/CN25/RB7 AVDD AVSS RP8/AN8/CN26/RB8 PMA7/RP9/AN9/CN27/RB9 TMS/PMA13/AN10/CVREF/CN28/RB10 TDO/AN11/PMA12/CN29/RB11 VSS VDD 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 PMD5/CN63/RE5 PMD6/SCL3/CN64/RE6 PMD7/SDA3/CN65/RE7 PMA5/RP21/C1IND/CN8/RG6 RP26/PMA4/C1INC/CN9/RG7 PMA3/RP19/C2IND/CN10/RG8 MCLR RP27/PMA2/C2INC/CN11/RG9 VSS VDD PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 VPIO/C2INA/AN3/CN5/RB3 VMIO/RP13/C2INB/AN2/CN4/RB2 PGEC1/RP1/VREF-/AN1/CN3/RB1 PGED1/RP0/PMA6/VREF+/AN0/CN2/RB0 RPn represents remappable pins for Peripheral Pin Select feature. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 3 PIC24FJ256GB110 FAMILY PMD5/CN63/RE5 1 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 RP24/VCPCON/CN50/RD1 65 64 63 62 61 PMRD/RP20/CN14/RD5 PMWR/RP25/CN13/RD4 CN19/RD13 RPI42/CN57/RD12 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 75 74 73 72 71 70 69 68 67 66 PMD1/CN59/RE1 PMD0/CN58/RE0 CN77/RG0 CN78/RG1 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 PMD2/CN60/RE2 80 79 78 77 76 PMD4/CN62/RE4 PMD3/CN61/RE3 Pin Diagram (80-Pin TQFP) 60 RPI37/SOSCO/C3INC/T1CK/CN0/RC14 59 SOSCI/C3IND/CN1/RC13 58 RP11/DMH/CN49/INT0/RD0 57 RP12/PMCS1/CN56/RD11 56 RP3/PMCS2/SCL1/CN55/RD10 PMD6/SCL3/CN64/RE6 2 PMD7/SDA3/CN65/RE7 3 RPI38/CN45/RC1 RPI40/CN47/RC3 4 PMA5/RP21/C1IND/CN8/RG6 6 55 RP4/DPLN/SDA1/CN54/RD9 RP26/PMA4/C1INC/CN9/RG7 7 54 RP2/DMLN/RTCC/CN53/RD8 PMA3/RP19/C2IND/CN10/RG8 8 53 RPI35/SDA2/CN44/RA15 MCLR 9 52 RPI36/SCL2/CN43/RA14 10 51 VSS 50 OSCO/CLKO/CN22/RC15 OSCI/CLKI/CN23/RC12 RP27/PMA2/C2INC/CN11/RG9 5 PIC24FJXXXGB108 VSS 11 VDD 12 49 TMS/RPI33/CN66/RE8 13 48 VDD TDO/RPI34/CN67/RE9 14 47 D+/RG2 Legend: 28 29 30 31 32 33 34 35 36 37 38 39 40 AN11/PMA12/CN29/RB11 Vss VDD TCK/AN12/CTED2/PMA11/CN30/RB12 TDI/AN13/CTED1/PMA10/CN31/RB13 CTPLS/RP14/PMA1/AN14/CN32/RB14 RP29/PMA0/AN15/REFO/CN12/RB15 RPI43/CN20/RD14 RP5/CN21/RD15 RP10/PMA9/CN17/RF4 RP17/PMA8/CN18/RF5 RP16/USBID/CN71/RF3 RP9/AN9/CN27/RB9 20 AN10/CVREF/PMA13/CN28/RB10 RP30/CN70/RF2 41 PGED1/RP0/AN0/CN2/RB0 27 42 AVSS RP8/AN8/CN26/RB8 19 25 26 RP15/CN74/RF8 PGEC1/RP1/AN1/CN3/RB1 AVDD 18 43 24 VBUS VMIO/RP13/C2INB/AN2/CN4/RB2 23 44 PMA7/VREF-/CN41/RA9 17 PMA6/VREF+/CN42/RA10 VUSB VPIO/C2INA/AN3/CN5/RB3 22 D-/RG3 45 21 46 16 PGEC2/AN6/RP6/CN24/RB6 15 PGED2/RCV/RP7/AN7/CN25/RB7 PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 RPn and RPIn represent remappable pins for Peripheral Pin Select feature. DS39897B-page 4 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PMD2/CN60/RE2 CN80/RG13 CN79/RG12 CN81/RG14 PMD1/CN59/RE1 PMD0/CN58/RE0 CN40/RA7 CN39/RA6 CN77/RG0 CN78/RG1 VCMPST2/CN69/RF1 VBUSST/VCMPST1/CN68/RF0 ENVREG VCAP/VDDCORE C3INA/CN16/RD7 C3INB/CN15/RD6 PMRD/RP20/CN14/RD5 PMWR/RP25/CN13/RD4 CN19/RD13 RPI42/CN57/RD12 RP22/PMBE/CN52/RD3 DPH/RP23/CN51/RD2 RP24/VCPCON/CN50/RD1 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 PMD4/CN62/RE4 PMD3/CN61/RE3 Pin Diagram (100-Pin TQFP) 1 75 VDD 2 74 PMD5/CN63/RE5 3 73 PMD6/SCL3/CN64/RE6 PMD7/SDA3/CN65/RE7 4 72 VSS RPI37/SOSCO/C3INC/T1CK/ CN0/RC14 SOSCI/C3IND/CN1/RC13 RP11/DMH/CN49/INT0/RD0 5 71 RP12/PMCS1/CN56/RD11 RPI38/CN45/RC1 6 70 RP3/PMCS2/CN55/RD10 RPI39/CN46/RC2 7 69 RP4/DPLN/CN54/RD9 RPI40/CN47/RC3 8 68 RP2/DMLN/RTCC/CN53/RD8 RPI41/CN48/RC4 9 67 RPI35/SDA1/CN44/RA15 PMA5/RP21/C1IND/CN8/RG6 10 66 RPI36/SCL1/CN43/RA14 RP26/PMA4/C1INC/CN9/RG7 11 65 RP19/PMA3/C2IND/CN10/RG8 12 64 VSS OSCO/CLKO/CN22/RC15 MCLR 13 63 OSCI/CLKI/CN23/RC12 RP27/PMA2/C2INC/CN11/RG9 14 62 VDD VSS 15 61 TDO/CN38/RA5 CN82/RG15 PIC24FJXXXGB110 16 60 TDI/CN37/RA4 17 59 SDA2/CN36/RA3 RPI33/CN66/RE8 18 58 SCL2/CN35/RA2 RPI34/CN67/RE9 PGEC3/RP18/VBUSON/C1INA/AN5/CN7/RB5 19 57 D+/RG2 20 56 D-/RG3 PGED3/RP28/USBOEN/C1INB/AN4/CN6/RB4 21 55 VUSB VPIO/C2INA/AN3/CN5/RB3 VMIO/RP13/C2INB/AN2/CN4/RB2 22 54 VBUS 23 53 RP15/CN74/RF8 PGEC1/RP1/AN1/CN3/RB1 24 52 RP30/CN70/RF2 PGED1/RP0/AN0/CN2/RB0 25 51 RP16/USBID/CN71/RF3 Legend: VSS VDD RPI43/CN20/RD14 RP5/CN21/RD15 RP10/PMA9/CN17/RF4 RP17/PMA8/CN18/RF5 PGEC2/AN6/RP6/CN24/RB6 PGED2/RCV/RP7/AN7/CN25/RB7 PMA7/VREF-/CN41/RA9 PMA6/VREF+/CN42/RA10 AVDD AVSS RP8/AN8/CN26/RB8 RP9/AN9/CN27/RB9 AN10/CVREF/PMA13/CN28/RB10 AN11/PMA12/CN29/RB11 VSS VDD TCK/CN34/RA1 RP31/CN76/RF13 RPI32/CN75/RF12 AN12/CTED2/PMA11/CN30/RB12 AN13/CTED1/PMA10/CN31/RB13 CTPLS/RP14/PMA1/AN14/CN32/RB14 RP29/PMA0/AN15/REFO/CN12/RB15 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 VDD TMS/CN33/RA0 RPn and RPIn represent remappable pins for Peripheral Pin Select feature. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 5 PIC24FJ256GB110 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 9 2.0 CPU ........................................................................................................................................................................................... 25 3.0 Memory Organization ................................................................................................................................................................. 31 4.0 Flash Program Memory .............................................................................................................................................................. 55 5.0 Resets ........................................................................................................................................................................................ 61 6.0 Interrupt Controller ..................................................................................................................................................................... 67 7.0 Oscillator Configuration ............................................................................................................................................................ 109 8.0 Power-Saving Features ............................................................................................................................................................ 119 9.0 I/O Ports ................................................................................................................................................................................... 121 10.0 Timer1 ...................................................................................................................................................................................... 147 11.0 Timer2/3 and Timer4/5 ............................................................................................................................................................ 149 12.0 Input Capture with Dedicated Timers ....................................................................................................................................... 155 13.0 Output Compare with Dedicated Timers .................................................................................................................................. 159 14.0 Serial Peripheral Interface (SPI)............................................................................................................................................... 169 15.0 Inter-Integrated Circuit (I2CTM) ................................................................................................................................................. 179 16.0 Universal Asynchronous Receiver Transmitter (UART) ........................................................................................................... 187 17.0 Universal Serial Bus with On-The-Go Support (USB OTG) ..................................................................................................... 195 18.0 Parallel Master Port (PMP)....................................................................................................................................................... 225 19.0 Real-Time Clock and Calendar (RTCC) .................................................................................................................................. 235 20.0 Programmable Cyclic Redundancy Check (CRC) Generator .................................................................................................. 245 21.0 10-bit High-Speed A/D Converter............................................................................................................................................. 249 22.0 Triple Comparator Module........................................................................................................................................................ 259 23.0 Comparator Voltage Reference................................................................................................................................................ 263 24.0 Charge Time Measurement Unit (CTMU) ................................................................................................................................ 265 25.0 Special Features ...................................................................................................................................................................... 269 26.0 Development Support............................................................................................................................................................... 281 27.0 Instruction Set Summary .......................................................................................................................................................... 285 28.0 Electrical Characteristics .......................................................................................................................................................... 293 29.0 Packaging Information.............................................................................................................................................................. 307 Appendix A: Revision History............................................................................................................................................................. 317 Index ................................................................................................................................................................................................. 319 The Microchip Web Site ..................................................................................................................................................................... 323 Customer Change Notification Service .............................................................................................................................................. 323 Customer Support .............................................................................................................................................................................. 323 Reader Response .............................................................................................................................................................................. 324 Product Identification System............................................................................................................................................................. 325 DS39897B-page 6 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TO OUR VALUED CUSTOMERS It is our intention to provide our valued customers with the best documentation possible to ensure successful use of your Microchip products. To this end, we will continue to improve our publications to better suit your needs. Our publications will be refined and enhanced as new volumes and updates are introduced. If you have any questions or comments regarding this publication, please contact the Marketing Communications Department via E-mail at docerrors@microchip.com or fax the Reader Response Form in the back of this data sheet to (480) 792-4150. We welcome your feedback. Most Current Data Sheet To obtain the most up-to-date version of this data sheet, please register at our Worldwide Web site at: http://www.microchip.com You can determine the version of a data sheet by examining its literature number found on the bottom outside corner of any page. The last character of the literature number is the version number, (e.g., DS30000A is version A of document DS30000). Errata An errata sheet, describing minor operational differences from the data sheet and recommended workarounds, may exist for current devices. As device/documentation issues become known to us, we will publish an errata sheet. The errata will specify the revision of silicon and revision of document to which it applies. To determine if an errata sheet exists for a particular device, please check with one of the following: * Microchip's Worldwide Web site; http://www.microchip.com * Your local Microchip sales office (see last page) When contacting a sales office, please specify which device, revision of silicon and data sheet (include literature number) you are using. Customer Notification System Register on our web site at www.microchip.com to receive the most current information on all of our products. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 7 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 8 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 1.0 DEVICE OVERVIEW This document contains device-specific information for the following devices: * PIC24FJ64GB106 * PIC24FJ192GB108 * PIC24FJ128GB106 * PIC24FJ256GB108 * PIC24FJ192GB106 * PIC24FJ64GB110 * PIC24FJ256GB106 * PIC24FJ128GB110 * PIC24FJ64GB108 * PIC24FJ192GB110 * PIC24FJ128GB108 * PIC24FJ256GB110 * Doze Mode Operation: When timing-sensitive applications, such as serial communications, require the uninterrupted operation of peripherals, the CPU clock speed can be selectively reduced, allowing incremental power savings without missing a beat. * Instruction-Based Power-Saving Modes: The microcontroller can suspend all operations, or selectively shut down its core while leaving its peripherals active, with a single instruction in software. 1.1.3 This expands on the existing line of Microchip`s 16-bit microcontrollers, combining an expanded peripheral feature set and enhanced computational performance with a new connectivity option: USB On-The-Go. The PIC24FJ256GB110 family provides a new platform for high-performance USB applications which may need more than an 8-bit platform, but don't require the power of a digital signal processor. 1.1 1.1.1 Core Features 16-BIT ARCHITECTURE Central to all PIC24F devices is the 16-bit modified Harvard architecture, first introduced with Microchip's dsPIC(R) digital signal controllers. The PIC24F CPU core offers a wide range of enhancements, such as: * 16-bit data and 24-bit address paths with the ability to move information between data and memory spaces * Linear addressing of up to 12 Mbytes (program space) and 64 Kbytes (data) * A 16-element working register array with built-in software stack support * A 17 x 17 hardware multiplier with support for integer math * Hardware support for 32 by 16-bit division * An instruction set that supports multiple addressing modes and is optimized for high-level languages such as `C' * Operational performance up to 16 MIPS 1.1.2 POWER-SAVING TECHNOLOGY All of the devices in the PIC24FJ256GB110 family incorporate a range of features that can significantly reduce power consumption during operation. Key items include: * On-the-Fly Clock Switching: The device clock can be changed under software control to the Timer1 source or the internal, low-power RC oscillator during operation, allowing the user to incorporate power-saving ideas into their software designs. (c) 2008 Microchip Technology Inc. OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC24FJ256GB110 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: * Two Crystal modes using crystals or ceramic resonators. * Two External Clock modes offering the option of a divide-by-2 clock output. * A Fast Internal Oscillator (FRC) with a nominal 8 MHz output, which can also be divided under software control to provide clock speeds as low as 31 kHz. * A Phase Lock Loop (PLL) frequency multiplier, available to the external oscillator modes and the FRC oscillator, which allows clock speeds of up to 32 MHz. * A separate internal RC oscillator (LPRC) with a fixed 31 kHz output, which provides a low-power option for timing-insensitive applications. The internal oscillator block also provides a stable reference source for the Fail-Safe Clock Monitor. This option constantly monitors the main clock source against a reference signal provided by the internal oscillator and enables the controller to switch to the internal oscillator, allowing for continued low-speed operation or a safe application shutdown. 1.1.4 EASY MIGRATION Regardless of the memory size, all devices share the same rich set of peripherals, allowing for a smooth migration path as applications grow and evolve. The consistent pinout scheme used throughout the entire family also aids in migrating from one device to the next larger, or even in jumping from 64-pin to 100-pin devices. The PIC24F family is pin-compatible with devices in the dsPIC33 family, and shares some compatibility with the pinout schema for PIC18 and dsPIC30. This extends the ability of applications to grow from the relatively simple, to the powerful and complex, yet still selecting a Microchip device. Preliminary DS39897B-page 9 PIC24FJ256GB110 FAMILY 1.2 USB On-The-Go With the PIC24FJ256GB110 family of devices, Microchip introduces USB On-The-Go functionality on a single chip to its product line. This new module provides on-chip functionality as a target device compatible with the USB 2.0 standard, as well as limited stand-alone functionality as a USB embedded host. By implementing USB Host Negotiation Protocol (HNP), the module can also dynamically switch between device and host operation, allowing for a much wider range of versatile USB-enabled applications on a microcontroller platform. * Parallel Master/Enhanced Parallel Slave Port: One of the general purpose I/O ports can be reconfigured for enhanced parallel data communications. In this mode, the port can be configured for both master and slave operations, and supports 8-bit and 16-bit data transfers with up to 16 external address lines in Master modes. * Real-Time Clock/Calendar: This module implements a full-featured clock and calendar with alarm functions in hardware, freeing up timer resources and program memory space for use of the core application. In addition to USB host functionality, PIC24FJ256GB110 family devices provide a true single-chip USB solution, including an on-chip transceiver and voltage regulator, and a voltage boost generator for sourcing bus power during host operations. 1.4 1.3 The devices are differentiated from each other in four ways: Other Special Features * Peripheral Pin Select: The peripheral pin select feature allows most digital peripherals to be mapped over a fixed set of digital I/O pins. Users may independently map the input and/or output of any one of the many digital peripherals to any one of the I/O pins. * Communications: The PIC24FJ256GB110 family incorporates a range of serial communication peripherals to handle a range of application requirements. There are three independent I2C modules that support both Master and Slave modes of operation. Devices also have, through the peripheral pin select feature, four independent UARTs with built-in IrDA encoder/decoders and three SPI modules. * Analog Features: All members of the PIC24FJ256GB110 family include a 10-bit A/D Converter module and a triple comparator module. The A/D module incorporates programmable acquisition time, allowing for a channel to be selected and a conversion to be initiated without waiting for a sampling period, as well as faster sampling speeds. The comparator module includes three analog comparators that are configurable for a wide range of operations. * CTMU Interface: In addition to their other analog features, members of the PIC24FJ256GB110 family include the brand new CTMU interface module. This provides a convenient method for precision time measurement and pulse generation, and can serve as an interface for capacitive sensors. DS39897B-page 10 Details on Individual Family Members Devices in the PIC24FJ256GB110 family are available in 64-pin, 80-pin and 100-pin packages. The general block diagram for all devices is shown in Figure 1-1. 1. 2. 3. 4. Flash program memory (64 Kbytes for PIC24FJ64GB1 devices, 128 Kbytes for PIC24FJ128GB1 devices, 192 Kbytes for PIC24FJ192GB1 devices and 256 Kbytes for PIC24FJ256GB1 devices). Available I/O pins and ports (51 pins on 6 ports for 64-pin devices, 65 pins on 7 ports for 80-pin devices and 83 pins on 7 ports for 100-pin devices). Available Interrupt-on-Change Notification (ICN) inputs (49 on 64-pin devices, 63 on 80-pin devices, and 81 on 100-pin devices). Available remappable pins (29 pins on 64-pin devices, 40 pins on 80-pin devices and 44 pins on 100-pin devices) All other features for devices in this family are identical. These are summarized in Table 1-1. A list of the pin features available on the PIC24FJ256GB110 family devices, sorted by function, is shown in Table 1-4. Note that this table shows the pin location of individual peripheral features and not how they are multiplexed on the same pin. This information is provided in the pinout diagrams in the beginning of the data sheet. Multiplexed features are sorted by the priority given to a feature, with the highest priority peripheral being listed first. Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-1: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 64-PIN DEVICES Features 64GB106 Operating Frequency Program Memory (bytes) Program Memory (instructions) 128GB106 192GB106 256GB106 DC - 32 MHz 64K 128K 22,016 44,032 Data Memory (bytes) 192K 256K 67,072 87,552 16,384 Interrupt Sources (soft vectors/NMI traps) 66 (62/4) I/O Ports Ports B, C, D, E, F, G Total I/O Pins 51 Remappable Pins 29 (28 I/O, 1 Input only) Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 9(1) Output Compare/PWM Channels 9(1) Input Change Notification Interrupt 49 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 3(1) I2CTM 3 Parallel Communications (PMP/PSP) Yes JTAG Boundary Scan/Programming Yes 10-Bit Analog-to-Digital Module (input channels) 16 Analog Comparators 3 CTMU Interface Resets (and delays) Instruction Set Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations Packages Note 1: 64-Pin TQFP Peripherals are accessible through remappable pins. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 11 PIC24FJ256GB110 FAMILY TABLE 1-2: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 80-PIN DEVICES Features 64GB108 Operating Frequency Program Memory (bytes) Program Memory (instructions) 128GB108 192GB108 256GB108 DC - 32 MHz 64K 128K 22,016 44,032 Data Memory (bytes) 192K 256K 67,072 87,552 16,384 Interrupt Sources (soft vectors/NMI traps) 66 (62/4) I/O Ports Ports A, B, C, D, E, F, G Total I/O Pins 65 Remappable Pins 40 (31 I/O, 9 Input only) Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 9(1) Output Compare/PWM Channels 9(1) Input Change Notification Interrupt 63 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 3(1) I2CTM 3 Parallel Communications (PMP/PSP) Yes JTAG Boundary Scan/Programming Yes 10-Bit Analog-to-Digital Module (input channels) 16 Analog Comparators 3 CTMU Interface Resets (and delays) Instruction Set Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations Packages Note 1: 80-Pin TQFP Peripherals are accessible through remappable pins. DS39897B-page 12 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-3: DEVICE FEATURES FOR THE PIC24FJ256GB110 FAMILY: 100-PIN DEVICES Features 64GB110 Operating Frequency Program Memory (bytes) Program Memory (instructions) 128GB110 192GB110 256GB110 DC - 32 MHz 64K 128K 192K 256K 22,016 44,032 67,072 87,552 Data Memory (bytes) 16,384 Interrupt Sources (soft vectors/NMI traps) 66 (62/4) I/O Ports Ports A, B, C, D, E, F, G Total I/O Pins 83 Remappable Pins 44 (32 I/O, 12 Input only) Timers: 5(1) Total Number (16-bit) 32-Bit (from paired 16-bit timers) 2 Input Capture Channels 9(1) Output Compare/PWM Channels 9(1) Input Change Notification Interrupt 81 Serial Communications: UART 4(1) SPI (3-wire/4-wire) 3(1) I2CTM 3 Parallel Communications (PMP/PSP) Yes JTAG Boundary Scan/Programming Yes 10-Bit Analog-to-Digital Module (input channels) 16 Analog Comparators 3 CTMU Interface Resets (and delays) Instruction Set Yes POR, BOR, RESET Instruction, MCLR, WDT; Illegal Opcode, REPEAT Instruction, Hardware Traps, Configuration Word Mismatch (PWRT, OST, PLL Lock) 76 Base Instructions, Multiple Addressing Mode Variations Packages Note 1: 100-Pin TQFP Peripherals are accessible through remappable pins. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 13 PIC24FJ256GB110 FAMILY FIGURE 1-1: PIC24FJ256GB110 FAMILY GENERAL BLOCK DIAGRAM Data Bus Interrupt Controller PORTA(1) 16 (13 I/O) 16 16 8 Data Latch PSV & Table Data Access Control Block Data RAM PCH PCL Program Counter Repeat Stack Control Control Logic Logic 23 Address Latch PORTB (16 I/O) 16 23 16 Read AGU Write AGU Address Latch PORTC(1) Program Memory (8 I/O) Data Latch 16 EA MUX Literal Data Address Bus 24 Inst Latch 16 16 PORTD(1) (16 I/O) Inst Register Instruction Decode & Control PORTE(1) Control Signals OSCO/CLKO OSCI/CLKI Timing Generation FRC/LPRC Oscillators REFO ENVREG Divide Support Power-up Timer (10 I/O) 16 x 16 W Reg Array 17x17 Multiplier Oscillator Start-up Timer Precision Band Gap Reference Watchdog Timer Voltage Regulator BOR and LVD(2) PORTF(1) 16-Bit ALU Power-on Reset (9 I/O) 16 PORTG(1) (12 I/O) VDDCORE/VCAP Timer1 Timer2/3(3) VDD, VSS Timer4/5(3) MCLR RTCC 10-Bit ADC Comparators(3) USB OTG PMP/PSP IC 1-9(3) Note 1: 2: 3: PWM/OC 1-9(3) ICNs(1) SPI 1/2/3(3) I2C 1/2/3 UART 1/2/3/4(3) CTMU Not all I/O pins or features are implemented on all device pinout configurations. See Table 1-4 for specific implementations by pin count. BOR functionality is provided when the on-board voltage regulator is enabled. These peripheral I/Os are only accessible through remappable pins. DS39897B-page 14 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS Pin Number Function 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer AN0 16 20 25 I ANA AN1 15 19 24 I ANA AN2 14 18 23 I ANA AN3 13 17 22 I ANA AN4 12 16 21 I ANA AN5 11 15 20 I ANA AN6 17 21 26 I ANA AN7 18 22 27 I ANA AN8 21 27 32 I ANA AN9 22 28 33 I ANA AN10 23 29 34 I ANA AN11 24 30 35 I ANA AN12 27 33 41 I ANA AN13 28 34 42 I ANA AN14 29 35 43 I ANA AN15 30 36 44 I ANA Description A/D Analog Inputs. AVDD 19 25 30 P -- AVSS 20 26 31 P -- C1INA 11 15 20 I ANA Comparator 1 Input A. C1INB 12 16 21 I ANA Comparator 1 Input B. C1INC 5 7 11 I ANA Comparator 1 Input C. C1IND 4 6 10 I ANA Comparator 1 Input D. C2INA 13 17 22 I ANA Comparator 2 Input A. C2INB 14 18 23 I ANA Comparator 2 Input B. C2INC 8 10 14 I ANA Comparator 2 Input C. C2IND 6 8 12 I ANA Comparator 2 Input D. C3INA 55 69 84 I ANA Comparator 3 Input A. C3INB 54 68 83 I ANA Comparator 3 Input B. C3INC 48 60 74 I ANA Comparator 3 Input C. C3IND 47 59 73 I ANA Comparator 3 Input D. CLKI 39 49 63 I ANA CLKO 40 50 64 O -- Legend: TTL = TTL input buffer ANA = Analog level input/output (c) 2008 Microchip Technology Inc. Positive Supply for Analog modules. Ground Reference for Analog modules. Main Clock Input Connection. System Clock Output. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary DS39897B-page 15 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer CN0 48 60 74 I ST CN1 47 59 73 I ST CN2 16 20 25 I ST CN3 15 19 24 I ST CN4 14 18 23 I ST CN5 13 17 22 I ST CN6 12 16 21 I ST CN7 11 15 20 I ST CN8 4 6 10 I ST CN9 5 7 11 I ST CN10 6 8 12 I ST CN11 8 10 14 I ST CN12 30 36 44 I ST CN13 52 66 81 I ST CN14 53 67 82 I ST CN15 54 68 83 I ST CN16 55 69 84 I ST CN17 31 39 49 I ST CN18 32 40 50 I ST CN19 -- 65 80 I ST CN20 -- 37 47 I ST CN21 -- 38 48 I ST CN22 40 50 64 I ST CN23 39 49 63 I ST CN24 17 21 26 I ST CN25 18 22 27 I ST CN26 21 27 32 I ST CN27 22 28 33 I ST CN28 23 29 34 I ST CN29 24 30 35 I ST CN30 27 33 41 I ST CN31 28 34 42 I ST CN32 29 35 43 I ST CN33 -- -- 17 I ST CN34 -- -- 38 I ST CN35 -- -- 58 I ST CN36 -- -- 59 I ST CN37 -- -- 60 I ST CN38 -- -- 61 I ST CN39 -- -- 91 I ST Function CN40 -- -- 92 I ST CN41 -- 23 28 I ST -- 24 29 I ST CN42 Legend: TTL = TTL input buffer ANA = Analog level input/output DS39897B-page 16 Description Interrupt-on-Change Inputs. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer CN43 -- 52 66 I ST CN44 -- 53 67 I ST CN45 -- 4 6 I ST CN46 -- -- 7 I ST CN47 -- 5 8 I ST CN48 -- -- 9 I ST CN49 46 58 72 I ST CN50 49 61 76 I ST CN51 50 62 77 I ST CN52 51 63 78 I ST CN53 42 54 68 I ST CN54 43 55 69 I ST CN55 44 56 70 I ST CN56 45 57 71 I ST CN57 -- 64 79 I ST CN58 60 76 93 I ST CN59 61 77 94 I ST CN60 62 78 98 I ST CN61 63 79 99 I ST CN62 64 80 100 I ST CN63 1 1 3 I ST CN64 2 2 4 I ST CN65 3 3 5 I ST CN66 -- 13 18 I ST CN67 -- 14 19 I ST CN68 58 72 87 I ST CN69 59 73 88 I ST CN70 -- 42 52 I ST CN71 33 41 51 I ST CN74 -- 43 53 I ST CN75 -- -- 40 I ST CN76 -- -- 39 I ST CN77 -- 75 90 I ST CN78 -- 74 89 I ST CN79 -- -- 96 I ST CN80 -- -- 97 I ST CN81 -- -- 95 I ST CN82 -- -- 1 I ST CTED1 28 34 42 I ANA CTMU External Edge Input 1. CTED2 27 33 41 I ANA CTMU External Edge Input 2. Function Description Interrupt-on-Change Inputs. CTPLS 29 35 43 O -- CTMU Pulse Output. CVREF 23 29 34 O -- Comparator Voltage Reference Output. Legend: TTL = TTL input buffer ANA = Analog level input/output (c) 2008 Microchip Technology Inc. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary DS39897B-page 17 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer D+ 37 47 57 I/O -- USB Differential Plus line (internal transceiver). D- 36 46 56 I/O -- USB Differential Minus line (internal transceiver). DMH 46 58 72 O -- D- External Pull-up Control Output. DMLN 42 54 68 O -- D- External Pull-down Control Output. DPH 50 62 77 O -- D+ External Pull-up Control Output. DPLN 43 55 69 O -- D+ External Pull-down Control Output. ENVREG 57 71 86 I ST Voltage Regulator Enable. INT0 46 58 72 I ST External Interrupt Input. MCLR 7 9 13 I ST Master Clear (device Reset) Input. This line is brought low to cause a Reset. OSCI 39 49 63 I ANA Main Oscillator Input Connection. OSCO 40 50 64 O ANA Main Oscillator Output Connection. PGEC1 15 19 24 I/O ST In-Circuit Debugger/Emulator/ICSPTM Programming Clock. PGED1 16 20 25 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data. PGEC2 17 21 26 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock. PGED2 18 22 27 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data. PGEC3 11 15 20 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Clock. PGED3 12 16 21 I/O ST In-Circuit Debugger/Emulator/ICSP Programming Data. PMA0 30 36 44 I/O ST Parallel Master Port Address Bit 0 Input (Buffered Slave modes) and Output (Master modes). PMA1 29 35 43 I/O ST Parallel Master Port Address Bit 1 Input (Buffered Slave modes) and Output (Master modes). PMA2 8 10 14 O -- PMA3 6 8 12 O -- Parallel Master Port Address (Demultiplexed Master modes). PMA4 5 7 11 O -- PMA5 4 6 10 O -- PMA6 16 24 29 O -- PMA7 22 23 28 O -- PMA8 32 40 50 O -- PMA9 31 39 49 O -- PMA10 28 34 42 O -- PMA11 27 33 41 O -- PMA12 24 30 35 O -- PMA13 23 29 34 O -- PMCS1 45 57 71 I/O ST/TTL Parallel Master Port Chip Select 1 Strobe/Address Bit 15. PMCS2 44 56 70 O ST Parallel Master Port Chip Select 2 Strobe/Address Bit 14. 51 63 78 O -- Parallel Master Port Byte Enable Strobe. Function PMBE Legend: TTL = TTL input buffer ANA = Analog level input/output DS39897B-page 18 Description ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer PMD0 60 76 93 I/O ST/TTL PMD1 61 77 94 I/O ST/TTL PMD2 62 78 98 I/O ST/TTL PMD3 63 79 99 I/O ST/TTL PMD4 64 80 100 I/O ST/TTL PMD5 1 1 3 I/O ST/TTL PMD6 2 2 4 I/O ST/TTL PMD7 3 3 5 I/O ST/TTL PMRD 53 67 82 O -- PMWR 52 66 81 O -- Parallel Master Port Write Strobe. RA0 -- -- 17 I/O ST PORTA Digital I/O. RA1 -- -- 38 I/O ST RA2 -- -- 58 I/O ST RA3 -- -- 59 I/O ST RA4 -- -- 60 I/O ST RA5 -- -- 61 I/O ST RA6 -- -- 91 I/O ST RA7 -- -- 92 I/O ST RA9 -- 23 28 I/O ST RA10 -- 24 29 I/O ST RA14 -- 52 66 I/O ST RA15 -- 53 67 I/O ST RB0 16 20 25 I/O ST RB1 15 19 24 I/O ST RB2 14 18 23 I/O ST RB3 13 17 22 I/O ST RB4 12 16 21 I/O ST RB5 11 15 20 I/O ST RB6 17 21 26 I/O ST RB7 18 22 27 I/O ST RB8 21 27 32 I/O ST RB9 22 28 33 I/O ST RB10 23 29 34 I/O ST RB11 24 30 35 I/O ST RB12 27 33 41 I/O ST RB13 28 34 42 I/O ST RB14 29 35 43 I/O ST RB15 30 36 44 I/O ST Function Legend: TTL = TTL input buffer ANA = Analog level input/output (c) 2008 Microchip Technology Inc. Description Parallel Master Port Data (Demultiplexed Master mode) or Address/Data (Multiplexed Master modes). Parallel Master Port Read Strobe. PORTB Digital I/O. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary DS39897B-page 19 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer Description RC1 -- 4 6 I/O ST RC2 -- -- 7 I/O ST RC3 -- 5 8 I/O ST RC4 -- -- 9 I/O ST RC12 39 49 63 I/O ST RC13 47 59 73 I/O ST RC14 48 60 74 I/O ST RC15 40 50 64 I/O ST RCV 18 22 27 I ST USB Receive Input (from external transceiver). RD0 46 58 72 I/O ST PORTD Digital I/O. RD1 49 61 76 I/O ST RD2 50 62 77 I/O ST RD3 51 63 78 I/O ST RD4 52 66 81 I/O ST RD5 53 67 82 I/O ST RD6 54 68 83 I/O ST RD7 55 69 84 I/O ST RD8 42 54 68 I/O ST RD9 43 55 69 I/O ST RD10 44 56 70 I/O ST RD11 45 57 71 I/O ST RD12 -- 64 79 I/O ST RD13 -- 65 80 I/O ST RD14 -- 37 47 I/O ST RD15 -- 38 48 I/O ST RE0 60 76 93 I/O ST RE1 61 77 94 I/O ST RE2 62 78 98 I/O ST RE3 63 79 99 I/O ST RE4 64 80 100 I/O ST RE5 1 1 3 I/O ST RE6 2 2 4 I/O ST RE7 3 3 5 I/O ST RE8 -- 13 18 I/O ST RE9 -- 14 19 I/O ST REFO 30 36 44 O -- Legend: TTL = TTL input buffer ANA = Analog level input/output DS39897B-page 20 PORTC Digital I/O. PORTE Digital I/O. Reference Clock Output. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer RF0 58 72 87 I/O ST RF1 59 73 88 I/O ST RF2 -- 42 52 I/O ST RF3 33 41 51 I/O ST RF4 31 39 49 I/O ST RF5 32 40 50 I/O ST RF8 -- 43 53 I/O ST RF12 -- -- 40 I/O ST ST Function RF13 -- -- 39 I/O RG0 -- 75 90 I/O ST RG1 -- 74 89 I/O ST RG2 37 47 57 I/O ST RG3 36 46 56 I/O ST RG6 4 6 10 I/O ST RG7 5 7 11 I/O ST RG8 6 8 12 I/O ST RG9 8 10 14 I/O ST RG12 -- -- 96 I/O ST RG13 -- -- 97 I/O ST RG14 -- -- 95 I/O ST ST RG15 -- -- 1 I/O RP0 16 20 25 I/O ST RP1 15 19 24 I/O ST RP2 42 54 68 I/O ST RP3 44 56 70 I/O ST RP4 43 55 69 I/O ST RP5 -- 38 48 I/O ST RP6 17 21 26 I/O ST RP7 18 22 27 I/O ST RP8 21 27 32 I/O ST RP9 22 28 33 I/O ST RP10 31 39 49 I/O ST RP11 46 58 72 I/O ST RP12 45 57 71 I/O ST RP13 14 18 23 I/O ST RP14 29 35 43 I/O ST RP15 -- 43 53 I/O ST RP16 33 41 51 I/O ST RP17 32 40 50 I/O ST RP18 11 15 20 I/O ST 6 8 12 I/O ST RP19 Legend: TTL = TTL input buffer ANA = Analog level input/output (c) 2008 Microchip Technology Inc. Description PORTF Digital I/O. PORTG Digital I/O. Remappable Peripheral (input or output). ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary DS39897B-page 21 PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 100-Pin TQFP I/O Input Buffer 64-Pin TQFP 80-Pin TQFP RP20 53 67 82 I/O ST RP21 4 6 10 I/O ST RP22 51 63 78 I/O ST RP23 50 62 77 I/O ST RP24 49 61 76 I/O ST RP25 52 66 81 I/O ST RP26 5 7 11 I/O ST RP27 8 10 14 I/O ST RP28 12 16 21 I/O ST RP29 30 36 44 I/O ST RP30 -- 42 52 I/O ST RP31 -- -- 39 I/O ST Description Remappable Peripheral (input or output). RPI32 -- -- 40 I ST RPI33 -- 13 18 I ST Remappable Peripheral (input only). RPI34 -- 14 19 I ST RPI35 -- 53 67 I ST RPI36 -- 52 66 I ST RPI37 48 60 74 I ST RPI38 -- 4 6 I ST RPI39 -- -- 7 I ST RPI40 -- 5 8 I ST RPI41 -- -- 9 I ST RPI42 -- 64 79 I ST RPI43 -- 37 47 I ST RTCC 42 54 68 O -- Real-Time Clock Alarm/Seconds Pulse Output. SCL1 44 56 66 I/O I2C I2C1 Synchronous Serial Clock Input/Output. SCL2 32 52 58 I/O I2C I2C2 Synchronous Serial Clock Input/Output. SCL3 2 2 4 I/O I2C I2C3 Synchronous Serial Clock Input/Output. I2C1 Data Input/Output. SDA1 43 55 67 I/O I2C SDA2 31 53 59 I/O I2C I2C2 Data Input/Output. SDA3 3 3 5 I/O I2C I2C3 Data Input/Output. SOSCI 47 59 73 I ANA Secondary Oscillator/Timer1 Clock Input. SOSCO 48 60 74 O ANA T1CK 48 60 74 I ST Timer1 Clock. Secondary Oscillator/Timer1 Clock Output. TCK 27 33 38 I ST JTAG Test Clock/Programming Clock Input. TDI 28 34 60 I ST JTAG Test Data/Programming Data Input. JTAG Test Data Output. TDO 24 14 61 O -- TMS 23 13 17 I ST JTAG Test Mode Select Input. USBID 33 41 51 I ST USB OTG ID (OTG mode only). USBOEN 12 16 21 O -- USB Output Enable Control (for external transceiver). Legend: TTL = TTL input buffer ANA = Analog level input/output DS39897B-page 22 ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 1-4: PIC24FJ256GB110 FAMILY PINOUT DESCRIPTIONS (CONTINUED) Pin Number Function 64-Pin TQFP 80-Pin TQFP 100-Pin TQFP I/O Input Buffer Description VBUS 34 44 54 P -- VBUSON 11 15 20 O -- USB Voltage, Host mode (5V). VBUSST 58 72 87 I ANA VCAP 56 70 85 P -- External Filter Capacitor Connection (regulator enabled). USB VBUS Boost Generator, Comparator Input 1. USB OTG External Charge Pump Control. USB OTG Internal Charge Pump Feedback Control. VCMPST1 58 72 87 I ST VCMPST2 59 73 88 I ST USB VBUS Boost Generator, Comparator Input 2. VCPCON 49 61 76 O -- USB OTG VBUS PWM/Charge Output. 10, 26, 38 12, 32, 48 2, 16, 37, 46, 62 P -- Positive Supply for Peripheral Digital Logic and I/O Pins. VDDCORE 56 70 85 P -- Positive Supply for Microcontroller Core Logic (regulator disabled). VMIO 14 18 23 I/O ST USB Differential Minus Input/Output (external transceiver). VPIO 13 17 22 I/O ST VREF- 15 23 28 I ANA VDD VREF+ VSS VUSB Legend: USB Differential Plus Input/Output (external transceiver). A/D and Comparator Reference Voltage (low) Input. 16 24 29 I ANA 9, 25, 41 11, 31, 51 15, 36, 45, 65, 75 P -- Ground Reference for Logic and I/O Pins. 35 45 55 P -- USB Voltage (3.3V) TTL = TTL input buffer ANA = Analog level input/output (c) 2008 Microchip Technology Inc. A/D and Comparator Reference Voltage (high) Input. ST = Schmitt Trigger input buffer I2CTM = I2C/SMBus input buffer Preliminary DS39897B-page 23 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 24 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 2.0 Note: CPU This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 2. CPU" (DS39703). The PIC24F CPU has a 16-bit (data) modified Harvard architecture with an enhanced instruction set and a 24-bit instruction word with a variable length opcode field. The Program Counter (PC) is 23 bits wide and addresses up to 4M instructions of user program memory space. A single-cycle instruction prefetch mechanism is used to help maintain throughput and provides predictable execution. All instructions execute in a single cycle, with the exception of instructions that change the program flow, the double-word move (MOV.D) instruction and the table instructions. Overhead-free program loop constructs are supported using the REPEAT instructions, which are interruptible at any point. PIC24F devices have sixteen, 16-bit working registers in the programmer's model. Each of the working registers can act as a data, address or address offset register. The 16th working register (W15) operates as a Software Stack Pointer for interrupts and calls. The upper 32 Kbytes of the data space memory map can optionally be mapped into program space at any 16K word boundary defined by the 8-bit Program Space Visibility Page Address (PSVPAG) register. The program to data space mapping feature lets any instruction access program space as if it were data space. The Instruction Set Architecture (ISA) has been significantly enhanced beyond that of the PIC18, but maintains an acceptable level of backward compatibility. All PIC18 instructions and addressing modes are supported, either directly, or through simple macros. Many of the ISA enhancements have been driven by compiler efficiency needs. For most instructions, the core is capable of executing a data (or program data) memory read, a working register (data) read, a data memory write and a program (instruction) memory read per instruction cycle. As a result, three parameter instructions can be supported, allowing trinary operations (that is, A + B = C) to be executed in a single cycle. A high-speed, 17-bit by 17-bit multiplier has been included to significantly enhance the core arithmetic capability and throughput. The multiplier supports Signed, Unsigned and Mixed mode, 16-bit by 16-bit or 8-bit by 8-bit, integer multiplication. All multiply instructions execute in a single cycle. The 16-bit ALU has been enhanced with integer divide assist hardware that supports an iterative non-restoring divide algorithm. It operates in conjunction with the REPEAT instruction looping mechanism and a selection of iterative divide instructions to support 32-bit (or 16-bit), divided by 16-bit, integer signed and unsigned division. All divide operations require 19 cycles to complete but are interruptible at any cycle boundary. The PIC24F has a vectored exception scheme with up to 8 sources of non-maskable traps and up to 118 interrupt sources. Each interrupt source can be assigned to one of seven priority levels. A block diagram of the CPU is shown in Figure 2-1. 2.1 Programmer's Model The programmer's model for the PIC24F is shown in Figure 2-2. All registers in the programmer's model are memory mapped and can be manipulated directly by instructions. A description of each register is provided in Table 2-1. All registers associated with the programmer's model are memory mapped. The core supports Inherent (no operand), Relative, Literal, Memory Direct and three groups of addressing modes. All modes support Register Direct and various Register Indirect modes. Each group offers up to seven addressing modes. Instructions are associated with predefined addressing modes depending upon their functional requirements. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 25 PIC24FJ256GB110 FAMILY FIGURE 2-1: PIC24F CPU CORE BLOCK DIAGRAM PSV & Table Data Access Control Block Data Bus Interrupt Controller 16 8 16 16 Data Latch 23 23 PCH PCL Program Counter Loop Stack Control Control Logic Logic 16 Data RAM Address Latch 23 16 RAGU WAGU Address Latch Program Memory EA MUX Address Bus Data Latch ROM Latch 24 Control Signals to Various Blocks Instruction Reg Hardware Multiplier Divide Support 16 Literal Data Instruction Decode & Control 16 16 x 16 W Register Array 16 16-Bit ALU 16 To Peripheral Modules DS39897B-page 26 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 2-1: CPU CORE REGISTERS Register(s) Name Description W0 through W15 Working Register Array PC 23-Bit Program Counter SR ALU STATUS Register SPLIM Stack Pointer Limit Value Register TBLPAG Table Memory Page Address Register PSVPAG Program Space Visibility Page Address Register RCOUNT Repeat Loop Counter Register CORCON CPU Control Register FIGURE 2-2: PROGRAMMER'S MODEL 15 Divider Working Registers 0 W0 (WREG) W1 W2 Multiplier Registers W3 W4 W5 W6 W7 Working/Address Registers W8 W9 W10 W11 W12 W13 W14 Frame Pointer W15 Stack Pointer 0 SPLIM 0 22 0 0 PC 7 0 TBLPAG 7 0 PSVPAG 15 0 RCOUNT SRH SRL -- -- -- -- -- -- -- DC IPL 2 1 0 RA N OV Z C 15 15 Stack Pointer Limit Value Register Program Counter Table Memory Page Address Register Program Space Visibility Page Address Register Repeat Loop Counter Register 0 ALU STATUS Register (SR) 0 -- -- -- -- -- -- -- -- -- -- -- -- IPL3 PSV -- -- CPU Control Register (CORCON) Registers or bits shadowed for PUSH.S and POP.S instructions. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 27 PIC24FJ256GB110 FAMILY 2.2 CPU Control Registers REGISTER 2-1: SR: ALU STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 -- -- -- -- -- -- -- DC bit 15 bit 8 R/W-0(1) IPL2 R/W-0(1) (2) IPL1 (2) R/W-0(1) IPL0 (2) R-0 R/W-0 R/W-0 R/W-0 R/W-0 RA N OV Z C bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as `0' bit 8 DC: ALU Half Carry/Borrow bit 1 = A carry out from the 4th low-order bit (for byte-sized data) or 8th low-order bit (for word-sized data) of the result occurred 0 = No carry out from the 4th or 8th low-order bit of the result has occurred bit 7-5 IPL2:IPL0: CPU Interrupt Priority Level Status bits(1,2) 111 = CPU interrupt priority level is 7 (15); user interrupts disabled 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority Level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) bit 4 RA: REPEAT Loop Active bit 1 = REPEAT loop in progress 0 = REPEAT loop not in progress bit 3 N: ALU Negative bit 1 = Result was negative 0 = Result was non-negative (zero or positive) bit 2 OV: ALU Overflow bit 1 = Overflow occurred for signed (2's complement) arithmetic in this arithmetic operation 0 = No overflow has occurred bit 1 Z: ALU Zero bit 1 = An operation which effects the Z bit has set it at some time in the past 0 = The most recent operation which effects the Z bit has cleared it (i.e., a non-zero result) bit 0 C: ALU Carry/Borrow bit 1 = A carry out from the Most Significant bit of the result occurred 0 = No carry out from the Most Significant bit of the result occurred Note 1: 2: The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1. The IPL Status bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU Interrupt Priority Level (IPL). The value in parentheses indicates the IPL when IPL3 = 1. DS39897B-page 28 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 2-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 U-0 -- U-0 -- -- U-0 R/C-0 (1) -- IPL3 R/W-0 U-0 U-0 PSV -- -- bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-4 Unimplemented: Read as `0' bit 3 IPL3: CPU Interrupt Priority Level Status bit(1) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less bit 2 PSV: Program Space Visibility in Data Space Enable bit 1 = Program space visible in data space 0 = Program space not visible in data space bit 1-0 Unimplemented: Read as `0' Note 1: 2.3 x = Bit is unknown User interrupts are disabled when IPL3 = 1. Arithmetic Logic Unit (ALU) The PIC24F ALU is 16 bits wide and is capable of addition, subtraction, bit shifts and logic operations. Unless otherwise mentioned, arithmetic operations are 2's complement in nature. Depending on the operation, the ALU may affect the values of the Carry (C), Zero (Z), Negative (N), Overflow (OV) and Digit Carry (DC) Status bits in the SR register. The C and DC Status bits operate as Borrow and Digit Borrow bits, respectively, for subtraction operations. The ALU can perform 8-bit or 16-bit operations, depending on the mode of the instruction that is used. Data for the ALU operation can come from the W register array, or data memory, depending on the addressing mode of the instruction. Likewise, output data from the ALU can be written to the W register array or a data memory location. (c) 2008 Microchip Technology Inc. The PIC24F CPU incorporates hardware support for both multiplication and division. This includes a dedicated hardware multiplier and support hardware for 16-bit divisor division. 2.3.1 MULTIPLIER The ALU contains a high-speed, 17-bit x 17-bit multiplier. It supports unsigned, signed or mixed sign operation in several multiplication modes: 1. 2. 3. 4. 5. 6. 7. Preliminary 16-bit x 16-bit signed 16-bit x 16-bit unsigned 16-bit signed x 5-bit (literal) unsigned 16-bit unsigned x 16-bit unsigned 16-bit unsigned x 5-bit (literal) unsigned 16-bit unsigned x 16-bit signed 8-bit unsigned x 8-bit unsigned DS39897B-page 29 PIC24FJ256GB110 FAMILY 2.3.2 DIVIDER 2.3.3 The divide block supports signed and unsigned integer divide operations with the following data sizes: 1. 2. 3. 4. 32-bit signed/16-bit signed divide 32-bit unsigned/16-bit unsigned divide 16-bit signed/16-bit signed divide 16-bit unsigned/16-bit unsigned divide The quotient for all divide instructions ends up in W0 and the remainder in W1. Sixteen-bit signed and unsigned DIV instructions can specify any W register for both the 16-bit divisor (Wn), and any W register (aligned) pair (W(m + 1):Wm) for the 32-bit dividend. The divide algorithm takes one cycle per bit of divisor, so both 32-bit/16-bit and 16-bit/16-bit instructions take the same number of cycles to execute. TABLE 2-2: Instruction MULTI-BIT SHIFT SUPPORT The PIC24F ALU supports both single bit and single-cycle, multi-bit arithmetic and logic shifts. Multi-bit shifts are implemented using a shifter block, capable of performing up to a 15-bit arithmetic right shift, or up to a 15-bit left shift, in a single cycle. All multi-bit shift instructions only support Register Direct Addressing for both the operand source and result destination. A full summary of instructions that use the shift operation is provided below in Table 2-2. INSTRUCTIONS THAT USE THE SINGLE AND MULTI-BIT SHIFT OPERATION Description ASR Arithmetic shift right source register by one or more bits. SL Shift left source register by one or more bits. LSR Logical shift right source register by one or more bits. DS39897B-page 30 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 3.0 MEMORY ORGANIZATION As Harvard architecture devices, PIC24F microcontrollers feature separate program and data memory spaces and busses. This architecture also allows the direct access of program memory from the data space during code execution. 3.1 Program Address Space The program address memory space of the PIC24FJ256GB110 family devices is 4M instructions. The space is addressable by a 24-bit value derived FIGURE 3-1: from either the 23-bit Program Counter (PC) during program execution, or from table operation or data space remapping, as described in Section 3.3 "Interfacing Program and Data Memory Spaces". User access to the program memory space is restricted to the lower half of the address range (000000h to 7FFFFFh). The exception is the use of TBLRD/TBLWT operations which use TBLPAG<7> to permit access to the Configuration bits and Device ID sections of the configuration memory space. Memory maps for the PIC24FJ256GB110 family of devices are shown in Figure 3-1. PROGRAM SPACE MEMORY MAP FOR PIC24FJ256GB110 FAMILY DEVICES PIC24FJ64GB1XX PIC24FJ128GB1XX PIC24FJ192GB1XX PIC24FJ256GB1XX GOTO Instruction Reset Address Interrupt Vector Table GOTO Instruction Reset Address Interrupt Vector Table GOTO Instruction Reset Address Interrupt Vector Table GOTO Instruction Reset Address Interrupt Vector Table Reserved Reserved Reserved Reserved Alternate Vector Table Alternate Vector Table Alternate Vector Table Alternate Vector Table User Flash Program Memory (22K instructions) User Memory Space Flash Config Words User Flash Program Memory (44K instructions) User Flash Program Memory (67K instructions) Flash Config Words User Flash Program Memory (87K instructions) Flash Config Words Unimplemented Read `0' Unimplemented Read `0' 0000FEh 000100h 000104h 0001FEh 000200h 00ABFEh 00AC00h 0157FEh 015800h 020BFEh 020C00h Flash Config Words Unimplemented Read `0' 000000h 000002h 000004h 02ABFEh 02AC00h Unimplemented Read `0' Configuration Memory Space 7FFFFFh 800000h Reserved Reserved Reserved Reserved Device Config Registers Device Config Registers Device Config Registers Device Config Registers Reserved Reserved Reserved Reserved DEVID (2) DEVID (2) DEVID (2) DEVID (2) F7FFFEh F80000h F8000Eh F80010h FEFFFEh FF0000h FFFFFFh Note: Memory areas are not shown to scale. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 31 PIC24FJ256GB110 FAMILY 3.1.1 PROGRAM MEMORY ORGANIZATION 3.1.3 In PIC24FJ256GB110 family devices, the top three words of on-chip program memory are reserved for configuration information. On device Reset, the configuration information is copied into the appropriate Configuration registers. The addresses of the Flash Configuration Word for devices in the PIC24FJ256GB110 family are shown in Table 3-1. Their location in the memory map is shown with the other memory vectors in Figure 3-1. The program memory space is organized in word-addressable blocks. Although it is treated as 24 bits wide, it is more appropriate to think of each address of the program memory as a lower and upper word, with the upper byte of the upper word being unimplemented. The lower word always has an even address, while the upper word has an odd address (Figure 3-2). The Configuration Words in program memory are a compact format. The actual Configuration bits are mapped in several different registers in the configuration memory space. Their order in the Flash Configuration Words do not reflect a corresponding arrangement in the configuration space. Additional details on the device Configuration Words are provided in Section 25.1 "Configuration Bits". Program memory addresses are always word-aligned on the lower word, and addresses are incremented or decremented by two during code execution. This arrangement also provides compatibility with data memory space addressing and makes it possible to access data in the program memory space. 3.1.2 HARD MEMORY VECTORS All PIC24F devices reserve the addresses between 00000h and 000200h for hard coded program execution vectors. A hardware Reset vector is provided to redirect code execution from the default value of the PC on device Reset to the actual start of code. A GOTO instruction is programmed by the user at 000000h with the actual address for the start of code at 000002h. TABLE 3-1: MSW Address Configuration Word Addresses PIC24FJ64GB 22,016 00ABFAh: 00ABFEh PIC24FJ128GB 44,032 0157FAh: 0157FEh PIC24FJ192GB 67,072 020BFAh: 020BFEh PIC24FJ256GB 87,552 02ABFAh: 02ABFEh least significant word most significant word 16 8 PC Address (LSW Address) 0 000000h 000002h 000004h 000006h 00000000 00000000 00000000 00000000 Program Memory `Phantom' Byte (read as `0') DS39897B-page 32 Program Memory (Words) PROGRAM MEMORY ORGANIZATION 23 000001h 000003h 000005h 000007h FLASH CONFIGURATION WORDS FOR PIC24FJ256GB110 FAMILY DEVICES Device PIC24F devices also have two interrupt vector tables, located from 000004h to 0000FFh and 000100h to 0001FFh. These vector tables allow each of the many device interrupt sources to be handled by separate ISRs. A more detailed discussion of the interrupt vector tables is provided in Section 6.1 "Interrupt Vector Table". FIGURE 3-2: FLASH CONFIGURATION WORDS Instruction Width Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 3.2 Data Address Space The PIC24F core has a separate, 16-bit wide data memory space, addressable as a single linear range. The data space is accessed using two Address Generation Units (AGUs), one each for read and write operations. The data space memory map is shown in Figure 3-3. All Effective Addresses (EAs) in the data memory space are 16 bits wide and point to bytes within the data space. This gives a data space address range of 64 Kbytes or 32K words. The lower half of the data memory space (that is, when EA<15> = 0) is used for implemented memory addresses, while the upper half (EA<15> = 1) is reserved for the program space visibility area (see Section 3.3.3 "Reading Data from Program Memory Using Program Space Visibility"). FIGURE 3-3: PIC24FJ256GB110 family devices implement a total of 16 Kbytes of data memory. Should an EA point to a location outside of this area, an all zero word or byte will be returned. 3.2.1 DATA SPACE WIDTH The data memory space is organized in byte-addressable, 16-bit wide blocks. Data is aligned in data memory and registers as 16-bit words, but all data space EAs resolve to bytes. The Least Significant Bytes of each word have even addresses, while the Most Significant Bytes have odd addresses. DATA SPACE MEMORY MAP FOR PIC24FJ256GB110 FAMILY DEVICES MSB Address 0001h 07FFh 0801h Implemented Data RAM MSB LSB SFR Space 1FFFh 2001h Data RAM 47FFh 4801h LSB Address 0000h 07FEh 0800h SFR Space Near Data Space 1FFEh 2000h 47FEh 4800h Unimplemented Read as `0' 7FFFh 8001h 7FFFh 8000h Program Space Visibility Area FFFFh Note: FFFEh Data memory areas are not shown to scale. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 33 PIC24FJ256GB110 FAMILY 3.2.2 DATA MEMORY ORGANIZATION AND ALIGNMENT A sign-extend instruction (SE) is provided to allow users to translate 8-bit signed data to 16-bit signed values. Alternatively, for 16-bit unsigned data, users can clear the MSB of any W register by executing a zero-extend (ZE) instruction on the appropriate address. To maintain backward compatibility with PIC(R) devices and improve data space memory usage efficiency, the PIC24F instruction set supports both word and byte operations. As a consequence of byte accessibility, all Effective Address calculations are internally scaled to step through word-aligned memory. For example, the core recognizes that Post-Modified Register Indirect Addressing mode [Ws++] will result in a value of Ws + 1 for byte operations and Ws + 2 for word operations. Although most instructions are capable of operating on word or byte data sizes, it should be noted that some instructions operate only on words. 3.2.3 The 8-Kbyte area between 0000h and 1FFFh is referred to as the near data space. Locations in this space are directly addressable via a 13-bit absolute address field within all memory direct instructions. The remainder of the data space is addressable indirectly. Additionally, the whole data space is addressable using MOV instructions, which support Memory Direct Addressing with a 16-bit address field. Data byte reads will read the complete word which contains the byte, using the LSb of any EA to determine which byte to select. The selected byte is placed onto the LSB of the data path. That is, data memory and registers are organized as two parallel, byte-wide entities with shared (word) address decode but separate write lines. Data byte writes only write to the corresponding side of the array or register which matches the byte address. 3.2.4 All word accesses must be aligned to an even address. Misaligned word data fetches are not supported, so care must be taken when mixing byte and word operations, or translating from 8-bit MCU code. If a misaligned read or write is attempted, an address error trap will be generated. If the error occurred on a read, the instruction underway is completed; if it occurred on a write, the instruction will be executed but the write will not occur. In either case, a trap is then executed, allowing the system and/or user to examine the machine state prior to execution of the address Fault. SFR SPACE The first 2 Kbytes of the near data space, from 0000h to 07FFh, are primarily occupied with Special Function Registers (SFRs). These are used by the PIC24F core and peripheral modules for controlling the operation of the device. SFRs are distributed among the modules that they control and are generally grouped together by module. Much of the SFR space contains unused addresses; these are read as `0'. A diagram of the SFR space, showing where SFRs are actually implemented, is shown in Table 3-2. Each implemented area indicates a 32-byte region where at least one address is implemented as an SFR. A complete listing of implemented SFRs, including their addresses, is shown in Tables 3-3 through 3-30. All byte loads into any W register are loaded into the Least Significant Byte. The Most Significant Byte is not modified. TABLE 3-2: NEAR DATA SPACE IMPLEMENTED REGIONS OF SFR DATA SPACE SFR Space Address xx00 xx20 000h xx40 xx60 Core 100h xx80 ICN Timers xxA0 xxC0 xxE0 Interrupts Capture -- Compare 200h I2CTM UART SPI/UART SPI/I2C SPI UART 300h A/D A/D/CTMU -- -- -- -- 400h -- -- -- -- 500h -- -- -- -- 600h PMP RTC/Comp CRC -- 700h -- -- System NVM/PMD I/O -- USB -- -- -- -- PPS -- -- -- -- -- -- -- Legend: -- = No implemented SFRs in this block DS39897B-page 34 Preliminary (c) 2008 Microchip Technology Inc. (c) 2008 Microchip Technology Inc. Preliminary 0012 0014 0016 0018 001A 001C 001E 0020 002E 0030 0032 0034 0036 WREG9 WREG10 WREG11 WREG12 WREG13 WREG14 WREG15 SPLIM PCL PCH TBLPAG PSVPAG RCOUNT -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 0010 WREG8 Legend: 000E WREG7 Bit 10 0052 000C WREG6 Bit 11 DISICNT 000A WREG5 Bit 12 0044 0008 WREG4 Bit 13 0042 0006 WREG3 Bit 14 SR 0004 WREG2 Bit 15 CPU CORE REGISTERS MAP CORCON 0000 0002 WREG0 WREG1 Addr File Name TABLE 3-3: Bit 7 Working Register 15 Working Register 14 Working Register 13 Working Register 12 Working Register 11 Working Register 10 Working Register 9 Working Register 8 Working Register 7 Working Register 6 Working Register 5 Working Register 4 Working Register 3 Working Register 2 Working Register 1 Working Register 0 Bit 8 Bit 6 -- -- -- -- -- -- IPL2 -- IPL1 Bit 4 Bit 3 Bit 2 -- IPL0 -- RA IPL3 N PSV OV Program Space Visibility Page Address Register Table Memory Page Address Register Program Counter Register High Byte Bit 5 Disable Interrupts Counter Register -- DC Repeat Loop Counter Register -- -- -- Program Counter Low Word Register Stack Pointer Limit Value Register Bit 9 -- Z Bit 1 -- C Bit 0 xxxx 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0800 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 All Resets PIC24FJ256GB110 FAMILY DS39897B-page 35 DS39897B-page 36 0064 0066 0068 CNEN3 CNEN4 CNEN5 Legend: Note 1: 2: -- -- -- -- CN59PUE -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Unimplemented in 64-pin devices; read as `0'. Unimplemented in 64-pin and 80-pin devices; read as `0'. -- CN60PUE CN25PUE CN24PUE -- -- -- -- -- CN58PUE CN57PUE(1) CN56PUE 0074 CN79PUE(2) CN78PUE(1) CN77PUE(1) CN76PUE(2) CN75PUE(2) CN74PUE(1) CNPU6(2) 0076 CN61PUE CNPU5 CN62PUE 0072 CNPU4 CN63PUE CN26PUE -- CN71PUE CN55PUE CN23PUE CN7PUE -- CN70PUE(1) CN54PUE CN22PUE CN6PUE -- CN4PUE -- CN68IE CN52IE CN36IE(2) CN3PUE -- CN67IE(1) CN51IE CN35IE(2) CN19IE(1) CN3IE -- -- CN69PUE CN53PUE CN65PDE CN49PDE CN64PDE CN51PUE -- -- 0000 CN48PDE(2) 0000 0000 0000 0000 All Resets CN50PUE CN18PUE CN2PUE CN82IE(2) CN66IE(1) CN50IE CN34IE(2) CN18IE CN2IE CN0IE 0000 0000 0000 0000 0000 0000 0000 0000 0000 CN64PUE 0000 CN48PUE(2) 0000 CN0PUE CN80IE(2) CN64IE CN48IE(2) CN32IE CN16IE CN82PUE(2) CN81PUE(2) CN80PUE(2) 0000 CN65PUE CN49PUE CN1PUE CN81IE(2) CN65IE CN49IE CN33IE(2) CN17IE CN1IE CN82PDE(2) CN81PDE(2) CN80PDE(2) 0000 CN68PUE CN67PUE(1) CN66PUE(1) CN52PUE CN21PUE(1) CN20PUE(1) CN19PUE(1) CN5PUE -- CN69IE CN53IE CN37IE(2) CN4IE CN20IE(1) CN5IE -- CN21IE(1) -- CN50PDE CN0PDE CN32PUE CN27PUE CN8PUE -- CN70IE(1) CN54IE CN38IE(2) CN22IE CN6IE -- CN51PDE CN68PDE CN67PDE(1) CN66PDE(1) CN52PDE CN1PDE 0070 CN47PUE(1) CN46PUE(2) CN45PUE(1) CN44PUE(1) CN43PUE(1) CN42PUE(1) CN41PUE(1) CN40PUE(2) CN39PUE(2) CN38PUE(2) CN37PUE(2) CN36PUE(2) CN35PUE(2) CN34PUE(2) CN33PUE(2) CN28PUE CN9PUE -- CN71IE CN55IE CN39IE(2) CN23IE CN7IE -- CN69PDE CN53PDE CN18PDE CN2PDE Bit 0 CNPU3 CN29PUE CN10PUE -- -- CN56IE CN57IE(1) -- CN40IE(2) CN24IE CN8IE -- CN41IE(1) CN25IE CN9IE -- CN3PDE Bit 1 CN16PUE CN30PUE CN11PUE -- CN74IE(1) CN58IE CN42IE(1) CN26IE CN10IE -- CN70PDE(1) CN4PDE CN21PDE(1) CN20PDE(1) CN19PDE(1) CN5PDE Bit 2 CN17PUE CN31PUE CN12PUE -- CN75IE(2) CN59IE CN43IE(1) CN27IE CN11IE -- CN71PDE CN54PDE CN22PDE CN6PDE Bit 3 006E CN13PUE -- CN76IE(2) CN60IE CN44IE(1) CN28IE CN12IE -- -- CN55PDE CN23PDE CN7PDE Bit 4 CNPU2 CN14PUE -- CN77IE(1) CN61IE CN45IE(1) CN29IE CN13IE -- -- CN58PDE CN57PDE(1) CN56PDE CN24PDE CN8PDE Bit 5 006C CN15PUE -- CN78IE(1) CN79IE(2) -- CN62IE CN46IE(2) CN47IE(1) CN63IE CN30IE CN14IE -- CN31IE CN15IE -- CN59PDE CN25PDE CN9PDE Bit 6 CNPU1 CNEN6(2) 006A 0060 0062 CNEN2 005E CNEN1 CNPD6 CN60PDE 005C CN79PDE(2) CN78PDE(1) CN77PDE(1) CN76PDE(2) CN75PDE(2) CN74PDE(1) (2) CN61PDE CNPD5 CN62PDE 005A CNPD4 CN63PDE CN26PDE CN10PDE Bit 7 CN32PDE CN27PDE CN11PDE Bit 8 0058 CN47PDE(1) CN46PDE(2) CN45PDE(1) CN44PDE(1) CN43PDE(1) CN42PDE(1) CN41PDE(1) CN40PDE(2) CN39PDE(2) CN38PDE(2) CN37PDE(2) CN36PDE(2) CN35PDE(2) CN34PDE(2) CN33PDE(2) CN28PDE CN12PDE Bit 9 CNPD3 CN29PDE CN13PDE Bit 10 CN16PDE CN30PDE CN14PDE Bit 11 CN17PDE CN31PDE CN15PDE Bit 12 0054 Bit 13 0056 Bit 14 CNPD2 Bit 15 ICN REGISTER MAP CNPD1 Addr File Name TABLE 3-4: PIC24FJ256GB110 FAMILY Preliminary (c) 2008 Microchip Technology Inc. (c) 2008 Microchip Technology Inc. Preliminary Legend: -- CNIP2 -- T2IP0 T1IP0 OC9IE -- -- OC8IE T5IE U1TXIE OC9IF -- -- OC8IF T5IF U1TXIF -- -- Bit 12 U3TXIP2 U3TXIP1 -- -- CRCIP1 -- -- -- -- OC7IP1 IC5IP1 -- U2TXIP1 T4IP1 IC8IP1 CNIP1 -- U3TXIP0 -- -- CRCIP0 -- -- -- -- OC7IP0 IC5IP0 -- U2TXIP0 T4IP0 IC8IP0 CNIP0 -- SPI3IP2 -- -- -- -- SPI3IP1 -- SPI3IP0 U4ERIP2 U4ERIP1 U4ERIP0 -- -- -- -- -- -- CRCIP2 -- -- -- -- -- -- -- -- OC7IP2 -- -- IC5IP2 -- -- U2TXIP2 -- -- T4IP2 -- IC8IP2 -- -- -- T2IP1 T1IP1 IC9IE CTMUIE -- PMPIE INT2IE AD1IE IC9IF CTMUIF -- PMPIF INT2IF AD1IF -- -- Bit 13 U1RXIP2 U1RXIP1 U1RXIP0 T2IP2 -- -- T1IP2 -- -- -- -- -- -- RTCIE -- U2RXIE -- -- U2TXIE -- -- -- -- -- RTCIF -- -- U2RXIF -- -- U2TXIF DISI -- Bit 14 ALTIVT NSTDIS Bit 15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- SPI3IE -- -- OC7IE T4IE U1RXIE SPI3IF -- -- OC7IF T4IF U1RXIF -- -- Bit 11 OC4IP1 IC7IP1 CMIP1 -- SPI1IP1 OC2IP1 OC1IP1 U4TXIE -- -- OC5IE OC3IE SPF1IE U4TXIF -- -- OC5IF OC3IF SPF1IF -- -- Bit 9 OC4IP0 IC7IP0 CMIP0 -- SPI1IP0 OC2IP0 OC1IP0 U4RXIE LVDIE -- -- OC6IP1 IC4IP1 -- -- OC6IP0 IC4IP0 -- RTCIP1 INT4IP1 RTCIP0 INT4IP0 -- -- -- -- -- SPF3IP2 -- SPF3IP1 -- SPF3IP0 USB1IP2 USB1IP1 USB1IP0 U3RXIP2 U3RXIP1 U3RXIP0 -- -- U2ERIP2 U2ERIP1 U2ERIP0 RTCIP2 INT4IP2 MI2C2P2 MI2C2P1 MI2C2P0 -- OC6IP2 IC4IP2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- U4ERIE -- -- IC5IE IC8IE -- IC6IE T2IE U4ERIF -- -- T3IE U4RXIF LVDIF -- IC5IF IC8IF -- IC6IF T2IF -- -- Bit 7 T3IF -- -- Bit 8 U2RXIP2 U2RXIP1 U2RXIP0 OC4IP2 IC7IP2 CMIP2 -- SPI1IP2 OC2IP2 OC1IP2 SPF3IE -- -- OC6IE OC4IE SPI1IE SPF3IF -- -- OC6IF OC4IF SPI1IF -- -- Bit 10 INTERRUPT CONTROLLER REGISTER MAP -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 00D2 00CC IPC20 IPC23 00CA IPC19 00D0 00C8 IPC18 IPC22 00C4 IPC16 00CE 00C2 IPC15 IPC21 00BE IPC13 00B6 IPC9 00BC 00B4 IPC8 IPC12 00B2 IPC7 00B8 00B0 IPC6 00BA 00AE IPC5 IPC11 00AC IPC4 IPC10 00A8 00A6 IPC1 00AA 00A4 IPC0 IPC3 009E IEC5 IPC2 009C IEC4 0096 IEC1 0098 0094 IEC0 009A 008E IFS5 IEC3 008C IFS4 IEC2 0088 008A 0086 IFS1 IFS3 0084 IFS0 IFS2 0080 0082 INTCON1 INTCON2 Addr File Name TABLE 3-5: AD1IP1 SPF1IP1 IC2IP1 IC1IP1 MI2C3IE -- INT3IE IC3IE -- IC2IE MI2C3IF -- INT3IF IC3IF -- IC2IF -- -- Bit 5 -- INT3IP1 SI2C2P1 PMPIP1 OC5IP1 IC3IP1 SPI2IP1 INT2IP1 OC3IP1 -- -- IC9IP2 U4TXIP2 IC9IP1 U4TXIP1 MI2C3P2 MI2C3P1 U3ERIP2 U3ERIP1 Bit 3 Bit 2 Bit 1 -- U1ERIP0 -- INT3IP0 SI2C2P0 PMPIP0 OC5IP0 IC3IP0 SPI2IP0 INT2IP0 OC3IP0 -- MI2C1P0 AD1IP0 SPF1IP0 IC2IP0 IC1IP0 SI2C3IE -- -- -- INT1IE -- SI2C3IF -- -- -- INT1IF -- -- U3ERIP0 IC9IP0 U4TXIP0 MI2C3P0 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- U3TXIE CRCIE -- -- CNIE T1IE U3TXIF CRCIF -- -- CNIF T1IF -- SI2C3P1 -- -- LVDIP1 -- -- -- -- OC8IP1 IC6IP1 -- SPF2IP1 T5IP1 -- INT1IP1 SI2C1P1 U1TXIP1 T3IP1 -- INT0IP1 U3ERIE U1ERIE SI2C2IE SPI2IE MI2C1IE IC1IE U3ERIF U1ERIF SI2C2IF SPI2IF MI2C1IF IC1IF INT1EP SI2C3P0 -- -- LVDIP0 -- -- -- -- OC8IP0 IC6IP0 -- SPF2IP0 T5IP0 -- INT1IP0 SI2C1P0 U1TXIP0 T3IP0 -- INT0IP0 -- -- -- SPF2IE SI2C1IE INT0IE -- -- -- SPF2IF SI2C1IF INT0IF INT0EP -- Bit 0 OC9IP2 OC9IP1 OC9IP0 U4RXIP2 U4RXIP1 U4RXIP0 SI2C3P2 -- -- LVDIP2 -- -- -- -- OC8IP2 IC6IP2 -- SPF2IP2 T5IP2 -- INT1IP2 SI2C1P2 U1TXIP2 T3IP2 -- INT0IP2 U3RXIE U2ERIE MI2C2IE -- CMIE OC1IE U3RXIF U2ERIF MI2C2IF -- CMIF OC1IF INT2EP MATHERR ADDRERR STKERR OSCFAIL Bit 4 CTMUIP2 CTMUIP1 CTMUIP0 -- U1ERIP2 U1ERIP1 -- INT3IP2 SI2C2P2 PMPIP2 OC5IP2 IC3IP2 SPI2IP2 INT2IP2 OC3IP2 -- MI2C1P2 MI2C1P1 AD1IP2 SPF1IP2 IC2IP2 IC1IP2 USB1IE -- INT4IE IC4IE IC7IE OC2IE USB1IF -- INT4IF IC4IF IC7IF OC2IF -- -- Bit 6 0044 4444 4444 4440 0040 0004 4440 0400 0440 0440 0044 4444 4440 0044 4444 4440 4404 4444 0044 4444 4440 4444 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 All Resets PIC24FJ256GB110 FAMILY DS39897B-page 37 DS39897B-page 38 0118 011A TMR5 PR4 TON -- -- TSIDL TSIDL -- -- -- -- -- -- -- -- -- TON -- TSIDL -- -- Bit 7 -- Timer2 Register -- Timer1 Period Register Timer1 Register Bit 8 TGATE Bit 6 Bit 5 TCKPS1 -- -- -- -- -- Timer4 Register -- -- Timer3 Period Register Timer2 Period Register Timer3 Register TGATE TGATE TCKPS1 TCKPS1 -- -- -- -- -- -- Timer5 Period Register Timer4 Period Register Timer5 Register TGATE TGATE TCKPS1 TCKPS1 Timer5 Holding Register (for 32-bit operations only) 0120 0116 TMR5HLD TON TSIDL -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 0114 TMR4 -- -- Bit 9 Timer3 Holding Register (for 32-bit timer operations only) -- Bit 10 Legend: 0112 T3CON TON -- Bit 11 T5CON 0110 T2CON -- Bit 12 011E 010E PR3 TSIDL Bit 13 T4CON 010C PR2 -- Bit 14 011C 010A TMR3 TON Bit 15 TIMER REGISTER MAP PR5 0106 0108 T1CON TMR3HLD 0104 PR1 TMR2 0100 0102 TMR1 Addr File Name TABLE 3-6: TCKPS0 TCKPS0 TCKPS0 TCKPS0 TCKPS0 Bit 4 -- T32 -- T32 -- Bit 3 -- -- -- -- TSYNC Bit 2 TCS TCS TCS TCS TCS Bit 1 -- -- -- -- -- Bit 0 0000 0000 FFFF FFFF 0000 0000 0000 0000 0000 FFFF FFFF 0000 0000 0000 0000 FFFF 0000 All Resets PIC24FJ256GB110 FAMILY Preliminary (c) 2008 Microchip Technology Inc. (c) 2008 Microchip Technology Inc. Preliminary 0180 IC9CON1 Legend: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 14 -- Bit 15 -- ICSIDL -- ICSIDL -- ICSIDL -- ICSIDL -- ICSIDL -- ICSIDL -- ICSIDL -- ICSIDL -- ICSIDL Bit 13 Bit 11 Bit 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- ICTSEL2 ICTSEL1 ICTSEL0 -- ICTSEL2 ICTSEL1 ICTSEL0 -- ICTSEL2 ICTSEL1 ICTSEL0 -- ICTSEL2 ICTSEL1 ICTSEL0 -- ICTSEL2 ICTSEL1 ICTSEL0 -- ICTSEL2 ICTSEL1 ICTSEL0 -- ICTSEL2 ICTSEL1 ICTSEL0 -- ICTSEL2 ICTSEL1 ICTSEL0 -- ICTSEL2 ICTSEL1 ICTSEL0 Bit 12 INPUT CAPTURE REGISTER MAP -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 0184 0186 IC9BUF IC9TMR 0182 017E IC9CON2 017C IC8CON2 IC8BUF 0178 017A IC8CON1 IC8TMR 0174 0172 IC7CON2 0176 0170 IC7CON1 IC7BUF 016E IC7TMR 016C IC6CON2 IC6BUF 0168 016A IC6CON1 IC6TMR 0164 0162 IC5CON2 0166 0160 IC5CON1 IC5BUF 015E IC5TMR 015C IC4CON2 IC4BUF 0158 015A IC4CON1 IC4TMR 0154 0156 0152 IC3CON2 IC3BUF 0150 IC3CON1 IC3TMR 014E IC2CON2 014C 0148 014A IC2CON1 IC2BUF 0146 IC2TMR 0144 IC1BUF 0140 0142 IC1CON1 IC1CON2 IC1TMR Addr File Name TABLE 3-7: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 9 ICTRIG -- Bit 7 TRIGSTAT ICI1 Bit 6 -- ICTRIG ICI1 TRIGSTAT -- ICTRIG ICI1 TRIGSTAT -- ICTRIG ICI1 TRIGSTAT -- ICTRIG ICI1 TRIGSTAT -- ICTRIG ICI1 TRIGSTAT -- ICTRIG ICI1 TRIGSTAT -- ICTRIG ICI1 TRIGSTAT -- ICTRIG ICI1 TRIGSTAT Timer Value 9 Register Input Capture 9 Buffer Register IC32 -- Timer Value 8 Register Input Capture 8 Buffer Register IC32 -- Timer Value 7 Register Input Capture 7 Buffer Register IC32 -- Timer Value 6 Register Input Capture 6 Buffer Register IC32 -- Timer Value 5 Register Input Capture 5 Buffer Register IC32 -- Timer Value 4 Register Input Capture 4 Buffer Register IC32 -- Timer Value 3 Register Input Capture 3 Buffer Register IC32 -- Timer Value 2 Register Input Capture 2 Buffer Register IC32 -- Timer Value 1 Register Input Capture 1 Buffer Register IC32 -- Bit 8 -- ICI0 -- ICI0 -- ICI0 -- ICI0 -- ICI0 -- ICI0 -- ICI0 -- ICI0 -- ICI0 Bit 5 ICBNE Bit 3 ICM2 Bit 2 ICM1 Bit 1 ICM0 Bit 0 ICBNE ICM2 ICM1 ICM0 ICBNE ICM2 ICM1 ICM0 ICBNE ICM2 ICM1 ICM0 ICBNE ICM2 ICM1 ICM0 ICBNE ICM2 ICM1 ICM0 ICBNE ICM2 ICM1 ICM0 ICBNE ICM2 ICM1 ICM0 ICBNE ICM2 ICM1 ICM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 ICOV SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 ICOV SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 ICOV SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 ICOV SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 ICOV SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 ICOV SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 ICOV SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 ICOV SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 ICOV Bit 4 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 xxxx 0000 0000 0000 All Resets PIC24FJ256GB110 FAMILY DS39897B-page 39 DS39897B-page 40 Preliminary 01C4 01C6 01C8 01CA 01CC 01CE 01D0 01D2 01D4 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. OC6CON2 OC6RS OC6R OC6TMR OC7CON1 OC7CON2 OC7RS OC7R OC7TMR Legend: FLTMD -- FLTMD -- OCSIDL OCSIDL FLTOUT FLTTRIEN -- FLTOUT FLTTRIEN -- -- 01C2 -- -- -- -- -- OCINV -- -- OCTSEL2 OCTSEL1 OCTSEL0 OCINV OCTSEL2 OCTSEL1 OCTSEL0 OCINV OCTSEL2 OCTSEL1 OCTSEL0 OCINV OC6CON1 OCSIDL FLTOUT FLTTRIEN -- FLTOUT FLTTRIEN 01C0 FLTMD -- FLTMD OC5TMR OCTSEL2 OCTSEL1 OCTSEL0 01BE OCSIDL OC5R -- -- 01BC -- -- OC5RS OC3TMR OCINV OCTSEL2 OCTSEL1 OCTSEL0 01BA 01AC OC3R FLTOUT FLTTRIEN OCSIDL OC5CON2 01AA OC3RS FLTMD -- 01B8 01A8 OC3CON2 -- -- OC5CON1 01A6 OC3CON1 -- 01B6 01A4 OC2TMR OCINV OCTSEL2 OCTSEL1 OCTSEL0 OC4TMR 01A2 OC2R FLTOUT FLTTRIEN OCSIDL -- 01B4 01A0 OC2RS FLTMD -- -- OC4R 019E OC2CON2 -- OCINV 01B2 019C OC2CON1 Bit 10 OC4RS 019A OC1TMR Bit 11 OCTSEL2 OCTSEL1 OCTSEL0 Bit 12 01B0 0198 OC1R OCSIDL FLTOUT FLTTRIEN -- Bit 13 OC4CON2 0196 OC1RS -- FLTMD Bit 14 01AE 0194 OC1CON2 Bit 15 OUTPUT COMPARE REGISTER MAP OC4CON1 0190 0192 OC1CON1 Addr File Name TABLE 3-8: -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 9 OCTRIG ENFLT0 Bit 7 TRIGSTAT -- Bit 6 OCTRIG ENFLT0 TRIGSTAT -- OCTRIG ENFLT0 TRIGSTAT -- OCTRIG ENFLT0 TRIGSTAT -- OCTRIG ENFLT0 TRIGSTAT -- OCTRIG ENFLT0 TRIGSTAT -- OCTRIG ENFLT0 TRIGSTAT -- Timer Value 7 Register Output Compare 7 Register Output Compare 7 Secondary Register OC32 -- Timer Value 6 Register Output Compare 6 Register Output Compare 6 Secondary Register OC32 -- Timer Value 5 Register Output Compare 5 Register Output Compare 5 Secondary Register OC32 -- Timer Value 4 Register Output Compare 4 Register Output Compare 4 Secondary Register OC32 -- Timer Value 3 Register Output Compare 3 Register Output Compare 3 Secondary Register OC32 -- Timer Value 2 Register Output Compare 2 Register Output Compare 2 Secondary Register OC32 -- Timer Value 1 Register Output Compare 1 Register Output Compare 1 Secondary Register OC32 -- Bit 8 OCTRIS -- OCTRIS -- OCTRIS -- OCTRIS -- OCTRIS -- OCTRIS -- OCTRIS -- Bit 5 TRIGMODE Bit 3 OCM2 Bit 2 OCM1 Bit 1 OCM0 Bit 0 TRIGMODE OCM2 OCM1 OCM0 TRIGMODE OCM2 OCM1 OCM0 TRIGMODE OCM2 OCM1 OCM0 TRIGMODE OCM2 OCM1 OCM0 TRIGMODE OCM2 OCM1 OCM0 TRIGMODE OCM2 OCM1 OCM0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 OCFLT0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 OCFLT0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 OCFLT0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 OCFLT0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 OCFLT0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 OCFLT0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 OCFLT0 Bit 4 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 All Resets PIC24FJ256GB110 FAMILY (c) 2008 Microchip Technology Inc. (c) 2008 Microchip Technology Inc. 01E0 01E2 01E4 01E6 01E8 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. OC9CON1 OC9CON2 OC9RS OC9R OC9TMR Legend: Preliminary 0204 0206 0208 020A 020C 0210 0212 0214 0216 0218 021A 021C 0270 0272 0274 0276 0278 027A 027C I2C1BRG I2C1CON I2C1STAT I2C1ADD I2C1MSK I2C2RCV I2C2TRN I2C2BRG I2C2CON I2C2STAT I2C2ADD I2C2MSK I2C3RCV I2C3TRN I2C3BRG I2C3CON I2C3STAT I2C3ADD I2C3MSK OCSIDL -- -- -- -- -- -- -- -- -- ACKSTAT TRSTAT -- -- -- I2CEN -- -- -- -- -- -- ACKSTAT TRSTAT -- -- -- I2CEN -- -- -- -- -- -- ACKSTAT TRSTAT I2CEN -- -- -- -- -- Bit 14 -- Bit 15 -- -- -- I2CSIDL -- -- -- -- -- -- I2CSIDL -- -- -- -- -- -- I2CSIDL -- -- -- Bit 13 -- -- -- -- SCLREL -- -- -- -- -- -- SCLREL -- -- -- -- -- -- SCLREL -- -- -- Bit 12 OCINV -- -- -- IPMIEN -- -- -- -- -- -- IPMIEN -- -- -- -- -- -- IPMIEN -- -- -- Bit 11 -- -- -- BCL A10M -- -- -- -- -- BCL A10M -- -- -- -- -- BCL A10M -- -- -- -- -- -- -- OCTRIG ENFLT0 Bit 7 TRIGSTAT -- Bit 6 OCTRIG ENFLT0 TRIGSTAT -- -- -- -- Bit 9 GCSTAT DISSLW -- -- -- GCSTAT DISSLW -- -- -- GCSTAT ADD10 SMEN -- -- ADD10 SMEN -- -- ADD10 SMEN -- -- Bit 8 IWCOL GCEN IWCOL GCEN IWCOL GCEN Bit 7 Timer Value 9 Register Output Compare 9 Register -- Bit 5 I2COV STREN I2COV STREN I2COV STREN OCFLT0 Bit 4 TRIGMODE Bit 3 OCM2 Bit 2 OCM1 Bit 1 OCM0 Bit 0 TRIGMODE OCM2 OCM1 OCM0 Bit 3 P ACKEN S RCEN P ACKEN S RCEN P ACKEN Address Mask Register Address Register D/A ACKDT S RCEN Baud Rate Generator Register Transmit Register Receive Register Address Mask Register Address Register D/A ACKDT Baud Rate Generator Register Transmit Register Receive Register Address Mask Register Address Register D/A ACKDT Baud Rate Generator Register Transmit Register Receive Register Bit 4 R/W PEN R/W PEN R/W PEN Bit 2 RBF RSEN RBF RSEN RBF RSEN Bit 1 TBF SEN TBF SEN TBF SEN Bit 0 xxxx 0000 0000 0000 0000 xxxx 0000 0000 0000 0000 All Resets 0000 0000 0000 1000 0000 00FF 0000 0000 0000 0000 1000 0000 00FF 0000 0000 0000 0000 1000 0000 00FF 0000 All Resets SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 OCFLT0 SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 Bit 5 OCTRIS -- OCTRIS Bit 6 Output Compare 9 Secondary Register OC32 -- Timer Value 8 Register Output Compare 8 Register Output Compare 8 Secondary Register OC32 -- Bit 8 DISSLW Bit 9 Bit 10 OCTSEL2 OCTSEL1 OCTSEL0 I2CTM REGISTER MAP FLTOUT FLTTRIEN -- -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 0200 0202 Addr I2C1RCV Legend: -- FLTMD I2C1TRN File Name TABLE 3-9: 01DE OC8TMR -- 01DC -- OC8R OCINV OCTSEL2 OCTSEL1 OCTSEL0 Bit 10 01DA OCSIDL FLTOUT FLTTRIEN -- Bit 11 OC8RS FLTMD -- Bit 12 01D6 Bit 13 01D8 Bit 14 OC8CON2 Bit 15 OUTPUT COMPARE REGISTER MAP (CONTINUED) OC8CON1 Addr File Name TABLE 3-8: PIC24FJ256GB110 FAMILY DS39897B-page 41 DS39897B-page 42 0252 0254 0256 0258 U3STA U3TXREG U3RXREG U3BRG UARTEN -- -- -- -- UARTEN -- -- UTXISEL1 UTXINV USIDL -- -- UTXISEL0 USIDL -- -- -- -- -- IREN -- -- RTSMD -- -- UTXBRK RTSMD -- -- UTXBRK -- -- -- -- UTXEN -- -- -- UTXEN Preliminary 0288 -- -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. SPIFPOL -- SPI3BUF SPIFSD DISSDO DISSCK -- MODE16 LPBACK Bit 6 URXISEL1 URXISEL0 WAKE Bit 7 WAKE LPBACK URXISEL1 URXISEL0 UEN0 TRMT WAKE LPBACK URXISEL1 URXISEL0 UEN0 TRMT WAKE LPBACK URXISEL1 URXISEL0 Bit 9 Bit 8 -- SMP -- SMP -- SMP -- SSEN SRMPT -- SSEN -- SSEN -- CKP -- CKP SPIROV Transmit and Receive Buffer -- CKE SRMPT -- CKP SPIROV Transmit and Receive Buffer -- CKE SRMPT Bit 6 SPIROV Transmit and Receive Buffer -- CKE Bit 7 Baud Rate Generator Prescaler Register -- -- UTXBF UEN1 Baud Rate Generator Prescaler Register -- -- UTXBF UEN1 Baud Rate Generator Prescaler Register -- -- UEN0 TRMT SPIBEC2 SPIBEC1 SPIBEC0 Legend: FRMEN -- -- -- MODE16 0284 -- -- -- -- -- UEN1 UTXBF SPIBEC2 SPIBEC1 SPIBEC0 SPI3CON2 -- SPIEN SPISIDL SPIFPOL DISSDO DISSCK -- -- 0282 SPIFSD -- -- -- MODE16 SPI3CON1 FRMEN -- SPISIDL -- TRMT UEN0 Bit 8 Baud Rate Generator Prescaler Register -- -- UTXBF UEN1 Bit 9 SPIBEC2 SPIBEC1 SPIBEC0 Bit 10 0280 0264 SPI2CON2 -- -- SPIFPOL DISSDO -- Bit 11 -- 0268 0262 SPI2CON1 SPIEN SPIFSD DISSCK -- Bit 12 -- -- UTXEN SPI2BUF 0260 FRMEN -- SPISIDL Bit 13 -- -- -- -- RTSMD UTXBRK IREN SPI3STAT 0248 SPI1BUF SPI2STAT 0244 -- -- SPI1CON2 -- SPIEN 0240 0242 Bit 14 Bit 15 SPI1STAT -- -- UTXISEL0 SPI REGISTER MAPS -- -- Addr SPI1CON1 File Name TABLE 3-11: -- -- UTXISEL1 UTXINV -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 0250 U3MODE -- -- -- IREN Legend: 0238 U2BRG -- -- USIDL UTXISEL0 -- 02B8 0236 U2RXREG -- -- -- U4BRG 0234 U2TXREG UARTEN UTXISEL1 UTXINV -- -- -- UTXEN 02B6 0232 U2STA -- -- -- U4RXREG 0230 U2MODE -- -- -- RTSMD UTXBRK IREN Bit 10 02B4 0228 U1BRG -- -- USIDL UTXISEL0 Bit 11 U4TXREG 0226 U1RXREG -- Bit 12 02B0 0224 U1TXREG UARTEN UTXISEL1 UTXINV Bit 13 02B2 0222 Bit 14 U4STA 0220 U1MODE U1STA Bit 15 UART REGISTER MAPS U4MODE Addr File Name TABLE 3-10: ABAUD ABAUD MSTEN SRXMPT Bit 5 MSTEN SRXMPT -- MSTEN SRXMPT -- SPRE2 SISEL2 -- SPRE2 SISEL2 -- SPRE2 SISEL2 Bit 4 Bit 3 PERR BRGH PERR BRGH PERR BRGH PERR BRGH Bit 3 -- SPRE1 SISEL1 -- SPRE1 SISEL1 -- SPRE1 SISEL1 Receive Register Transmit Register RIDLE RXINV Receive Register ADDEN -- RIDLE RXINV Transmit Register ADDEN ABAUD Receive Register Transmit Register RIDLE RXINV Receive Register ADDEN -- RIDLE RXINV Bit 4 Transmit Register ADDEN ABAUD Bit 5 -- SPRE0 SISEL0 -- SPRE0 SISEL0 -- SPRE0 SISEL0 Bit 2 FERR PDSEL1 FERR PDSEL1 FERR PDSEL1 FERR PDSEL1 Bit 2 SPIFE PPRE1 SPITBF SPIFE PPRE1 SPITBF SPIFE PPRE1 SPITBF Bit 1 OERR PDSEL0 OERR PDSEL0 OERR PDSEL0 OERR PDSEL0 Bit 1 SPIBEN PPRE0 SPIRBF SPIBEN PPRE0 SPIRBF SPIBEN PPRE0 SPIRBF Bit 0 URXDA STSEL URXDA STSEL URXDA STSEL URXDA STSEL Bit 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 All Resets 0000 0000 xxxx 0110 0000 0000 0000 xxxx 0110 0000 0000 0000 xxxx 0110 0000 0000 0000 xxxx 0110 0000 All Resets PIC24FJ256GB110 FAMILY (c) 2008 Microchip Technology Inc. 02C4 02C6 LATA ODCA (c) 2008 Microchip Technology Inc. 02CE ODCB ODA14 LATA14 RA14 -- -- -- -- -- -- -- -- Bit 12 -- -- -- -- Bit 11 ODA10 LATA10 RA10 TRISA10 Bit 10 ODA9 LATA9 RA9 TRISA9 Bit 9 -- -- -- -- Bit 8 ODA7 LATA7 RA7 TRISA7 Bit 7(2) ODA6 LATA6 RA6 TRISA6 Bit 6(2) ODA5 LATA5 RA5 TRISA5 Bit 5(2) ODA4 LATA4 RA4 TRISA4 Bit 4(2) ODA3 LATA3 RA3 TRISA3 Bit 3(2) ODA2 LATA2 RA2 TRISA2 Bit2(2) Bit 14 Bit 13 Bit 12 Bit 11 ODB15 LATB15 RB15 ODB14 LATB14 RB14 ODB13 LATB13 RB13 Preliminary 02DE LATD ODCD Bit 14(1) Bit 13(1) Bit 12(1) Bit 11 -- Bit 10 -- ODD15 LATD15 RD15 ODD14 LATD14 RD14 ODD13 LATD13 RD13 ODD12 LATD12 RD12 ODD11 LATD11 RD11 ODD10 LATD10 RD10 TRISD15 TRISD14 TRISD13 TRISD12 TRISD11 TRISD10 Bit 15(1) PORTD REGISTER MAP ODC12 ODD9 LATD9 RD9 TRISD9 Bit 9 -- ODD8 LATD8 RD8 TRISD8 Bit 8 -- -- ODD7 LATD7 RD7 TRISD7 Bit 7 -- -- ODD6 LATD6 RD6 TRISD6 Bit 6 -- -- -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented on 64-pin devices; read as `0'. 02DC PORTD Legend: Note 1: 02D8 02DA TRISD Addr File Name TABLE 3-15: ODC13 -- ODD5 LATD5 RD5 TRISD5 Bit 5 -- -- -- -- ODD4 LATD4 RD4 TRISD4 Bit 4 ODC4 LATC4 RC4 TRISC4 Bit 4(1) ODD3 LATD3 RD3 TRISD3 Bit 3 ODC3 LATC3 RC3 TRISC3 Bit 3(2) ODB3 LATB3 RB3 TRISB3 ODD2 LATD2 RD2 TRISD2 Bit 2 ODC2 LATC2 RC2 TRISC2 Bit 2(1) ODB2 LATB2 RB2 TRISB2 Bit 2 ODD1 LATD1 RD1 TRISD1 Bit 1 ODC1 LATC1 RC1 TRISC1 Bit 1(2) ODB1 LATB1 RB1 TRISB1 Bit 1 ODD0 LATD0 RD0 TRISD0 Bit 0 -- -- -- -- Bit 0 ODB0 LATB0 RB0 TRISB0 Bit 0 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin and 80-pin devices; read as `0'. Bits are unimplemented in 64-pin devices; read as `0'. RC12 and RC15 are only available when the primary oscillator is disabled or when EC mode is selected (POSCMD1:POSCMD0 Configuration bits = 11 or 00); otherwise read as `0'. RC15 is only available when POSCMD1:POSCMD0 Configuration bits = 11 or 00 and the OSCIOFN Configuration bit = 1. ODC14 LATC12 -- -- Bit 5 ODB4 LATB4 RB4 TRISB4 Bit 3 Legend: Note 1: 2: 3: 4: ODC15 LATC13 -- -- Bit 6 ODB5 LATB5 RB5 TRISB5 Bit 4 02D6 LATC14 -- -- Bit 7 ODB6 LATB6 RB6 TRISB6 Bit 5 ODCC -- -- LATC15 -- -- Bit 8 ODB7 LATB7 RB7 TRISB7 Bit 6 02D4 -- Bit 9 ODB8 LATB8 RB8 TRISB8 Bit 7 LATC RC12(3) -- RC13 -- RC14 -- Bit 10 TRISC15 TRISC14 TRISC13 TRISC12 Bit 11 RC15(3,4) Bit 12 ODB9 LATB9 RB9 TRISB9 Bit 8 02D0 Bit 13 ODB10 LATB10 RB10 TRISB10 Bit 9 02D2 Bit 14 ODB11 LATB11 RB11 Bit 10 ODA0 LATA0 RA0 TRISA0 Bit 0(2) TRISC Bit 15 PORTC REGISTER MAP ODB12 LATB12 RB12 TRISB15 TRISB14 TRISB13 TRISB12 TRISB11 Bit 15 PORTB REGISTER MAP ODA1 LATA1 RA1 TRISA1 Bit 1(2) PORTC Addr TABLE 3-14: File Name ODA15 LATA15 RA15 Bit 13 Reset values are shown in hexadecimal. 02CC LATB Legend: 02C8 02CA TRISB PORTB Addr TABLE 3-13: File Name Bit 14 TRISA15 TRISA14 Bit 15 PORTA REGISTER MAP(1) -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. PORTA and all associated bits are unimplemented on 64-pin devices and read as `0'. Bits are available on 80-pin and 100-pin devices only, unless otherwise noted. Bits are implemented on 100-pin devices only; otherwise read as `0'. 02C2 Legend: Note 1: 2: 02C0 PORTA Addr TRISA File Name TABLE 3-12: 0000 xxxx xxxx FFFF All Resets 0000 xxxx xxxx F01E All Resets 0000 xxxx xxxx FFFF All Resets 0000 xxxx xxxx 36FF All Resets PIC24FJ256GB110 FAMILY DS39897B-page 43 DS39897B-page 44 Preliminary 02EE LATF ODCF -- -- -- -- -- -- -- Bit 11 -- -- -- -- Bit 10 ODE9 LATE9 RE9 TRISE9 Bit 9(1) ODE8 LATE8 RE8 TRISE8 Bit 8(1) ODE7 LATE7 RE7 TRISE7 Bit 7 ODE6 LATE6 RE6 TRISE6 Bit 6 -- -- -- -- -- -- Bit 14 -- -- Bit 15 ODF13 LATF13 RF13 TRISF13 Bit 13(1) ODF12 LATF12 RF12 TRISF12 Bit 12(1) PORTF REGISTER MAP -- -- -- -- Bit 11 -- -- -- -- Bit 10 -- -- -- -- Bit 9 ODF8 LATF8 RF8 TRISF8 Bit 8(2) ODF7 LATF7 RF7 TRISF7 Bit 7(2) ODF6 LATF6 RF6 TRISF6 Bit 6(2) 02F0 02F2 02F4 02F6 TRISG PORTG LATG ODCG Bit 14(1) Bit 13(1) Bit 12(1) ODG15 LATG15 RG15 ODG14 LATG14 RG14 ODG13 LATG13 RG13 ODG12 LATG12 RG12 TRISG15 TRISG14 TRISG13 TRISG12 Bit 15(1) PORTG REGISTER MAP -- -- -- -- -- -- -- Bit 10 -- Bit 11 ODG9 LATG9 RG9 TRISG9 Bit 9 ODG8 LATG8 RG8 TRISG8 Bit 8 ODG7 LATG7 RG7 TRISG7 Bit 7 ODG6 LATG6 RG6 TRISG6 Bit 6 -- -- -- -- -- Bit 11 -- Bit 10 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Bit 12 02FC Bit 13 PADCFG1 Bit 14 Legend: Bit 15 Addr PAD CONFIGURATION REGISTER MAP File Name TABLE 3-19: -- Bit 9 -- Bit 8 -- Bit 7 -- Bit 6 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin and 80-pin devices; read as `0'. Addr File Name TABLE 3-18: Legend: Note 1: -- -- -- -- -- Bit 12 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin and 80-pin devices; read as `0'. Bits are unimplemented in 64-pin devices; read as `0'. 02EC PORTF Legend: Note 1: 2: 02E8 02EA TRISF Addr TABLE 3-17: File Name -- -- -- -- Bit 13 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset values shown are for 100-pin devices. Bits are unimplemented in 64-pin devices; read as `0'. 02E6 ODCE Legend: Note 1: 02E4 -- -- LATE -- -- 02E0 02E2 TRISE Bit 15 Bit 14 PORTE REGISTER MAP Addr PORTE File Name TABLE 3-16: -- Bit 5 -- -- -- -- Bit 5 ODF5 LATF5 RF5 TRISF5 Bit 5 ODE5 LATE5 RE5 TRISE5 Bit 5 -- Bit 4 -- -- -- -- Bit 4 ODF4 LATF4 RF4 TRISF4 Bit 4 ODE4 LATE4 RE4 TRISE4 Bit 4 -- Bit 3 ODG3 LATG3 RG3 TRISG3 Bit 3 ODF3 LATF3 RF3 TRISF3 Bit 3 ODE3 LATE3 RE3 TRISE3 Bit 3 -- Bit 2 ODG2 LATG2 RG2 Bit 1 ODG1 LATG1 RG1 TRISG1 Bit 1(1) ODF1 LATF1 RF1 TRISF1 Bit 1 ODE1 LATE1 RE1 TRISE1 Bit 1 RTSECSEL TRISG2 Bit 2 ODF2 LATF2 RF2 TRISF2 Bit 2(2) ODE2 LATE2 RE2 TRISE2 Bit 2 PMPTTL Bit 0 ODG0 LATG0 RG0 TRISG0 Bit 0(1) ODF0 LATF0 RF0 TRISF0 Bit 0 ODE0 LATE0 RE0 TRISE0 Bit 0 0000 All Resets 0000 xxxx xxxx F3CF All Resets 0000 xxxx xxxx 31FF All Resets 0000 xxxx xxxx 03FF All Resets PIC24FJ256GB110 FAMILY (c) 2008 Microchip Technology Inc. (c) 2008 Microchip Technology Inc. 0306 0308 030A 030C 030E 0310 0312 0314 0316 0318 031A 031C ADC1BUF3 ADC1BUF4 ADC1BUF5 ADC1BUF6 ADC1BUF7 ADC1BUF8 ADC1BUF9 ADC1BUFA ADC1BUFB ADC1BUFC ADC1BUFD ADC1BUFE Preliminary 0332 AD1CSSH -- CSSL14 -- CSSL15 -- -- CSSL13 PCFG13 -- -- r VCFG0 ADSIDL Bit 13 -- CSSL12 PCFG12 -- CH0SB4 SAMC4 r -- Bit 12 -- CSSL11 PCFG11 -- CH0SB3 -- CSSL10 PCFG10 -- CH0SB2 SAMC2 CSCNA -- SAMC3 -- Bit 10 -- Bit 11 ITRIM4 -- Bit 14 -- CSSL9 PCFG9 -- CH0SB1 SAMC1 -- FORM1 Bit 9 Bit 7 -- CSSL8 PCFG8 -- CH0SB0 SAMC0 -- FORM0 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8 Bit 7 -- Bit 6 CSSL7 PCFG7 -- CH0NA ADCS7 BUFS SSRC2 ADC Data Buffer 15 ADC Data Buffer 14 ADC Data Buffer 13 ADC Data Buffer 12 ADC Data Buffer 11 ADC Data Buffer 10 ADC Data Buffer 9 ADC Data Buffer 8 ADC Data Buffer 7 ADC Data Buffer 6 ADC Data Buffer 5 ADC Data Buffer 4 ADC Data Buffer 3 ADC Data Buffer 2 ADC Data Buffer 1 ADC Data Buffer 0 Bit 8 -- CSSL6 Bit 5 -- CSSL5 PCFG5 -- -- ADCS5 SMPI3 SSRC0 Bit 5 PCFG6 -- -- ADCS6 -- SSRC1 Bit 6 Bit 4 -- CSSL4 PCFG4 -- CH0SA4 ADCS4 SMPI2 -- Bit 4 Bit 3 -- CSSL3 PCFG3 -- CH0SA3 ADCS3 SMPI1 -- Bit 3 Bit 2 -- CSSL2 PCFG2 -- CH0SA2 ADCS2 SMPI0 ASAM Bit 2 Bit 1 CSS17 CSSL1 PCFG1 PCFG17 CH0SA1 ADCS1 BUFM SAMP Bit 1 Bit 0 CSS16 CSSL0 PCFG0 PCFG16 CH0SA0 ADCS0 ALTS DONE Bit 0 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 -- -- -- -- -- -- -- -- CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT Bit 13 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. ITRIM5 033C CTMUEN CTMUICON 033E CTMUCON Bit 15 Addr CTMU REGISTER MAP File Name TABLE 3-21: Legend: PCFG14 -- PCFG15 -- r VCFG1 -- Bit 14 CH0NB ADRC VCFG2 ADON Bit 15 ADC REGISTER MAP -- = unimplemented, read as `0', r = reserved, maintain as `0'. Reset values are shown in hexadecimal. 0330 AD1CSSL Legend: 032A 032C AD1PCFGH 0328 AD1CHS0 AD1PCFGL 0322 0324 AD1CON2 AD1CON3 0320 0304 ADC1BUF2 AD1CON1 0302 ADC1BUF1 031E 0300 ADC1BUF0 ADC1BUFF Addr File Name TABLE 3-20: 0000 0000 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx xxxx All Resets PIC24FJ256GB110 FAMILY DS39897B-page 45 DS39897B-page 46 048E(1) 0490(1) U1EIE U1STAT U1CON -- Preliminary 049E 04A0 04A6 04A8 U1FRMH U1TOK(2) U1SOF(2) U1CNFG1 U1CNFG2 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 9 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Alternate register or bit definitions when the module is operating in Host mode. This register is available in Host mode only. 049C U1FRML Legend: Note 1: 2: 0498 049A U1BDTP1 0496 -- -- 0492 0494(1) U1ADDR -- -- -- -- -- -- -- -- -- -- U1EIR -- 048C(1) U1IE -- -- -- -- -- -- -- U1PWRC -- -- -- 0486 U1OTGCON -- -- -- -- 0488 0484 U1OTGSTAT -- -- Bit 14 048A(1) 0482 Bit 15 USB OTG REGISTER MAP U1IR 0480 U1OTGIR Addr U1OTGIE File Name TABLE 3-22: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 8 -- UTEYE PID3 LSPDEN(1) JSTATE(1) -- ENDPT3 BTSEE BTSEE BTSEF BTSEF STALLIE STALLIE STALLIF STALLIF UACTPND DPPULUP ID IDIE IDIF Bit 7 -- UOEMON PID2 SE0 SE0 ENDPT2 -- -- -- RESET -- ENDPT0 BTOEE BTOEE BTOEF BTOEF HOSTEN HOSTEN DIR DFN8EE DFN8EE DFN8EF DFN8EF TRNIE TRNIE TRNIF TRNIF -- VBUSON SESVD -- -- PID1 CRC16EF CRC16EF SOFIE SOFIE SOFIF SOFIF -- OTGEN SESEND RESUME RESUME PPBI CRC16EE CRC16EE EP3 PUVBUS USBSIDL -- EP2 PPB1 EP1 PPBRST UTRDIS PPB0 EP0 -- SOFEN(1) USBEN -- PIDEE -- PIDEE CRC5EE EOFEE(1) PIDEF PIDEF CRC5EF PPBRST 0000 0000 0000 0000 0000 0000 0000 0000 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 DETACHIE(1) 0000 URSTIE DETACHIF(1) URSTIF USBPWR VBUSDIS VBUSVD VBUSVDIE VBUSVDIF Bit 0 EOFEF(1) UERRIE UERRIE UERRIF UERRIF USUSPND VBUSCHG -- -- -- Bit 1 EXTI2CEN UVBUSDIS UVCMPDIS -- Start-Of-Frame Count Register PID0 Frame Count Register High Byte Frame Count Register Low Byte Buffer Descriptor Table Base Address Register TOKBUSY PKTDIS ENDPT1 DMAEE DMAEE DMAEF IDLEIE IDLEIE IDLEIF IDLEIF USLPGRD SESENDIF Bit 2 SESVDIE SESENDIE SESVDIF Bit 3 USB Device Address (DEVADDR) Register RESUMEIE DMAEF RESUMEIE -- ATTACHIE(1) RESUMEIF ATTACHIF(1) -- RESUMEIF -- -- ACTVIE ACTVIF Bit 4 DPPULDWN DMPULDWN LSTATE LSTATEIE LSTATEIF Bit 5 -- -- DMPULUP -- T1MSECIE T1MSECIF Bit 6 PIC24FJ256GB110 FAMILY (c) 2008 Microchip Technology Inc. (c) 2008 Microchip Technology Inc. 04B0 04B2 04B4 04B6 04B8 04BA 04BC 04BE 04C0 04C2 04C4 04C6 04C8 04CC 04CE U1EP3 U1EP4 U1EP5 U1EP6 U1EP7 U1EP8 U1EP9 U1EP10 U1EP11 U1EP12 U1EP13 U1EP14 U1EP15 U1PWMRRS U1PWMCON PWMEN -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 13 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 12 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 11 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 10 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 8 PWMPOL CNTEN -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 9 USB Power Supply PWM Duty Cycle Register Bit 14 -- Bit 15 USB OTG REGISTER MAP (CONTINUED) Preliminary 0604 Legend: PMSTAT IBF IBOV PTEN14 -- PTEN13 -- PTEN12 IB3F PTEN11 IB2F PTEN10 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 060E PTEN15 060C IB1F PTEN9 IB0F PTEN8 OBE PTEN7 OBUF PTEN6 Parallel Port Data In Register 2 (Buffers 2 and 3) PMAEN ADDR6 060A ADDR7 PMDIN2 ADDR8 CSF0 WAITB0 Parallel Port Data In Register 1 (Buffers 0 and 1) ADDR9 CSF1 WAITB1 0608 ADDR10 MODE0 PMDIN1 ADDR11 MODE1 Parallel Port Data Out Register 2 (Buffers 2 and 3) ADDR12 MODE16 Bit 6 -- PMDOUT2 0606 ADDR13 INCM0 Bit 7 EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS EPCONDIS Bit 4 EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN EPRXEN Bit 3 EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN EPTXEN Bit 2 -- PTEN5 ADDR5 WAITM3 ALP Bit 5 -- -- PTEN4 ADDR4 WAITM2 CS2P Bit 4 CS1P Bit 3 OB3E PTEN3 ADDR3 WAITM1 -- OB2E PTEN2 ADDR2 WAITM0 BEP Bit 2 -- USB Power Supply PWM Period Register -- -- -- -- -- -- -- -- -- -- -- -- -- -- Parallel Port Data Out Register 1 (Buffers 0 and 1) CS1 INCM1 ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN Bit 8 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 5 PMDOUT1 CS2 IRQM0 PSIDL IRQM1 -- PMADDR BUSY PMPEN Bit 9 0602 Bit 10 0600 Bit 11 PMMODE Bit 12 PMCON Bit 13 Bit 15 File Name Addr Bit 14 PARALLEL MASTER/SLAVE PORT REGISTER MAP -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- RETRYDIS(1) LSPD(1) -- Bit 6 Bit 7 TABLE 3-23: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Alternate register or bit definitions when the module is operating in Host mode. This register is available in Host mode only. 04AE U1EP2 Legend: Note 1: 2: 04AA 04AC U1EP0 Addr U1EP1 File Name TABLE 3-22: OB1E PTEN1 ADDR1 WAITE1 WRSP Bit 1 -- EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL EPSTALL Bit 1 OB0E PTEN0 ADDR0 WAITE0 RDSP Bit 0 -- EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK EPHSHK Bit 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 All Resets 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 All Resets PIC24FJ256GB110 FAMILY DS39897B-page 47 DS39897B-page 48 CON CON COE COE CPOL CPOL CPOL -- -- Bit 13 -- -- -- -- -- Bit 12 -- -- -- -- Bit 11 Preliminary -- -- -- -- C3EVT Bit 10 RTCOE -- Bit 6 ARPT7 ARPT6 Bit 10 Bit 9 CEVT CEVT CEVT -- C2EVT Bit 9 RTCPTR1 Bit 8 COUT COUT COUT -- C1EVT Bit 8 -- Bit 7 Bit 7 EVPOL1 EVPOL1 EVPOL1 CVROE -- Bit 6 CAL6 Bit 6 EVPOL0 EVPOL0 EVPOL0 CAL7 CVREN RTCPTR0 X10 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. X11 Legend: X12 X9 X7 CRC Result Register CRC Data Input Register X8 X6 VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 CRCFUL CRCMPT Bit 11 0644 X13 CSIDL Bit 12 0646 X14 -- X15 Bit 13 CRCWDAT CRCXOR Bit 14 Bit 15 CRC REGISTER MAP Bit 7 -- X5 -- Bit 5 -- -- -- CVRR Bit 4 CREF CREF CREF CVRSS -- Bit 4 CAL4 X4 Bit 3 -- -- -- CVR3 -- Bit 3 CAL3 X3 Bit 2 -- -- -- CVR2 C3OUT Bit 2 CAL2 X2 Bit 1 CCH1 CCH1 CCH1 CVR1 C2OUT Bit 1 CAL1 ARPT1 Bit 1 X1 PLEN1 ARPT2 Bit 2 PLEN2 ARPT3 Bit 3 PLEN3 ARPT4 Bit 4 CRCGO CAL5 ARPT5 Bit 5 Bit 5 RTCC Value Register Window Based on RTCPTR<1:0> CRCDAT 0640 0642 CRCCON Addr File Name TABLE 3-26: Bit 8 AMASK0 ALRMPTR1 ALRMPTR0 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. 0638 CM3CON Legend: 0634 0636 CM1CON CM2CON COE -- -- CON -- CMIDL 0630 0632 Bit 14 Bit 15 CMSTAT RTCWREN RTCSYNC HALFSEC COMPARATORS REGISTER MAP Addr CVRCON File Name TABLE 3-25: -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. -- Bit 9 Alarm Value Register Window Based on ALRMPTR<1:0> Legend: RTCEN AMASK1 0626 AMASK2 RCFGCAL AMASK3 0624 CHIME Bit 10 RTCVAL ALRMEN Bit 11 0622 Bit 12 0620 Bit 13 ALCFGRPT Bit 14 ALRMVAL Bit 15 Addr REAL-TIME CLOCK AND CALENDAR REGISTER MAP File Name TABLE 3-24: -- PLEN0 Bit 0 CCH0 CCH0 CCH0 CVR0 C1OUT Bit 0 CAL0 ARPT0 Bit 0 0000 0000 0000 0040 All Resets 0000 0000 0000 0000 0000 All Resets 0000 xxxx 0000 xxxx All Resets PIC24FJ256GB110 FAMILY (c) 2008 Microchip Technology Inc. (c) 2008 Microchip Technology Inc. Preliminary 06C6 06C8 06CA 06CC 06CE 06D0 06D2 06D4 06D6 06D8 06DA 06DC 06DE RPOR3 RPOR4 RPOR5 RPOR6 RPOR7 RPOR8 RPOR9 RPOR10 RPOR11 RPOR12 RPOR13 RPOR14 RPOR15 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 14 -- Bit 15 U3RXR4 IC9R4 OCFBR4 IC8R4 IC6R4 IC4R4 IC2R4 T5CKR4 T3CKR4 T1CKR4 INT3R4 INT1R4 Bit 12 U3RXR3 IC9R3 OCFBR3 IC8R3 IC6R3 IC4R3 IC2R3 T5CKR3 T3CKR3 T1CKR3 INT3R3 INT1R3 Bit 11 U3RXR2 IC9R2 OCFBR2 IC8R2 IC6R2 IC4R2 IC2R2 T5CKR2 T3CKR2 T1CKR2 INT3R2 INT1R2 Bit 10 U3RXR1 IC9R1 OCFBR1 IC8R1 IC6R1 IC4R1 IC2R1 T5CKR1 T3CKR1 T1CKR1 INT3R1 INT1R1 Bit 9 U3RXR0 IC9R0 OCFBR0 IC8R0 IC6R0 IC4R0 IC2R0 T5CKR0 T3CKR0 T1CKR0 INT3R0 INT1R0 Bit 8 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 -- SCK2R4 -- SCK2R3 -- SCK2R2 -- SCK2R1 -- SCK2R0 RP11R0 RP9R0 -- -- -- -- -- -- -- -- RP29R1 RP27R1 RP25R1 RP23R1 RP21R1 RP19R1 RP17R1 RP27R0 RP25R0 RP23R0 RP21R0 RP19R0 RP17R0 -- -- -- -- -- -- -- RP29R2 RP27R2 RP25R2 RP23R2 RP21R2 RP19R2 RP17R2 RP31R5(2) RP31R4(2) RP31R3(2) RP31R2(2) RP31R1(2) RP31R0(2) RP29R3 RP27R3 RP25R3 RP23R3 RP21R3 RP19R3 RP17R3 -- RP29R4 RP27R4 RP25R4 RP23R4 RP21R4 RP19R4 RP17R4 RP29R0 RP29R5 RP27R5 RP25R5 RP23R5 RP21R5 RP19R5 RP17R5 RP13R1 RP11R1 RP9R1 RP7R0 RP5R0(1) RP3R0 RP1R0 -- SCK3R0 -- RP13R2 RP11R2 RP9R2 RP7R1 RP5R1(1) RP3R1 RP1R1 -- SCK3R1 RP15R5(1) RP15R4(1) RP15R3(1) RP15R2(1) RP15R1(1) RP15R0(1) RP13R3 RP11R3 RP9R3 RP7R2 RP5R2(1) RP3R2 RP1R2 -- SCK3R2 -- RP13R4 RP11R4 RP9R4 RP7R3 RP5R3(1) RP3R3 RP1R3 -- SCK3R3 -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 7 RP13R0 RP13R5 RP11R5 RP9R5 RP7R4 RP5R4(1) RP5R5(1) RP7R5 RP3R4 RP1R4 -- SCK3R4 RP3R5 RP1R5 -- SCK3R5 U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 -- SCK2R5 U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0 SCK1R5 U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 U3RXR5 IC9R5 OCFBR5 IC8R5 IC6R5 IC4R5 IC2R5 T5CKR5 T3CKR5 T1CKR5 INT3R5 INT1R5 Bit 13 PERIPHERAL PIN SELECT REGISTER MAP -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Bits are unimplemented in 64-pin devices; read as `0'. Bits are unimplemented in 64-pin and 80-pin devices; read as `0'. 06C4 RPOR2 Legend: Note 1: 2: 06C2 06A8 RPINR20 RPOR1 06A6 RPINR19 06C0 06A4 RPINR18 RPOR0 06A2 RPINR17 06BA 069E RPINR15 RPINR29 0696 RPINR11 06B8 0694 RPINR10 RPINR28 0692 RPINR9 06B6 0690 RPINR8 RPINR27 068E RPINR7 06AE 0688 RPINR4 RPINR23 0686 RPINR3 06AC 0684 RPINR2 RPINR22 0682 RPINR1 06AA 0680 RPINR0 RPINR21 Addr File Name TABLE 3-27: -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Bit 6 RP30R5 RP28R5 RP26R5 RP24R5 RP22R5 RP20R5 RP18R5 RP16R5 RP14R5 RP12R5 RP10R5 RP8R5 RP6R5 RP4R5 RP2R5 RP0R5 SS3R5 SDI3R5 U4RXR5 SS2R5 SDI2R5 SS1R5 SDI1R5 U2RXR5 U1RXR5 -- -- OCFAR5 IC7R5 IC5R5 IC3R5 IC1R5 T4CKR5 T2CKR5 INT4R5 INT2R5 -- Bit 5 RP30R4 RP28R4 RP26R4 RP24R4 RP22R4 RP20R4 RP18R4 RP16R4 RP14R4 RP12R4 RP10R4 RP8R4 RP6R4 RP4R4 RP2R4 RP0R4 SS3R4 SDI3R4 U4RXR4 SS2R4 SDI2R4 SS1R4 SDI1R4 U2RXR4 U1RXR4 -- -- OCFAR4 IC7R4 IC5R4 IC3R4 IC1R4 T4CKR4 T2CKR4 INT4R4 INT2R4 -- Bit 4 RP30R3 RP28R3 RP26R3 RP24R3 RP22R3 RP20R3 RP18R3 RP16R3 RP14R3 RP12R3 RP10R3 RP8R3 RP6R3 RP4R3 RP2R3 RP0R3 SS3R3 SDI3R3 U4RXR3 SS2R3 SDI2R3 SS1R3 SDI1R3 U2RXR3 U1RXR3 -- -- OCFAR3 IC7R3 IC5R3 IC3R3 IC1R3 T4CKR3 T2CKR3 INT4R3 INT2R3 -- Bit 3 RP30R2 RP28R2 RP26R2 RP24R2 RP22R2 RP20R2 RP18R2 RP16R2 RP14R2 RP12R2 RP10R2 RP8R2 RP6R2 RP4R2 RP2R2 RP0R2 SS3R2 SDI3R2 U4RXR2 SS2R2 SDI2R2 SS1R2 SDI1R2 U2RXR2 U1RXR2 -- -- OCFAR2 IC7R2 IC5R2 IC3R2 IC1R2 T4CKR2 T2CKR2 INT4R2 INT2R2 -- Bit 2 RP30R1 RP28R1 RP26R1 RP24R1 RP22R1 RP20R1 RP18R1 RP16R1 RP14R1 RP12R1 RP10R1 RP8R1 RP6R1 RP4R1 RP2R1 RP0R1 SS3R1 SDI3R1 U4RXR1 SS2R1 SDI2R1 SS1R1 SDI1R1 U2RXR1 U1RXR1 -- -- OCFAR1 IC7R1 IC5R1 IC3R1 IC1R1 T4CKR1 T2CKR1 INT4R1 INT2R1 -- Bit 1 RP30R0 RP28R0 RP26R0 RP24R0 RP22R0 RP20R0 RP18R0 RP16R0 RP14R0 RP12R0 RP10R0 RP8R0 RP6R0 RP4R0 RP2R0 RP0R0 SS3R0 SDI3R0 U4RXR0 SS2R0 SDI2R0 SS1R0 SDI1R0 U2RXR0 U1RXR0 -- -- OCFAR0 IC7R0 IC5R0 IC3R0 IC1R0 T4CKR0 T2CKR0 INT4R0 INT2R0 -- Bit 0 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 003F 3F3F 3F3F 003F 3F3F 3F3F 3F3F 3F3F 3F3F 3F00 3F00 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F3F 3F00 All Resets PIC24FJ256GB110 FAMILY DS39897B-page 49 Bit 0 DS39897B-page 50 Preliminary -- -- -- -- -- -- -- -- IC1MD -- Bit 8 -- -- -- -- -- -- -- -- -- IC9MD -- CMPMD RTCCMD PMPMD IC2MD -- IC3MD Bit 9 -- -- Bit 10 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. -- -- -- -- IC4MD T1MD Bit 11 Legend: -- -- -- -- IC5MD T2MD Bit 12 0778 -- -- -- IC6MD T3MD Bit 13 -- -- 077A 0776 PMD4 -- -- IC7MD T4MD Bit 14 -- -- PMD5 0774 PMD3 IC8MD T5MD Bit 15 PMD REGISTER MAP -- -- PMD6 0770 0772 PMD1 PMD2 Addr File Name TABLE 3-30: -- WRERR -- -- -- CRCMD OC8MD I2C1MD Bit 7 -- -- -- UPWMMD -- OC7MD U2MD Bit 6 ERASE Bit 6 -- -- U4MD -- OC6MD U1MD Bit 5 -- Bit 5 -- -- -- -- OC5MD SPI2MD Bit 4 IDLE BOR Bit 2 -- TUN2 -- Bit 1 -- TUN1 -- POSCEN SOSCEN POR Bit 0 -- TUN0 -- OSWEN All Resets 0000 0000 0100 Note 2 Note 1 All Resets I2C3MD OC3MD -- Bit 2 -- -- -- -- REFOMD CTMUMD U3MD OC4MD SPI1MD Bit 3 -- -- LVDMD I2C2MD OC2MD -- Bit 1 SPI3MD OC9MD USB1MD -- OC1MD ADC1MD Bit 0 0000 0000 0000 0000 0000 0000 All Resets 0000 NVMOP3 NVMOP2 NVMOP1 NVMOP0 0000(1) Bit 3 -- NVMKEY Register<7:0> -- Bit 4 -- TUN3 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. Reset value shown is for POR only. Value on other Reset states is dependent on the state of memory write or erase operations at the time of Reset. -- WREN Bit 7 -- TUN4 Legend: Note 1: -- WR Bit 8 -- TUN5 -- -- CF SLEEP 0766 Bit 9 -- -- CPDIV0 -- WDTO LOCK SWDTEN 0760 Bit 10 -- -- CPDIV1 SWR IOLOCK NVMKEY Bit 13 Bit 11 RODIV0 -- RCDIV0 EXTR CLKLOCK NVMCON Bit 14 Bit 12 RODIV1 -- RCDIV1 NOSC0 VREGS Bit 15 RODIV2 -- RCDIV2 CM NOSC1 Addr RODIV3 -- DOZEN -- NOSC2 File Name ROSEL -- DOZE0 -- -- NVM REGISTER MAP ROSSLP -- DOZE1 COSC0 TABLE 3-29: -- -- -- ROEN DOZE2 ROI COSC1 074E Bit 1 -- = unimplemented, read as `0'. Reset values are shown in hexadecimal. The Reset value of the RCON register is dependent on the type of Reset event. See Section 5.0 "Resets" for more information. The Reset value of the OSCCON register is dependent on both the type of Reset event and the device configuration. See Section 7.0 "Oscillator Configuration" for more information. Bit 2 Legend: Note 1: 2: Bit 3 REFOCON Bit 4 0748 Bit 5 OSCTUN Bit 6 0744 COSC2 IOPUWR -- Bit 7 CLKDIV -- -- Bit 8 TRAPR Bit 9 0742 Bit 10 0740 Bit 11 RCON Bit 12 Bit 13 OSCCON Bit 14 Bit 15 SYSTEM REGISTER MAP Addr File Name TABLE 3-28: PIC24FJ256GB110 FAMILY (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 3.2.5 3.3 SOFTWARE STACK In addition to its use as a working register, the W15 register in PIC24F devices is also used as a Software Stack Pointer. The pointer always points to the first available free word and grows from lower to higher addresses. It pre-decrements for stack pops and post-increments for stack pushes, as shown in Figure 3-4. Note that for a PC push during any CALL instruction, the MSB of the PC is zero-extended before the push, ensuring that the MSB is always clear. Note: A PC push during exception processing will concatenate the SRL register to the MSB of the PC prior to the push. The Stack Pointer Limit Value register (SPLIM), associated with the Stack Pointer, sets an upper address boundary for the stack. SPLIM is uninitialized at Reset. As is the case for the Stack Pointer, SPLIM<0> is forced to `0' because all stack operations must be word-aligned. Whenever an EA is generated using W15 as a source or destination pointer, the resulting address is compared with the value in SPLIM. If the contents of the Stack Pointer (W15) and the SPLIM register are equal, and a push operation is performed, a stack error trap will not occur. The stack error trap will occur on a subsequent push operation. Thus, for example, if it is desirable to cause a stack error trap when the stack grows beyond address 2000h in RAM, initialize the SPLIM with the value, 1FFEh. Similarly, a Stack Pointer underflow (stack error) trap is generated when the Stack Pointer address is found to be less than 0800h. This prevents the stack from interfering with the Special Function Register (SFR) space. A write to the SPLIM register should not be immediately followed by an indirect read operation using W15. FIGURE 3-4: Stack Grows Towards Higher Address 0000h CALL STACK FRAME 15 0 PC<15:0> 000000000 PC<22:16> <Free Word> W15 (before CALL) W15 (after CALL) POP : [--W15] PUSH : [W15++] (c) 2008 Microchip Technology Inc. Interfacing Program and Data Memory Spaces The PIC24F architecture uses a 24-bit wide program space and 16-bit wide data space. The architecture is also a modified Harvard scheme, meaning that data can also be present in the program space. To use this data successfully, it must be accessed in a way that preserves the alignment of information in both spaces. Aside from normal execution, the PIC24F architecture provides two methods by which program space can be accessed during operation: * Using table instructions to access individual bytes or words anywhere in the program space * Remapping a portion of the program space into the data space (program space visibility) Table instructions allow an application to read or write to small areas of the program memory. This makes the method ideal for accessing data tables that need to be updated from time to time. It also allows access to all bytes of the program word. The remapping method allows an application to access a large block of data on a read-only basis, which is ideal for look ups from a large table of static data. It can only access the least significant word of the program word. 3.3.1 ADDRESSING PROGRAM SPACE Since the address ranges for the data and program spaces are 16 and 24 bits, respectively, a method is needed to create a 23-bit or 24-bit program address from 16-bit data registers. The solution depends on the interface method to be used. For table operations, the 8-bit Table Memory Page Address register (TBLPAG) is used to define a 32K word region within the program space. This is concatenated with a 16-bit EA to arrive at a full 24-bit program space address. In this format, the Most Significant bit of TBLPAG is used to determine if the operation occurs in the user memory (TBLPAG<7> = 0) or the configuration memory (TBLPAG<7> = 1). For remapping operations, the 8-bit Program Space Visibility Page Address register (PSVPAG) is used to define a 16K word page in the program space. When the Most Significant bit of the EA is `1', PSVPAG is concatenated with the lower 15 bits of the EA to form a 23-bit program space address. Unlike table operations, this limits remapping operations strictly to the user memory area. Table 3-31 and Figure 3-5 show how the program EA is created for table operations and remapping accesses from the data EA. Here, P<23:0> refers to a program space word, whereas D<15:0> refers to a data space word. Preliminary DS39897B-page 51 PIC24FJ256GB110 FAMILY TABLE 3-31: PROGRAM SPACE ADDRESS CONSTRUCTION Program Space Address Access Space Access Type <23> <22:16> <15> <14:1> <0> Instruction Access (Code Execution) User TBLRD/TBLWT (Byte/Word Read/Write) User TBLPAG<7:0> Data EA<15:0> 0xxx xxxx xxxx xxxx xxxx xxxx Configuration TBLPAG<7:0> Data EA<15:0> 1xxx xxxx xxxx xxxx xxxx xxxx 0 0xx xxxx xxxx xxxx xxxx xxx0 Program Space Visibility (Block Remap/Read) Note 1: PC<22:1> 0 User 0 PSVPAG<7:0> Data EA<14:0>(1) 0 xxxx xxxx xxx xxxx xxxx xxxx Data EA<15> is always `1' in this case, but is not used in calculating the program space address. Bit 15 of the address is PSVPAG<0>. FIGURE 3-5: DATA ACCESS FROM PROGRAM SPACE ADDRESS GENERATION Program Counter(1) Program Counter 0 0 23 Bits EA Table Operations(2) 1/0 1/0 TBLPAG 8 Bits 16 Bits 24 Bits Select Program Space Visibility(1) (Remapping) 0 EA 1 0 PSVPAG 8 Bits 15 Bits 23 Bits User/Configuration Space Select Byte Select Note 1: The LSb of program space addresses is always fixed as `0' in order to maintain word alignment of data in the program and data spaces. 2: Table operations are not required to be word-aligned. Table read operations are permitted in the configuration memory space. DS39897B-page 52 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 3.3.2 DATA ACCESS FROM PROGRAM MEMORY USING TABLE INSTRUCTIONS The TBLRDL and TBLWTL instructions offer a direct method of reading or writing the lower word of any address within the program space without going through data space. The TBLRDH and TBLWTH instructions are the only method to read or write the upper 8 bits of a program space word as data. The PC is incremented by two for each successive 24-bit program word. This allows program memory addresses to directly map to data space addresses. Program memory can thus be regarded as two, 16-bit word-wide address spaces, residing side by side, each with the same address range. TBLRDL and TBLWTL access the space which contains the least significant data word, and TBLRDH and TBLWTH access the space which contains the upper data byte. Two table instructions are provided to move byte or word-sized (16-bit) data to and from program space. Both function as either byte or word operations. 1. TBLRDL (Table Read Low): In Word mode, it maps the lower word of the program space location (P<15:0>) to a data address (D<15:0>). In Byte mode, either the upper or lower byte of the lower program word is mapped to the lower byte of a data address. The upper byte is selected when byte select is `1'; the lower byte is selected when it is `0'. FIGURE 3-6: 2. TBLRDH (Table Read High): In Word mode, it maps the entire upper word of a program address (P<23:16>) to a data address. Note that D<15:8>, the `phantom' byte, will always be `0'. In Byte mode, it maps the upper or lower byte of the program word to D<7:0> of the data address, as above. Note that the data will always be `0' when the upper `phantom' byte is selected (byte select = 1). In a similar fashion, two table instructions, TBLWTH and TBLWTL, are used to write individual bytes or words to a program space address. The details of their operation are explained in Section 4.0 "Flash Program Memory". For all table operations, the area of program memory space to be accessed is determined by the Table Memory Page Address register (TBLPAG). TBLPAG covers the entire program memory space of the device, including user and configuration spaces. When TBLPAG<7> = 0, the table page is located in the user memory space. When TBLPAG<7> = 1, the page is located in configuration space. Note: Only table read operations will execute in the configuration memory space, and only then, in implemented areas such as the Device ID. Table write operations are not allowed. ACCESSING PROGRAM MEMORY WITH TABLE INSTRUCTIONS Program Space TBLPAG 02 Data EA<15:0> 23 15 0 000000h 23 16 8 0 00000000 00000000 00000000 020000h 030000h 00000000 `Phantom' Byte TBLRDH.B (Wn<0> = 0) TBLRDL.B (Wn<0> = 1) TBLRDL.B (Wn<0> = 0) TBLRDL.W 800000h (c) 2008 Microchip Technology Inc. The address for the table operation is determined by the data EA within the page defined by the TBLPAG register. Only read operations are shown; write operations are also valid in the user memory area. Preliminary DS39897B-page 53 PIC24FJ256GB110 FAMILY 3.3.3 READING DATA FROM PROGRAM MEMORY USING PROGRAM SPACE VISIBILITY The upper 32 Kbytes of data space may optionally be mapped into any 16K word page of the program space. This provides transparent access of stored constant data from the data space without the need to use special instructions (i.e., TBLRDL/H). Program space access through the data space occurs if the Most Significant bit of the data space EA is `1', and program space visibility is enabled by setting the PSV bit in the CPU Control register (CORCON<2>). The location of the program memory space to be mapped into the data space is determined by the Program Space Visibility Page Address register (PSVPAG). This 8-bit register defines any one of 256 possible pages of 16K words in program space. In effect, PSVPAG functions as the upper 8 bits of the program memory address, with the 15 bits of the EA functioning as the lower bits. Note that by incrementing the PC by 2 for each program memory word, the lower 15 bits of data space addresses directly map to the lower 15 bits in the corresponding program space addresses. Data reads to this area add an additional cycle to the instruction being executed, since two program memory fetches are required. Although each data space address, 8000h and higher, maps directly into a corresponding program memory address (see Figure 3-7), only the lower 16 bits of the FIGURE 3-7: 24-bit program word are used to contain the data. The upper 8 bits of any program space locations used as data should be programmed with `1111 1111' or `0000 0000' to force a NOP. This prevents possible issues should the area of code ever be accidentally executed. Note: PSV access is temporarily disabled during table reads/writes. For operations that use PSV and are executed outside a REPEAT loop, the MOV and MOV.D instructions will require one instruction cycle in addition to the specified execution time. All other instructions will require two instruction cycles in addition to the specified execution time. For operations that use PSV which are executed inside a REPEAT loop, there will be some instances that require two instruction cycles in addition to the specified execution time of the instruction: * Execution in the first iteration * Execution in the last iteration * Execution prior to exiting the loop due to an interrupt * Execution upon re-entering the loop after an interrupt is serviced Any other iteration of the REPEAT loop will allow the instruction accessing data, using PSV, to execute in a single cycle. PROGRAM SPACE VISIBILITY OPERATION When CORCON<2> = 1 and EA<15> = 1: Program Space PSVPAG 02 23 15 Data Space 0 000000h 0000h Data EA<14:0> 010000h 018000h The data in the page designated by PSVPAG is mapped into the upper half of the data memory space.... 8000h PSV Area FFFFh 800000h DS39897B-page 54 Preliminary ...while the lower 15 bits of the EA specify an exact address within the PSV area. This corresponds exactly to the same lower 15 bits of the actual program space address. (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 4.0 Note: FLASH PROGRAM MEMORY RTSP is accomplished using TBLRD (table read) and TBLWT (table write) instructions. With RTSP, the user may write program memory data in blocks of 64 instructions (192 bytes) at a time, and erase program memory in blocks of 512 instructions (1536 bytes) at a time. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 4. Program Memory" (DS39715). 4.1 Regardless of the method used, all programming of Flash memory is done with the table read and table write instructions. These allow direct read and write access to the program memory space from the data memory while the device is in normal operating mode. The 24-bit target address in the program memory is formed using the TBLPAG<7:0> bits and the Effective Address (EA) from a W register specified in the table instruction, as shown in Figure 4-1. The PIC24FJ256GB110 family of devices contains internal Flash program memory for storing and executing application code. It can be programmed in four ways: * * * * In-Circuit Serial ProgrammingTM (ICSPTM) Run-Time Self-Programming (RTSP) JTAG Enhanced In-Circuit Serial ProgrammingTM (Enhanced ICSPTM) The TBLRDL and the TBLWTL instructions are used to read or write to bits<15:0> of program memory. TBLRDL and TBLWTL can access program memory in both Word and Byte modes. ICSP allows a PIC24FJ256GB110 family device to be serially programmed while in the end application circuit. This is simply done with two lines for the programming clock and programming data (which are named PGECx and PGEDx, respectively), and three other lines for power (VDD), ground (VSS) and Master Clear (MCLR). This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. FIGURE 4-1: Table Instructions and Flash Programming The TBLRDH and TBLWTH instructions are used to read or write to bits<23:16> of program memory. TBLRDH and TBLWTH can also access program memory in Word or Byte mode. ADDRESSING FOR TABLE REGISTERS 24 Bits Using Program Counter Program Counter 0 0 Working Reg EA Using Table Instruction User/Configuration Space Select (c) 2008 Microchip Technology Inc. 1/0 TBLPAG Reg 8 Bits 16 Bits 24-Bit EA Preliminary Byte Select DS39897B-page 55 PIC24FJ256GB110 FAMILY 4.2 RTSP Operation 4.3 The PIC24F Flash program memory array is organized into rows of 64 instructions or 192 bytes. RTSP allows the user to erase blocks of eight rows (512 instructions) at a time and to program one row at a time. It is also possible to program single words. The 8-row erase blocks and single row write blocks are edge-aligned, from the beginning of program memory, on boundaries of 1536 bytes and 192 bytes, respectively. When data is written to program memory using TBLWT instructions, the data is not written directly to memory. Instead, data written using table writes is stored in holding latches until the programming sequence is executed. Any number of TBLWT instructions can be executed and a write will be successfully performed. However, 64 TBLWT instructions are required to write the full row of memory. To ensure that no data is corrupted during a write, any unused addresses should be programmed with FFFFFFh. This is because the holding latches reset to an unknown state, so if the addresses are left in the Reset state, they may overwrite the locations on rows which were not rewritten. The basic sequence for RTSP programming is to set up a Table Pointer, then do a series of TBLWT instructions to load the buffers. Programming is performed by setting the control bits in the NVMCON register. Data can be loaded in any order and the holding registers can be written to multiple times before performing a write operation. Subsequent writes, however, will wipe out any previous writes. Note: Writing to a location multiple times without erasing is not recommended. All of the table write operations are single-word writes (2 instruction cycles), because only the buffers are written. A programming cycle is required for programming each row. DS39897B-page 56 JTAG Operation The PIC24F family supports JTAG programming and boundary scan. Boundary scan can improve the manufacturing process by verifying pin-to-PCB connectivity. Programming can be performed with industry standard JTAG programmers supporting Serial Vector Format (SVF). 4.4 Enhanced In-Circuit Serial Programming Enhanced In-Circuit Serial Programming uses an on-board bootloader, known as the program executive, to manage the programming process. Using an SPI data frame format, the program executive can erase, program and verify program memory. For more information on Enhanced ICSP, see the device programming specification. 4.5 Control Registers There are two SFRs used to read and write the program Flash memory: NVMCON and NVMKEY. The NVMCON register (Register 4-1) controls which blocks are to be erased, which memory type is to be programmed and when the programming cycle starts. NVMKEY is a write-only register that is used for write protection. To start a programming or erase sequence, the user must consecutively write 55h and AAh to the NVMKEY register. Refer to Section 4.6 "Programming Operations" for further details. 4.6 Programming Operations A complete programming sequence is necessary for programming or erasing the internal Flash in RTSP mode. During a programming or erase operation, the processor stalls (waits) until the operation is finished. Setting the WR bit (NVMCON<15>) starts the operation and the WR bit is automatically cleared when the operation is finished. Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 4-1: NVMCON: FLASH MEMORY CONTROL REGISTER R/SO-0(1) R/W-0(1) R/W-0(1) U-0 U-0 U-0 U-0 U-0 WR WREN WRERR -- -- -- -- -- bit 15 bit 8 U-0 R/W-0(1) U-0 U-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0(1) -- ERASE -- -- NVMOP3(2) NVMOP2(2) NVMOP1(2) NVMOP0(2) bit 7 bit 0 Legend: SO = Set Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 WR: Write Control bit(1) 1 = Initiates a Flash memory program or erase operation. The operation is self-timed and the bit is cleared by hardware once operation is complete. 0 = Program or erase operation is complete and inactive bit 14 WREN: Write Enable bit(1) 1 = Enable Flash program/erase operations 0 = Inhibit Flash program/erase operations bit 13 WRERR: Write Sequence Error Flag bit(1) 1 = An improper program or erase sequence attempt or termination has occurred (bit is set automatically on any set attempt of the WR bit) 0 = The program or erase operation completed normally bit 12-7 Unimplemented: Read as `0' bit 6 ERASE: Erase/Program Enable bit(1) 1 = Perform the erase operation specified by NVMOP3:NVMOP0 on the next WR command 0 = Perform the program operation specified by NVMOP3:NVMOP0 on the next WR command bit 5-4 Unimplemented: Read as `0' bit 3-0 NVMOP3:NVMOP0: NVM Operation Select bits(1,2) 1111 = Memory bulk erase operation (ERASE = 1) or no operation (ERASE = 0)(3) 0011 = Memory word program operation (ERASE = 0) or no operation (ERASE = 1) 0010 = Memory page erase operation (ERASE = 1) or no operation (ERASE = 0) 0001 = Memory row program operation (ERASE = 0) or no operation (ERASE = 1) Note 1: 2: 3: These bits can only be reset on POR. All other combinations of NVMOP3:NVMOP0 are unimplemented. Available in ICSPTM mode only. Refer to device programming specification. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 57 PIC24FJ256GB110 FAMILY 4.6.1 PROGRAMMING ALGORITHM FOR FLASH PROGRAM MEMORY 4. 5. The user can program one row of Flash program memory at a time. To do this, it is necessary to erase the 8-row erase block containing the desired row. The general process is: 1. 2. 3. Read eight rows of program memory (512 instructions) and store in data RAM. Update the program data in RAM with the desired new data. Erase the block (see Example 4-1): a) Set the NVMOP bits (NVMCON<3:0>) to `0010' to configure for block erase. Set the ERASE (NVMCON<6>) and WREN (NVMCON<14>) bits. b) Write the starting address of the block to be erased into the TBLPAG and W registers. c) Write 55h to NVMKEY. d) Write AAh to NVMKEY. e) Set the WR bit (NVMCON<15>). The erase cycle begins and the CPU stalls for the duration of the erase cycle. When the erase is done, the WR bit is cleared automatically. EXAMPLE 4-1: DS39897B-page 58 For protection against accidental operations, the write initiate sequence for NVMKEY must be used to allow any erase or program operation to proceed. After the programming command has been executed, the user must wait for the programming time until programming is complete. The two instructions following the start of the programming sequence should be NOPs, as shown in Example 4-3. ERASING A PROGRAM MEMORY BLOCK ; Set up NVMCON for block erase operation MOV #0x4042, W0 MOV W0, NVMCON ; Init pointer to row to be ERASED MOV #tblpage(PROG_ADDR), W0 MOV W0, TBLPAG MOV #tbloffset(PROG_ADDR), W0 TBLWTL W0, [W0] DISI #5 MOV MOV MOV MOV BSET NOP NOP 6. Write the first 64 instructions from data RAM into the program memory buffers (see Example 4-1). Write the program block to Flash memory: a) Set the NVMOP bits to `0001' to configure for row programming. Clear the ERASE bit and set the WREN bit. b) Write 55h to NVMKEY. c) Write AAh to NVMKEY. d) Set the WR bit. The programming cycle begins and the CPU stalls for the duration of the write cycle. When the write to Flash memory is done, the WR bit is cleared automatically. Repeat steps 4 and 5, using the next available 64 instructions from the block in data RAM by incrementing the value in TBLPAG, until all 512 instructions are written back to Flash memory. #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR ; ; Initialize NVMCON ; ; ; ; ; ; ; ; ; ; ; ; Initialize PM Page Boundary SFR Initialize in-page EA[15:0] pointer Set base address of erase block Block all interrupts with priority <7 for next 5 instructions Write the 55 key Write the AA key Start the erase sequence Insert two NOPs after the erase command is asserted Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY EXAMPLE 4-2: LOADING THE WRITE BUFFERS ; Set up NVMCON for row programming operations MOV #0x4001, W0 ; MOV W0, NVMCON ; Initialize NVMCON ; Set up a pointer to the first program memory location to be written ; program memory selected, and writes enabled MOV #0x0000, W0 ; MOV W0, TBLPAG ; Initialize PM Page Boundary SFR MOV #0x6000, W0 ; An example program memory address ; Perform the TBLWT instructions to write the latches ; 0th_program_word MOV #LOW_WORD_0, W2 ; MOV #HIGH_BYTE_0, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 1st_program_word MOV #LOW_WORD_1, W2 ; MOV #HIGH_BYTE_1, W3 ; TBLWTL W2, [W0] ; Write PM low word into program latch TBLWTH W3, [W0++] ; Write PM high byte into program latch ; 2nd_program_word MOV #LOW_WORD_2, W2 ; MOV #HIGH_BYTE_2, W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] ; Write PM high byte into program latch TBLWTH W3, [W0++] * * * ; 63rd_program_word MOV #LOW_WORD_31, W2 ; MOV #HIGH_BYTE_31, W3 ; ; Write PM low word into program latch TBLWTL W2, [W0] ; Write PM high byte into program latch TBLWTH W3, [W0] EXAMPLE 4-3: INITIATING A PROGRAMMING SEQUENCE DISI #5 MOV MOV MOV MOV BSET BTSC BRA #0x55, W0 W0, NVMKEY #0xAA, W1 W1, NVMKEY NVMCON, #WR NVMCON, #15 $-2 (c) 2008 Microchip Technology Inc. ; Block all interrupts with priority <7 ; for next 5 instructions ; ; ; ; ; ; Write the 55 key Write the AA key Start the erase sequence and wait for it to be completed Preliminary DS39897B-page 59 PIC24FJ256GB110 FAMILY 4.6.2 PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY If a Flash location has been erased, it can be programmed using table write instructions to write an instruction word (24-bit) into the write latch. The TBLPAG register is loaded with the 8 Most Significant Bytes of the Flash address. The TBLWTL and TBLWTH EXAMPLE 4-4: instructions write the desired data into the write latches and specify the lower 16 bits of the program memory address to write to. To configure the NVMCON register for a word write, set the NVMOP bits (NVMCON<3:0>) to `0011'. The write is performed by executing the unlock sequence and setting the WR bit (see Example 4-4). PROGRAMMING A SINGLE WORD OF FLASH PROGRAM MEMORY ; Setup a pointer to data Program Memory MOV #tblpage(PROG_ADDR), W0 ; MOV W0, TBLPAG ;Initialize PM Page Boundary SFR MOV #tbloffset(PROG_ADDR), W0 ;Initialize a register with program memory address MOV MOV TBLWTL TBLWTH #LOW_WORD_N, W2 #HIGH_BYTE_N, W3 W2, [W0] W3, [W0++] ; ; ; Write PM low word into program latch ; Write PM high byte into program latch ; Setup NVMCON for programming one word to data Program Memory MOV #0x4003, W0 ; MOV W0, NVMCON ; Set NVMOP bits to 0011 DISI MOV MOV MOV MOV BSET #5 #0x55, W0 W0, NVMKEY #0xAA, W0 W0, NVMKEY NVMCON, #WR DS39897B-page 60 ; Disable interrupts while the KEY sequence is written ; Write the key sequence ; Start the write cycle Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 5.0 Note: RESETS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 7. Reset" (DS39712). The Reset module combines all Reset sources and controls the device Master Reset Signal, SYSRST. The following is a list of device Reset sources: * * * * * * * * * POR: Power-on Reset MCLR: Pin Reset SWR: RESET Instruction WDT: Watchdog Timer Reset BOR: Brown-out Reset CM: Configuration Mismatch Reset TRAPR: Trap Conflict Reset IOPUWR: Illegal Opcode Reset UWR: Uninitialized W Register Reset Any active source of Reset will make the SYSRST signal active. Many registers associated with the CPU and peripherals are forced to a known Reset state. Most registers are unaffected by a Reset; their status is unknown on POR and unchanged by all other Resets. Note: All types of device Reset will set a corresponding status bit in the RCON register to indicate the type of Reset (see Register 5-1). A Power-on Reset will clear all bits, except for the BOR and POR bits (RCON<1:0>), which are set. The user may set or clear any bit at any time during code execution. The RCON bits only serve as status bits. Setting a particular Reset status bit in software will not cause a device Reset to occur. The RCON register also has other bits associated with the Watchdog Timer and device power-saving states. The function of these bits is discussed in other sections of this manual. A simplified block diagram of the Reset module is shown in Figure 5-1. FIGURE 5-1: Refer to the specific peripheral or CPU section of this manual for register Reset states. Note: The status bits in the RCON register should be cleared after they are read so that the next RCON register value after a device Reset will be meaningful. RESET SYSTEM BLOCK DIAGRAM RESET Instruction Glitch Filter MCLR WDT Module Sleep or Idle VDD Rise Detect POR Brown-out Reset BOR SYSRST VDD Enable Voltage Regulator Trap Conflict Illegal Opcode Configuration Mismatch Uninitialized W Register (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 61 PIC24FJ256GB110 FAMILY RCON: RESET CONTROL REGISTER(1) REGISTER 5-1: R/W-0 TRAPR bit 15 R/W-0 IOPUWR U-0 -- U-0 -- U-0 -- U-0 -- R/W-0 CM R/W-0 VREGS bit 8 R/W-0 EXTR bit 7 R/W-0 SWR R/W-0 SWDTEN(2) R/W-0 WDTO R/W-0 SLEEP R/W-0 IDLE R/W-1 BOR R/W-1 POR bit 0 Legend: R = Readable bit -n = Value at POR bit 15 bit 14 bit 13-10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 Note 1: 2: W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown TRAPR: Trap Reset Flag bit 1 = A Trap Conflict Reset has occurred 0 = A Trap Conflict Reset has not occurred IOPUWR: Illegal Opcode or Uninitialized W Access Reset Flag bit 1 = An illegal opcode detection, an illegal address mode or uninitialized W register used as an Address Pointer caused a Reset 0 = An illegal opcode or uninitialized W Reset has not occurred Unimplemented: Read as `0' CM: Configuration Word Mismatch Reset Flag bit 1 = A Configuration Word Mismatch Reset has occurred 0 = A Configuration Word Mismatch Reset has not occurred VREGS: Voltage Regulator Standby Enable bit 1 = Regulator remains active during Sleep 0 = Regulator goes to standby during Sleep EXTR: External Reset (MCLR) Pin bit 1 = A Master Clear (pin) Reset has occurred 0 = A Master Clear (pin) Reset has not occurred SWR: Software Reset (Instruction) Flag bit 1 = A RESET instruction has been executed 0 = A RESET instruction has not been executed SWDTEN: Software Enable/Disable of WDT bit(2) 1 = WDT is enabled 0 = WDT is disabled WDTO: Watchdog Timer Time-out Flag bit 1 = WDT time-out has occurred 0 = WDT time-out has not occurred SLEEP: Wake From Sleep Flag bit 1 = Device has been in Sleep mode 0 = Device has not been in Sleep mode IDLE: Wake-up From Idle Flag bit 1 = Device has been in Idle mode 0 = Device has not been in Idle mode BOR: Brown-out Reset Flag bit 1 = A Brown-out Reset has occurred. Note that BOR is also set after a Power-on Reset. 0 = A Brown-out Reset has not occurred POR: Power-on Reset Flag bit 1 = A Power-up Reset has occurred 0 = A Power-up Reset has not occurred All of the Reset status bits may be set or cleared in software. Setting one of these bits in software does not cause a device Reset. If the FWDTEN Configuration bit is `1' (unprogrammed), the WDT is always enabled, regardless of the SWDTEN bit setting. DS39897B-page 62 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 5-1: RESET FLAG BIT OPERATION Flag Bit Setting Event Clearing Event TRAPR (RCON<15>) Trap Conflict Event POR IOPUWR (RCON<14>) Illegal Opcode or Uninitialized W Register Access POR CM (RCON<9>) Configuration Mismatch Reset POR EXTR (RCON<7>) MCLR Reset POR SWR (RCON<6>) RESET Instruction POR WDTO (RCON<4>) WDT Time-out SLEEP (RCON<3>) PWRSAV #SLEEP Instruction POR IDLE (RCON<2>) PWRSAV #IDLE Instruction POR BOR (RCON<1>) POR, BOR -- POR (RCON<0>) POR -- Note: 5.1 PWRSAV Instruction, POR All Reset flag bits may be set or cleared by the user software. Clock Source Selection at Reset If clock switching is enabled, the system clock source at device Reset is chosen as shown in Table 5-2. If clock switching is disabled, the system clock source is always selected according to the oscillator Configuration bits. Refer to Section 7.0 "Oscillator Configuration" for further details. TABLE 5-2: Reset Type POR BOR MCLR WDTO OSCILLATOR SELECTION vs. TYPE OF RESET (CLOCK SWITCHING ENABLED) Clock Source Determinant FNOSC Configuration bits (CW2<10:8>) 5.2 Device Reset Times The Reset times for various types of device Reset are summarized in Table 5-3. Note that the system Reset signal, SYSRST, is released after the POR and PWRT delay times expire. The time at which the device actually begins to execute code will also depend on the system oscillator delays, which include the Oscillator Start-up Timer (OST) and the PLL lock time. The OST and PLL lock times occur in parallel with the applicable SYSRST delay times. The FSCM delay determines the time at which the FSCM begins to monitor the system clock source after the SYSRST signal is released. COSC Control bits (OSCCON<14:12>) SWR (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 63 PIC24FJ256GB110 FAMILY TABLE 5-3: Reset Type RESET DELAY TIMES FOR VARIOUS DEVICE RESETS Clock Source SYSRST Delay EC, FRC, FRCDIV, LPRC TPOR + TSTARTUP + TRST POR BOR System Clock Delay FSCM Delay -- -- Notes 1, 2, 3 ECPLL, FRCPLL TPOR + TSTARTUP + TRST TLOCK TFSCM 1, 2, 3, 5, 6 XT, HS, SOSC TPOR + TSTARTUP + TRST TOST TFSCM 1, 2, 3, 4, 6 XTPLL, HSPLL TPOR + TSTARTUP + TRST TOST + TLOCK TFSCM 1, 2, 3, 4, 5, 6 EC, FRC, FRCDIV, LPRC TSTARTUP + TRST -- -- 2, 3 ECPLL, FRCPLL TSTARTUP + TRST TLOCK TFSCM 2, 3, 5, 6 XT, HS, SOSC TSTARTUP + TRST TOST TFSCM 2, 3, 4, 6 XTPLL, HSPLL TSTARTUP + TRST TOST + TLOCK TFSCM 2, 3, 4, 5, 6 MCLR Any Clock TRST -- -- 3 WDT Any Clock TRST -- -- 3 Software Any clock TRST -- -- 3 Illegal Opcode Any Clock TRST -- -- 3 Uninitialized W Any Clock TRST -- -- 3 Trap Conflict Any Clock TRST -- -- 3 Note 1: 2: 3: 4: 5: 6: TPOR = Power-on Reset delay (10 s nominal). TSTARTUP = TVREG (10 s nominal) if on-chip regulator is enabled or TPWRT (64 ms nominal) if on-chip regulator is disabled. TRST = Internal state Reset time (32 s nominal). TOST = Oscillator Start-up Timer. A 10-bit counter counts 1024 oscillator periods before releasing the oscillator clock to the system. TLOCK = PLL lock time. TFSCM = Fail-Safe Clock Monitor delay (100 s nominal). DS39897B-page 64 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 5.2.1 POR AND LONG OSCILLATOR START-UP TIMES 5.2.2.1 The oscillator start-up circuitry and its associated delay timers are not linked to the device Reset delays that occur at power-up. Some crystal circuits (especially low-frequency crystals) will have a relatively long start-up time. Therefore, one or more of the following conditions is possible after SYSRST is released: * The oscillator circuit has not begun to oscillate. * The Oscillator Start-up Timer has not expired (if a crystal oscillator is used). * The PLL has not achieved a lock (if PLL is used). The device will not begin to execute code until a valid clock source has been released to the system. Therefore, the oscillator and PLL start-up delays must be considered when the Reset delay time must be known. 5.2.2 FAIL-SAFE CLOCK MONITOR (FSCM) AND DEVICE RESETS If the FSCM is enabled, it will begin to monitor the system clock source when SYSRST is released. If a valid clock source is not available at this time, the device will automatically switch to the FRC oscillator and the user can switch to the desired crystal oscillator in the Trap Service Routine. (c) 2008 Microchip Technology Inc. FSCM Delay for Crystal and PLL Clock Sources When the system clock source is provided by a crystal oscillator and/or the PLL, a small delay, TFSCM, will automatically be inserted after the POR and PWRT delay times. The FSCM will not begin to monitor the system clock source until this delay expires. The FSCM delay time is nominally 100 s and provides additional time for the oscillator and/or PLL to stabilize. In most cases, the FSCM delay will prevent an oscillator failure trap at a device Reset when the PWRT is disabled. 5.3 Special Function Register Reset States Most of the Special Function Registers (SFRs) associated with the PIC24F CPU and peripherals are reset to a particular value at a device Reset. The SFRs are grouped by their peripheral or CPU function and their Reset values are specified in each section of this manual. The Reset value for each SFR does not depend on the type of Reset, with the exception of four registers. The Reset value for the Reset Control register, RCON, will depend on the type of device Reset. The Reset value for the Oscillator Control register, OSCCON, will depend on the type of Reset and the programmed values of the FNOSC bits in Flash Configuration Word 2 (CW2) (see Table 5-2). The RCFGCAL and NVMCON registers are only affected by a POR. Preliminary DS39897B-page 65 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 66 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 6.0 Note: INTERRUPT CONTROLLER 6.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 8. Interrupts" (DS39707). The PIC24F interrupt controller reduces the numerous peripheral interrupt request signals to a single interrupt request signal to the PIC24F CPU. It has the following features: * * * * Up to 8 processor exceptions and software traps 7 user-selectable priority levels Interrupt Vector Table (IVT) with up to 118 vectors A unique vector for each interrupt or exception source * Fixed priority within a specified user priority level * Alternate Interrupt Vector Table (AIVT) for debug support * Fixed interrupt entry and return latencies 6.1 Interrupt Vector Table The Interrupt Vector Table (IVT) is shown in Figure 6-1. The IVT resides in program memory, starting at location 000004h. The IVT contains 126 vectors, consisting of 8 non-maskable trap vectors, plus up to 118 sources of interrupt. In general, each interrupt source has its own vector. Each interrupt vector contains a 24-bit wide address. The value programmed into each interrupt vector location is the starting address of the associated Interrupt Service Routine (ISR). ALTERNATE INTERRUPT VECTOR TABLE The Alternate Interrupt Vector Table (AIVT) is located after the IVT, as shown in Figure 6-1. Access to the AIVT is provided by the ALTIVT control bit (INTCON2<15>). If the ALTIVT bit is set, all interrupt and exception processes will use the alternate vectors instead of the default vectors. The alternate vectors are organized in the same manner as the default vectors. The AIVT supports emulation and debugging efforts by providing a means to switch between an application and a support environment without requiring the interrupt vectors to be reprogrammed. This feature also enables switching between applications for evaluation of different software algorithms at run time. If the AIVT is not needed, the AIVT should be programmed with the same addresses used in the IVT. 6.2 Reset Sequence A device Reset is not a true exception because the interrupt controller is not involved in the Reset process. The PIC24F devices clear their registers in response to a Reset which forces the PC to zero. The microcontroller then begins program execution at location 000000h. The user programs a GOTO instruction at the Reset address, which redirects program execution to the appropriate start-up routine. Note: Any unimplemented or unused vector locations in the IVT and AIVT should be programmed with the address of a default interrupt handler routine that contains a RESET instruction. Interrupt vectors are prioritized in terms of their natural priority; this is linked to their position in the vector table. All other things being equal, lower addresses have a higher natural priority. For example, the interrupt associated with vector 0 will take priority over interrupts at any other vector address. PIC24FJ256GB110 family devices implement non-maskable traps and unique interrupts. These are summarized in Table 6-1 and Table 6-2. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 67 PIC24FJ256GB110 FAMILY FIGURE 6-1: PIC24F INTERRUPT VECTOR TABLE Decreasing Natural Order Priority Reset - GOTO Instruction Reset - GOTO Address Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 -- -- -- Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 -- -- -- Interrupt Vector 116 Interrupt Vector 117 Reserved Reserved Reserved Oscillator Fail Trap Vector Address Error Trap Vector Stack Error Trap Vector Math Error Trap Vector Reserved Reserved Reserved Interrupt Vector 0 Interrupt Vector 1 -- -- -- Interrupt Vector 52 Interrupt Vector 53 Interrupt Vector 54 -- -- -- Interrupt Vector 116 Interrupt Vector 117 Start of Code Note 1: TABLE 6-1: 000000h 000002h 000004h 000014h 00007Ch 00007Eh 000080h Interrupt Vector Table (IVT)(1) 0000FCh 0000FEh 000100h 000102h 000114h Alternate Interrupt Vector Table (AIVT)(1) 00017Ch 00017Eh 000180h 0001FEh 000200h See Table 6-2 for the interrupt vector list. TRAP VECTOR DETAILS Vector Number IVT Address AIVT Address Trap Source 0 000004h 000104h 1 000006h 000106h Oscillator Failure 2 000008h 000108h Address Error Reserved 3 00000Ah 00010Ah Stack Error 4 00000Ch 00010Ch Math Error 5 00000Eh 00010Eh Reserved 6 000010h 000110h Reserved 7 000012h 0001172h Reserved DS39897B-page 68 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 6-2: IMPLEMENTED INTERRUPT VECTORS Interrupt Bit Locations Vector Number IVT Address AIVT Address Flag Enable ADC1 Conversion Done 13 00002Eh 00012Eh IFS0<13> IEC0<13> IPC3<6:4> Comparator Event 18 000038h 000138h IFS1<2> IEC1<2> IPC4<10:8> CRC Generator 67 00009Ah 00019Ah IFS4<3> IEC4<3> IPC16<14:12> CTMU Event 77 0000AEh 0001AEh IFS4<13> IEC4<13> IPC19<6:4> Interrupt Source Priority External Interrupt 0 0 000014h 000114h IFS0<0> IEC0<0> IPC0<2:0> External Interrupt 1 20 00003Ch 00013Ch IFS1<4> IEC1<4> IPC5<2:0> External Interrupt 2 29 00004Eh 00014Eh IFS1<13> IEC1<13> IPC7<6:4> External Interrupt 3 53 00007Eh 00017Eh IFS3<5> IEC3<5> IPC13<6:4> IPC13<10:8> External Interrupt 4 54 000080h 000180h IFS3<6> IEC3<6> I2C1 Master Event 17 000036h 000136h IFS1<1> IEC1<1> IPC4<6:4> I2C1 Slave Event 16 000034h 000134h IFS1<0> IEC1<0> IPC4<2:0> I2C2 Master Event 50 000078h 000178h IFS3<2> IEC3<2> IPC12<10:8> I2C2 Slave Event 49 000076h 000176h IFS3<1> IEC3<1> IPC12<6:4> I2C3 Master Event 85 0000BEh 0001BEh IFS5<5> IEC5<5> IPC21<6:4> I2C3 Slave Event 84 0000BCh 0001BCh IFS5<4> IEC5<4> IPC21<2:0> Input Capture 1 1 000016h 000116h IFS0<1> IEC0<1> IPC0<6:4> Input Capture 2 5 00001Eh 00011Eh IFS0<5> IEC0<5> IPC1<6:4> Input Capture 3 37 00005Eh 00015Eh IFS2<5> IEC2<5> IPC9<6:4> Input Capture 4 38 000060h 000160h IFS2<6> IEC2<6> IPC9<10:8> Input Capture 5 39 000062h 000162h IFS2<7> IEC2<7> IPC9<14:12> Input Capture 6 40 000064h 000164h IFS2<8> IEC2<8> IPC10<2:0> Input Capture 7 22 000040h 000140h IFS1<6> IEC1<6> IPC5<10:8> Input Capture 8 23 000042h 000142h IFS1<7> IEC1<7> IPC5<14:12> Input Capture 9 93 0000CEh 0001CEh IFS5<13> IEC5<13> IPC23<6:4> Input Change Notification 19 00003Ah 00013Ah IFS1<3> IEC1<3> IPC4<14:12> LVD Low-Voltage Detect 72 0000A4h 0001A4h IFS4<8> IEC4<8> IPC18<2:0> Output Compare 1 2 000018h 000118h IFS0<2> IEC0<2> IPC0<10:8> Output Compare 2 6 000020h 000120h IFS0<6> IEC0<6> IPC1<10:8> Output Compare 3 25 000046h 000146h IFS1<9> IEC1<9> IPC6<6:4> Output Compare 4 26 000048h 000148h IFS1<10> IEC1<10> IPC6<10:8> Output Compare 5 41 000066h 000166h IFS2<9> IEC2<9> IPC10<6:4> Output Compare 6 42 000068h 000168h IFS2<10> IEC2<10> IPC10<10:8> Output Compare 7 43 00006Ah 00016Ah IFS2<11> IEC2<11> IPC10<14:12> Output Compare 8 44 00006Ch 00016Ch IFS2<12> IEC2<12> IPC11<2:0> Output Compare 9 92 0000CCh 0001CCh IFS5<12> IEC5<12> IPC23<2:0> Parallel Master Port 45 00006Eh 00016Eh IFS2<13> IEC2<13> IPC11<6:4> Real-Time Clock/Calendar 62 000090h 000190h IFS3<14> IEC3<14> IPC15<10:8> SPI1 Error 9 000026h 000126h IFS0<9> IEC0<9> IPC2<6:4> SPI1 Event 10 000028h 000128h IFS0<10> IEC0<10> IPC2<10:8> SPI2 Error 32 000054h 000154h IFS2<0> IEC2<0> IPC8<2:0> SPI2 Event 33 000056h 000156h IFS2<1> IEC2<1> IPC8<6:4> SPI3 Error 90 0000C8h 0001C8h IFS5<10> IEC5<10> IPC22<10:8> SPI3 Event 91 0000CAh 0001CAh IFS5<11> IEC5<11> IPC22<14:12> (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 69 PIC24FJ256GB110 FAMILY TABLE 6-2: IMPLEMENTED INTERRUPT VECTORS (CONTINUED) Interrupt Bit Locations Vector Number IVT Address AIVT Address Flag Enable Priority Timer1 3 00001Ah 00011Ah IFS0<3> IEC0<3> IPC0<14:12> Timer2 7 000022h 000122h IFS0<7> IEC0<7> IPC1<14:12> Timer3 8 000024h 000124h IFS0<8> IEC0<8> IPC2<2:0> Timer4 27 00004Ah 00014Ah IFS1<11> IEC1<11> IPC6<14:12> Timer5 28 00004Ch 00014Ch IFS1<12> IEC1<12> IPC7<2:0> UART1 Error 65 000096h 000196h IFS4<1> IEC4<1> IPC16<6:4> UART1 Receiver 11 00002Ah 00012Ah IFS0<11> IEC0<11> IPC2<14:12> UART1 Transmitter 12 00002Ch 00012Ch IFS0<12> IEC0<12> IPC3<2:0> UART2 Error 66 000098h 000198h IFS4<2> IEC4<2> IPC16<10:8> Interrupt Source UART2 Receiver 30 000050h 000150h IFS1<14> IEC1<14> IPC7<10:8> UART2 Transmitter 31 000052h 000152h IFS1<15> IEC1<15> IPC7<14:12> UART3 Error 81 0000B6h 0001B6h IFS5<1> IEC5<1> IPC20<6:4> UART3 Receiver 82 0000B8h 0001B8h IFS5<2> IEC5<2> IPC20<10:8> UART3 Transmitter 83 0000BAh 0001BAh IFS5<3> IEC5<3> IPC20<14:12> UART4 Error 87 0000C2h 0001C2h IFS5<7> IEC5<7> IPC21<14:12> UART4 Receiver 88 0000C4h 0001C4h IFS5<8> IEC5<8> IPC22<2:0> UART4 Transmitter 89 0000C6h 0001C6h IFS5<9> IEC5<9> IPC22<6:4> USB Interrupt 86 0000C0h 0001C0h IFS5<6> IEC5<6> IPC21<10:8> 6.3 Interrupt Control and Status Registers The PIC24FJ256GB110 family of devices implements a total of 36 registers for the interrupt controller: * * * * * INTCON1 INTCON2 IFS0 through IFS5 IEC0 through IEC5 IPC0 through IPC23 (except IPC14 and IPC17) Global interrupt control functions are controlled from INTCON1 and INTCON2. INTCON1 contains the Interrupt Nesting Disable (NSTDIS) bit, as well as the control and status flags for the processor trap sources. The INTCON2 register controls the external interrupt request signal behavior and the use of the Alternate Interrupt Vector Table. The IFSx registers maintain all of the interrupt request flags. Each source of interrupt has a status bit which is set by the respective peripherals, or an external signal, and is cleared via software. The interrupt sources are assigned to the IFSx, IECx and IPCx registers in the order of their vector numbers, as shown in Table 6-2. For example, the INT0 (External Interrupt 0) is shown as having a vector number and a natural order priority of 0. Thus, the INT0IF status bit is found in IFS0<0>, the INT0IE enable bit in IEC0<0> and the INT0IP<2:0> priority bits in the first position of IPC0 (IPC0<2:0>). Although they are not specifically part of the interrupt control hardware, two of the CPU control registers contain bits that control interrupt functionality. The ALU STATUS register (SR) contains the IPL2:IPL0 bits (SR<7:5>). These indicate the current CPU interrupt priority level. The user may change the current CPU priority level by writing to the IPL bits. The CORCON register contains the IPL3 bit, which, together with IPL2:IPL0, indicates the current CPU priority level. IPL3 is a read-only bit so that trap events cannot be masked by the user software. All interrupt registers are described in Register 6-1 through Register 6-38, in the following pages. The IECx registers maintain all of the interrupt enable bits. These control bits are used to individually enable interrupts from the peripherals or external signals. The IPCx registers are used to set the interrupt priority level for each source of interrupt. Each user interrupt source can be assigned to one of eight priority levels. DS39897B-page 70 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-1: SR: ALU STATUS REGISTER (IN CPU) U-0 U-0 U-0 U-0 U-0 U-0 U-0 R-0 -- -- -- -- -- -- -- DC(1) bit 15 bit 8 R/W-0 IPL2 (2,3) R/W-0 R/W-0 R-0 R/W-0 R/W-0 R/W-0 R/W-0 IPL1(2,3) IPL0(2,3) RA(1) N(1) OV(1) Z(1) C(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown IPL2:IPL0: CPU Interrupt Priority Level Status bits(2,3) 111 = CPU interrupt priority level is 7 (15). User interrupts disabled. 110 = CPU interrupt priority level is 6 (14) 101 = CPU interrupt priority level is 5 (13) 100 = CPU interrupt priority level is 4 (12) 011 = CPU interrupt priority level is 3 (11) 010 = CPU interrupt priority level is 2 (10) 001 = CPU interrupt priority level is 1 (9) 000 = CPU interrupt priority level is 0 (8) bit 7-5 Note 1: 2: 3: See Register 2-1 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. The IPL bits are concatenated with the IPL3 bit (CORCON<3>) to form the CPU interrupt priority level. The value in parentheses indicates the interrupt priority level if IPL3 = 1. The IPL Status bits are read-only when NSTDIS (INTCON1<15>) = 1. REGISTER 6-2: CORCON: CPU CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 U-0 U-0 U-0 R/C-0 R/W-0 U-0 U-0 -- -- -- -- IPL3(2) PSV(1) -- -- bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown IPL3: CPU Interrupt Priority Level Status bit(2) 1 = CPU interrupt priority level is greater than 7 0 = CPU interrupt priority level is 7 or less bit 3 Note 1: 2: See Register 2-2 for the description of the remaining bit(s) that are not dedicated to interrupt control functions. The IPL3 bit is concatenated with the IPL2:IPL0 bits (SR<7:5>) to form the CPU interrupt priority level. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 71 PIC24FJ256GB110 FAMILY REGISTER 6-3: INTCON1: INTERRUPT CONTROL REGISTER 1 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 NSTDIS -- -- -- -- -- -- -- bit 15 bit 8 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 -- -- -- MATHERR ADDRERR STKERR OSCFAIL -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 NSTDIS: Interrupt Nesting Disable bit 1 = Interrupt nesting is disabled 0 = Interrupt nesting is enabled bit 14-5 Unimplemented: Read as `0' bit 4 MATHERR: Arithmetic Error Trap Status bit 1 = Overflow trap has occurred 0 = Overflow trap has not occurred bit 3 ADDRERR: Address Error Trap Status bit 1 = Address error trap has occurred 0 = Address error trap has not occurred bit 2 STKERR: Stack Error Trap Status bit 1 = Stack error trap has occurred 0 = Stack error trap has not occurred bit 1 OSCFAIL: Oscillator Failure Trap Status bit 1 = Oscillator failure trap has occurred 0 = Oscillator failure trap has not occurred bit 0 Unimplemented: Read as `0' DS39897B-page 72 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-4: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-0 R-0 U-0 U-0 U-0 U-0 U-0 U-0 ALTIVT DISI -- -- -- -- -- -- bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 -- -- -- -- -- INT2EP INT1EP INT0EP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 ALTIVT: Enable Alternate Interrupt Vector Table bit 1 = Use Alternate Interrupt Vector Table 0 = Use standard (default) vector table bit 14 DISI: DISI Instruction Status bit 1 = DISI instruction is active 0 = DISI instruction is not active bit 13-3 Unimplemented: Read as `0' bit 2 INT2EP: External Interrupt 2 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 1 INT1EP: External Interrupt 1 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge bit 0 INT0EP: External Interrupt 0 Edge Detect Polarity Select bit 1 = Interrupt on negative edge 0 = Interrupt on positive edge (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 73 PIC24FJ256GB110 FAMILY REGISTER 6-5: IFS0: INTERRUPT FLAG STATUS REGISTER 0 U-0 -- bit 15 U-0 -- R/W-0 AD1IF R/W-0 U1TXIF R/W-0 U1RXIF R/W-0 SPI1IF R/W-0 SPF1IF R/W-0 T3IF bit 8 R/W-0 T2IF bit 7 R/W-0 OC2IF R/W-0 IC2IF U-0 -- R/W-0 T1IF R/W-0 OC1IF R/W-0 IC1IF R/W-0 INT0IF bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' AD1IF: A/D Conversion Complete Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1TXIF: UART1 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U1RXIF: UART1 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI1IF: SPI1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF1IF: SPI1 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T3IF: Timer3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T2IF: Timer2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC2IF: Output Compare Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC2IF: Input Capture Channel 2 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' T1IF: Timer1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC1IF: Output Compare Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC1IF: Input Capture Channel 1 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT0IF: External Interrupt 0 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS39897B-page 74 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-6: IFS1: INTERRUPT FLAG STATUS REGISTER 1 R/W-0 U2TXIF bit 15 R/W-0 U2RXIF R/W-0 IC8IF bit 7 R/W-0 IC7IF bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W-0 T5IF R/W-0 T4IF R/W-0 OC4IF R/W-0 OC3IF U-0 -- bit 8 Legend: R = Readable bit -n = Value at POR bit 15 R/W-0 INT2IF U-0 -- W = Writable bit `1' = Bit is set R/W-0 INT1IF R/W-0 CNIF R/W-0 CMIF R/W-0 MI2C1IF R/W-0 SI2C1IF bit 0 U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U2TXIF: UART2 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U2RXIF: UART2 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred INT2IF: External Interrupt 2 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T5IF: Timer5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred T4IF: Timer4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC4IF: Output Compare Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC3IF: Output Compare Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' IC8IF: Input Capture Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred IC7IF: Input Capture Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' INT1IF: External Interrupt 1 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CNIF: Input Change Notification Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred CMIF: Comparator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred MI2C1IF: Master I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C1IF: Slave I2C1 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 75 PIC24FJ256GB110 FAMILY REGISTER 6-7: IFS2: INTERRUPT FLAG STATUS REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- PMPIF OC8IF OC7IF OC6IF OC5IF IC6IF bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 IC5IF IC4IF IC3IF -- -- -- SPI2IF SPF2IF bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-14 Unimplemented: Read as `0' bit 13 PMPIF: Parallel Master Port Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12 OC8IF: Output Compare Channel 8 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 11 OC7IF: Output Compare Channel 7 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 10 OC6IF: Output Compare Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 9 OC5IF: Output Compare Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 8 IC6IF: Input Capture Channel 6 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7 IC5IF: Input Capture Channel 5 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 6 IC4IF: Input Capture Channel 4 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 IC3IF: Input Capture Channel 3 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4-2 Unimplemented: Read as `0' bit 1 SPI2IF: SPI2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 SPF2IF: SPI2 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred DS39897B-page 76 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-8: IFS3: INTERRUPT FLAG STATUS REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 -- RTCIF -- -- -- -- -- -- bit 15 bit 8 U-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 -- INT4IF INT3IF -- -- MI2C2IF SI2C2IF -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14 RTCIF: Real-Time Clock/Calendar Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 13-7 Unimplemented: Read as `0' bit 6 INT4IF: External Interrupt 4 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 5 INT3IF: External Interrupt 3 Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 4-3 Unimplemented: Read as `0' bit 2 MI2C2IF: Master I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 SI2C2IF: Slave I2C2 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as `0' (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 77 PIC24FJ256GB110 FAMILY REGISTER 6-9: IFS4: INTERRUPT FLAG STATUS REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 -- -- CTMUIF -- -- -- -- LVDIF bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 -- -- -- -- CRCIF U2ERIF U1ERIF -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-14 Unimplemented: Read as `0' bit 13 CTMUIF: CTMU Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 12-9 Unimplemented: Read as `0' bit 8 LVDIF: Low-Voltage Detect Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 7-4 Unimplemented: Read as `0' bit 3 CRCIF: CRC Generator Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 2 U2ERIF: UART2 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 1 U1ERIF: UART1 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred bit 0 Unimplemented: Read as `0' DS39897B-page 78 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-10: U-0 -- bit 15 R/W-0 U4ERIF bit 7 U-0 -- R/W-0 IC9IF R/W-0 OC9IF R/W-0 SPI3IF R/W-0 SPF3IF R/W-0 U4TXIF R/W-0 USB1IF R/W-0 MI2C3IF R/W-0 SI2C3IF R/W-0 U3TXIF R/W-0 U3RXIF R/W-0 U3ERIF bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W-0 U4RXIF bit 8 U-0 -- bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 IFS5: INTERRUPT FLAG STATUS REGISTER 5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' IC9IF: Input Capture Channel 9 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred OC9IF: Output Compare Channel 9 Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPI3IF: SPI3 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SPF3IF: SPI3 Fault Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U4TXIF: UART4 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U4RXIF: UART4 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U4ERIF: UART4 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred USB1IF: USB1 (USB OTG) Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred MI2C3IF: Master I2C3 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred SI2C3IF: Slave I2C3 Event Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U3TXIF: UART3 Transmitter Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U3RXIF: UART3 Receiver Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred U3ERIF: UART3 Error Interrupt Flag Status bit 1 = Interrupt request has occurred 0 = Interrupt request has not occurred Unimplemented: Read as `0' (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 79 PIC24FJ256GB110 FAMILY REGISTER 6-11: IEC0: INTERRUPT ENABLE CONTROL REGISTER 0 U-0 -- bit 15 U-0 -- R/W-0 AD1IE R/W-0 U1TXIE R/W-0 U1RXIE R/W-0 SPI1IE R/W-0 SPF1IE R/W-0 T3IE bit 8 R/W-0 T2IE bit 7 R/W-0 OC2IE R/W-0 IC2IE U-0 -- R/W-0 T1IE R/W-0 OC1IE R/W-0 IC1IE R/W-0 INT0IE bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' AD1IE: A/D Conversion Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1TXIE: UART1 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U1RXIE: UART1 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI1IE: SPI1 Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPF1IE: SPI1 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T3IE: Timer3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T2IE: Timer2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC2IE: Output Compare Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC2IE: Input Capture Channel 2 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' T1IE: Timer1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC1IE: Output Compare Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC1IE: Input Capture Channel 1 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT0IE: External Interrupt 0 Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled DS39897B-page 80 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-12: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 R/W-0 U2TXIE bit 15 R/W-0 U2RXIE R/W-0 IC8IE bit 7 R/W-0 IC7IE bit 14 bit 13 bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 Note 1: R/W-0 T5IE R/W-0 T4IE R/W-0 OC4IE R/W-0 OC3IE U-0 -- bit 8 Legend: R = Readable bit -n = Value at POR bit 15 R/W-0 INT2IE(1) U-0 -- W = Writable bit `1' = Bit is set R/W-0 INT1IE(1) R/W-0 CNIE R/W-0 CMIE R/W-0 MI2C1IE R/W-0 SI2C1IE bit 0 U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown U2TXIE: UART2 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U2RXIE: UART2 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled INT2IE: External Interrupt 2 Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled T5IE: Timer5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled T4IE: Timer4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC4IE: Output Compare Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC3IE: Output Compare Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' IC8IE: Input Capture Channel 8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled IC7IE: Input Capture Channel 7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' INT1IE: External Interrupt 1 Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled CNIE: Input Change Notification Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled CMIE: Comparator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or PRIx pin. See Section 9.4 "Peripheral Pin Select" for more information. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 81 PIC24FJ256GB110 FAMILY REGISTER 6-12: bit 1 bit 0 Note 1: IEC1: INTERRUPT ENABLE CONTROL REGISTER 1 (CONTINUED) MI2C1IE: Master I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C1IE: Slave I2C1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or PRIx pin. See Section 9.4 "Peripheral Pin Select" for more information. DS39897B-page 82 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-13: IEC2: INTERRUPT ENABLE CONTROL REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- PMPIE OC8IE OC7IE OC6IE OC5IE IC6IE bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 IC5IE IC4IE IC3IE -- -- -- SPI2IE SPF2IE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-14 Unimplemented: Read as `0' bit 13 PMPIE: Parallel Master Port Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12 OC8IE: Output Compare Channel 8 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 11 OC7IE: Output Compare Channel 7 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 10 OC6IE: Output Compare Channel 6 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 OC5IE: Output Compare Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8 IC6IE: Input Capture Channel 6 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7 IC5IE: Input Capture Channel 5 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 6 IC4IE: Input Capture Channel 4 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 IC3IE: Input Capture Channel 3 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4-2 Unimplemented: Read as `0' bit 1 SPI2IE: SPI2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 SPF2IE: SPI2 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 83 PIC24FJ256GB110 FAMILY REGISTER 6-14: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 -- RTCIE -- -- -- -- -- -- bit 15 bit 8 U-0 -- R/W-0 INT4IE (1) R/W-0 (1) INT3IE U-0 U-0 R/W-0 R/W-0 U-0 -- -- MI2C2IE SI2C2IE -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14 RTCIE: Real-Time Clock/Calendar Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13-7 Unimplemented: Read as `0' bit 6 INT4IE: External Interrupt 4 Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 5 INT3IE: External Interrupt 3 Enable bit(1) 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 4-3 Unimplemented: Read as `0' bit 2 MI2C2IE: Master I2C2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 SI2C2IE: Slave I2C2 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as `0' Note 1: x = Bit is unknown If an external interrupt is enabled, the interrupt input must also be configured to an available RPx or PRIx pin. See Section 9.4 "Peripheral Pin Select" for more information. DS39897B-page 84 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-15: IEC4: INTERRUPT ENABLE CONTROL REGISTER 4 U-0 U-0 R/W-0 U-0 U-0 U-0 U-0 R/W-0 -- -- CTMUIE -- -- -- -- LVDIE bit 15 bit 8 U-0 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 U-0 -- -- -- -- CRCIE U2ERIE U1ERIE -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-14 Unimplemented: Read as `0' bit 13 CTMUIE: CTMU Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12-9 Unimplemented: Read as `0' bit 8 LVDIE: Low-Voltage Detect Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 7-4 Unimplemented: Read as `0' bit 3 CRCIE: CRC Generator Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 2 U2ERIE: UART2 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 1 U1ERIE: UART1 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 0 Unimplemented: Read as `0' (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 85 PIC24FJ256GB110 FAMILY REGISTER 6-16: U-0 -- bit 15 R/W-0 U4ERIE bit 7 U-0 -- R/W-0 IC9IE R/W-0 OC9IE R/W-0 SPI3IE R/W-0 SPF3IE R/W-0 U4TXIE R/W-0 USB1IE R/W-0 MI2C3IE R/W-0 SI2C3IE R/W-0 U3TXIE R/W-0 U3RXIE R/W-0 U3ERIE bit 12 bit 11 bit 10 bit 9 bit 8 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 R/W-0 U4RXIE bit 8 U-0 -- bit 0 Legend: R = Readable bit -n = Value at POR bit 15-14 bit 13 IEC5: INTERRUPT ENABLE CONTROL REGISTER 5 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' IC9IE: Input Capture Channel 9 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled OC9IE: Output Compare Channel 9 Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPI3IE: SPI3 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SPF3IE: SPI3 Fault Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U4TXIE: UART4 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U4RXIE: UART4 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U4ERIE: UART4 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled USB1IE: USB1 (USB OTG) Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled MI2C3IE: Master I2C3 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled SI2C3IE: Slave I2C3 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U3TXIE: UART3 Transmitter Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U3RXIE: UART3 Receiver Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled U3ERIE: UART3 Error Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled Unimplemented: Read as `0' DS39897B-page 86 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-17: IPC0: INTERRUPT PRIORITY CONTROL REGISTER 0 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- T1IP2 T1IP1 T1IP0 -- OC1IP2 OC1IP1 OC1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- IC1IP2 IC1IP1 IC1IP0 -- INT0IP2 INT0IP1 INT0IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14-12 T1IP2:T1IP0: Timer1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as `0' bit 10-8 OC1IP2:OC1IP0: Output Compare Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as `0' bit 6-4 IC1IP2:IC1IP0: Input Capture Channel 1 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as `0' bit 2-0 INT0IP2:INT0IP0: External Interrupt 0 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 87 PIC24FJ256GB110 FAMILY REGISTER 6-18: IPC1: INTERRUPT PRIORITY CONTROL REGISTER 1 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- T2IP2 T2IP1 T2IP0 -- OC2IP2 OC2IP1 OC2IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 -- IC2IP2 IC2IP1 IC2IP0 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14-12 T2IP2:T2IP0: Timer2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as `0' bit 10-8 OC2IP2:OC2IP0: Output Compare Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as `0' bit 6-4 IC2IP2:IC2IP0: Input Capture Channel 2 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' DS39897B-page 88 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-19: IPC2: INTERRUPT PRIORITY CONTROL REGISTER 2 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- U1RXIP2 U1RXIP1 U1RXIP0 -- SPI1IP2 SPI1IP1 SPI1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- SPF1IP2 SPF1IP1 SPF1IP0 -- T3IP2 T3IP1 T3IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14-12 U1RXIP2:U1RXIP0: UART1 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as `0' bit 10-8 SPI1IP2:SPI1IP0: SPI1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as `0' bit 6-4 SPF1IP2:SPF1IP0: SPI1 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as `0' bit 2-0 T3IP2:T3IP0: Timer3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 89 PIC24FJ256GB110 FAMILY REGISTER 6-20: IPC3: INTERRUPT PRIORITY CONTROL REGISTER 3 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- AD1IP2 AD1IP1 AD1IP0 -- U1TXIP2 U1TXIP1 U1TXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-7 Unimplemented: Read as `0' bit 6-4 AD1IP2:AD1IP0: A/D Conversion Complete Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as `0' bit 2-0 U1TXIP2:U1TXIP0: UART1 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39897B-page 90 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-21: IPC4: INTERRUPT PRIORITY CONTROL REGISTER 4 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- CNIP2 CNIP1 CNIP0 -- CMIP2 CMIP1 CMIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- MI2C1P2 MI2C1P1 MI2C1P0 -- SI2C1P2 SI2C1P1 SI2C1P0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14-12 CNIP2:CNIP0: Input Change Notification Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as `0' bit 10-8 CMIP2:CMIP0: Comparator Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as `0' bit 6-4 MI2C1P2:MI2C1P0: Master I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as `0' bit 2-0 SI2C1P2:SI2C1P0: Slave I2C1 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 91 PIC24FJ256GB110 FAMILY REGISTER 6-22: IPC5: INTERRUPT PRIORITY CONTROL REGISTER 5 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- IC8IP2 IC8IP1 IC8IP0 -- IC7IP2 IC7IP1 IC7IP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 -- -- -- -- -- INT1IP2 INT1IP1 INT1IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14-12 IC8IP2:IC8IP0: Input Capture Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as `0' bit 10-8 IC7IP2:IC7IP0: Input Capture Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-3 Unimplemented: Read as `0' bit 2-0 INT1IP2:INT1IP0: External Interrupt 1 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39897B-page 92 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-23: IPC6: INTERRUPT PRIORITY CONTROL REGISTER 6 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- T4IP2 T4IP1 T4IP0 -- OC4IP2 OC4IP1 OC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 -- OC3IP2 OC3IP1 OC3IP0 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14-12 T4IP2:T4IP0: Timer4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as `0' bit 10-8 OC4IP2:OC4IP0: Output Compare Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as `0' bit 6-4 OC3IP2:OC3IP0: Output Compare Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 93 PIC24FJ256GB110 FAMILY REGISTER 6-24: IPC7: INTERRUPT PRIORITY CONTROL REGISTER 7 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- U2TXIP2 U2TXIP1 U2TXIP0 -- U2RXIP2 U2RXIP1 U2RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- INT2IP2 INT2IP1 INT2IP0 -- T5IP2 T5IP1 T5IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14-12 U2TXIP2:U2TXIP0: UART2 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as `0' bit 10-8 U2RXIP2:U2RXIP0: UART2 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as `0' bit 6-4 INT2IP2:INT2IP0: External Interrupt 2 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as `0' bit 2-0 T5IP2:T5IP0: Timer5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39897B-page 94 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-25: IPC8: INTERRUPT PRIORITY CONTROL REGISTER 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- SPI2IP2 SPI2IP1 SPI2IP0 -- SPF2IP2 SPF2IP1 SPF2IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-7 Unimplemented: Read as `0' bit 6-4 SPI2IP2:SPI2IP0: SPI2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as `0' bit 2-0 SPF2IP2:SPF2IP0: SPI2 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 95 PIC24FJ256GB110 FAMILY REGISTER 6-26: IPC9: INTERRUPT PRIORITY CONTROL REGISTER 9 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- IC5IP2 IC5IP1 IC5IP0 -- IC4IP2 IC4IP1 IC4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 -- IC3IP2 IC3IP1 IC3IP0 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14-12 IC5IP2:IC5IP0: Input Capture Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as `0' bit 10-8 IC4IP2:IC4IP0: Input Capture Channel 4 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as `0' bit 6-4 IC3IP2:IC3IP0: Input Capture Channel 3 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' DS39897B-page 96 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-27: IPC10: INTERRUPT PRIORITY CONTROL REGISTER 10 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- OC7IP2 OC7IP1 OC7IP0 -- OC6IP2 OC6IP1 OC6IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- OC5IP2 OC5IP1 OC5IP0 -- IC6IP2 IC6IP1 IC6IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14-12 OC7IP2:OC7IP0: Output Compare Channel 7 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as `0' bit 10-8 OC6IP2:OC6IP0: Output Compare Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as `0' bit 6-4 OC5IP2:OC5IP0: Output Compare Channel 5 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as `0' bit 2-0 IC6IP2:IC6IP0: Input Capture Channel 6 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 97 PIC24FJ256GB110 FAMILY REGISTER 6-28: IPC11: INTERRUPT PRIORITY CONTROL REGISTER 11 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- PMPIP2 PMPIP1 PMPIP0 -- OC8IP2 OC8IP1 OC8IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-7 Unimplemented: Read as `0' bit 6-4 PMPIP2:PMPIP0: Parallel Master Port Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as `0' bit 2-0 OC8IP2:OC8IP0: Output Compare Channel 8 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39897B-page 98 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-29: IPC12: INTERRUPT PRIORITY CONTROL REGISTER 12 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 -- -- -- -- -- MI2C2P2 MI2C2P1 MI2C2P0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 -- SI2C2P2 SI2C2P1 SI2C2P0 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-11 Unimplemented: Read as `0' bit 10-8 MI2C2P2:MI2C2P0: Master I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as `0' bit 6-4 SI2C2P2:SI2C2P0: Slave I2C2 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 99 PIC24FJ256GB110 FAMILY REGISTER 6-30: IPC13: INTERRUPT PRIORITY CONTROL REGISTER 13 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 -- -- -- -- -- INT4IP2 INT4IP1 INT4IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 -- INT3IP2 INT3IP1 INT3IP0 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-11 Unimplemented: Read as `0' bit 10-8 INT4IP2:INT4IP0: External Interrupt 4 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as `0' bit 6-4 INT3IP2:INT3IP0: External Interrupt 3 Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' DS39897B-page 100 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-31: IPC15: INTERRUPT PRIORITY CONTROL REGISTER 15 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 -- -- -- -- -- RTCIP2 RTCIP1 RTCIP0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-11 Unimplemented: Read as `0' bit 10-8 RTCIP2:RTCIP0: Real-Time Clock/Calendar Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7-0 Unimplemented: Read as `0' (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 101 PIC24FJ256GB110 FAMILY REGISTER 6-32: IPC16: INTERRUPT PRIORITY CONTROL REGISTER 16 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- CRCIP2 CRCIP1 CRCIP0 -- U2ERIP2 U2ERIP1 U2ERIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 -- U1ERIP2 U1ERIP1 U1ERIP0 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14-12 CRCIP2:CRCIP0: CRC Generator Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as `0' bit 10-8 U2ERIP2:U2ERIP0: UART2 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as `0' bit 6-4 U1ERIP2:U1ERIP0: UART1 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' DS39897B-page 102 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-33: IPC18: INTERRUPT PRIORITY CONTROL REGISTER 18 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R/W-1 R/W-0 R/W-0 -- -- -- -- -- LVDIP2 LVDIP1 LVDIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-3 Unimplemented: Read as `0' bit 2-0 LVDIP2:LVDIP0: Low-Voltage Detect Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled REGISTER 6-34: x = Bit is unknown IPC19: INTERRUPT PRIORITY CONTROL REGISTER 19 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 -- CTMUIP2 CTMUIP1 CTMUIP0 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-7 Unimplemented: Read as `0' bit 6-4 CTMUIP2:CTMUIP0: CTMU Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 103 PIC24FJ256GB110 FAMILY REGISTER 6-35: IPC20: INTERRUPT PRIORITY CONTROL REGISTER 20 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- U3TXIP2 U3TXIP1 U3TXIP0 -- U3RXIP2 U3RXIP1 U3RXIP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 U-0 U-0 U-0 -- U3ERIP2 U3ERIP1 U3ERIP0 -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14-12 U3TXIP2:U3TXIP0: UART3 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as `0' bit 10-8 U3RXIP2:U3RXIP0: UART3 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as `0' bit 6-4 U3ERIP2:U3ERIP0: UART3 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3-0 Unimplemented: Read as `0' DS39897B-page 104 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-36: IPC21: INTERRUPT PRIORITY CONTROL REGISTER 21 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- U4ERIP2 U4ERIP1 U4ERIP0 -- USB1IP2 USB1IP1 USB1IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- MI2C3P2 MI2C3P1 MI2C3P0 -- SI2C3P2 SI2C3P1 SI2C3P0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14-12 U4ERIP2:U4ERIP0: UART4 Error Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as `0' bit 10-8 USB1IP2:USB1IP0: USB1 (USB OTG) Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as `0' bit 6-4 MI2C3P2:MI2C3P0: Master I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as `0' bit 2-0 SI2C3P2:SI2C3P0: Slave I2C3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 105 PIC24FJ256GB110 FAMILY REGISTER 6-37: IPC22: INTERRUPT PRIORITY CONTROL REGISTER 22 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- SPI3IP2 SPI3IP1 SPI3IP0 -- SPF3IP2 SPF3IP1 SPF3IP0 bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- U4TXIP2 U4TXIP1 U4TXIP0 -- U4RXIP2 U4RXIP1 U4RXIP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14-12 SPI3IP2:SP3IP0: SPI3 Event Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 11 Unimplemented: Read as `0' bit 10-8 SPF3IP2:SPF3IP0: SPI3 Fault Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 7 Unimplemented: Read as `0' bit 6-4 U4TXIP2:U4TXIP0: UART4 Transmitter Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as `0' bit 2-0 U4RXIP2:U4RXIP0: UART4 Receiver Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled DS39897B-page 106 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 6-38: IPC23: INTERRUPT PRIORITY CONTROL REGISTER 23 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 R/W-1 R/W-0 R/W-0 U-0 R/W-1 R/W-0 R/W-0 -- IC9IP2 IC9IP1 IC9IP0 -- OC9IP2 OC9IP1 OC9IP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-7 Unimplemented: Read as `0' bit 6-4 IC9IP2:IC9IP0: Input Capture Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled bit 3 Unimplemented: Read as `0' bit 2-0 OC9IP2:OC9IP0: Output Compare Channel 9 Interrupt Priority bits 111 = Interrupt is priority 7 (highest priority interrupt) * * * 001 = Interrupt is priority 1 000 = Interrupt source is disabled (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 107 PIC24FJ256GB110 FAMILY 6.4 Interrupt Setup Procedures 6.4.1 6.4.3 INITIALIZATION To configure an interrupt source: 1. 2. Set the NSTDIS Control bit (INTCON1<15>) if nested interrupts are not desired. Select the user-assigned priority level for the interrupt source by writing the control bits in the appropriate IPCx register. The priority level will depend on the specific application and type of interrupt source. If multiple priority levels are not desired, the IPCx register control bits for all enabled interrupt sources may be programmed to the same non-zero value. Note: 3. 4. At a device Reset, the IPCx registers are initialized, such that all user interrupt sources are assigned to priority level 4. Clear the interrupt flag status bit associated with the peripheral in the associated IFSx register. Enable the interrupt source by setting the interrupt enable control bit associated with the source in the appropriate IECx register. 6.4.2 TRAP SERVICE ROUTINE A Trap Service Routine (TSR) is coded like an ISR, except that the appropriate trap status flag in the INTCON1 register must be cleared to avoid re-entry into the TSR. 6.4.4 INTERRUPT DISABLE All user interrupts can be disabled using the following procedure: 1. 2. Push the current SR value onto the software stack using the PUSH instruction. Force the CPU to priority level 7 by inclusive ORing the value OEh with SRL. To enable user interrupts, the POP instruction may be used to restore the previous SR value. Note that only user interrupts with a priority level of 7 or less can be disabled. Trap sources (level 8-15) cannot be disabled. The DISI instruction provides a convenient way to disable interrupts of priority levels 1-6 for a fixed period of time. Level 7 interrupt sources are not disabled by the DISI instruction. INTERRUPT SERVICE ROUTINE The method that is used to declare an ISR and initialize the IVT with the correct vector address will depend on the programming language (i.e., `C' or assembler) and the language development toolsuite that is used to develop the application. In general, the user must clear the interrupt flag in the appropriate IFSx register for the source of the interrupt that the ISR handles. Otherwise, the ISR will be re-entered immediately after exiting the routine. If the ISR is coded in assembly language, it must be terminated using a RETFIE instruction to unstack the saved PC value, SRL value and old CPU priority level. DS39897B-page 108 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 7.0 OSCILLATOR CONFIGURATION Note: * An on-chip USB PLL block to provide a stable 48 MHz clock for the USB module as well as a range of frequency options for the system clock * Software-controllable switching between various clock sources * Software-controllable postscaler for selective clocking of CPU for system power savings * A Fail-Safe Clock Monitor (FSCM) that detects clock failure and permits safe application recovery or shutdown * A separate and independently configurable system clock output for synchronizing external hardware This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 6. Oscillator" (DS39700). The oscillator system for PIC24FJ256GB110 family devices has the following features: * A total of four external and internal oscillator options as clock sources, providing 11 different clock modes FIGURE 7-1: A simplified diagram of the oscillator system is shown in Figure 7-1. PIC24FJ256GB110 FAMILY CLOCK DIAGRAM PIC24FJ256GB110 Family 48 MHz USB Clock Primary Oscillator XT, HS, EC OSCO USB PLL ECPLL,FRCPLL PLL & DIV OSCI PLLDIV<2:0> 8 MHz 4 MHz FRCDIV Peripherals CLKDIV<10:8> LPRC Oscillator REFO FRC CLKO Postscaler 8 MHz (nominal) Reference Clock Generator CPDIV<1:0> Postscaler FRC Oscillator REFOCON<15:8> XTPLL, HSPLL LPRC 31 kHz (nominal) Secondary Oscillator CLKDIV<14:12> SOSC SOSCO SOSCI CPU SOSCEN Enable Oscillator Clock Control Logic Fail-Safe Clock Monitor WDT, PWRT Clock Source Option for Other Modules (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 109 PIC24FJ256GB110 FAMILY 7.1 CPU Clocking Scheme 7.2 The system clock source can be provided by one of four sources: * Primary Oscillator (POSC) on the OSCI and OSCO pins * Secondary Oscillator (SOSC) on the SOSCI and SOSCO pins * Fast Internal RC (FRC) Oscillator * Low-Power Internal RC (LPRC) Oscillator The primary oscillator and FRC sources have the option of using the internal USB PLL block, which generates both the USB module clock and a separate system clock from the 96 MHZ PLL. Refer to Section 7.5 "Oscillator Modes and USB Operation" for additional information. The internal FRC provides an 8 MHz clock source. It can optionally be reduced by the programmable clock divider to provide a range of system clock frequencies. The selected clock source generates the processor and peripheral clock sources. The processor clock source is divided by two to produce the internal instruction cycle clock, FCY. In this document, the instruction cycle clock is also denoted by FOSC/2. The internal instruction cycle clock, FOSC/2, can be provided on the OSCO I/O pin for some operating modes of the primary oscillator. TABLE 7-1: Initial Configuration on POR The oscillator source (and operating mode) that is used at a device Power-on Reset event is selected using Configuration bit settings. The oscillator Configuration bit settings are located in the Configuration registers in the program memory (refer to Section 25.1 "Configuration Bits" for further details). The Primary Oscillator Configuration bits, POSCMD1:POSCMD0 (Configuration Word 2<1:0>), and the Initial Oscillator Select Configuration bits, FNOSC2:FNOSC0 (Configuration Word 2<10:8>), select the oscillator source that is used at a Power-on Reset. The FRC primary oscillator with postscaler (FRCDIV) is the default (unprogrammed) selection. The secondary oscillator, or one of the internal oscillators, may be chosen by programming these bit locations. The Configuration bits allow users to choose between the various clock modes, shown in Table 7-1. 7.2.1 CLOCK SWITCHING MODE CONFIGURATION BITS The FCKSM Configuration bits (Configuration Word 2<7:6>) are used to jointly configure device clock switching and the Fail-Safe Clock Monitor (FSCM). Clock switching is enabled only when FCKSM1 is programmed (`0'). The FSCM is enabled only when FCKSM1:FCKSM0 are both programmed (`00'). CONFIGURATION BIT VALUES FOR CLOCK SELECTION Oscillator Source POSCMD1: POSCMD0 FNOSC2: FNOSC0 Note Fast RC Oscillator with Postscaler (FRCDIV) Internal 11 111 1, 2 (Reserved) Internal xx 110 1 Oscillator Mode Low-Power RC Oscillator (LPRC) Internal 11 101 1 Secondary 11 100 1 Primary Oscillator (XT) with PLL Module (XTPLL) Primary 01 011 Primary Oscillator (EC) with PLL Module (ECPLL) Primary 00 011 Primary Oscillator (HS) Primary 10 010 Primary Oscillator (XT) Primary 01 010 Primary Oscillator (EC) Primary 00 010 Fast RC Oscillator with PLL Module (FRCPLL) Internal 11 001 1 Fast RC Oscillator (FRC) Internal 11 000 1 Secondary (Timer1) Oscillator (SOSC) Note 1: 2: OSCO pin function is determined by the OSCIOFCN Configuration bit. This is the default oscillator mode for an unprogrammed (erased) device. DS39897B-page 110 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 7.3 Control Registers The operation of the oscillator is controlled by three Special Function Registers: * OSCCON * CLKDIV * OSCTUN REGISTER 7-1: The OSCCON register (Register 7-1) is the main control register for the oscillator. It controls clock source switching and allows the monitoring of clock sources. The CLKDIV register (Register 7-2) controls the features associated with Doze mode, as well as the postscaler for the FRC oscillator. The OSCTUN register (Register 7-3) allows the user to fine tune the FRC oscillator over a range of approximately 12%. OSCCON: OSCILLATOR CONTROL REGISTER U-0 R-0 R-0 R-0 U-0 R/W-x(1) R/W-x(1) R/W-x(1) -- COSC2 COSC1 COSC0 -- NOSC2 NOSC1 NOSC0 bit 15 bit 8 R/SO-0 R/W-0 R-0(3) U-0 R/CO-0 R/W-0 R/W-0 R/W-0 CLKLOCK IOLOCK(2) LOCK -- CF POSCEN SOSCEN OSWEN bit 7 bit 0 Legend: CO = Clear Only bit SO = Set Only bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 Unimplemented: Read as `0' bit 14-12 COSC2:COSC0: Current Oscillator Selection bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) bit 11 Unimplemented: Read as `0' bit 10-8 NOSC2:NOSC0: New Oscillator Selection bits(1) 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with Postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) Note 1: 2: 3: x = Bit is unknown Reset values for these bits are determined by the FNOSC Configuration bits. The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is `1', once the IOLOCK bit is set, it cannot be cleared. Also resets to `0' during any valid clock switch or whenever a non-PLL clock mode is selected. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 111 PIC24FJ256GB110 FAMILY REGISTER 7-1: OSCCON: OSCILLATOR CONTROL REGISTER (CONTINUED) bit 7 CLKLOCK: Clock Selection Lock Enabled bit If FSCM is enabled (FCKSM1 = 1): 1 = Clock and PLL selections are locked 0 = Clock and PLL selections are not locked and may be modified by setting the OSWEN bit If FSCM is disabled (FCKSM1 = 0): Clock and PLL selections are never locked and may be modified by setting the OSWEN bit. bit 6 IOLOCK: I/O Lock Enable bit(2) 1 = I/O lock is active 0 = I/O lock is not active bit 5 LOCK: PLL Lock Status bit(3) 1 = PLL module is in lock or PLL module start-up timer is satisfied 0 = PLL module is out of lock, PLL start-up timer is running or PLL is disabled bit 4 Unimplemented: Read as `0' bit 3 CF: Clock Fail Detect bit 1 = FSCM has detected a clock failure 0 = No clock failure has been detected bit 2 POSCEN: Primary Oscillator Sleep Enable bit 1 = Primary oscillator continues to operate during Sleep mode 0 = Primary oscillator disabled during Sleep mode bit 1 SOSCEN: 32 kHz Secondary Oscillator (SOSC) Enable bit 1 = Enable secondary oscillator 0 = Disable secondary oscillator bit 0 OSWEN: Oscillator Switch Enable bit 1 = Initiate an oscillator switch to clock source specified by NOSC2:NOSC0 bits 0 = Oscillator switch is complete Note 1: 2: 3: Reset values for these bits are determined by the FNOSC Configuration bits. The state of the IOLOCK bit can only be changed once an unlocking sequence has been executed. In addition, if the IOL1WAY Configuration bit is `1', once the IOLOCK bit is set, it cannot be cleared. Also resets to `0' during any valid clock switch or whenever a non-PLL clock mode is selected. DS39897B-page 112 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 7-2: R/W-0 CLKDIV: CLOCK DIVIDER REGISTER R/W-0 ROI R/W-0 DOZE2 DOZE1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-1 DOZE0 DOZEN(1) RCDIV2 RCDIV1 RCDIV0 bit 15 bit 8 R/W-0 R/W-0 U-0 U-0 U-0 U-0 U-0 U-0 CPDIV1 CPDIV0 -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 ROI: Recover on Interrupt bit 1 = Interrupts clear the DOZEN bit and reset the CPU peripheral clock ratio to 1:1 0 = Interrupts have no effect on the DOZEN bit bit 14-12 DOZE2:DOZE0: CPU Peripheral Clock Ratio Select bits 111 = 1:128 110 = 1:64 101 = 1:32 100 = 1:16 011 = 1:8 010 = 1:4 001 = 1:2 000 = 1:1 bit 11 DOZEN: DOZE Enable bit(1) 1 = DOZE2:DOZE0 bits specify the CPU peripheral clock ratio 0 = CPU peripheral clock ratio set to 1:1 bit 10-8 RCDIV2:RCDIV0: FRC Postscaler Select bits 111 = 31.25 kHz (divide by 256) 110 = 125 kHz (divide by 64) 101 = 250 kHz (divide by 32) 100 = 500 kHz (divide by 16) 011 = 1 MHz (divide by 8) 010 = 2 MHz (divide by 4) 001 = 4 MHz (divide by 2) 000 = 8 MHz (divide by 1) bit 7-6 CPDIV1:CPDIV0: USB System Clock Select bits (postscaler select from 32 MHz clock branch) 11 = 4 MHz (divide by 8)(2) 10 = 8 MHz (divide by 4)(2) 01 = 16 MHz (divide by 2) 00 = 32 MHz (divide by 1) bit 5-0 Unimplemented: Read as `0' Note 1: 2: This bit is automatically cleared when the ROI bit is set and an interrupt occurs. This setting is not allowed while the USB module is enabled. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 113 PIC24FJ256GB110 FAMILY REGISTER 7-3: OSCTUN: FRC OSCILLATOR TUNE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 -- U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- TUN5(1) TUN4(1) TUN3(1) TUN2(1) TUN1(1) TUN0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as `0' bit 5-0 TUN5:TUN0: FRC Oscillator Tuning bits 011111 = Maximum frequency deviation 011110 = * * * 000001 = 000000 = Center frequency, oscillator is running at factory calibrated frequency 111111 = * * * 100001 = 100000 = Minimum frequency deviation Note 1: 7.4 Increments or decrements of TUN5:TUN0 may not change the FRC frequency in equal steps over the FRC tuning range, and may not be monotonic. Clock Switching Operation 7.4.1 With few limitations, applications are free to switch between any of the four clock sources (POSC, SOSC, FRC and LPRC) under software control and at any time. To limit the possible side effects that could result from this flexibility, PIC24F devices have a safeguard lock built into the switching process. Note: The primary oscillator mode has three different submodes (XT, HS and EC) which are determined by the POSCMDx Configuration bits. While an application can switch to and from primary oscillator mode in software, it cannot switch between the different primary submodes without reprogramming the device. DS39897B-page 114 ENABLING CLOCK SWITCHING To enable clock switching, the FCKSM1 Configuration bit in CW2 must be programmed to `0'. (Refer to Section 25.1 "Configuration Bits" for further details.) If the FCKSM1 Configuration bit is unprogrammed (`1'), the clock switching function and Fail-Safe Clock Monitor function are disabled. This is the default setting. The NOSCx control bits (OSCCON<10:8>) do not control the clock selection when clock switching is disabled. However, the COSCx bits (OSCCON<14:12>) will reflect the clock source selected by the FNOSCx Configuration bits. The OSWEN control bit (OSCCON<0>) has no effect when clock switching is disabled. It is held at `0' at all times. Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 7.4.2 OSCILLATOR SWITCHING SEQUENCE A recommended code sequence for a clock switch includes the following: At a minimum, performing a clock switch requires this basic sequence: 1. 1. 2. 2. 3. 4. 5. If desired, read the COSCx bits (OSCCON<14:12>), to determine the current oscillator source. Perform the unlock sequence to allow a write to the OSCCON register high byte. Write the appropriate value to the NOSCx bits (OSCCON<10:8>) for the new oscillator source. Perform the unlock sequence to allow a write to the OSCCON register low byte. Set the OSWEN bit to initiate the oscillator switch. 3. 4. 5. Once the basic sequence is completed, the system clock hardware responds automatically as follows: 6. 1. 7. 2. 3. 4. 5. 6. The clock switching hardware compares the COSCx bits with the new value of the NOSCx bits. If they are the same, then the clock switch is a redundant operation. In this case, the OSWEN bit is cleared automatically and the clock switch is aborted. If a valid clock switch has been initiated, the LOCK (OSCCON<5>) and CF (OSCCON<3>) bits are cleared. The new oscillator is turned on by the hardware if it is not currently running. If a crystal oscillator must be turned on, the hardware will wait until the OST expires. If the new source is using the PLL, then the hardware waits until a PLL lock is detected (LOCK = 1). The hardware waits for 10 clock cycles from the new clock source and then performs the clock switch. The hardware clears the OSWEN bit to indicate a successful clock transition. In addition, the NOSCx bit values are transferred to the COSCx bits. The old clock source is turned off at this time, with the exception of LPRC (if WDT or FSCM are enabled) or SOSC (if SOSCEN remains set). Note 1: The processor will continue to execute code throughout the clock switching sequence. Timing sensitive code should not be executed during this time. 8. Disable interrupts during the OSCCON register unlock and write sequence. Execute the unlock sequence for the OSCCON high byte by writing 78h and 9Ah to OSCCON<15:8> in two back-to-back instructions. Write new oscillator source to the NOSCx bits in the instruction immediately following the unlock sequence. Execute the unlock sequence for the OSCCON low byte by writing 46h and 57h to OSCCON<7:0> in two back-to-back instructions. Set the OSWEN bit in the instruction immediately following the unlock sequence. Continue to execute code that is not clock sensitive (optional). Invoke an appropriate amount of software delay (cycle counting) to allow the selected oscillator and/or PLL to start and stabilize. Check to see if OSWEN is `0'. If it is, the switch was successful. If OSWEN is still set, then check the LOCK bit to determine the cause of failure. The core sequence for unlocking the OSCCON register and initiating a clock switch is shown in Example 7-1. EXAMPLE 7-1: BASIC CODE SEQUENCE FOR CLOCK SWITCHING ;Place the new oscillator selection in W0 ;OSCCONH (high byte) Unlock Sequence MOV #OSCCONH, w1 MOV #0x78, w2 MOV #0x9A, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Set new oscillator selection MOV.b WREG, OSCCONH ;OSCCONL (low byte) unlock sequence MOV #OSCCONL, w1 MOV #0x46, w2 MOV #0x57, w3 MOV.b w2, [w1] MOV.b w3, [w1] ;Start oscillator switch operation BSET OSCCON,#0 2: Direct clock switches between any primary oscillator mode with PLL and FRCPLL mode are not permitted. This applies to clock switches in either direction. In these instances, the application must switch to FRC mode as a transition clock source between the two PLL modes. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 115 PIC24FJ256GB110 FAMILY 7.5 Oscillator Modes and USB Operation TABLE 7-2: Because of the timing requirements imposed by USB, an internal clock of 48 MHz is required at all times while the USB module is enabled. Since this is well beyond the maximum CPU clock speed, a method is provided to internally generate both the USB and system clocks from a single oscillator source. PIC24FJ256GB110 family devices use the same clock structure as other PIC24FJ devices, but include a two-branch PLL system to generate the two clock signals. The USB PLL block is shown in Figure 7-2. In this system, the input from the primary oscillator is divided down by a PLL prescaler to generate a 4 MHz output. This is used to drive an on-chip 96 MHz PLL frequency multiplier to drive the two clock branches. One branch uses a fixed divide-by-2 frequency divider to generate the 48 MHz USB clock. The other branch uses a fixed divide-by-3 frequency divider and configurable PLL prescaler/divider to generate a range of system clock frequencies. The CPDIV bits select the system clock speed; available clock options are listed in Table 7-2. FIGURE 7-2: MCU Clock Division (CPDIV1:CPDIV0) Microcontroller Clock Frequency None (00) 32 MHz /2 (01) 16 MHz /4 (10) 8 MHz /8 (11) 4 MHz TABLE 7-3: Input Oscillator Frequency The USB PLL prescaler does not automatically sense the incoming oscillator frequency. The user must manually configure the PLL divider to generate the required 4 MHz output, using the PLLDIV2:PLLDIV0 Configuration bits. This limits the choices for primary oscillator frequency to a total of 8 possibilities, shown in Table 7-3. SYSTEM CLOCK OPTIONS DURING USB OPERATION VALID PRIMARY OSCILLATOR CONFIGURATIONS FOR USB OPERATIONS Clock Mode PLL Division (PLLDIV2: PLLDIV0) 48 MHz ECPLL /12 (111) 40 MHz ECPLL /10 (110) 24 MHz HSPLL, ECPLL /6 (101) 20 MHz HSPLL, ECPLL /5 (100) 16 MHz HSPLL, ECPLL /4 (011) 12 MHz HSPLL, ECPLL /3 (010) 8 MHz HSPLL, ECPLL /2 (001) 4 MHz HSPLL, ECPLL, XTPLL /1 (000) USB PLL BLOCK PLLDIV2:PLLDIV0 Input from FRC (4 MHz or 8 MHz) / 12 / 10 /6 /5 /4 /3 /2 /1 111 110 101 100 011 010 001 000 48 MHz Clock for USB Module /2 4 MHz 96 MHz PLL /3 32 MHz PLL Prescaler Input from POSC PLL Prescaler FNOSC2:FNOSC0 /8 /4 /2 /1 11 10 01 PLL Output for System Clock 00 CPDIV1:CPDIV0 DS39897B-page 116 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 7.5.1 7.6 CONSIDERATIONS FOR USB OPERATION When using the USB On-The-Go module in PIC24FJ256GB110 family devices, users must always observe these rules in configuring the system clock: * For USB operation, the selected clock source (EC, HS or XT) must meet the USB clock tolerance requirements. * The Primary Oscillator/PLL modes are the only oscillator configurations that permit USB operation. There is no provision to provide a separate external clock source to the USB module. * While the FRCPLL Oscillator mode is available in these devices, it should never be used for USB applications. FRCPLL mode is still available when the application is not using the USB module. However, the user must always ensure that the FRC source is configured to provide a frequency of 4 MHz or 8 MHz (RCDIV2:RCDIV0 = 001 or 000), and that the USB PLL prescaler is configured appropriately. * All other oscillator modes are available; however, USB operation is not possible when these modes are selected. They may still be useful in cases where other power levels of operation are desirable and the USB module is not needed (e.g., the application is sleeping and waiting for bus attachment). (c) 2008 Microchip Technology Inc. Reference Clock Output In addition to the CLKO output (FOSC/2) available in certain oscillator modes, the device clock in the PIC24FJ256GB110 family devices can also be configured to provide a reference clock output signal to a port pin. This feature is available in all oscillator configurations and allows the user to select a greater range of clock submultiples to drive external devices in the application. This reference clock output is controlled by the REFOCON register (Register 7-4). Setting the ROEN bit (REFOCON<15>) makes the clock signal available on the REFO pin. The RODIV bits (REFOCON<11:8>) enable the selection of 16 different clock divider options. The ROSSLP and ROSEL bits (REFOCON<13:12>) control the availability of the reference output during Sleep mode. The ROSEL bit determines if the oscillator on OSC1 and OSC2, or the current system clock source, is used for the reference clock output. The ROSSLP bit determines if the reference source is available on REFO when the device is in Sleep mode. To use the reference clock output in Sleep mode, both the ROSSLP and ROSEL bits must be set. The device clock must also be configured for one of the primary modes (EC, HS or XT); otherwise, if the POSCEN bit is not also set, the oscillator on OSC1 and OSC2 will be powered down when the device enters Sleep mode. Clearing the ROSEL bit allows the reference output frequency to change as the system clock changes during any clock switches. Preliminary DS39897B-page 117 PIC24FJ256GB110 FAMILY REGISTER 7-4: REFOCON: REFERENCE OSCILLATOR CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ROEN -- ROSSLP ROSEL RODIV3 RODIV2 RODIV1 RODIV0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 ROEN: Reference Oscillator Output Enable bit 1 = Reference oscillator enabled on REFO pin 0 = Reference oscillator disabled bit 14 Unimplemented: Read as `0' bit 13 ROSSLP: Reference Oscillator Output Stop in Sleep bit 1 = Reference oscillator continues to run in Sleep 0 = Reference oscillator is disabled in Sleep bit 12 ROSEL: Reference Oscillator Source Select bit 1 = Primary oscillator used as the base clock. Note that the crystal oscillator must be enabled using the FOSC2:FOSC0 bits; crystal maintains the operation in Sleep mode. 0 = System clock used as the base clock; base clock reflects any clock switching of the device bit 11-8 RODIV3:RODIV0: Reference Oscillator Divisor Select bits 1111 = Base clock value divided by 32,768 1110 = Base clock value divided by 16,384 1101 = Base clock value divided by 8,192 1100 = Base clock value divided by 4,096 1011 = Base clock value divided by 2,048 1010 = Base clock value divided by 1,024 1001 = Base clock value divided by 512 1000 = Base clock value divided by 256 0111 = Base clock value divided by 128 0110 = Base clock value divided by 64 0101 = Base clock value divided by 32 0100 = Base clock value divided by 16 0011 = Base clock value divided by 8 0010 = Base clock value divided by 4 0001 = Base clock value divided by 2 0000 = Base clock value bit 7-0 Unimplemented: Read as `0' DS39897B-page 118 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 8.0 Note: POWER-SAVING FEATURES This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 10. Power-Saving Features" (DS39698). The PIC24FJ256GB110 family of devices provides the ability to manage power consumption by selectively managing clocking to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. All PIC24F devices manage power consumption in four different ways: * * * * Clock frequency Instruction-based Sleep and Idle modes Software controlled Doze mode Selective peripheral control in software Combinations of these methods can be used to selectively tailor an application's power consumption, while still maintaining critical application features, such as timing-sensitive communications. 8.1 Clock Frequency and Clock Switching PIC24F devices allow for a wide range of clock frequencies to be selected under application control. If the system clock configuration is not locked, users can choose low-power or high-precision oscillators by simply changing the NOSC bits. The process of changing a system clock during operation, as well as limitations to the process, are discussed in more detail in Section 7.0 "Oscillator Configuration". 8.2 Instruction-Based Power-Saving Modes Sleep and Idle modes can be exited as a result of an enabled interrupt, WDT time-out or a device Reset. When the device exits these modes, it is said to "wake-up". Note: 8.2.1 SLEEP_MODE and IDLE_MODE are constants defined in the assembler include file for the selected device. SLEEP MODE Sleep mode has these features: * The system clock source is shut down. If an on-chip oscillator is used, it is turned off. * The device current consumption will be reduced to a minimum provided that no I/O pin is sourcing current. * The Fail-Safe Clock Monitor does not operate during Sleep mode since the system clock source is disabled. * The LPRC clock will continue to run in Sleep mode if the WDT is enabled. * The WDT, if enabled, is automatically cleared prior to entering Sleep mode. * Some device features or peripherals may continue to operate in Sleep mode. This includes items such as the input change notification on the I/O ports, or peripherals that use an external clock input. Any peripheral that requires the system clock source for its operation will be disabled in Sleep mode. The device will wake-up from Sleep mode on any of the these events: * On any interrupt source that is individually enabled * On any form of device Reset * On a WDT time-out On wake-up from Sleep, the processor will restart with the same clock source that was active when Sleep mode was entered. PIC24F devices have two special power-saving modes that are entered through the execution of a special PWRSAV instruction. Sleep mode stops clock operation and halts all code execution; Idle mode halts the CPU and code execution, but allows peripheral modules to continue operation. The assembly syntax of the PWRSAV instruction is shown in Example 8-1. EXAMPLE 8-1: PWRSAV PWRSAV PWRSAV INSTRUCTION SYNTAX #SLEEP_MODE #IDLE_MODE (c) 2008 Microchip Technology Inc. ; Put the device into SLEEP mode ; Put the device into IDLE mode Preliminary DS39897B-page 119 PIC24FJ256GB110 FAMILY 8.2.2 IDLE MODE Idle mode has these features: * The CPU will stop executing instructions. * The WDT is automatically cleared. * The system clock source remains active. By default, all peripheral modules continue to operate normally from the system clock source, but can also be selectively disabled (see Section 8.4 "Selective Peripheral Module Control"). * If the WDT or FSCM is enabled, the LPRC will also remain active. The device will wake from Idle mode on any of these events: * Any interrupt that is individually enabled. * Any device Reset. * A WDT time-out. On wake-up from Idle, the clock is reapplied to the CPU and instruction execution begins immediately, starting with the instruction following the PWRSAV instruction or the first instruction in the ISR. 8.2.3 INTERRUPTS COINCIDENT WITH POWER SAVE INSTRUCTIONS Any interrupt that coincides with the execution of a PWRSAV instruction will be held off until entry into Sleep or Idle mode has completed. The device will then wake-up from Sleep or Idle mode. 8.3 Doze Mode Generally, changing clock speed and invoking one of the power-saving modes are the preferred strategies for reducing power consumption. There may be circumstances, however, where this is not practical. For example, it may be necessary for an application to maintain uninterrupted synchronous communication, even while it is doing nothing else. Reducing system clock speed may introduce communication errors, while using a power-saving mode may stop communications completely. Doze mode is a simple and effective alternative method to reduce power consumption while the device is still executing code. In this mode, the system clock continues to operate from the same source and at the same speed. Peripheral modules continue to be clocked at the same speed while the CPU clock speed is reduced. Synchronization between the two clock domains is maintained, allowing the peripherals to access the SFRs while the CPU executes code at a slower rate. Doze mode is enabled by setting the DOZEN bit (CLKDIV<11>). The ratio between peripheral and core clock speed is determined by the DOZE2:DOZE0 bits (CLKDIV<14:12>). There are eight possible configurations, from 1:1 to 1:256, with 1:1 being the default. DS39897B-page 120 It is also possible to use Doze mode to selectively reduce power consumption in event driven applications. This allows clock sensitive functions, such as synchronous communications, to continue without interruption while the CPU Idles, waiting for something to invoke an interrupt routine. Enabling the automatic return to full-speed CPU operation on interrupts is enabled by setting the ROI bit (CLKDIV<15>). By default, interrupt events have no effect on Doze mode operation. 8.4 Selective Peripheral Module Control Idle and Doze modes allow users to substantially reduce power consumption by slowing or stopping the CPU clock. Even so, peripheral modules still remain clocked and thus consume power. There may be cases where the application needs what these modes do not provide: the allocation of power resources to CPU processing with minimal power consumption from the peripherals. PIC24F devices address this requirement by allowing peripheral modules to be selectively disabled, reducing or eliminating their power consumption. This can be done with two control bits: * The Peripheral Enable bit, generically named, "XXXEN", located in the module's main control SFR. * The Peripheral Module Disable (PMD) bit, generically named, "XXXMD", located in one of the PMD control registers. Both bits have similar functions in enabling or disabling its associated module. Setting the PMD bit for a module disables all clock sources to that module, reducing its power consumption to an absolute minimum. In this state, the control and status registers associated with the peripheral will also be disabled, so writes to those registers will have no effect and read values will be invalid. Many peripheral modules have a corresponding PMD bit. In contrast, disabling a module by clearing its XXXEN bit disables its functionality, but leaves its registers available to be read and written to. This reduces power consumption, but not by as much as setting the PMD bit does. Most peripheral modules have an enable bit; exceptions include input capture, output compare and RTCC. To achieve more selective power savings, peripheral modules can also be selectively disabled when the device enters Idle mode. This is done through the control bit of the generic name format, "XXXIDL". By default, all modules that can operate during Idle mode will do so. Using the disable on Idle feature allows further reduction of power consumption during Idle mode, enhancing power savings for extremely critical power applications. Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 9.0 Note: I/O PORTS peripheral that shares the same pin. Figure 9-1 shows how ports are shared with other peripherals and the associated I/O pin to which they are connected. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 12. I/O Ports with Peripheral Pin Select (PPS)" (DS39711). All of the device pins (except VDD, VSS, MCLR and OSCI/CLKI) are shared between the peripherals and the parallel I/O ports. All I/O input ports feature Schmitt Trigger inputs for improved noise immunity. 9.1 Parallel I/O (PIO) Ports A parallel I/O port that shares a pin with a peripheral is, in general, subservient to the peripheral. The peripheral's output buffer data and control signals are provided to a pair of multiplexers. The multiplexers select whether the peripheral or the associated port has ownership of the output data and control signals of the I/O pin. The logic also prevents "loop through", in which a port's digital output can drive the input of a FIGURE 9-1: When a peripheral is enabled and the peripheral is actively driving an associated pin, the use of the pin as a general purpose output pin is disabled. The I/O pin may be read, but the output driver for the parallel port bit will be disabled. If a peripheral is enabled, but the peripheral is not actively driving a pin, that pin may be driven by a port. All port pins have three registers directly associated with their operation as digital I/O. The Data Direction register (TRISx) determines whether the pin is an input or an output. If the data direction bit is a `1', then the pin is an input. All port pins are defined as inputs after a Reset. Reads from the Output Latch register (LATx), read the latch. Writes to the latch, write the latch. Reads from the port (PORTx), read the port pins, while writes to the port pins, write the latch. Any bit and its associated data and control registers that are not valid for a particular device will be disabled. That means the corresponding LATx and TRISx registers and the port pin will read as zeros. BLOCK DIAGRAM OF A TYPICAL SHARED PORT STRUCTURE Peripheral Module Output Multiplexers Peripheral Input Data Peripheral Module Enable Peripheral Output Enable Peripheral Output Data PIO Module WR TRIS Output Enable 0 1 Output Data 0 Read TRIS Data Bus I/O 1 D Q I/O Pin CK TRIS Latch D WR LAT + WR PORT Q CK Data Latch Read LAT Input Data Read PORT (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 121 PIC24FJ256GB110 FAMILY 9.1.1 9.3 OPEN-DRAIN CONFIGURATION In addition to the PORT, LAT and TRIS registers for data control, each port pin can also be individually configured for either digital or open-drain output. This is controlled by the Open-Drain Control register, ODCx, associated with each port. Setting any of the bits configures the corresponding pin to act as an open-drain output. The open-drain feature allows the generation of outputs higher than VDD (e.g., 5V) on any desired digital only pins by using external pull-up resistors. The maximum open-drain voltage allowed is the same as the maximum VIH specification. 9.2 Configuring Analog Port Pins The AD1PCFGL and TRIS registers control the operation of the A/D port pins. Setting a port pin as an analog input also requires that the corresponding TRIS bit be set. If the TRIS bit is cleared (output), the digital output level (VOH or VOL) will be converted. When reading the PORT register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will not convert an analog input. Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. 9.2.1 I/O PORT WRITE/READ TIMING One instruction cycle is required between a port direction change or port write operation and a read operation of the same port. Typically, this instruction would be a NOP. EXAMPLE 9-1: MOV MOV NOP BTSS 0xFF00, W0 W0, TRISBB PORTB, #13 DS39897B-page 122 Input Change Notification The input change notification function of the I/O ports allows the PIC24FJ256GB110 family of devices to generate interrupt requests to the processor in response to a change of state on selected input pins. This feature is capable of detecting input change of states even in Sleep mode, when the clocks are disabled. Depending on the device pin count, there are up to 81 external inputs that may be selected (enabled) for generating an interrupt request on a change of state. Registers CNEN1 through CNEN6 contain the interrupt enable control bits for each of the CN input pins. Setting any of these bits enables a CN interrupt for the corresponding pins. Each CN pin has a both a weak pull-up and a weak pull-down connected to it. The pull-ups act as a current source that is connected to the pin, while the pull-downs act as a current sink that is connected to the pin. These eliminate the need for external resistors when push button or keypad devices are connected. The pull-ups and pull-downs are separately enabled using the CNPU1 through CNPU6 registers (for pull-ups) and the CNPD1 through CNPD6 registers (for pull-downs). Each CN pin has individual control bits for its pull-up and pull-down. Setting a control bit enables the weak pull-up or pull-down for the corresponding pin. When the internal pull-up is selected, the pin pulls up to VDD - 0.7V (typical). Make sure that there is no external pull-up source when the internal pull-ups are enabled, as the voltage difference can cause a current path. Note: Pull-ups on change notification pins should always be disabled whenever the port pin is configured as a digital output. PORT WRITE/READ EXAMPLE ; ; ; ; Configure PORTB<15:8> as inputs and PORTB<7:0> as outputs Delay 1 cycle Next Instruction Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 9.4 Peripheral Pin Select 9.4.2 A major challenge in general purpose devices is providing the largest possible set of peripheral features while minimizing the conflict of features on I/O pins. In an application that needs to use more than one peripheral multiplexed on a single pin, inconvenient workarounds in application code or a complete redesign may be the only option. The peripheral pin select feature provides an alternative to these choices by enabling the user's peripheral set selection and their placement on a wide range of I/O pins. By increasing the pinout options available on a particular device, users can better tailor the microcontroller to their entire application, rather than trimming the application to fit the device. The peripheral pin select feature operates over a fixed subset of digital I/O pins. Users may independently map the input and/or output of any one of many digital peripherals to any one of these I/O pins. Peripheral pin select is performed in software and generally does not require the device to be reprogrammed. Hardware safeguards are included that prevent accidental or spurious changes to the peripheral mapping once it has been established. 9.4.1 AVAILABLE PINS The peripheral pin select feature is used with a range of up to 44 pins, depending on the particular device and its pin count. Pins that support the peripheral pin select feature include the designation "RPn" or "RPIn" in their full pin designation, where "n" is the remappable pin number. "RP" is used to designate pins that support both remappable input and output functions, while "RPI" indicates pins that support remappable input functions only. PIC24FJ256GB110 family devices support a larger number of remappable input only pins than remappable input/output pins. In this device family, there are up to 32 remappable input/output pins, depending on the pin count of the particular device selected; these are numbered RP0 through RP31. Remappable input only pins are numbered above this range, from RPI32 to RPI43 (or the upper limit for that particular device). AVAILABLE PERIPHERALS The peripherals managed by the peripheral pin select are all digital only peripherals. These include general serial communications (UART and SPI), general purpose timer clock inputs, timer related peripherals (input capture and output compare) and external interrupt inputs. Also included are the outputs of the comparator module, since these are discrete digital signals. Peripheral pin select is not available for I2CTM change notification inputs, RTCC alarm outputs or peripherals with analog inputs. A key difference between pin select and non pin select peripherals is that pin select peripherals are not associated with a default I/O pin. The peripheral must always be assigned to a specific I/O pin before it can be used. In contrast, non pin select peripherals are always available on a default pin, assuming that the peripheral is active and not conflicting with another peripheral. 9.4.2.1 Peripheral Pin Select Function Priority When a pin selectable peripheral is active on a given I/O pin, it takes priority over all other digital I/O and digital communication peripherals associated with the pin. Priority is given regardless of the type of peripheral that is mapped. Pin select peripherals never take priority over any analog functions associated with the pin. 9.4.3 CONTROLLING PERIPHERAL PIN SELECT Peripheral pin select features are controlled through two sets of Special Function Registers: one to map peripheral inputs, and one to map outputs. Because they are separately controlled, a particular peripheral's input and output (if the peripheral has both) can be placed on any selectable function pin without constraint. The association of a peripheral to a peripheral selectable pin is handled in two different ways, depending on if an input or an output is being mapped. See Table 1-4 for a summary of pinout options in each package offering. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 123 PIC24FJ256GB110 FAMILY 9.4.3.1 Input Mapping The inputs of the peripheral pin select options are mapped on the basis of the peripheral; that is, a control register associated with a peripheral dictates the pin it will be mapped to. The RPINRx registers are used to configure peripheral input mapping (see Register 9-1 through Register 9-21). Each register contains two sets TABLE 9-1: of 6-bit fields, with each set associated with one of the pin selectable peripherals. Programming a given peripheral's bit field with an appropriate 6-bit value maps the RPn pin with that value to that peripheral. For any given device, the valid range of values for any of the bit fields corresponds to the maximum number of peripheral pin selections supported by the device. SELECTABLE INPUT SOURCES (MAPS INPUT TO FUNCTION)(1) Function Name Register Function Mapping Bits External Interrupt 1 External Interrupt 2 INT1 INT2 RPINR0 RPINR1 INT1R5:INT1R0 INT2R5:INT2R0 External Interrupt 3 External Interrupt 4 INT3 INT4 RPINR1 RPINR2 INT3R5:INT3R0 INT4R5:INT4R0 Input Capture 1 Input Capture 2 IC1 IC2 RPINR7 RPINR7 IC1R5:IC1R0 IC2R5:IC2R0 Input Capture 3 Input Capture 4 IC3 IC4 RPINR8 RPINR8 IC3R5:IC3R0 IC4R5:IC4R0 Input Capture 5 Input Capture 6 IC5 IC6 RPINR9 RPINR9 IC5R5:IC5R0 IC6R5:IC6R0 Input Capture 7 Input Capture 8 IC7 IC8 RPINR10 RPINR10 IC7R5:IC7R0 IC8R5:IC8R0 Input Capture 9 Output Compare Fault A IC9 OCFA RPINR15 RPINR11 IC9R5:IC9R0 OCFAR5:OCFAR0 Output Compare Fault B SPI1 Clock Input OCFB SCK1IN RPINR11 RPINR20 OCFBR5:OCFBR0 SCK1R5:SCK1R0 SPI1 Data Input SPI1 Slave Select Input SDI1 SS1IN RPINR20 RPINR21 SDI1R5:SDI1R0 SS1R5:SS1R0 SPI2 Clock Input SPI2 Data Input SCK2IN SDI2 RPINR22 RPINR22 SCK2R5:SCK2R0 SDI2R5:SDI2R0 SPI2 Slave Select Input SPI3 Clock Input SS2IN SCK3IN RPINR23 RPINR23 SS2R5:SS2R0 SCK3R5:SCK3R0 SPI3 Data Input SPI3 Slave Select Input SDI3 SS3IN RPINR28 RPINR29 SDI3R5:SDI3R0 SS3R5:SS3R0 Timer1 External Clock Timer2 External Clock T1CK T2CK RPINR2 RPINR3 T1CKR5:T1CKR0 T2CKR5:T2CKR0 Timer3 External Clock Timer4 External Clock T3CK T4CK RPINR3 RPINR4 T3CKR5:T3CKR0 T4CKR5:T4CKR0 Input Name Timer5 External Clock T5CK RPINR4 T5CKR5:T5CKR0 UART1 Clear To Send UART1 Receive U1CTS U1RX RPINR18 RPINR18 U1CTSR5:U1CTSR0 U1RXR5:U1RXR0 UART2 Clear To Send UART2 Receive U2CTS U2RX RPINR19 RPINR19 U2CTSR5:U2CTSR0 U2RXR5:U2RXR0 UART3 Clear To Send U3CTS RPINR21 U3CTSR5:U3CTSR0 U3RX RPINR17 U3RXR5:U3RXR0 U4CTS U4RX RPINR27 RPINR27 U4CTSR5:U4CTSR0 U4RXR5:U4RXR0 UART3 Receive UART4 Clear To Send UART4 Receive Note 1: Unless otherwise noted, all inputs use the Schmitt Trigger input buffers. DS39897B-page 124 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 9.4.3.2 Output Mapping corresponds to one of the peripherals and that peripheral's output is mapped to the pin (see Table 9-2). In contrast to inputs, the outputs of the peripheral pin select options are mapped on the basis of the pin. In this case, a control register associated with a particular pin dictates the peripheral output to be mapped. The RPORx registers are used to control output mapping. Each register contains two 6-bit fields, with each field being associated with one RPn pin (see Register 9-22 through Register 9-37). The value of the bit field TABLE 9-2: Because of the mapping technique, the list of peripherals for output mapping also includes a null value of `000000'. This permits any given pin to remain disconnected from the output of any of the pin selectable peripherals. SELECTABLE OUTPUT SOURCES (MAPS FUNCTION TO OUTPUT) Output Function Number(1) Function Output Name 0 NULL(2) Null 1 C1OUT Comparator 1 Output 2 C2OUT Comparator 2 Output 3 U1TX UART1 Transmit 4 U1RTS 5 U2TX (3) UART1 Request To Send UART2 Transmit UART2 Request To Send 6 U2RTS 7 SDO1 8 SCK1OUT SPI1 Clock Output 9 SS1OUT SPI1 Slave Select Output SPI1 Data Output 10 SDO2 SPI2 Data Output 11 SCK2OUT SPI2 Clock Output 12 SS2OUT SPI2 Slave Select Output 18 OC1 Output Compare 1 19 OC2 Output Compare 2 20 OC3 Output Compare 3 21 OC4 Output Compare 4 22 OC5 Output Compare 5 23 OC6 Output Compare 6 24 OC7 Output Compare 7 25 OC8 Output Compare 8 28 U3TX 29 Note 1: 2: 3: (3) U3RTS (3) UART3 Transmit UART3 Request To Send 30 U4TX UART4 Transmit 31 U4RTS(3) UART4 Request To Send 32 SDO3 SPI3 Data Output 33 SCK3OUT SPI3 Clock Output 34 SS3OUT SPI3 Slave Select Output 35 OC9 Output Compare 9 37-63 (unused) NC Setting the RPORx register with the listed value assigns that output function to the associated RPn pin. The NULL function is assigned to all RPn outputs at device Reset and disables the RPn output function. IrDA(R) BCLK functionality uses this output. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 125 PIC24FJ256GB110 FAMILY 9.4.3.3 Mapping Limitations 9.4.4.1 The control schema of the peripheral pin select is extremely flexible. Other than systematic blocks that prevent signal contention caused by two physical pins being configured as the same functional input or two functional outputs configured as the same pin, there are no hardware enforced lock outs. The flexibility extends to the point of allowing a single input to drive multiple peripherals or a single functional output to drive multiple output pins. 9.4.3.4 Mapping Exceptions for PIC24FJ256GB110 Family Devices Although the PPS registers theoretically allow for up to 64 remappable I/O pins, not all of these are implemented in all devices. For PIC24FJ256GB110 family devices, the maximum number of remappable pins available are 44, which includes 12 input only pins. In addition, some pins in the RP and RPI sequences are unimplemented in lower pin count devices. The differences in available remappable pins are summarized in Table 9-3. When developing applications that use remappable pins, users should also keep these things in mind: * For the RPINRx registers, bit combinations corresponding to an unimplemented pin for a particular device are treated as invalid; the corresponding module will not have an input mapped to it. For all PIC24FJ256GB110 family devices, this includes all values greater than 43 (`101011'). * For RPORx registers, the bit fields corresponding to an unimplemented pin will also be unimplemented. Writing to these fields will have no effect. 9.4.4 Because peripheral remapping can be changed during run time, some restrictions on peripheral remapping are needed to prevent accidental configuration changes. PIC24F devices include three features to prevent alterations to the peripheral map: * Control register lock sequence * Continuous state monitoring * Configuration bit remapping lock TABLE 9-3: Under normal operation, writes to the RPINRx and RPORx registers are not allowed. Attempted writes will appear to execute normally, but the contents of the registers will remain unchanged. To change these registers, they must be unlocked in hardware. The register lock is controlled by the IOLOCK bit (OSCCON<6>). Setting IOLOCK prevents writes to the control registers; clearing IOLOCK allows writes. To set or clear IOLOCK, a specific command sequence must be executed: 1. 2. 3. Write 46h to OSCCON<7:0>. Write 57h to OSCCON<7:0>. Clear (or set) IOLOCK as a single operation. Unlike the similar sequence with the oscillator's LOCK bit, IOLOCK remains in one state until changed. This allows all of the peripheral pin selects to be configured with a single unlock sequence followed by an update to all control registers, then locked with a second lock sequence. 9.4.4.2 Continuous State Monitoring In addition to being protected from direct writes, the contents of the RPINRx and RPORx registers are constantly monitored in hardware by shadow registers. If an unexpected change in any of the registers occurs (such as cell disturbances caused by ESD or other external events), a Configuration Mismatch Reset will be triggered. 9.4.4.3 CONTROLLING CONFIGURATION CHANGES Control Register Lock Configuration Bit Pin Select Lock As an additional level of safety, the device can be configured to prevent more than one write session to the RPINRx and RPORx registers. The IOL1WAY (CW2<4>) Configuration bit blocks the IOLOCK bit from being cleared after it has been set once. If IOLOCK remains set, the register unlock procedure will not execute and the Peripheral Pin Select Control registers cannot be written to. The only way to clear the bit and re-enable peripheral remapping is to perform a device Reset. In the default (unprogrammed) state, IOL1WAY is set, restricting users to one write session. Programming IOL1WAY allows users unlimited access (with the proper use of the unlock sequence) to the peripheral pin select registers. REMAPPABLE PIN EXCEPTIONS FOR PIC24FJ256GB110 FAMILY DEVICES Device Pin Count RP Pins (I/O) RPI Pins Total Unimplemented Total Unimplemented 28 RP5, RP15, RP30, RP31 1 RPI32-36, RPI38-43 80-pin 31 RP31 9 RPI32, RPI39, RPI41 100-pin 32 -- 12 -- 64-pin DS39897B-page 126 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 9.4.5 CONSIDERATIONS FOR PERIPHERAL PIN SELECTION The ability to control peripheral pin selection introduces several considerations into application design that could be overlooked. This is particularly true for several common peripherals that are available only as remappable peripherals. The main consideration is that the peripheral pin selects are not available on default pins in the device's default (Reset) state. Since all RPINRx registers reset to `111111' and all RPORx registers reset to `000000', all peripheral pin select inputs are tied to VSS and all peripheral pin select outputs are disconnected. Note: In tying peripheral pin select inputs to RP63, RP63 does not have to exist on a device for the registers to be reset to it. This situation requires the user to initialize the device with the proper peripheral configuration before any other application code is executed. Since the IOLOCK bit resets in the unlocked state, it is not necessary to execute the unlock sequence after the device has come out of Reset. For application safety, however, it is best to set IOLOCK and lock the configuration after writing to the control registers. Because the unlock sequence is timing critical, it must be executed as an assembly language routine in the same manner as changes to the oscillator configuration. If the bulk of the application is written in C or another high-level language, the unlock sequence should be performed by writing inline assembly. Choosing the configuration requires the review of all peripheral pin selects and their pin assignments, especially those that will not be used in the application. In all cases, unused pin-selectable peripherals should be disabled completely. Unused peripherals should have their inputs assigned to an unused RPn pin function. I/O pins with unused RPn functions should be configured with the null peripheral output. The assignment of a peripheral to a particular pin does not automatically perform any other configuration of the pin's I/O circuitry. In theory, this means adding a pin-selectable output to a pin may mean inadvertently driving an existing peripheral input when the output is driven. Users must be familiar with the behavior of other fixed peripherals that share a remappable pin and know when to enable or disable them. To be safe, fixed digital peripherals that share the same pin should be disabled when not in use. (c) 2008 Microchip Technology Inc. Along these lines, configuring a remappable pin for a specific peripheral does not automatically turn that feature on. The peripheral must be specifically configured for operation and enabled, as if it were tied to a fixed pin. Where this happens in the application code (immediately following device Reset and peripheral configuration or inside the main application routine) depends on the peripheral and its use in the application. A final consideration is that peripheral pin select functions neither override analog inputs, nor reconfigure pins with analog functions for digital I/O. If a pin is configured as an analog input on device Reset, it must be explicitly reconfigured as digital I/O when used with a peripheral pin select. Example 9-2 shows a configuration for bidirectional communication with flow control using UART1. The following input and output functions are used: * Input Functions: U1RX, U1CTS * Output Functions: U1TX, U1RTS EXAMPLE 9-2: CONFIGURING UART1 INPUT AND OUTPUT FUNCTIONS // Unlock Registers asm volatile ( "MOV #OSCCON, w1 "MOV #0x46, w2 "MOV #0x57, w3 "MOV.b w2, [w1] "MOV.b w3, [w1] "BCLR OSCCON,#6"); \n" \n" \n" \n" \n" // Configure Input Functions (Table 9-1)) // Assign U1RX To Pin RP0 RPINR18bits.U1RXR = 0; // Assign U1CTS To Pin RP1 RPINR18bits.U1CTSR = 1; // Configure Output Functions (Table 9-2) // Assign U1TX To Pin RP2 RPOR1bits.RP2R = 3; // Assign U1RTS To Pin RP3 RPOR1bits.RP3R = 4; // Lock Registers asm volatile ( "MOV "MOV "MOV "MOV.b "MOV.b "BSET Preliminary #OSCCON, w1 #0x46, w2 #0x57, w3 w2, <w1> w3, <w1> OSCCON, #6" \n" \n" \n" \n" \n" ); DS39897B-page 127 PIC24FJ256GB110 FAMILY 9.4.6 PERIPHERAL PIN SELECT REGISTERS Note: The PIC24FJ256GB110 family of devices implements a total of 37 registers for remappable peripheral configuration: * Input Remappable Peripheral Registers (21) * Output Remappable Peripheral Registers (16) REGISTER 9-1: Input and output register values can only be changed if IOLOCK (OSCCON<6>) = 0. See Section 9.4.4.1 "Control Register Lock" for a specific command sequence. RPINR0: PERIPHERAL PIN SELECT INPUT REGISTER 0 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- INT1R5 INT1R4 INT1R3 INT1R2 INT1R1 INT1R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 INT1R5:INT1R0: Assign External Interrupt 1 (INT1) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as `0' REGISTER 9-2: RPINR1: PERIPHERAL PIN SELECT INPUT REGISTER 1 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- INT3R5 INT3R4 INT3R3 INT3R2 INT3R1 INT3R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- INT2R5 INT2R4 INT2R3 INT2R2 INT2R1 INT2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 INT3R5:INT3R0: Assign External Interrupt 3 (INT3) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 INT2R5:INT2R0: Assign External Interrupt 2 (INT2) to Corresponding RPn or RPIn Pin bits DS39897B-page 128 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 9-3: RPINR2: PERIPHERAL PIN SELECT INPUT REGISTER 2 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- T1CKR5 T1CKR4 T1CKR3 T1CKR2 T1CKR1 T1CKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- INT4R5 INT4R4 INT4R3 INT4R2 INT4R1 INT4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 T1CKR5:T1CKR0: Assign Timer1 External Clock (T1CK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 INT4R5:INT4R0: Assign External Interrupt 4 (INT4) to Corresponding RPn or RPIn Pin bits REGISTER 9-4: RPINR3: PERIPHERAL PIN SELECT INPUT REGISTER 3 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- T3CKR5 T3CKR4 T3CKR3 T3CKR2 T3CKR1 T3CKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- T2CKR5 T2CKR4 T2CKR3 T2CKR2 T2CKR1 T2CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 T3CKR5:T3CKR0: Assign Timer3 External Clock (T3CK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 T2CKR5:T2CKR0: Assign Timer2 External Clock (T2CK) to Corresponding RPn or RPIn Pin bits (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 129 PIC24FJ256GB110 FAMILY REGISTER 9-5: RPINR4: PERIPHERAL PIN SELECT INPUT REGISTER 4 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- T5CKR5 T5CKR4 T5CKR3 T5CKR2 T5CKR1 T5CKR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- T4CKR5 T4CKR4 T4CKR3 T4CKR2 T4CKR1 T4CKR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 T5CKR5:T5CKR0: Assign Timer5 External Clock (T5CK) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 T4CKR5:T4CKR0: Assign Timer4 External Clock (T4CK) to Corresponding RPn or RPIn Pin bits REGISTER 9-6: RPINR7: PERIPHERAL PIN SELECT INPUT REGISTER 7 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- IC2R5 IC2R4 IC2R3 IC2R2 IC2R1 IC2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- IC1R5 IC1R4 IC1R3 IC1R2 IC1R1 IC1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 IC2R5:IC2R0: Assign Input Capture 2 (IC2) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 IC1R5:IC1R0: Assign Input Capture 1 (IC1) to Corresponding RPn or RPIn Pin bits DS39897B-page 130 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 9-7: RPINR8: PERIPHERAL PIN SELECT INPUT REGISTER 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- IC4R5 IC4R4 IC4R3 IC4R2 IC4R1 IC4R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- IC3R5 IC3R4 IC3R3 IC3R2 IC3R1 IC3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 IC4R5:IC4R0: Assign Input Capture 4 (IC4) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 IC3R5:IC3R0: Assign Input Capture 3 (IC3) to Corresponding RPn or RPIn Pin bits REGISTER 9-8: RPINR9: PERIPHERAL PIN SELECT INPUT REGISTER 9 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- IC6R5 IC6R4 IC6R3 IC6R2 IC6R1 IC6R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- IC5R5 IC5R4 IC5R3 IC5R2 IC5R1 IC5R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 IC6R5:IC6R0: Assign Input Capture 6 (IC6) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 IC5R5:IC5R0: Assign Input Capture 5 (IC5) to Corresponding RPn or RPIn Pin bits (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 131 PIC24FJ256GB110 FAMILY REGISTER 9-9: RPINR10: PERIPHERAL PIN SELECT INPUT REGISTER 10 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- IC8R5 IC8R4 IC8R3 IC8R2 IC8R1 IC8R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- IC7R5 IC7R4 IC7R3 IC7R2 IC7R1 IC7R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 IC8R5:IC8R0: Assign Input Capture 8 (IC8) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 IC7R5:IC7R0: Assign Input Capture 7 (IC7) to Corresponding RPn or RPIn Pin bits REGISTER 9-10: RPINR11: PERIPHERAL PIN SELECT INPUT REGISTER 11 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- OCFBR5 OCFBR4 OCFBR3 OCFBR2 OCFBR1 OCFBR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- OCFAR5 OCFAR4 OCFAR3 OCFAR2 OCFAR1 OCFAR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 OCFBR5:OCFBR0: Assign Output Compare Fault B (OCFB) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 OCFAR5:OCFAR0: Assign Output Compare Fault A (OCFA) to Corresponding RPn or RPIn Pin bits DS39897B-page 132 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 9-11: RPINR15: PERIPHERAL PIN SELECT INPUT REGISTER 15 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- IC9R5 IC9R4 IC9R3 IC9R2 IC9R1 IC9R0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 IC9R5:IC9R0: Assign Input Capture 9 (IC9) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as `0' REGISTER 9-12: RPINR17: PERIPHERAL PIN SELECT INPUT REGISTER 17 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- U3RXR5 U3RXR4 U3RXR3 U3RXR2 U3RXR1 U3RXR0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 U3RXR5:U3RXR0: Assign UART3 Receive (U3RX) to Corresponding RPn or RPIn Pin bits bit 7-0 Unimplemented: Read as `0' (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 133 PIC24FJ256GB110 FAMILY REGISTER 9-13: RPINR18: PERIPHERAL PIN SELECT INPUT REGISTER 18 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- U1CTSR5 U1CTSR4 U1CTSR3 U1CTSR2 U1CTSR1 U1CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- U1RXR5 U1RXR4 U1RXR3 U1RXR2 U1RXR1 U1RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 U1CTSR5:U1CTSR0: Assign UART1 Clear to Send (U1CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 U1RXR5:U1RXR0: Assign UART1 Receive (U1RX) to Corresponding RPn or RPIn Pin bits REGISTER 9-14: RPINR19: PERIPHERAL PIN SELECT INPUT REGISTER 19 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- U2CTSR5 U2CTSR4 U2CTSR3 U2CTSR2 U2CTSR1 U2CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- U2RXR5 U2RXR4 U2RXR3 U2RXR2 U2RXR1 U2RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 U2CTSR5:U2CTSR0: Assign UART2 Clear to Send (U2CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 U2RXR5:U2RXR0: Assign UART2 Receive (U2RX) to Corresponding RPn or RPIn Pin bits DS39897B-page 134 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 9-15: RPINR20: PERIPHERAL PIN SELECT INPUT REGISTER 20 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- SCK1R5 SCK1R4 SCK1R3 SCK1R2 SCK1R1 SCK1R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- SDI1R5 SDI1R4 SDI1R3 SDI1R2 SDI1R1 SDI1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 SCK1R5:SCK1R0: Assign SPI1 Clock Input (SCK1IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 SDI1R5:SDI1R0: Assign SPI1 Data Input (SDI1) to Corresponding RPn or RPIn Pin bits REGISTER 9-16: RPINR21: PERIPHERAL PIN SELECT INPUT REGISTER 21 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- U3CTSR5 U3CTSR4 U3CTSR3 U3CTSR2 U3CTSR1 U3CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- SS1R5 SS1R4 SS1R3 SS1R2 SS1R1 SS1R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 U3CTSR5:U3CTSR0: Assign UART3 Clear to Send (U3CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 SS1R5:SS1R0: Assign SPI1 Slave Select Input (SS1IN) to Corresponding RPn or RPIn Pin bits (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 135 PIC24FJ256GB110 FAMILY REGISTER 9-17: RPINR22: PERIPHERAL PIN SELECT INPUT REGISTER 22 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- SCK2R5 SCK2R4 SCK2R3 SCK2R2 SCK2R1 SCK2R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- SDI2R5 SDI2R4 SDI2R3 SDI2R2 SDI2R1 SDI2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 SCK2R5:SCK2R0: Assign SPI2 Clock Input (SCK2IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 SDI2R5:SDI2R0: Assign SPI2 Data Input (SDI2) to Corresponding RPn or RPIn Pin bits REGISTER 9-18: RPINR23: PERIPHERAL PIN SELECT INPUT REGISTER 23 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- SS2R5 SS2R4 SS2R3 SS2R2 SS2R1 SS2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as `0' bit 5-0 SS2R5:SS2R0: Assign SPI2 Slave Select Input (SS2IN) to Corresponding RPn or RPIn Pin bits DS39897B-page 136 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 9-19: RPINR27: PERIPHERAL PIN SELECT INPUT REGISTER 27 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- U4CTSR5 U4CTSR4 U4CTSR3 U4CTSR2 U4CTSR1 U4CTSR0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- U4RXR5 U4RXR4 U4RXR3 U4RXR2 U4RXR1 U4RXR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 U4CTSR5:U4CTSR0: Assign UART4 Clear to Send (U4CTS) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 U4RXR5:U4RXR0: Assign UART4 Receive (U4RX) to Corresponding RPn or RPIn Pin bits REGISTER 9-20: RPINR28: PERIPHERAL PIN SELECT INPUT REGISTER 28 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- SCK3R5 SCK3R4 SCK3R3 SCK3R2 SCK3R1 SCK3R0 bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- SDI3R5 SDI3R4 SDI3R3 SDI3R2 SDI3R1 SDI3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 SCK3R5:SCK3R0: Assign SPI3 Clock Input (SCK3IN) to Corresponding RPn or RPIn Pin bits bit 7-6 Unimplemented: Read as `0' bit 5-0 SDI3R5:SDI3R0: Assign SPI3 Data Input (SDI3) to Corresponding RPn or RPIn Pin bits (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 137 PIC24FJ256GB110 FAMILY REGISTER 9-21: RPINR29: PERIPHERAL PIN SELECT INPUT REGISTER 29 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 U-0 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 R/W-1 -- -- SS3R5 SS3R4 SS3R3 SS3R2 SS3R1 SS3R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-6 Unimplemented: Read as `0' bit 5-0 SS3R5:SS3R0: Assign SPI3 Slave Select Input (SS31IN) to Corresponding RPn or RPIn Pin bits REGISTER 9-22: RPOR0: PERIPHERAL PIN SELECT OUTPUT REGISTER 0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP1R5 RP1R4 RP1R3 RP1R2 RP1R1 RP1R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP0R5 RP0R4 RP0R3 RP0R2 RP0R1 RP0R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP1R5:RP1R0: RP1 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP1 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP0R5:RP0R0: RP0 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP0 (see Table 9-2 for peripheral function numbers) DS39897B-page 138 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 9-23: RPOR1: PERIPHERAL PIN SELECT OUTPUT REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP3R5 RP3R4 RP3R3 RP3R2 RP3R1 RP3R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP2R5 RP2R4 RP2R3 RP2R2 RP2R1 RP2R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP3R5:RP3R0: RP3 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP3 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP2R5:RP2R0: RP2 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP2 (see Table 9-2 for peripheral function numbers) REGISTER 9-24: RPOR2: PERIPHERAL PIN SELECT OUTPUT REGISTER 2 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP5R5(1) RP5R4(1) RP5R3(1) RP5R2(1) RP5R1(1) RP5R0(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP4R5 RP4R4 RP4R3 RP4R2 RP4R1 RP4R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP5R5:RP5R0: RP5 Output Pin Mapping bits(1) Peripheral Output number n is assigned to pin RP5 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP4R5:RP4R0: RP4 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP4 (see Table 9-2 for peripheral function numbers) Note 1: Unimplemented in 64-pin devices; read as `0'. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 139 PIC24FJ256GB110 FAMILY REGISTER 9-25: RPOR3: PERIPHERAL PIN SELECT OUTPUT REGISTER 3 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP7R5 RP7R4 RP7R3 RP7R2 RP7R1 RP7R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP6R5 RP6R4 RP6R3 RP6R2 RP6R1 RP6R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP7R5:RP7R0: RP7 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP7 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP6R5:RP6R0: RP6 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP6 (see Table 9-2 for peripheral function numbers) REGISTER 9-26: RPOR4: PERIPHERAL PIN SELECT OUTPUT REGISTER 4 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP9R5 RP9R4 RP9R3 RP9R2 RP9R1 RP9R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP8R5 RP8R4 RP8R3 RP8R2 RP8R1 RP8R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP9R5:RP9R0: RP9 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP9 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP8R5:RP8R0: RP8 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP8 (see Table 9-2 for peripheral function numbers) DS39897B-page 140 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 9-27: RPOR5: PERIPHERAL PIN SELECT OUTPUT REGISTER 5 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP11R5 RP11R4 RP11R3 RP11R2 RP11R1 RP11R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP10R5 RP10R4 RP10R3 RP10R2 RP10R1 RP10R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP11R5:RP11R0: RP11 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP11 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP10R5:RP10R0: RP10 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP10 (see Table 9-2 for peripheral function numbers) REGISTER 9-28: RPOR6: PERIPHERAL PIN SELECT OUTPUT REGISTER 6 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP13R5 RP13R4 RP13R3 RP13R2 RP13R1 RP13R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP12R5 RP12R4 RP12R3 RP12R2 RP12R1 RP12R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP13R5:RP13R0: RP13 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP13 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP12R5:RP12R0: RP12 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP12 (see Table 9-2 for peripheral function numbers) (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 141 PIC24FJ256GB110 FAMILY REGISTER 9-29: U-0 -- RPOR7: PERIPHERAL PIN SELECT OUTPUT REGISTER 7 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- RP15R5(1) RP15R4(1) RP15R3(1) RP15R2(1) RP15R1(1) RP15R0(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP14R5 RP14R4 RP14R3 RP14R2 RP14R1 RP14R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP15R5:RP15R0: RP15 Output Pin Mapping bits(1) Peripheral Output number n is assigned to pin RP0 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP14R5:RP14R0: RP14 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP14 (see Table 9-2 for peripheral function numbers) Note 1: Unimplemented in 64-pin devices; read as `0'. REGISTER 9-30: RPOR8: PERIPHERAL PIN SELECT OUTPUT REGISTER 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP17R5 RP17R4 RP17R3 RP17R2 RP17R1 RP17R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP16R5 RP16R4 RP16R3 RP16R2 RP16R1 RP16R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP17R5:RP17R0: RP17 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP17 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP16R5:RP16R0: RP16 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP16 (see Table 9-2 for peripheral function numbers) DS39897B-page 142 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 9-31: RPOR9: PERIPHERAL PIN SELECT OUTPUT REGISTER 9 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP19R5 RP19R4 RP19R3 RP19R2 RP19R1 RP19R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP18R5 RP18R4 RP18R3 RP18R2 RP18R1 RP18R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP19R5:RP19R0: RP19 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP19 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP18R5:RP18R0: RP18 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP18 (see Table 9-2 for peripheral function numbers) REGISTER 9-32: RPOR10: PERIPHERAL PIN SELECT OUTPUT REGISTER 10 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP21R5 RP21R4 RP21R3 RP21R2 RP21R1 RP21R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP20R5 RP20R4 RP20R3 RP20R2 RP20R1 RP20R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP21R5:RP21R0: RP21 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP21 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP20R5:RP20R0: RP20 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP20 (see Table 9-2 for peripheral function numbers) (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 143 PIC24FJ256GB110 FAMILY REGISTER 9-33: RPOR11: PERIPHERAL PIN SELECT OUTPUT REGISTER 11 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP23R5 RP23R4 RP23R3 RP23R2 RP23R1 RP23R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP22R5 RP22R4 RP22R3 RP22R2 RP22R1 RP22R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP23R5:RP23R0: RP23 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP23 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP22R5:RP22R0: RP22 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP22 (see Table 9-2 for peripheral function numbers) REGISTER 9-34: RPOR12: PERIPHERAL PIN SELECT OUTPUT REGISTER 12 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP25R5 RP25R4 RP25R3 RP25R2 RP25R1 RP25R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP24R5 RP24R4 RP24R3 RP24R2 RP24R1 RP24R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP25R5:RP25R0: RP25 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP25 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP24R5:RP24R0: RP24 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP24 (see Table 9-2 for peripheral function numbers) DS39897B-page 144 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 9-35: RPOR13: PERIPHERAL PIN SELECT OUTPUT REGISTER 13 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP27R5 RP27R4 RP27R3 RP27R2 RP27R1 RP27R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP26R5 RP26R4 RP26R3 RP26R2 RP26R1 RP26R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP27R5:RP27R0: RP27 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP27 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP26R5:RP26R0: RP26 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP26 (see Table 9-2 for peripheral function numbers) REGISTER 9-36: RPOR14: PERIPHERAL PIN SELECT OUTPUT REGISTER 14 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP29R5 RP29R4 RP29R3 RP29R2 RP29R1 RP29R0 bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP28R5 RP28R4 RP28R3 RP28R2 RP28R1 RP28R0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP29R5:RP29R0: RP29 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP29 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP28R5:RP28R0: RP28 Output Pin Mapping bits Peripheral Output number n is assigned to pin RP28 (see Table 9-2 for peripheral function numbers) (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 145 PIC24FJ256GB110 FAMILY REGISTER 9-37: U-0 RPOR15: PERIPHERAL PIN SELECT OUTPUT REGISTER 15 U-0 -- -- R/W-0 (1) RP31R5 R/W-0 RP31R4 (1) R/W-0 RP31R3 (1) R/W-0 RP31R2 (1) R/W-0 RP31R1 R/W-0 (1) RP31R0(1) bit 15 bit 8 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- RP30R5(2) RP30R4(2) RP30R3(2) RP30R2(2) RP30R1(2) RP30R0(2) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13-8 RP31R5:RP31R0: RP31 Output Pin Mapping bits(1) Peripheral Output number n is assigned to pin RP31 (see Table 9-2 for peripheral function numbers) bit 7-6 Unimplemented: Read as `0' bit 5-0 RP30R5:RP30R0: RP30 Output Pin Mapping bits(2) Peripheral Output number n is assigned to pin RP30 (see Table 9-2 for peripheral function numbers) Note 1: 2: Unimplemented in 64-pin and 80-pin devices; read as `0'. Unimplemented in 64-pin devices; read as `0'. DS39897B-page 146 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 10.0 Note: TIMER1 Figure 10-1 presents a block diagram of the 16-bit timer module. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 14. Timers" (DS39704). To configure Timer1 for operation: 1. 2. 3. The Timer1 module is a 16-bit timer which can serve as the time counter for the Real-Time Clock (RTC), or operate as a free-running, interval timer/counter. Timer1 can operate in three modes: 4. 5. * 16-Bit Timer * 16-Bit Synchronous Counter * 16-Bit Asynchronous Counter 6. Set the TON bit (= 1). Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. Set the Clock and Gating modes using the TCS and TGATE bits. Set or clear the TSYNC bit to configure synchronous or asynchronous operation. Load the timer period value into the PR1 register. If interrupts are required, set the interrupt enable bit, T1IE. Use the priority bits, T1IP2:T1IP0, to set the interrupt priority. Timer1 also supports these features: * Timer Gate Operation * Selectable Prescaler Settings * Timer Operation during CPU Idle and Sleep modes * Interrupt on 16-Bit Period Register Match or Falling Edge of External Gate Signal FIGURE 10-1: 16-BIT TIMER1 MODULE BLOCK DIAGRAM TCKPS1:TCKPS0 SOSCO/ T1CK 1x SOSCEN SOSCI Gate Sync 01 TCY 00 Prescaler 1, 8, 64, 256 TGATE TCS TGATE Set T1IF 2 TON 1 Q D 0 Q CK Reset 0 TMR1 1 Equal Comparator Sync TSYNC PR1 (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 147 PIC24FJ256GB110 FAMILY REGISTER 10-1: T1CON: TIMER1 CONTROL REGISTER(1) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON -- TSIDL -- -- -- -- -- bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 R/W-0 U-0 -- TGATE TCKPS1 TCKPS0 -- TSYNC TCS -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 TON: Timer1 On bit 1 = Starts 16-bit Timer1 0 = Stops 16-bit Timer1 bit 14 Unimplemented: Read as `0' bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as `0' bit 6 TGATE: Timer1 Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS1:TCKPS0: Timer1 Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 Unimplemented: Read as `0' bit 2 TSYNC: Timer1 External Clock Input Synchronization Select bit When TCS = 1: 1 = Synchronize external clock input 0 = Do not synchronize external clock input When TCS = 0: This bit is ignored. bit 1 TCS: Timer1 Clock Source Select bit 1 = External clock from T1CK pin (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as `0' Note 1: x = Bit is unknown Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. DS39897B-page 148 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 11.0 Note: TIMER2/3 AND TIMER4/5 To configure Timer2/3 or Timer4/5 for 32-bit operation: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 14. Timers" (DS39704). The Timer2/3 and Timer4/5 modules are 32-bit timers, which can also be configured as four independent 16-bit timers with selectable operating modes. 1. 2. 3. 4. As 32-bit timers, Timer2/3 and Timer4/5 can each operate in three modes: Set the T32 bit (T2CON<3> or T4CON<3> = 1). Select the prescaler ratio for Timer2 or Timer4 using the TCKPS1:TCKPS0 bits. Set the Clock and Gating modes using the TCS and TGATE bits. If TCS is set to external clock, RPINRx (TxCK) must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. Load the timer period value. PR3 (or PR5) will contain the most significant word of the value while PR2 (or PR4) contains the least significant word. If interrupts are required, set the interrupt enable bit, T3IE or T5IE; use the priority bits, T3IP2:T3IP0 or T5IP2:T5IP0, to set the interrupt priority. Note that while Timer2 or Timer4 controls the timer, the interrupt appears as a Timer3 or Timer5 interrupt. Set the TON bit (= 1). * Two independent 16-bit timers with all 16-bit operating modes (except Asynchronous Counter mode) * Single 32-bit timer * Single 32-bit synchronous counter 5. They also support these features: 6. * * * * * The timer value, at any point, is stored in the register pair, TMR3:TMR2 (or TMR5:TMR4). TMR3 (TMR5) always contains the most significant word of the count, while TMR2 (TMR4) contains the least significant word. Timer Gate Operation Selectable Prescaler Settings Timer Operation during Idle and Sleep modes Interrupt on a 32-Bit Period Register Match ADC Event Trigger (Timer4/5 only) Individually, all four of the 16-bit timers can function as synchronous timers or counters. They also offer the features listed above, except for the ADC Event Trigger; this is implemented only with Timer5. The operating modes and enabled features are determined by setting the appropriate bit(s) in the T2CON, T3CON, T4CON and T5CON registers. T2CON and T4CON are shown in generic form in Register 11-1; T3CON and T5CON are shown in Register 11-2. For 32-bit timer/counter operation, Timer2 and Timer4 are the least significant word; Timer3 and Timer4 are the most significant word of the 32-bit timers. Note: For 32-bit operation, T3CON and T5CON control bits are ignored. Only T2CON and T4CON control bits are used for setup and control. Timer2 and Timer4 clock and gate inputs are utilized for the 32-bit timer modules, but an interrupt is generated with the Timer3 or Timer5 interrupt flags. (c) 2008 Microchip Technology Inc. To configure any of the timers for individual 16-bit operation: 1. 2. 3. 4. 5. 6. Preliminary Clear the T32 bit corresponding to that timer (T2CON<3> for Timer2 and Timer3 or T4CON<3> for Timer4 and Timer5). Select the timer prescaler ratio using the TCKPS1:TCKPS0 bits. Set the Clock and Gating modes using the TCS and TGATE bits. See Section 9.4 "Peripheral Pin Select" for more information. Load the timer period value into the PRx register. If interrupts are required, set the interrupt enable bit, TxIE; use the priority bits, TxIP2:TxIP0, to set the interrupt priority. Set the TON bit (TxCON<15> = 1). DS39897B-page 149 PIC24FJ256GB110 FAMILY FIGURE 11-1: TIMER2/3 AND TIMER4/5 (32-BIT) BLOCK DIAGRAM T2CK (T4CK) 1x Gate Sync 01 TCY 00 TCKPS1:TCKPS0 2 TON Prescaler 1, 8, 64, 256 TGATE(2) TGATE TCS(2) Set T3IF (T5IF) Q 1 Q 0 PR3 (PR5) ADC Event Trigger(3) Equal D CK PR2 (PR4) Comparator MSB LSB TMR3 (TMR5) Reset TMR2 (TMR4) Sync 16 Read TMR2 (TMR4) (1) Write TMR2 (TMR4)(1) 16 TMR3HLD (TMR5HLD) 16 Data Bus<15:0> Note 1: 2: 3: The 32-Bit Timer Configuration bit, T32, must be set for 32-bit timer/counter operation. All control bits are respective to the T2CON and T4CON registers. The timer clock input must be assigned to an available RPn pin before use. Please see Section 9.4 "Peripheral Pin Select" for more information. The ADC Event Trigger is available only on Timer 2/3 in 32-bit mode and Timer 3 in 16-bit mode. DS39897B-page 150 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY FIGURE 11-2: TIMER2 AND TIMER4 (16-BIT SYNCHRONOUS) BLOCK DIAGRAM T2CK (T4CK) 1x Gate Sync TON TCKPS1:TCKPS0 2 Prescaler 1, 8, 64, 256 01 00 TGATE TCS(1) TCY 1 Set T2IF (T4IF) 0 Reset Equal Q D Q CK TMR2 (TMR4) TGATE(1) Sync Comparator PR2 (PR4) Note 1: The timer clock input must be assigned to an available RPn pin before use. Please see Section 9.4 "Peripheral Pin Select" for more information. FIGURE 11-3: TIMER3 AND TIMER5 (16-BIT ASYNCHRONOUS) BLOCK DIAGRAM T3CK (T5CK) 1x Sync TON TCKPS1:TCKPS0 2 Prescaler 1, 8, 64, 256 01 00 TGATE TCY 1 Set T3IF (T5IF) 0 Reset ADC Event Trigger(2) Equal Q D Q CK TCS(1) TGATE(1) TMR3 (TMR5) Comparator PR3 (PR5) Note 1: 2: The timer clock input must be assigned to an available RPn pin before use. Please see Section 9.4 "Peripheral Pin Select" for more information. The ADC Event Trigger is available only on Timer3. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 151 PIC24FJ256GB110 FAMILY REGISTER 11-1: TxCON: TIMER2 AND TIMER4 CONTROL REGISTER(3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON -- TSIDL -- -- -- -- -- bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 U-0 -- TGATE TCKPS1 TCKPS0 T32(1) -- TCS(2) -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 TON: Timerx On bit When TxCON<3> = 1: 1 = Starts 32-bit Timerx/y 0 = Stops 32-bit Timerx/y When TxCON<3> = 0: 1 = Starts 16-bit Timerx 0 = Stops 16-bit Timerx bit 14 Unimplemented: Read as `0' bit 13 TSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as `0' bit 6 TGATE: Timerx Gated Time Accumulation Enable bit When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS1:TCKPS0: Timerx Input Clock Prescale Select bits 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3 T32: 32-Bit Timer Mode Select bit(1) 1 = Timerx and Timery form a single 32-bit timer 0 = Timerx and Timery act as two 16-bit timers In 32-bit mode, T3CON control bits do not affect 32-bit timer operation. bit 2 Unimplemented: Read as `0' bit 1 TCS: Timerx Clock Source Select bit(2) 1 = External clock from pin, TxCK (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as `0' Note 1: 2: 3: x = Bit is unknown In 32-bit mode, the T3CON or T5CON control bits do not affect 32-bit timer operation. If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. For more information, see Section 9.4 "Peripheral Pin Select". Changing the value of TxCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. DS39897B-page 152 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 11-2: TyCON: TIMER3 AND TIMER5 CONTROL REGISTER(3) R/W-0 U-0 R/W-0 U-0 U-0 U-0 U-0 U-0 TON(1) -- TSIDL(1) -- -- -- -- -- bit 15 bit 8 U-0 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 U-0 -- TGATE(1) TCKPS1(1) TCKPS0(1) -- -- TCS(1,2) -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 TON: Timery On bit(1) 1 = Starts 16-bit Timery 0 = Stops 16-bit Timery bit 14 Unimplemented: Read as `0' bit 13 TSIDL: Stop in Idle Mode bit(1) 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-7 Unimplemented: Read as `0' bit 6 TGATE: Timery Gated Time Accumulation Enable bit(1) When TCS = 1: This bit is ignored. When TCS = 0: 1 = Gated time accumulation enabled 0 = Gated time accumulation disabled bit 5-4 TCKPS1:TCKPS0: Timery Input Clock Prescale Select bits(1) 11 = 1:256 10 = 1:64 01 = 1:8 00 = 1:1 bit 3-2 Unimplemented: Read as `0' bit 1 TCS: Timery Clock Source Select bit(1,2) 1 = External clock from pin TyCK (on the rising edge) 0 = Internal clock (FOSC/2) bit 0 Unimplemented: Read as `0' Note 1: 2: 3: x = Bit is unknown When 32-bit operation is enabled (T2CON<3> or T4CON<3> = 1), these bits have no effect on Timery operation; all timer functions are set through T2CON and T4CON. If TCS = 1, RPINRx (TxCK) must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. Changing the value of TyCON while the timer is running (TON = 1) causes the timer prescale counter to reset and is not recommended. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 153 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 154 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 12.0 INPUT CAPTURE WITH DEDICATED TIMERS Note: 12.1 12.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", Section 34. "Input Capture with Dedicated Timer" (DS39722). Devices in the PIC24FJ256GB110 family all feature 9 independent input capture modules. Each of the modules offers a wide range of configuration and operating options for capturing external pulse events and generating interrupts. Key features of the input capture module include: * Hardware-configurable for 32-bit operation in all modes by cascading two adjacent modules * Synchronous and Trigger modes of output compare operation, with up to 30 user-selectable trigger/sync sources available * A 4-level FIFO buffer for capturing and holding timer values for several events * Configurable interrupt generation * Up to 6 clock sources available for each module, driving a separate internal 16-bit counter The module is controlled through two registers, ICxCON1 (Register 12-1) and ICxCON2 (Register 12-2). A general block diagram of the module is shown in Figure 12-1. FIGURE 12-1: SYNCHRONOUS AND TRIGGER MODES By default, the input capture module operates in a free-running mode. The internal 16-bit counter ICxTMR counts up continuously, wrapping around from FFFFh to 0000h on each overflow, with its period synchronized to the selected external clock source. When a capture event occurs, the current 16-bit value of the internal counter is written to the FIFO buffer. In Synchronous mode, the module begins capturing events on the ICx pin as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the internal counter is reset. In Trigger mode, the module waits for a Sync event from another internal module to occur before allowing the internal counter to run. Standard, free-running operation is selected by setting the SYNCSEL bits to `00000', and clearing the ICTRIG bit (ICxCON2<7>). Synchronous and Trigger modes are selected any time the SYNCSEL bits are set to any value except `00000'. The ICTRIG bit selects either Synchronous or Trigger mode; setting the bit selects Trigger mode operation. In both modes, the SYNCSEL bits determine the sync/trigger source. When the SYNCSEL bits are set to `00000' and ICTRIG is set, the module operates in Software Trigger mode. In this case, capture operations are started by manually setting the TRIGSTAT bit (ICxCON2<6>). INPUT CAPTURE BLOCK DIAGRAM ICM2:ICM0 ICx Pin(1) General Operating Modes Prescaler Counter 1:1/4/16 ICI1:ICI0 Event and Interrupt Logic Edge Detect Logic and Clock Synchronizer Set ICxIF ICTSEL2:ICTSEL0 IC Clock Sources Clock Select Trigger and Sync Logic Trigger and Sync Sources Increment 16 ICxTMR 4-Level FIFO Buffer 16 Reset ICxBUF SYNCSEL4:SYNCSEL0 TRIGGER ICOV, ICBNE Note 1: 16 System Bus The ICx inputs must be assigned to an available RPn pin before use. Please see Section 9.4 "Peripheral Pin Select" for more information. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 155 PIC24FJ256GB110 FAMILY 12.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own 16-bit timer. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, modules 1 and 2 are paired, as are modules 3 and 4, and so on.) The odd-numbered module (ICx) provides the Least Significant 16 bits of the 32-bit register pairs, and the even module (ICy) provides the Most Significant 16 bits. Wraparounds of the ICx registers cause an increment of their corresponding ICy registers. Cascaded operation is configured in hardware by setting the IC32 bits (ICxCON2<8>) for both modules. 12.2 For 32-bit cascaded operations, the setup procedure is slightly different: 1. Set the IC32 bits for both modules (ICyCON2<8> and (ICxCON2<8>), enabling the even-numbered module first. This ensures the modules will start functioning in unison. Set the ICTSEL and SYNCSEL bits for both modules to select the same sync/trigger and time base source. Set the even module first, then the odd module. Both modules must use the same ICTSEL and SYNCSEL settings. Clear the ICTRIG bit of the even module (ICyCON2<7>); this forces the module to run in Synchronous mode with the odd module, regardless of its trigger setting. Use the odd module's ICI bits (ICxCON1<6:5>) to the desired interrupt frequency. Use the ICTRIG bit of the odd module (ICxCON2<7>) to configure Trigger or Synchronous mode operation. 2. 3. Capture Operations The input capture module can be configured to capture timer values and generate interrupts on rising edges on ICx, or all transitions on ICx. Captures can be configured to occur on all rising edges, or just some (every 4th or 16th). Interrupts can be independently configured to generate on each event, or a subset of events. 4. 5. Note: To set up the module for capture operations: 1. 2. 3. 4. 5. 6. 7. 8. 9. Configure the ICx input for one of the available peripheral pin select pins. If Synchronous mode is to be used, disable the sync source before proceeding. Make sure that any previous data has been removed from the FIFO by reading ICxBUF until the ICBNE bit (ICxCON1<3>) is cleared. Set the SYNCSEL bits (ICxCON2<4:0>) to the desired sync/trigger source. Set the ICTSEL bits (ICxCON1<12:10>) for the desired clock source. Set the ICI bits (ICxCON1<6:5>) to the desired interrupt frequency Select Synchronous or Trigger mode operation: a) Check that the SYNCSEL bits are not set to `00000'. b) For Synchronous mode, clear the ICTRIG bit (ICxCON2<7>). c) For Trigger mode, set ICTRIG, and clear the TRIGSTAT bit (ICxCON2<6>). Set the ICM bits (ICxCON1<2:0>) to the desired operational mode. Enable the selected trigger/sync source. DS39897B-page 156 6. For Synchronous mode operation, enable the sync source as the last step. Both input capture modules are held in Reset until the sync source is enabled. Use the ICM bits of the odd module (ICxCON1<2:0>) to set the desired capture mode. The module is ready to capture events when the time base and the trigger/sync source are enabled. When the ICBNE bit (ICxCON1<3>) becomes set, at least one capture value is available in the FIFO. Read input capture values from the FIFO until the ICBNE clears to `0'. For 32-bit operation, read both the ICxBUF and ICyBUF for the full 32-bit timer value (ICxBUF for the lsw, ICyBUF for the msw). At least one capture value is available in the FIFO buffer when the odd module's ICBNE bit (ICxCON1<3>) becomes set. Continue to read the buffer registers until ICBNE is cleared (perform automatically by hardware). Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 12-1: ICxCON1: INPUT CAPTURE x CONTROL REGISTER 1 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 -- -- ICSIDL ICTSEL2 ICTSEL1 ICTSEL0 -- -- bit 15 bit 8 U-0 R/W-0 R/W-0 R-0, HC R-0, HC R/W-0 R/W-0 R/W-0 -- ICI1 ICI0 ICOV ICBNE ICM2(1) ICM1(1) ICM0(1) bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13 ICSIDL: Input Capture x Module Stop in Idle Control bit 1 = Input capture module halts in CPU Idle mode 0 = Input capture module continues to operate in CPU Idle mode bit 12-10 ICTSEL2:ICTSEL0: Input Capture Timer Select bits 111 = System clock (FOSC/2) 110 = Reserved 101 = Reserved 100 = Timer1 011 = Timer5 010 = Timer4 001 = Timer2 000 = Timer3 bit 9-7 Unimplemented: Read as `0' bit 6-5 ICI1:ICI0: Select Number of Captures per Interrupt bits 11 = Interrupt on every fourth capture event 10 = Interrupt on every third capture event 01 = Interrupt on every second capture event 00 = Interrupt on every capture event bit 4 ICOV: Input Capture x Overflow Status Flag bit (read-only) 1 = Input capture overflow occurred 0 = No input capture overflow occurred bit 3 ICBNE: Input Capture x Buffer Empty Status bit (read-only) 1 = Input capture buffer is not empty, at least one more capture value can be read 0 = Input capture buffer is empty bit 2-0 ICM2:ICM0: Input Capture Mode Select bits(1) 111 = Interrupt mode: input capture functions as interrupt pin only when device is in Sleep or Idle mode (rising edge detect only, all other control bits are not applicable) 110 = Unused (module disabled) 101 = Prescaler Capture mode: capture on every 16th rising edge 100 = Prescaler Capture mode: capture on every 4th rising edge 011 = Simple Capture mode: capture on every rising edge 010 = Simple Capture mode: capture on every falling edge 001 = Edge Detect Capture mode: capture on every edge (rising and falling), ICI1:ICI0 bits do not control interrupt generation for this mode 000 = Input capture module turned off Note 1: The ICx input must also be configured to an available RPn pin. For more information, see Section 9.4 "Peripheral Pin Select". (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 157 PIC24FJ256GB110 FAMILY REGISTER 12-2: ICxCON2: INPUT CAPTURE x CONTROL REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 -- -- -- -- -- -- -- IC32 bit 15 bit 8 R/W-0 R/W-0 HS U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ICTRIG TRIGSTAT -- SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-9 Unimplemented: Read as `0' bit 8 IC32: Cascade Two IC Modules Enable bit (32-bit operation) 1 = ICx and ICy operate in cascade as a 32-bit module (this bit must be set in both modules) 0 = ICx functions independently as a 16-bit module bit 7 ICTRIG: ICx Trigger/Sync Select bit 1 = Trigger ICx from source designated by SYNCSELx bits 0 = Synchronize ICx with source designated by SYNCSELx bits bit 6 TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running (set in hardware, can be set in software) 0 = Timer source has not been triggered and is being held clear bit 5 Unimplemented: Read as `0' bit 4-0 SYNCSEL4:SYNCSEL0: Trigger/Synchronization Source Selection bits 11111 = Reserved 11110 = Input Capture 9 11101 = Input Capture 6 11100 = CTMU(1) 11011 = A/D(1) 11010 = Comparator 3(1) 11001 = Comparator 2(1) 11000 = Comparator 1(1) 10111 = Input Capture 4 10110 = Input Capture 3 10101 = Input Capture 2 10100 = Input Capture 1 10011 = Input Capture 8 10010 = Input Capture 7 1000x = reserved 01111 = Timer 5 01110 = Timer 4 01101 = Timer 3 01100 = Timer 2 01011 = Timer 1 01010 = Input Capture 5 01001 = Output Compare 9 01000 = Output Compare 8 00111 = Output Compare 7 00110 = Output Compare 6 00101 = Output Compare 5 00100 = Output Compare 4 00011 = Output Compare 3 00010 = Output Compare 2 00001 = Output Compare 1 00000 = Not synchronized to any other module Note 1: Use these inputs as trigger sources only and never as sync sources. DS39897B-page 158 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 13.0 Note: OUTPUT COMPARE WITH DEDICATED TIMERS This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual". Devices in the PIC24FJ256GB110 family all feature 9 independent output compare modules. Each of these modules offers a wide range of configuration and operating options for generating pulse trains on internal device events, and can produce pulse-width modulated waveforms for driving power applications. Key features of the output compare module include: * Hardware-configurable for 32-bit operation in all modes by cascading two adjacent modules * Synchronous and Trigger modes of output compare operation, with up to 30 user-selectable trigger/sync sources available * Two separate period registers (a main register, OCxR, and a secondary register, OCxRS) for greater flexibility in generating pulses of varying widths * Configurable for single-pulse or continuous pulse generation on an output event, or continuous PWM waveform generation * Up to 6 clock sources available for each module, driving a separate internal 16-bit counter 13.1 13.1.1 In Synchronous mode, the module begins performing its compare or PWM operation as soon as its selected clock source is enabled. Whenever an event occurs on the selected sync source, the module's internal counter is reset. In Trigger mode, the module waits for a sync event from another internal module to occur before allowing the counter to run. Free-running mode is selected by default, or any time that the SYNCSEL bits (OCxCON2<4:0>) are set to `00000'. Synchronous or Trigger modes are selected any time the SYNCSEL bits are set to any value except `00000'. The OCTRIG bit (OCxCON2<7>) selects either Synchronous or Trigger mode; setting the bit selects Trigger mode operation. In both modes, the SYNCSEL bits determine the sync/trigger source. 13.1.2 CASCADED (32-BIT) MODE By default, each module operates independently with its own set of 16-bit timer and duty cycle registers. To increase resolution, adjacent even and odd modules can be configured to function as a single 32-bit module. (For example, modules 1 and 2 are paired, as are modules 3 and 4, and so on.) The odd-numbered module (OCx) provides the Least Significant 16 bits of the 32-bit register pairs, and the even module (OCy) provides the Most Significant 16 bits. Wraparounds of the OCx registers cause an increment of their corresponding OCy registers. Cascaded operation is configured in hardware by setting the OC32 bits (OCxCON2<8>) for both modules. General Operating Modes SYNCHRONOUS AND TRIGGER MODES By default, the output compare module operates in a free-running mode. The internal 16-bit counter, OCxTMR, runs counts up continuously, wrapping around from FFFFh to 0000h on each overflow, with its period synchronized to the selected external clock source. Compare or PWM events are generated each time a match between the internal counter and one of the period registers occurs. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 159 PIC24FJ256GB110 FAMILY FIGURE 13-1: OUTPUT COMPARE BLOCK DIAGRAM (16-BIT MODE) OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT0 OCFLT0 OCxCON1 OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG Clock Select OC Clock Sources OCxCON2 OCxR Increment Comparator OC Output and Fault Logic OCxTMR Reset Match Event Trigger and Sync Sources Trigger and Sync Logic Comparator OCx Pin(1) Match Event Match Event OCFA/OCFB OCxRS Reset OCx Interrupt Note 1: The OCx outputs must be assigned to an available RPn pin before use. Please see Section 9.4 "Peripheral Pin Select" for more information. DS39897B-page 160 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 13.2 Compare Operations In Compare mode (Figure 13-1), the output compare module can be configured for single-shot or continuous pulse generation; it can also repeatedly toggle an output pin on each timer event. To set up the module for compare operations: 1. 2. 3. 4. 5. 6. 7. 8. Configure the OCx output for one of the available Peripheral Pin Select pins. Calculate the required values for the OCxR and (for Double Compare modes) OCxRS duty cycle registers: a) Determine the instruction clock cycle time. Take into account the frequency of the external clock to the timer source (if one is used) and the timer prescaler settings. b) Calculate time to the rising edge of the output pulse relative to the timer start value (0000h). c) Calculate the time to the falling edge of the pulse based on the desired pulse width and the time to the rising edge of the pulse. Write the rising edge value to OCxR, and the falling edge value to OCxRS. Set the Timer Period register, PRy, to a value equal to or greater than the value in OCxRS. Set the OCM2:OCM0 bits for the appropriate compare operation (= 0xx). For Trigger mode operations, set OCTRIG to enable Trigger mode. Set or clear TRIGMODE to configure trigger operation, and TRIGSTAT to select a hardware or software trigger. For Synchronous mode, clear OCTRIG. Set the SYNCSEL4:SYNCSEL0 bits to configure the trigger or synchronization source. If free-running timer operation is required, set the SYNCSEL bits to `00000' (no sync/trigger source). Select the time base source with the OCTSEL2:OCTSEL0 bits. If necessary, set the TON bit for the selected timer which enables the compare time base to count. Synchronous mode operation starts as soon as the time base is enabled; Trigger mode operation starts after a trigger source event occurs. (c) 2008 Microchip Technology Inc. For 32-bit cascaded operation, these steps are also necessary: 1. 2. 3. 4. 5. 6. Set the OC32 bits for both registers (OCyCON2<8> and (OCxCON2<8>). Enable the even-numbered module first to ensure the modules will start functioning in unison. Clear the OCTRIG bit of the even module (OCyCON2), so the module will run in Synchronous mode. Configure the desired output and Fault settings for OCy. Force the output pin for OCx to the output state by clearing the OCTRIS bit. If Trigger mode operation is required, configure the trigger options in OCx by using the OCTRIG (OCxCON2<7>), TRIGSTAT (OCxCON2<6>), and SYNCSEL (OCxCON2<4:0>) bits. Configure the desired compare or PWM mode of operation (OCM<2:0>) for OCy first, then for OCx. Depending on the output mode selected, the module holds the OCx pin in its default state, and forces a transition to the opposite state when OCxR matches the timer. In Double Compare modes, OCx is forced back to its default state when a match with OCxRS occurs. The OCxIF interrupt flag is set after an OCxR match in Single Compare modes, and after each OCxRS match in Double Compare modes. Single-shot pulse events only occur once, but may be repeated by simply rewriting the value of the OCxCON1 register. Continuous pulse events continue indefinitely until terminated. Preliminary DS39897B-page 161 PIC24FJ256GB110 FAMILY 13.3 Pulse-Width Modulation (PWM) Mode 5. Select a clock source by writing the OCTSEL2<2:0> (OCxCON<12:10>) bits. Enable interrupts, if required, for the timer and output compare modules. The output compare interrupt is required for PWM Fault pin utilization. Select the desired PWM mode in the OCM<2:0> (OCxCON1<2:0>) bits. If a timer is selected as a clock source, set the TMRy prescale value and enable the time base by setting the TON (TxCON<15>) bit. 6. In PWM mode, the output compare module can be configured for edge-aligned or center-aligned pulse waveform generation. All PWM operations are double-buffered (buffer registers are internal to the module and are not mapped into SFR space). 7. 8. To configure the output compare module for PWM operation: 1. 2. 3. 4. Note: Configure the OCx output for one of the available Peripheral Pin Select pins. Calculate the desired duty cycles and load them into the OCxR register. Calculate the desired period and load it into the OCxRS register. Select the current OCx as the trigger/sync source by writing 0x1F to SYNCSEL<4:0> (OCxCON2<4:0>). FIGURE 13-2: This peripheral contains input and output functions that may need to be configured by the peripheral pin select. See Section 9.4 "Peripheral Pin Select" for more information. OUTPUT COMPARE BLOCK DIAGRAM (DOUBLE-BUFFERED, 16-BIT PWM MODE) OCxCON1 OCxCON2 OCTSELx SYNCSELx TRIGSTAT TRIGMODE OCTRIG OCxR Rollover/Reset OCxR buffer OCMx OCINV OCTRIS FLTOUT FLTTRIEN FLTMD ENFLT0 OCFLT0 OCx Pin Clock Select OC Clock Sources Increment Comparator OCxTMR Reset Trigger and Sync Logic Trigger and Sync Sources Match Event Comparator Match Event Rollover OC Output and Fault Logic OCFA/OCFB Match Event OCxRS buffer Rollover/Reset OCxRS OCx Interrupt Reset Note 1: The OCx outputs must be assigned to an available RPn pin before use. Please see Section 9.4 "Peripheral Pin Select" for more information. DS39897B-page 162 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 13.3.1 PWM PERIOD 13.3.2 The PWM period is specified by writing to PRy, the Timer Period register. The PWM period can be calculated using Equation 13-1. EQUATION 13-1: The PWM duty cycle is specified by writing to the OCxRS and OCxR registers. The OCxRS and OCxR registers can be written to at any time, but the duty cycle value is not latched until a match between PRy and TMRy occurs (i.e., the period is complete). This provides a double buffer for the PWM duty cycle and is essential for glitchless PWM operation. CALCULATING THE PWM PERIOD(1) PWM Period = [(PRy) + 1] * TCY * (Timer Prescale Value) Some important boundary parameters of the PWM duty cycle include: where: PWM Frequency = 1/[PWM Period] Note 1: Note: * If OCxR, OCxRS, and PRy are all loaded with 0000h, the OCx pin will remain low (0% duty cycle). * *If OCxRS is greater than PRy, the pin will remain high (100% duty cycle). Based on TCY = TOSC * 2, Doze mode and PLL are disabled. A PRy value of N will produce a PWM period of N + 1 time base count cycles. For example, a value of 7 written into the PRy register will yield a period consisting of 8 time base cycles. EQUATION 13-2: PWM DUTY CYCLE See Example 13-1 for PWM mode timing details. Table 13-1 and Table 13-2 show example PWM frequencies and resolutions for a device operating at 4 MIPS and 10 MIPS, respectively. CALCULATION FOR MAXIMUM PWM RESOLUTION(1) log10 Maximum PWM Resolution (bits) = (F PWM ) FCY * (Timer Prescale Value) bits log10(2) Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled. EXAMPLE 13-1: PWM PERIOD AND DUTY CYCLE CALCULATIONS(1) 1. Find the Timer Period register value for a desired PWM frequency of 52.08 kHz, where FOSC = 8 MHz with PLL (32 MHz device clock rate) and a Timer2 prescaler setting of 1:1. TCY = 2 * TOSC = 62.5 ns PWM Period = 1/PWM Frequency = 1/52.08 kHz = 19.2 s PWM Period = (PR2 + 1) * TCY * (Timer 2 Prescale Value) 19.2 s = (PR2 + 1) * 62.5 ns * 1 PR2 = 306 2. Find the maximum resolution of the duty cycle that can be used with a 52.08 kHz frequency and a 32 MHz device clock rate: PWM Resolution = log10 (FCY/FPWM)/log102) bits = (log10 (16 MHz/52.08 kHz)/log102) bits = 8.3 bits Note 1: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 163 PIC24FJ256GB110 FAMILY TABLE 13-1: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 4 MIPS (FCY = 4 MHz)(1) PWM Frequency 7.6 Hz 61 Hz 122 Hz 977 Hz 3.9 kHz 31.3 kHz 125 kHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh 16 16 15 12 10 7 5 Resolution (bits) Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled. TABLE 13-2: EXAMPLE PWM FREQUENCIES AND RESOLUTIONS AT 16 MIPS (FCY = 16 MHz)(1) PWM Frequency 30.5 Hz 244 Hz 488 Hz 3.9 kHz 15.6 kHz 125 kHz 500 kHz Timer Prescaler Ratio 8 1 1 1 1 1 1 Period Register Value FFFFh FFFFh 7FFFh 0FFFh 03FFh 007Fh 001Fh 16 16 15 12 10 7 5 Resolution (bits) Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled. DS39897B-page 164 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 13-1: U-0 -- bit 15 U-0 -- ENFLT0 bit 7 Legend: R = Readable bit -n = Value at POR bit 12-10 bit 9-8 bit 7 bit 6-5 bit 4 bit 3 bit 2-0 Note 1: 2: R/W-0 OCSIDL R/W-0 OCTSEL2 R/W-0 OCTSEL1 R/W-0 OCTSEL0 U-0 -- U-0 -- bit 8 R/W-0 bit 15-14 bit 13 OCxCON1: OUTPUT COMPARE x CONTROL REGISTER 1 U-0 U-0 R/W-0, HCS -- -- OCFLT0 W = Writable bit `1' = Bit is set R/W-0 TRIGMODE R/W-0 OCM2(1) R/W-0 OCM1(1) R/W-0 OCM0(1) bit 0 HCS = Hardware Clearable/Settable bit U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' OCSIDL: Stop Output Compare x in Idle Mode Control bit 1 = Output Compare x halts in CPU Idle mode 0 = Output Compare x continues to operate in CPU Idle mode OCTSEL2:OCTSEL0: Output Compare x Timer Select bits 111 = System Clock 110 = Reserved 101 = Reserved 100 = Timer1 011 = Timer5 010 = Timer4 001 = Timer3 000 = Timer2 Unimplemented: Read as `0' ENFLT0: Fault 0 Input Enable bit 1 = Fault 0 input is enabled 0 = Fault 0 input is disabled Unimplemented: Read as `0' OCFLT0: PWM Fault Condition Status bit 1 = PWM Fault condition has occurred (cleared in HW only) 0 = No PWM Fault condition has occurred (this bit is only used when OCM<2:0> = 111) TRIGMODE: Trigger Status Mode Select bit 1 = TRIGSTAT (OCxCON2<6>) is cleared when OCxRS = OCxTMR or in software 0 = TRIGSTAT is only cleared by software OCM2:OCM0: Output Compare x Mode Select bits(1) 111 = Center-aligned PWM mode on OCx(2) 110 = Edge-aligned PWM Mode on OCx(2) 101 = Double Compare Continuous Pulse mode: Initialize OCx pin low, toggle OCx state continuously on alternate matches of OCxR and OCxRS 100 = Double Compare Single-Shot mode: Initialize OCx pin low, toggle OCx state on matches of OCxR and OCxRS for one cycle 011 = Single Compare Continuous Pulse mode: Compare events continuously toggle OCx pin 010 = Single Compare Single-Shot mode: Initialize OCx pin high, compare event forces OCx pin low 001 = Single Compare Single-Shot mode: Initialize OCx pin low, compare event forces OCx pin high 000 = Output compare channel is disabled The OCx output must also be configured to an available RPn pin. For more information, see Section 9.4 "Peripheral Pin Select". OCFA pin controls OC1-OC4 channels; OCFB pin controls the OC5-OC9 channels. OCxR and OCxRS are double-buffered only in PWM modes. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 165 PIC24FJ256GB110 FAMILY REGISTER 13-2: OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 FLTMD FLTOUT FLTTRIEN OCINV -- -- -- OC32 bit 15 bit 8 R/W-0 R/W-0 HS R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 OCTRIG TRIGSTAT OCTRIS SYNCSEL4 SYNCSEL3 SYNCSEL2 SYNCSEL1 SYNCSEL0 bit 7 bit 0 Legend: HS = Hardware Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 FLTMD: Fault Mode Select bit 1 = Fault mode is maintained until the Fault source is removed and the corresponding OCFLT0 bit is cleared in software 0 = Fault mode is maintained until the Fault source is removed and a new PWM period starts bit 14 FLTOUT: Fault Out bit 1 = PWM output is driven high on a Fault 0 = PWM output is driven low on a Fault bit 13 FLTTRIEN: Fault Output State Select bit 1 = Pin is forced to an output on a Fault condition 0 = Pin I/O condition is unaffected by a Fault bit 12 OCINV: OCMP Invert bit 1 = OCx output is inverted 0 = OCx output is not inverted bit 11-9 Unimplemented: Read as `0' bit 8 OC32: Cascade Two OC Modules Enable bit (32-bit operation) 1 = Cascade module operation enabled 0 = Cascade module operation disabled bit 7 OCTRIG: OCx Trigger/Sync Select bit 1 = Trigger OCx from source designated by SYNCSELx bits 0 = Synchronize OCx with source designated by SYNCSELx bits bit 6 TRIGSTAT: Timer Trigger Status bit 1 = Timer source has been triggered and is running 0 = Timer source has not been triggered and is being held clear bit 5 OCTRIS: OCx Output Pin Direction Select bit 1 = OCx pin is tristated 0 = Output compare peripheral x connected to OCx pin Note 1: 2: Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. Use these inputs as trigger sources only and never as sync sources. DS39897B-page 166 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 13-2: bit 4-0 OCxCON2: OUTPUT COMPARE x CONTROL REGISTER 2 SYNCSEL4:SYNCSEL0: Trigger/Synchronization Source Selection bits 11111 = This OC module(1) 11110 = Input Capture 9(2) 11101 = Input Capture 6(2) 11100 = CTMU(2) 11011 = A/D(2) 11010 = Comparator 3(2) 11001 = Comparator 2(2) 11000 = Comparator 1(2) 10111 = Input Capture 4(2) 10110 = Input Capture 3(2) 10101 = Input Capture 2(2) 10100 = Input Capture 1(2) 10011 = Input Capture 8(2) 10010 = Input Capture 7(2) 1000x = reserved 01111 = Timer 5 01110 = Timer 4 01101 = Timer 3 01100 = Timer 2 01011 = Timer 1 01010 = Input Capture 5(2) 01001 = Output Compare 9(1) 01000 = Output Compare 8(1) 00111 = Output Compare 7(1) 00110 = Output Compare 6(1) 00101 = Output Compare 5(1) 00100 = Output Compare 4(1) 00011 = Output Compare 3(1) 00010 = Output Compare 2(1) 00001 = Output Compare 1(1) 00000 = Not synchronized to any other module Note 1: 2: Never use an OC module as its own trigger source, either by selecting this mode or another equivalent SYNCSEL setting. Use these inputs as trigger sources only and never as sync sources. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 167 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 168 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 14.0 Note: SERIAL PERIPHERAL INTERFACE (SPI) The SPI serial interface consists of four pins: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 23. Serial Peripheral Interface (SPI)" (DS39699). The Serial Peripheral Interface (SPI) module is a synchronous serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, shift registers, display drivers, A/D Converters, etc. The SPI module is compatible with Motorola's SPI and SIOP interfaces. All devices of the PIC24FJ256GB110 family include three SPI modules * * * * SDIx: Serial Data Input SDOx: Serial Data Output SCKx: Shift Clock Input or Output SSx: Active-Low Slave Select or Frame Synchronization I/O Pulse The SPI module can be configured to operate using 2, 3 or 4 pins. In the 3-pin mode, SSx is not used. In the 2-pin mode, both SDOx and SSx are not used. Block diagrams of the module in Standard and Enhanced modes are shown in Figure 14-1 and Figure 14-2. Note: The module supports operation in two buffer modes. In Standard mode, data is shifted through a single serial buffer. In Enhanced Buffer mode, data is shifted through an 8-level FIFO buffer. Note: In this section, the SPI modules are referred to together as SPIx or separately as SPI1, SPI2 or SPI3. Special Function Registers will follow a similar notation. For example, SPIxCON1 and SPIxCON2 refer to the control registers for any of the 3 SPI modules. Do not perform read-modify-write operations (such as bit-oriented instructions) on the SPIxBUF register in either Standard or Enhanced Buffer mode. The module also supports a basic framed SPI protocol while operating in either Master or Slave mode. A total of four framed SPI configurations are supported. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 169 PIC24FJ256GB110 FAMILY To set up the SPI module for the Standard Master mode of operation: To set up the SPI module for the Standard Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 1. Clear the SPIROV bit (SPIxSTAT<6>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will start as soon as data is written to the SPIxBUF register. FIGURE 14-1: Clear the SPIxBUF register. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 0. Clear the SMP bit. If the CKE bit (SPIxCON1<8>) is set, then the SSEN bit (SPIxCON1<7>) must be set to enable the SSx pin. Clear the SPIROV bit (SPIxSTAT<6>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). 3. 4. 5. 6. 7. SPIx MODULE BLOCK DIAGRAM (STANDARD MODE) SCKx 1:1 to 1:8 Secondary Prescaler SSx/FSYNCx Sync Control 1:1/4/16/64 Primary Prescaler Select Edge Control Clock SPIxCON1<1:0> SPIxCON1<4:2> Shift Control SDOx Enable Master Clock bit 0 SDIx FCY SPIxSR Transfer Transfer SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus DS39897B-page 170 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY To set up the SPI module for the Enhanced Buffer Master mode of operation: To set up the SPI module for the Enhanced Buffer Slave mode of operation: 1. 1. 2. 2. 3. 4. 5. 6. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 1. Clear the SPIROV bit (SPIxSTAT<6>). Select Enhanced Buffer mode by setting the SPIBEN bit (SPIxCON2<0>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). Write the data to be transmitted to the SPIxBUF register. Transmission (and reception) will start as soon as data is written to the SPIxBUF register. FIGURE 14-2: Clear the SPIxBUF register. If using interrupts: a) Clear the SPIxIF bit in the respective IFS register. b) Set the SPIxIE bit in the respective IEC register. c) Write the SPIxIP bits in the respective IPC register to set the interrupt priority. Write the desired settings to the SPIxCON1 and SPIxCON2 registers with MSTEN (SPIxCON1<5>) = 0. Clear the SMP bit. If the CKE bit is set, then the SSEN bit must be set, thus enabling the SSx pin. Clear the SPIROV bit (SPIxSTAT<6>). Select Enhanced Buffer mode by setting the SPIBEN bit (SPIxCON2<0>). Enable SPI operation by setting the SPIEN bit (SPIxSTAT<15>). 3. 4. 5. 6. 7. 8. SPIx MODULE BLOCK DIAGRAM (ENHANCED MODE) SCKx 1:1 to 1:8 Secondary Prescaler SSx/FSYNCx Sync Control 1:1/4/16/64 Primary Prescaler Select Edge Control Clock SPIxCON1<1:0> SPIxCON1<4:2> Shift Control SDOx Enable Master Clock bit0 SDIx FCY SPIxSR Transfer Transfer 8-Level FIFO Receive Buffer 8-Level FIFO Transmit Buffer SPIxBUF Read SPIxBUF Write SPIxBUF 16 Internal Data Bus (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 171 PIC24FJ256GB110 FAMILY REGISTER 14-1: R/W-0 SPIEN (1) SPIxSTAT: SPIx STATUS AND CONTROL REGISTER U-0 R/W-0 U-0 U-0 R-0 R-0 R-0 -- SPISIDL -- -- SPIBEC2 SPIBEC1 SPIBEC0 bit 15 bit 8 R-0 R/C-0 R/W-0 R/W-0 R/W-0 R/W-0 R-0 R-0 SRMPT SPIROV SRXMPT SISEL2 SISEL1 SISEL0 SPITBF SPIRBF bit 7 bit 0 Legend: C = Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 SPIEN: SPIx Enable bit(1) 1 = Enables module and configures SCKx, SDOx, SDIx and SSx as serial port pins 0 = Disables module bit 14 Unimplemented: Read as `0' bit 13 SPISIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 Unimplemented: Read as `0' bit 10-8 SPIBEC2:SPIBEC0: SPIx Buffer Element Count bits (valid in Enhanced Buffer mode) Master mode: Number of SPI transfers pending. Slave mode: Number of SPI transfers unread. bit 7 SRMPT: Shift Register (SPIxSR) Empty bit (valid in Enhanced Buffer mode) 1 = SPIx Shift register is empty and ready to send or receive 0 = SPIx Shift register is not empty bit 6 SPIROV: Receive Overflow Flag bit 1 = A new byte/word is completely received and discarded. The user software has not read the previous data in the SPIxBUF register. 0 = No overflow has occurred bit 5 SRXMPT: Receive FIFO Empty bit (valid in Enhanced Buffer mode) 1 = Receive FIFO is empty 0 = Receive FIFO is not empty bit 4-2 SISEL2:SISEL0: SPIx Buffer Interrupt Mode bits (valid in Enhanced Buffer mode) 111 = Interrupt when SPIx transmit buffer is full (SPITBF bit is set) 110 = Interrupt when last bit is shifted into SPIxSR, as a result, the TX FIFO is empty 101 = Interrupt when the last bit is shifted out of SPIxSR, now the transmit is complete 100 = Interrupt when one data is shifted into the SPIxSR, as a result, the TX FIFO has one open spot 011 = Interrupt when SPIx receive buffer is full (SPIRBF bit set) 010 = Interrupt when SPIx receive buffer is 3/4 or more full 001 = Interrupt when data is available in receive buffer (SRMPT bit is set) 000 = Interrupt when the last data in the receive buffer is read, as a result, the buffer is empty (SRXMPT bit set) Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 9.4 "Peripheral Pin Select" for more information. DS39897B-page 172 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 14-1: SPIxSTAT: SPIx STATUS AND CONTROL REGISTER (CONTINUED) bit 1 SPITBF: SPIx Transmit Buffer Full Status bit 1 = Transmit not yet started, SPIxTXB is full 0 = Transmit started, SPIxTXB is empty In Standard Buffer mode: Automatically set in hardware when CPU writes SPIxBUF location, loading SPIxTXB. Automatically cleared in hardware when SPIx module transfers data from SPIxTXB to SPIxSR. In Enhanced Buffer mode: Automatically set in hardware when CPU writes SPIxBUF location, loading the last available buffer location. Automatically cleared in hardware when a buffer location is available for a CPU write. bit 0 SPIRBF: SPIx Receive Buffer Full Status bit 1 = Receive complete, SPIxRXB is full 0 = Receive is not complete, SPIxRXB is empty In Standard Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to SPIxRXB. Automatically cleared in hardware when core reads SPIxBUF location, reading SPIxRXB. In Enhanced Buffer mode: Automatically set in hardware when SPIx transfers data from SPIxSR to buffer, filling the last unread buffer location. Automatically cleared in hardware when a buffer location is available for a transfer from SPIxSR. Note 1: If SPIEN = 1, these functions must be assigned to available RPn pins before use. See Section 9.4 "Peripheral Pin Select" for more information. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 173 PIC24FJ256GB110 FAMILY REGISTER 14-2: SPIXCON1: SPIx CONTROL REGISTER 1 U-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 -- -- -- DISSCK(1) DISSDO(2) MODE16 SMP CKE(3) bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CKP MSTEN SPRE2 SPRE1 SPRE0 PPRE1 PPRE0 (4) SSEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as `0' bit 12 DISSCK: Disable SCKx pin bit (SPI Master modes only)(1) 1 = Internal SPI clock is disabled; pin functions as I/O 0 = Internal SPI clock is enabled bit 11 DISSDO: Disable SDOx pin bit(2) 1 = SDOx pin is not used by module; pin functions as I/O 0 = SDOx pin is controlled by the module bit 10 MODE16: Word/Byte Communication Select bit 1 = Communication is word-wide (16 bits) 0 = Communication is byte-wide (8 bits) bit 9 SMP: SPIx Data Input Sample Phase bit Master mode: 1 = Input data sampled at end of data output time 0 = Input data sampled at middle of data output time Slave mode: SMP must be cleared when SPIx is used in Slave mode. bit 8 CKE: SPIx Clock Edge Select bit(3) 1 = Serial output data changes on transition from active clock state to Idle clock state (see bit 6) 0 = Serial output data changes on transition from Idle clock state to active clock state (see bit 6) bit 7 SSEN: Slave Select Enable (Slave mode) bit(4) 1 = SSx pin used for Slave mode 0 = SSx pin not used by module; pin controlled by port function bit 6 CKP: Clock Polarity Select bit 1 = Idle state for clock is a high level; active state is a low level 0 = Idle state for clock is a low level; active state is a high level bit 5 MSTEN: Master Mode Enable bit 1 = Master mode 0 = Slave mode Note 1: 2: 3: 4: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. The CKE bit is not used in the Framed SPI modes. The user should program this bit to `0' for the Framed SPI modes (FRMEN = 1). If SSEN = 1, SSx must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. DS39897B-page 174 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 14-2: SPIXCON1: SPIx CONTROL REGISTER 1 (CONTINUED) bit 4-2 SPRE2:SPRE0: Secondary Prescale bits (Master mode) 111 = Secondary prescale 1:1 110 = Secondary prescale 2:1 ... 000 = Secondary prescale 8:1 bit 1-0 PPRE1:PPRE0: Primary Prescale bits (Master mode) 11 = Primary prescale 1:1 10 = Primary prescale 4:1 01 = Primary prescale 16:1 00 = Primary prescale 64:1 Note 1: 2: 3: 4: If DISSCK = 0, SCKx must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. If DISSDO = 0, SDOx must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. The CKE bit is not used in the Framed SPI modes. The user should program this bit to `0' for the Framed SPI modes (FRMEN = 1). If SSEN = 1, SSx must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. REGISTER 14-3: R/W-0 SPIxCON2: SPIx CONTROL REGISTER 2 R/W-0 FRMEN SPIFSD R/W-0 U-0 U-0 U-0 U-0 U-0 SPIFPOL -- -- -- -- -- bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- -- -- -- SPIFE SPIBEN bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 FRMEN: Framed SPIx Support bit 1 = Framed SPIx support enabled 0 = Framed SPIx support disabled bit 14 SPIFSD: Frame Sync Pulse Direction Control on SSx pin bit 1 = Frame sync pulse input (slave) 0 = Frame sync pulse output (master) bit 13 SPIFPOL: Frame Sync Pulse Polarity bit (Frame mode only) 1 = Frame sync pulse is active-high 0 = Frame sync pulse is active-low bit 12-2 Unimplemented: Read as `0' bit 1 SPIFE: Frame Sync Pulse Edge Select bit 1 = Frame sync pulse coincides with first bit clock 0 = Frame sync pulse precedes first bit clock bit 0 SPIBEN: Enhanced Buffer Enable bit 1 = Enhanced Buffer enabled 0 = Enhanced Buffer disabled (Legacy mode) (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 175 PIC24FJ256GB110 FAMILY FIGURE 14-3: SPI MASTER/SLAVE CONNECTION (STANDARD MODE) PROCESSOR 1 (SPI Master) PROCESSOR 2 (SPI Slave) SDIx SDOx Serial Receive Buffer (SPIxRXB) Serial Receive Buffer (SPIxRXB) SDOx SDIx Shift Register (SPIxSR) LSb MSb MSb Serial Transmit Buffer (SPIxTXB) LSb Serial Transmit Buffer (SPIxTXB) Serial Clock SCKx SPIx Buffer (SPIxBUF) Shift Register (SPIxSR) SCKx SPIx Buffer (SPIxBUF) SSx SSEN (SPIxCON1<7>) = 1 and MSTEN (SPIxCON1<5>) = 0 MSTEN (SPIxCON1<5>) = 1) Note 1: 2: FIGURE 14-4: Using the SSx pin in Slave mode of operation is optional. User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. SPI MASTER/SLAVE CONNECTION (ENHANCED BUFFER MODES) PROCESSOR 1 (SPI Enhanced Buffer Master) Shift Register (SPIxSR) PROCESSOR 2 (SPI Enhanced Buffer Slave) SDOx SDIx SDIx SDOx LSb MSb MSb 8-Level FIFO Buffer SPIx Buffer (SPIxBUF) SCKx Serial Clock SCKx SPIx Buffer (SPIxBUF) SSx SSEN (SPIxCON1<7>) = 1, MSTEN (SPIxCON1<5>) = 0 and SPIBEN (SPIxCON2<0>) = 1 MSTEN (SPIxCON1<5>) = 1 and SPIBEN (SPIxCON2<0>) = 1 1: 2: LSb 8-Level FIFO Buffer SSx Note Shift Register (SPIxSR) Using the SSx pin in Slave mode of operation is optional. User must write transmit data to read received data from SPIxBUF. The SPIxTXB and SPIxRXB registers are memory mapped to SPIxBUF. DS39897B-page 176 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY FIGURE 14-5: SPI MASTER, FRAME MASTER CONNECTION DIAGRAM PROCESSOR 2 PIC24F (SPI Slave, Frame Slave) SDIx SDOx SDOx SDIx SCKx SSx FIGURE 14-6: Serial Clock Frame Sync Pulse SCKx SSx SPI MASTER, FRAME SLAVE CONNECTION DIAGRAM PROCESSOR 2 PIC24F SPI Master, Frame Slave) SDOx SDIx SDIx SDOx SCKx SSx FIGURE 14-7: Serial Clock Frame Sync Pulse SCKx SSx SPI SLAVE, FRAME MASTER CONNECTION DIAGRAM PROCESSOR 2 PIC24F (SPI Slave, Frame Slave) SDOx SDIx SDIx SDOx SCKx SSx FIGURE 14-8: Serial Clock Frame Sync. Pulse SCKx SSx SPI SLAVE, FRAME SLAVE CONNECTION DIAGRAM PROCESSOR 2 PIC24F (SPI Master, Frame Slave) SDIx SDOx SDOx SDIx SCKx SSx (c) 2008 Microchip Technology Inc. Serial Clock Frame Sync Pulse Preliminary SCKx SSx DS39897B-page 177 PIC24FJ256GB110 FAMILY EQUATION 14-1: RELATIONSHIP BETWEEN DEVICE AND SPI CLOCK SPEED(1) FSCK = FCY Primary Prescaler * Secondary Prescaler Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled. TABLE 14-1: SAMPLE SCK FREQUENCIES(1,2) Secondary Prescaler Settings FCY = 16 MHz Primary Prescaler Settings 1:1 2:1 4:1 6:1 8:1 1:1 Invalid 8000 4000 2667 2000 4:1 4000 2000 1000 667 500 16:1 1000 500 250 167 125 64:1 250 125 63 42 31 1:1 5000 2500 1250 833 625 FCY = 5 MHz Primary Prescaler Settings Note 1: 2: 4:1 1250 625 313 208 156 16:1 313 156 78 52 39 64:1 78 39 20 13 10 Based on FCY = FOSC/2, Doze mode and PLL are disabled. SCKx frequencies shown in kHz. DS39897B-page 178 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 15.0 Note: INTER-INTEGRATED CIRCUIT (I2CTM) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 24. Inter-Integrated Circuit (I2CTM)" (DS39702). The Inter-Integrated Circuit (I2C) module is a serial interface useful for communicating with other peripheral or microcontroller devices. These peripheral devices may be serial EEPROMs, display drivers, A/D Converters, etc. The I * * * * * * * * * 2C module supports these features: Independent master and slave logic 7-bit and 10-bit device addresses General call address, as defined in the I2C protocol Clock stretching to provide delays for the processor to respond to a slave data request Both 100 kHz and 400 kHz bus specifications. Configurable address masking Multi-Master modes to prevent loss of messages in arbitration Bus Repeater mode, allowing the acceptance of all messages as a slave regardless of the address Automatic SCL 15.1 The details of sending a message in Master mode depends on the communications protocol for the device being communicated with. Typically, the sequence of events is as follows: 1. 2. 3. 4. 5. 6. 7. 8. 9. 10. 11. 12. A block diagram of the module is shown in Figure 15-1. 13. (c) 2008 Microchip Technology Inc. Communicating as a Master in a Single Master Environment Preliminary Assert a Start condition on SDAx and SCLx. Send the I 2C device address byte to the slave with a write indication. Wait for and verify an Acknowledge from the slave. Send the first data byte (sometimes known as the command) to the slave. Wait for and verify an Acknowledge from the slave. Send the serial memory address low byte to the slave. Repeat steps 4 and 5 until all data bytes are sent. Assert a Repeated Start condition on SDAx and SCLx. Send the device address byte to the slave with a read indication. Wait for and verify an Acknowledge from the slave. Enable master reception to receive serial memory data. Generate an ACK or NACK condition at the end of a received byte of data. Generate a Stop condition on SDAx and SCLx. DS39897B-page 179 PIC24FJ256GB110 FAMILY FIGURE 15-1: I2CTM BLOCK DIAGRAM Internal Data Bus I2CxRCV SCLx Read Shift Clock I2CxRSR LSB SDAx Address Match Match Detect Write I2CxMSK Write Read I2CxADD Read Start and Stop Bit Detect Write Start and Stop Bit Generation Control Logic I2CxSTAT Collision Detect Read Write I2CxCON Acknowledge Generation Read Clock Stretching Write I2CxTRN LSB Read Shift Clock Reload Control Write BRG Down Counter I2CxBRG Read TCY/2 DS39897B-page 180 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 15.2 Setting Baud Rate When Operating as a Bus Master 15.3 The I2CxMSK register (Register 15-3) designates address bit positions as "don't care" for both 7-Bit and 10-Bit Addressing modes. Setting a particular bit location (= 1) in the I2CxMSK register causes the slave module to respond whether the corresponding address bit value is a `0' or a `1'. For example, when I2CxMSK is set to `00100000', the slave module will detect both addresses, `0000000' and `0100000'. To compute the Baud Rate Generator reload value, use Equation 15-1. EQUATION 15-1: Slave Address Masking COMPUTING BAUD RATE RELOAD VALUE(1,2) FCY FSCL = ---------------------------------------------------------------------FCY I2CxBRG + 1 + -----------------------------10, 000, 000 or FCY FCY I2CxBRG = ------------ - ------------------------------ - 1 FSCL 10, 000, 000 To enable address masking, the IPMI (Intelligent Peripheral Management Interface) must be disabled by clearing the IPMIEN bit (I2CxCON<11>). Note: Note 1: Based on FCY = FOSC/2; Doze mode and PLL are disabled. 2: These clock rate values are for guidance only. The actual clock rate can be affected by various system level parameters. The actual clock rate should be measured in its intended application. TABLE 15-1: As a result of changes in the I2CTM protocol, the addresses in Table 15-2 are reserved and will not be acknowledged in Slave mode. This includes any address mask settings that include any of these addresses. I2CTM CLOCK RATES(1,2) Required System FSCL FCY 100 kHz 100 kHz 100 kHz I2CxBRG Value Actual FSCL (Decimal) (Hexadecimal) 16 MHz 157 9D 100 kHz 8 MHz 4 MHz 78 39 4E 27 100 kHz 99 kHz 400 kHz 400 kHz 16 MHz 8 MHz 37 18 25 12 404 kHz 404 kHz 400 kHz 400 kHz 4 MHz 2 MHz 9 4 9 4 385 kHz 385 kHz 1 MHz 1 MHz 16 MHz 8 MHz 13 6 D 6 1.026 MHz 1.026 MHz 1 MHz 4 MHz 3 3 0.909 MHz Note 1: Based on FCY = FOSC/2, Doze mode and PLL are disabled. 2: These clock rate values are for guidance only. The actual clock rate can be affected by various system level parameters. The actual clock rate should be measured in its intended application. TABLE 15-2: Slave Address I2CTM RESERVED ADDRESSES(1) R/W Bit Description Address(2) 0000 000 0 General Call 0000 000 1 Start Byte 0000 001 x Cbus Address 0000 010 x Reserved 0000 011 x Reserved 0000 1xx x HS Mode Master Code 1111 1xx x Reserved 1111 Note 1: 2: 3: 0xx x 10-Bit Slave Upper Byte(3) The address bits listed here will never cause an address match, independent of address mask settings. Address will be Acknowledged only if GCEN = 1. Match on this address can only occur on the upper byte in 10-Bit Addressing mode. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 181 PIC24FJ256GB110 FAMILY REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-1 HC R/W-0 R/W-0 R/W-0 R/W-0 I2CEN -- I2CSIDL SCLREL IPMIEN A10M DISSLW SMEN bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC R/W-0, HC GCEN STREN ACKDT ACKEN RCEN PEN RSEN SEN bit 7 bit 0 Legend: HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 I2CEN: I2Cx Enable bit 1 = Enables the I2Cx module and configures the SDAx and SCLx pins as serial port pins 0 = Disables I2Cx module. All I2C pins are controlled by port functions. bit 14 Unimplemented: Read as `0' bit 13 I2CSIDL: Stop in Idle Mode bit 1 = Discontinues module operation when device enters an Idle mode 0 = Continues module operation in Idle mode bit 12 SCLREL: SCLx Release Control bit (when operating as I2C Slave) 1 = Releases SCLx clock 0 = Holds SCLx clock low (clock stretch) If STREN = 1: Bit is R/W (i.e., software may write `0' to initiate stretch and write `1' to release clock). Hardware clear at beginning of slave transmission. Hardware clear at end of slave reception. If STREN = 0: Bit is R/S (i.e., software may only write `1' to release clock). Hardware clear at beginning of slave transmission. bit 11 IPMIEN: Intelligent Platform Management Interface (IPMI) Enable bit 1 = IPMI Support mode is enabled; all addresses Acknowledged 0 = IPMI mode disabled bit 10 A10M: 10-Bit Slave Addressing bit 1 = I2CxADD is a 10-bit slave address 0 = I2CxADD is a 7-bit slave address bit 9 DISSLW: Disable Slew Rate Control bit 1 = Slew rate control disabled 0 = Slew rate control enabled bit 8 SMEN: SMBus Input Levels bit 1 = Enables I/O pin thresholds compliant with SMBus specification 0 = Disables SMBus input thresholds bit 7 GCEN: General Call Enable bit (when operating as I2C slave) 1 = Enables interrupt when a general call address is received in the I2CxRSR (module is enabled for reception) 0 = General call address disabled bit 6 STREN: SCLx Clock Stretch Enable bit (when operating as I2C slave) Used in conjunction with SCLREL bit. 1 = Enables software or receive clock stretching 0 = Disables software or receive clock stretching DS39897B-page 182 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 15-1: I2CxCON: I2Cx CONTROL REGISTER (CONTINUED) bit 5 ACKDT: Acknowledge Data bit (When operating as I2C master. Applicable during master receive.) Value that will be transmitted when the software initiates an Acknowledge sequence. 1 = Sends NACK during Acknowledge 0 = Sends ACK during Acknowledge bit 4 ACKEN: Acknowledge Sequence Enable bit (When operating as I2C master. Applicable during master receive.) 1 = Initiates Acknowledge sequence on SDAx and SCLx pins and transmits ACKDT data bit. Hardware clear at end of master Acknowledge sequence. 0 = Acknowledge sequence not in progress bit 3 RCEN: Receive Enable bit (when operating as I2C master) 1 = Enables Receive mode for I2C. Hardware clear at end of eighth bit of master receive data byte. 0 = Receives sequence not in progress bit 2 PEN: Stop Condition Enable bit (when operating as I2C master) 1 = Initiates Stop condition on SDAx and SCLx pins. Hardware clear at end of master Stop sequence. 0 = Stop condition not in progress bit 1 RSEN: Repeated Start Condition Enabled bit (when operating as I2C master) 1 = Initiates Repeated Start condition on SDAx and SCLx pins. Hardware clear at end of master Repeated Start sequence. 0 = Repeated Start condition not in progress bit 0 SEN: Start Condition Enabled bit (when operating as I2C master) 1 = Initiates Start condition on SDAx and SCLx pins. Hardware clear at end of master Start sequence. 0 = Start condition not in progress (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 183 PIC24FJ256GB110 FAMILY REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER R-0, HSC R-0, HSC U-0 U-0 U-0 R/C-0, HS R-0, HSC R-0, HSC ACKSTAT TRSTAT -- -- -- BCL GCSTAT ADD10 bit 15 bit 8 R/C-0, HS R/C-0, HS R-0, HSC R/C-0, HSC R/C-0, HSC R-0, HSC R-0, HSC R-0, HSC IWCOL I2COV D/A P S R/W RBF TBF bit 7 bit 0 Legend: C = Clearable bit HS = Hardware Settable bit HSC = Hardware Settable/ Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 ACKSTAT: Acknowledge Status bit 1 = NACK was detected last 0 = ACK was detected last Hardware set or clear at end of Acknowledge. bit 14 TRSTAT: Transmit Status bit (When operating as I2C master. Applicable to master transmit operation.) 1 = Master transmit is in progress (8 bits + ACK) 0 = Master transmit is not in progress Hardware set at beginning of master transmission. Hardware clear at end of slave Acknowledge. bit 13-11 Unimplemented: Read as `0' bit 10 BCL: Master Bus Collision Detect bit 1 = A bus collision has been detected during a master operation 0 = No collision Hardware set at detection of bus collision. bit 9 GCSTAT: General Call Status bit 1 = General call address was received 0 = General call address was not received Hardware set when address matches general call address. Hardware clear at Stop detection. bit 8 ADD10: 10-Bit Address Status bit 1 = 10-bit address was matched 0 = 10-bit address was not matched Hardware set at match of 2nd byte of matched 10-bit address. Hardware clear at Stop detection. bit 7 IWCOL: Write Collision Detect bit 1 = An attempt to write the I2CxTRN register failed because the I2C module is busy 0 = No collision Hardware set at occurrence of write to I2CxTRN while busy (cleared by software). bit 6 I2COV: Receive Overflow Flag bit 1 = A byte was received while the I2CxRCV register is still holding the previous byte 0 = No overflow Hardware set at attempt to transfer I2CxRSR to I2CxRCV (cleared by software). bit 5 D/A: Data/Address bit (when operating as I2C slave) 1 = Indicates that the last byte received was data 0 = Indicates that the last byte received was device address Hardware clear at device address match. Hardware set by write to I2CxTRN or by reception of slave byte. DS39897B-page 184 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 15-2: I2CxSTAT: I2Cx STATUS REGISTER (CONTINUED) bit 4 P: Stop bit 1 = Indicates that a Stop bit has been detected last 0 = Stop bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 3 S: Start bit 1 = Indicates that a Start (or Repeated Start) bit has been detected last 0 = Start bit was not detected last Hardware set or clear when Start, Repeated Start or Stop detected. bit 2 R/W: Read/Write Information bit (when operating as I2C slave) 1 = Read - indicates data transfer is output from slave 0 = Write - indicates data transfer is input to slave Hardware set or clear after reception of I 2C device address byte. bit 1 RBF: Receive Buffer Full Status bit 1 = Receive complete, I2CxRCV is full 0 = Receive not complete, I2CxRCV is empty Hardware set when I2CxRCV is written with received byte. Hardware clear when software reads I2CxRCV. bit 0 TBF: Transmit Buffer Full Status bit 1 = Transmit in progress, I2CxTRN is full 0 = Transmit complete, I2CxTRN is empty Hardware set when software writes I2CxTRN. Hardware clear at completion of data transmission. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 185 PIC24FJ256GB110 FAMILY REGISTER 15-3: I2CxMSK: I2Cx SLAVE MODE ADDRESS MASK REGISTER U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- -- -- -- AMSK9 AMSK8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 AMSK7 AMSK6 AMSK5 AMSK4 AMSK3 AMSK2 AMSK1 AMSK0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-10 Unimplemented: Read as `0' bit 9-0 AMSK9:AMSK0: Mask for Address Bit x Select bits 1 = Enable masking for bit x of incoming message address; bit match not required in this position 0 = Disable masking for bit x; bit match required in this position DS39897B-page 186 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 16.0 UNIVERSAL ASYNCHRONOUS RECEIVER TRANSMITTER (UART) Note: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 21. UART" (DS39708). The Universal Asynchronous Receiver Transmitter (UART) module is one of the serial I/O modules available in the PIC24F device family. The UART is a full-duplex asynchronous system that can communicate with peripheral devices, such as personal computers, LIN, RS-232 and RS-485 interfaces. The module also supports a hardware flow control option with the UxCTS and UxRTS pins and also includes an IrDA(R) encoder and decoder. The primary features of the UART module are: * Full-Duplex, 8 or 9-Bit data transmission through the UxTX and UxRX pins * Even, Odd or No Parity options (for 8-bit data) * One or two Stop bits * Hardware Flow Control option with UxCTS and UxRTS pins FIGURE 16-1: * Fully Integrated Baud Rate Generator with 16-Bit Prescaler * Baud Rates Ranging from 1 Mbps to 15 bps at 16 MIPS * 4-Deep, First-In-First-Out (FIFO) Transmit Data Buffer * 4-Deep FIFO Receive Data Buffer * Parity, Framing and Buffer Overrun Error Detection * Support for 9-bit mode with Address Detect (9th bit = 1) * Transmit and Receive Interrupts * Loopback mode for Diagnostic Support * Support for Sync and Break Characters * Supports Automatic Baud Rate Detection * IrDA Encoder and Decoder Logic * 16x Baud Clock Output for IrDA Support A simplified block diagram of the UART is shown in Figure 16-1. The UART module consists of these key important hardware elements: * Baud Rate Generator * Asynchronous Transmitter * Asynchronous Receiver UART SIMPLIFIED BLOCK DIAGRAM Baud Rate Generator IrDA(R) UxRTS/BCLKx Hardware Flow Control UxCTS Note: UARTx Receiver UxRX UARTx Transmitter UxTX The UART inputs and outputs must all be assigned to available RPn pins before use. Please see Section 9.4 "Peripheral Pin Select" for more information. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 187 PIC24FJ256GB110 FAMILY 16.1 UART Baud Rate Generator (BRG) The UART module includes a dedicated 16-bit Baud Rate Generator. The UxBRG register controls the period of a free-running, 16-bit timer. Equation 16-1 shows the formula for computation of the baud rate with BRGH = 0. EQUATION 16-1: Baud Rate = The maximum baud rate (BRGH = 0) possible is FCY/16 (for UxBRG = 0) and the minimum baud rate possible is FCY/(16 * 65536). Equation 16-2 shows the formula for computation of the baud rate with BRGH = 1. EQUATION 16-2: UART BAUD RATE WITH BRGH = 0(1,2) Baud Rate = FCY 16 * (UxBRG + 1) UxBRG = UxBRG = Note 1: FCY -1 16 * Baud Rate Note 1: FCY denotes the instruction cycle clock frequency (FOSC/2). Based on FCY = FOSC/2, Doze mode and PLL are disabled. 2: Example 16-1 shows the calculation of the baud rate error for the following conditions: * FCY = 4 MHz * Desired Baud Rate = 9600 EXAMPLE 16-1: Desired Baud Rate UART BAUD RATE WITH BRGH = 1(1,2) 2: FCY 4 * (UxBRG + 1) FCY 4 * Baud Rate -1 FCY denotes the instruction cycle clock frequency. Based on FCY = FOSC/2, Doze mode and PLL are disabled. The maximum baud rate (BRGH = 1) possible is FCY/4 (for UxBRG = 0) and the minimum baud rate possible is FCY/(4 * 65536). Writing a new value to the UxBRG register causes the BRG timer to be reset (cleared). This ensures the BRG does not wait for a timer overflow before generating the new baud rate. BAUD RATE ERROR CALCULATION (BRGH = 0)(1) = FCY/(16 (UxBRG + 1)) Solving for UxBRG value: UxBRG UxBRG UxBRG = ((FCY/Desired Baud Rate)/16) - 1 = ((4000000/9600)/16) - 1 = 25 Calculated Baud Rate= 4000000/(16 (25 + 1)) = 9615 Error Note 1: = (Calculated Baud Rate - Desired Baud Rate) Desired Baud Rate = (9615 - 9600)/9600 = 0.16% Based on FCY = FOSC/2, Doze mode and PLL are disabled. DS39897B-page 188 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 16.2 1. 2. 3. 4. 5. 6. 2. 3. 4. 5. 6. 16.5 Set up the UART: a) Write appropriate values for data, parity and Stop bits. b) Write appropriate baud rate value to the UxBRG register. c) Set up transmit and receive interrupt enable and priority bits. Enable the UART. Set the UTXEN bit (causes a transmit interrupt two cycles after being set). Write data byte to lower byte of UxTXREG word. The value will be immediately transferred to the Transmit Shift Register (TSR), and the serial bit stream will start shifting out with next rising edge of the baud clock. Alternately, the data byte may be transferred while UTXEN = 0, and then the user may set UTXEN. This will cause the serial bit stream to begin immediately because the baud clock will start from a cleared state. A transmit interrupt will be generated as per interrupt control bit, UTXISELx. 16.3 1. Transmitting in 8-Bit Data Mode Transmitting in 9-Bit Data Mode Set up the UART (as described in Section 16.2 "Transmitting in 8-Bit Data Mode"). Enable the UART. Set the UTXEN bit (causes a transmit interrupt). Write UxTXREG as a 16-bit value only. A word write to UxTXREG triggers the transfer of the 9-bit data to the TSR. Serial bit stream will start shifting out with the first rising edge of the baud clock. A transmit interrupt will be generated as per the setting of control bit, UTXISELx. 16.4 Break and Sync Transmit Sequence The following sequence will send a message frame header made up of a Break, followed by an auto-baud Sync byte. 1. 2. 3. 4. 5. Configure the UART for the desired mode. Set UTXEN and UTXBRK to set up the Break character. Load the UxTXREG with a dummy character to initiate transmission (value is ignored). Write `55h' to UxTXREG; this loads the Sync character into the transmit FIFO. After the Break has been sent, the UTXBRK bit is reset by hardware. The Sync character now transmits. (c) 2008 Microchip Technology Inc. 1. 2. 3. 4. 5. Receiving in 8-Bit or 9-Bit Data Mode Set up the UART (as described in Section 16.2 "Transmitting in 8-Bit Data Mode"). Enable the UART. A receive interrupt will be generated when one or more data characters have been received as per interrupt control bit, URXISELx. Read the OERR bit to determine if an overrun error has occurred. The OERR bit must be reset in software. Read UxRXREG. The act of reading the UxRXREG character will move the next character to the top of the receive FIFO, including a new set of PERR and FERR values. 16.6 Operation of UxCTS and UxRTS Control Pins UARTx Clear to Send (UxCTS) and Request to Send (UxRTS) are the two hardware controlled pins that are associated with the UART module. These two pins allow the UART to operate in Simplex and Flow Control mode. They are implemented to control the transmission and reception between the Data Terminal Equipment (DTE). The UEN1:UEN0 bits in the UxMODE register configure these pins. 16.7 Infrared Support The UART module provides two types of infrared UART support: one is the IrDA clock output to support external IrDA encoder and decoder device (legacy module support) and the other is the full implementation of the IrDA encoder and decoder. Note that because the IrDA modes require a 16x baud clock, they will only work when the BRGH bit (UxMODE<3>) is `0'. 16.7.1 IRDA CLOCK OUTPUT FOR EXTERNAL IRDA SUPPORT To support external IrDA encoder and decoder devices, the BCLKx pin (same as the UxRTS pin) can be configured to generate the 16x baud clock. With UEN1:UEN0 = 11, the BCLKx pin will output the 16x baud clock if the UART module is enabled. It can be used to support the IrDA codec chip. 16.7.2 BUILT-IN IRDA ENCODER AND DECODER The UART has full implementation of the IrDA encoder and decoder as part of the UART module. The built-in IrDA encoder and decoder functionality is enabled using the IREN bit (UxMODE<12>). When enabled (IREN = 1), the receive pin (UxRX) acts as the input from the infrared receiver. The transmit pin (UxTX) acts as the output to the infrared transmitter. Preliminary DS39897B-page 189 PIC24FJ256GB110 FAMILY REGISTER 16-1: R/W-0 UxMODE: UARTx MODE REGISTER U-0 (1) UARTEN -- R/W-0 USIDL R/W-0 IREN (2) R/W-0 U-0 R/W-0 R/W-0 RTSMD -- UEN1 UEN0 bit 15 bit 8 R/C-0, HC R/W-0 R/W-0, HC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAKE LPBACK ABAUD RXINV BRGH PDSEL1 PDSEL0 STSEL bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 UARTEN: UARTx Enable bit(1) 1 = UARTx is enabled; all UARTx pins are controlled by UARTx as defined by UEN1:UEN0 0 = UARTx is disabled; all UARTx pins are controlled by PORT latches; UARTx power consumption minimal bit 14 Unimplemented: Read as `0' bit 13 USIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 IREN: IrDA(R) Encoder and Decoder Enable bit(2) 1 = IrDA encoder and decoder enabled 0 = IrDA encoder and decoder disabled bit 11 RTSMD: Mode Selection for UxRTS Pin bit 1 = UxRTS pin in Simplex mode 0 = UxRTS pin in Flow Control mode bit 10 Unimplemented: Read as `0' bit 9-8 UEN1:UEN0: UARTx Enable bits 11 = UxTX, UxRX and BCLKx pins are enabled and used; UxCTS pin controlled by PORT latches 10 = UxTX, UxRX, UxCTS and UxRTS pins are enabled and used 01 = UxTX, UxRX and UxRTS pins are enabled and used; UxCTS pin controlled by PORT latches 00 = UxTX and UxRX pins are enabled and used; UxCTS and UxRTS/BCLKx pins controlled by PORT latches bit 7 WAKE: Wake-up on Start Bit Detect During Sleep Mode Enable bit 1 = UARTx will continue to sample the UxRX pin; interrupt generated on falling edge, bit cleared in hardware on following rising edge 0 = No wake-up enabled bit 6 LPBACK: UARTx Loopback Mode Select bit 1 = Enable Loopback mode 0 = Loopback mode is disabled bit 5 ABAUD: Auto-Baud Enable bit 1 = Enable baud rate measurement on the next character - requires reception of a Sync field (55h); cleared in hardware upon completion 0 = Baud rate measurement disabled or completed Note 1: 2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. This feature is only available for the 16x BRG mode (BRGH = 0). DS39897B-page 190 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 16-1: UxMODE: UARTx MODE REGISTER (CONTINUED) bit 4 RXINV: Receive Polarity Inversion bit 1 = UxRX Idle state is `0' 0 = UxRX Idle state is `1' bit 3 BRGH: High Baud Rate Enable bit 1 = BRG generates 4 clocks per bit period (4x baud clock, High-Speed mode) 0 = BRG generates 16 clocks per bit period (16x baud clock, Standard mode) bit 2-1 PDSEL1:PDSEL0: Parity and Data Selection bits 11 = 9-bit data, no parity 10 = 8-bit data, odd parity 01 = 8-bit data, even parity 00 = 8-bit data, no parity bit 0 STSEL: Stop Bit Selection bit 1 = Two Stop bits 0 = One Stop bit Note 1: 2: If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. This feature is only available for the 16x BRG mode (BRGH = 0). (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 191 PIC24FJ256GB110 FAMILY REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTER R/W-0 R/W-0 R/W-0 U-0 R/W-0 HC R/W-0 R-0 R-1 UTXISEL1 UTXINV(1) UTXISEL0 -- UTXBRK UTXEN(2) UTXBF TRMT bit 15 bit 8 R/W-0 R/W-0 R/W-0 R-1 R-0 R-0 R/C-0 R-0 URXISEL1 URXISEL0 ADDEN RIDLE PERR FERR OERR URXDA bit 7 bit 0 Legend: C = Clearable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15,13 UTXISEL1:UTXISEL0: Transmission Interrupt Mode Selection bits 11 = Reserved; do not use 10 = Interrupt when a character is transferred to the Transmit Shift Register (TSR) and as a result, the transmit buffer becomes empty 01 = Interrupt when the last character is shifted out of the Transmit Shift Register; all transmit operations are completed 00 = Interrupt when a character is transferred to the Transmit Shift Register (this implies there is at least one character open in the transmit buffer) bit 14 UTXINV: IrDA(R) Encoder Transmit Polarity Inversion bit(1) IREN = 0: 1 = UxTX Idle `0' 0 = UxTX Idle `1' IREN = 1: 1 = UxTX Idle `1' 0 = UxTX Idle `0' bit 12 Unimplemented: Read as `0' bit 11 UTXBRK: Transmit Break bit 1 = Send Sync Break on next transmission - Start bit, followed by twelve `0' bits, followed by Stop bit; cleared by hardware upon completion 0 = Sync Break transmission disabled or completed bit 10 UTXEN: Transmit Enable bit(2) 1 = Transmit enabled, UxTX pin controlled by UARTx 0 = Transmit disabled, any pending transmission is aborted and buffer is reset. UxTX pin controlled by PORT. bit 9 UTXBF: Transmit Buffer Full Status bit (read-only) 1 = Transmit buffer is full 0 = Transmit buffer is not full, at least one more character can be written bit 8 TRMT: Transmit Shift Register Empty bit (read-only) 1 = Transmit Shift Register is empty and transmit buffer is empty (the last transmission has completed) 0 = Transmit Shift Register is not empty, a transmission is in progress or queued Note 1: 2: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. DS39897B-page 192 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 16-2: UxSTA: UARTx STATUS AND CONTROL REGISTER (CONTINUED) bit 7-6 URXISEL1:URXISEL0: Receive Interrupt Mode Selection bits 11 = Interrupt is set on RSR transfer, making the receive buffer full (i.e., has 4 data characters) 10 = Interrupt is set on RSR transfer, making the receive buffer 3/4 full (i.e., has 3 data characters) 0x = Interrupt is set when any character is received and transferred from the RSR to the receive buffer. Receive buffer has one or more characters. bit 5 ADDEN: Address Character Detect bit (bit 8 of received data = 1) 1 = Address Detect mode enabled. If 9-bit mode is not selected, this does not take effect. 0 = Address Detect mode disabled bit 4 RIDLE: Receiver Idle bit (read-only) 1 = Receiver is Idle 0 = Receiver is active bit 3 PERR: Parity Error Status bit (read-only) 1 = Parity error has been detected for the current character (character at the top of the receive FIFO) 0 = Parity error has not been detected bit 2 FERR: Framing Error Status bit (read-only) 1 = Framing error has been detected for the current character (character at the top of the receive FIFO) 0 = Framing error has not been detected bit 1 OERR: Receive Buffer Overrun Error Status bit (clear/read-only) 1 = Receive buffer has overflowed 0 = Receive buffer has not overflowed (clearing a previously set OERR bit (1 0 transition) will reset the receiver buffer and the RSR to the empty state bit 0 URXDA: Receive Buffer Data Available bit (read-only) 1 = Receive buffer has data, at least one more character can be read 0 = Receive buffer is empty Note 1: 2: Value of bit only affects the transmit properties of the module when the IrDA encoder is enabled (IREN = 1). If UARTEN = 1, the peripheral inputs and outputs must be configured to an available RPn pin. See Section 9.4 "Peripheral Pin Select" for more information. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 193 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 194 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 17.0 Note: UNIVERSAL SERIAL BUS WITH ON-THE-GO SUPPORT (USB OTG) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 27. USB On-The-Go (OTG)". PIC24FJ256GB110 family devices contain a full-speed and low-speed compatible, On-The-Go (OTG) USB Serial Interface Engine (SIE). The OTG capability allows the device to act either as a USB peripheral device or as a USB embedded host with limited host capabilities. The OTG capability allows the device to dynamically switch from device to host operation using OTG's Host Negotiation Protocol (HNP). For more details on OTG operation, refer to the "On-The-Go Supplement to the USB 2.0 Specification", published by the USB-IF. For more details on USB operation, refer to the "Universal Serial Bus Specification", v2.0. The USB OTG module can function as a USB peripheral device or as a USB host, and may dynamically switch between Device and Host modes under software control. In either mode, the same data paths and buffer descriptors are used for the transmission and reception of data. In discussing USB operation, this section will use a controller-centric nomenclature for describing the direction of the data transfer between the microcontroller and the USB. Rx (Receive) will be used to describe transfers that move data from the USB to the microcontroller, and Tx (Transmit) will be used to describe transfers that move data from the microcontroller to the USB. Table 17-1 shows the relationship between data direction in this nomenclature and the USB tokens exchanged. TABLE 17-1: USB Mode The USB OTG module offers these features: * USB functionality in Device and Host modes, and OTG capabilities for application-controlled mode switching * Software-selectable module speeds of full speed (12 Mbps) or low speed (1.5 Mbps, available in Host mode only) * Support for all four USB transfer types: control, interrupt, bulk and isochronous * 16 bidirectional endpoints for a total of 32 unique endpoints * DMA interface for data RAM access * Queues up to sixteen unique endpoint transfers without servicing * Integrated on-chip USB transceiver, with support for off-chip transceivers via a digital interface: * Integrated VBUS generation with on-chip comparators and boost generation, and support of external VBUS comparators and regulators through a digital interface * Configurations for on-chip bus pull-up and pull-down resistors CONTROLLER-CENTRIC DATA DIRECTION FOR USB HOST OR TARGET Direction Rx Tx Device OUT or SETUP IN Host IN OUT or SETUP This chapter presents the most basic operations needed to implement USB OTG functionality in an application. A complete and detailed discussion of the USB protocol and its OTG supplement are beyond the scope of this data sheet. It is assumed that the user already has a basic understanding of USB architecture and the latest version of the protocol. Not all steps for proper USB operation (such as device enumeration) are presented here. It is recommended that application developers use an appropriate device driver to implement all of the necessary features. Microchip provides a number of application-specific resources, such as USB firmware and driver support. Refer to www.microchip.com for the latest firmware and driver support. A simplified block diagram of the USB OTG module is shown in Figure 17-1. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 195 PIC24FJ256GB110 FAMILY FIGURE 17-1: USB OTG MODULE BLOCK DIAGRAM Full-Speed Pull-up Host Pull-down 48 MHz USB Clock D+(1) Registers and Control Interface Transceiver D-(1) Host Pull-down USBID(1) USB SIE VMIO(1) VPIO(1) DMH(1) DPH(1) External Transceiver Interface DMLN(1) DPLN(1) RCV(1) System RAM USBOEN(1) VBUSON(1) SRP Charge USB Voltage Comparators VBUS SRP Discharge VUSB Transceiver Power 3.3V USB 3.3V Regulator VCMPST1(1) VCMPST2(1) VBUS Boost Assist VBUSST(1) VCPCON(1) Note 1: Pins are multiplexed with digital I/O and other device features. DS39897B-page 196 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 17.1 USB Buffer Descriptors and the BDT Endpoint buffer control is handled through a structure called the Buffer Descriptor Table (BDT). This provides a flexible method for users to construct and control endpoint buffers of various lengths and configurations. The BDT can be located in any available, 512-byte aligned block of data RAM. The BDT Pointer (U1BDTP1) contains the upper address byte of the BDT, and sets the location of the BDT in RAM. The user must set this pointer to indicate the table's location. The BDT is composed of Buffer Descriptors (BDs) which are used to define and control the actual buffers in the USB RAM space. Each BD consists of two, 16-bit "soft" (non-fixed-address) registers, BDnSTAT and BDnADR, where n represents one of the 64 possible BDs (range of 0 to 63). BDnSTAT is the status register for BDn, while BDnADR specifies the starting address for the buffer associated with BDn. FIGURE 17-2: Depending on the endpoint buffering configuration used, there are up to 64 sets of buffer descriptors, for a total of 256 bytes. At a minimum, the BDT must be at least 8 bytes long. This is because the USB specification mandates that every device must have Endpoint 0 with both input and output for initial setup. Endpoint mapping in the BDT is dependent on three variables: * Endpoint number (0 to 15) * Endpoint direction (Rx or Tx) * Ping-pong settings (U1CNFG1<1:0>) Figure 17-2 illustrates how these variables are used to map endpoints in the BDT. In Host mode, only Endpoint 0 buffer descriptors are used. All transfers utilize the Endpoint 0 buffer descriptor and Endpoint Control register (U1EP0). For received packets, the attached device's source endpoint is indicated by the value of ENDPT3:ENDPT0 in the USB status register (U1STAT<7:4>). For transmitted packet, the attached device's destination endpoint is indicated by the value written to the Token register (U1TOK). BDT MAPPING FOR ENDPOINT BUFFERING MODES PPB1:PPB0 = 00 No Ping-Pong Buffers PPB1:PPB0 = 01 Ping-Pong Buffer on EP0 OUT PPB1:PPB0 = 10 Ping-Pong Buffers on all EPs Total BDT Space: 128 bytes Total BDT Space: 132 bytes Total BDT Space: 256 bytes PPB1:PPB0 = 11 Ping-Pong Buffers on all other EPs except EP0 Total BDT Space: 248 bytes EP0 Rx Descriptor EP0 Rx Even Descriptor EP0 Rx Even Descriptor EP0 Rx Descriptor EP0 Tx Descriptor EP0 Rx Odd Descriptor EP0 Rx Odd Descriptor EP0 Tx Descriptor EP0 Tx Even Descriptor EP1 Rx Even Descriptor EP0 Tx Odd Descriptor EP1 Rx Odd Descriptor EP1 Rx Even Descriptor EP1 Tx Even Descriptor EP1 Rx Odd Descriptor EP1 Tx Odd Descriptor EP1 Rx Descriptor EP1 Tx Descriptor EP0 Tx Descriptor EP1 Rx Descriptor EP1 Tx Descriptor EP15 Tx Descriptor EP15 Tx Descriptor EP1 Tx Even Descriptor EP1 Tx Odd Descriptor EP15 Tx Odd Descriptor Note: EP15 Tx Odd Descriptor Memory area not shown to scale. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 197 PIC24FJ256GB110 FAMILY 17.1.1 BUFFER OWNERSHIP Because the buffers and their BDs are shared between the CPU and the USB module, a simple semaphore mechanism is used to distinguish which is allowed to update the BD and associated buffers in memory. This is done by using the UOWN bit as a semaphore to distinguish which is allowed to update the BD and associated buffers in memory. UOWN is the only bit that is shared between the two configurations of BDnSTAT. When UOWN is clear, the BD entry is "owned" by the microcontroller core. When the UOWN bit is set, the BD entry and the buffer memory are "owned" by the USB peripheral. The core should not modify the BD or its corresponding data buffer during this time. Note that the microcontroller core can still read BDnSTAT while the SIE owns the buffer and vice versa. When UOWN is set, the user can no longer depend on the values that were written to the BDs. From this point, the USB module updates the BDs as necessary, overwriting the original BD values. The BDnSTAT register is updated by the SIE with the token PID and the transfer count is updated. 17.1.2 DMA INTERFACE The USB OTG module uses a dedicated DMA to access both the BDT and the endpoint data buffers. Since part of the address space of the DMA is dedicated to the Buffer Descriptors, a portion of the memory connected to the DMA must comprise a contiguous address space properly mapped for the access by the module. The buffer descriptors have a different meaning based on the source of the register update. Register 17-1 and Register 17-2 show the differences in BDnSTAT depending on its current "ownership". REGISTER 17-1: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, USB MODE (BD0STAT THROUGH BD63STAT) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x UOWN DTS PID3 PID2 PID1 PID0 BC9 BC8 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 UOWN: USB Own bit 1 = The USB module owns the BD and its corresponding buffer; the CPU must not modify the BD or the buffer bit 14 DTS: Data Toggle Packet bit 1 = Data 1 packet 0 = Data 0 packet bit 13-10 PID3:PID0: Packet Identifier bits (written by the USB module) In Device mode: Represents the PID of the received token during the last transfer. In Host mode: Represents the last returned PID, or the transfer status indicator. bit 9-0 BC9:BC0: Byte Count This represents the number of bytes to be transmitted or the maximum number of bytes to be received during a transfer. Upon completion, the byte count is updated by the USB module with the actual number of bytes transmitted or received. DS39897B-page 198 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 17-2: BDnSTAT: BUFFER DESCRIPTOR n STATUS REGISTER PROTOTYPE, CPU MODE (BD0STAT THROUGH BD63STAT) R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x UOWN DTS(1) 0 0 DTSEN BSTALL BC9 BC8 bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x BC7 BC6 BC5 BC4 BC3 BC2 BC1 BC0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 UOWN: USB Own bit 0 = The microcontroller core owns the BD and its corresponding buffer. The USB module ignores all other fields in the BD. bit 14 DTS: Data Toggle Packet bit(1) 1 = Data 1 packet 0 = Data 0 packet bit 13-12 Reserved Function: Maintain as `0' bit 11 DTSEN: Data Toggle Synchronization Enable bit 1 = Data toggle synchronization is enabled; data packets with incorrect sync value will be ignored 0 = No data toggle synchronization is performed bit 10 BSTALL: Buffer Stall Enable bit 1 = Buffer STALL enabled; STALL handshake issued if a token is received that would use the BD in the given location (UOWN bit remains set, BD value is unchanged); corresponding EPSTALL bit will get set on any STALL handshake 0 = Buffer STALL disabled bit 9-0 BC9:BC0: Byte Count bits This represents the number of bytes to be transmitted or the maximum number of bytes to be received during a transfer. Upon completion, the byte count is updated by the USB module with the actual number of bytes transmitted or received. Note 1: This bit is ignored unless DTSEN = 1. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 199 PIC24FJ256GB110 FAMILY 17.2 VBUS Voltage Generation 3. When operating as a USB host, either as an A-device in an OTG configuration or as an embedded host, VBUS must be supplied to the attached device. PIC24FJ256GB110 family devices have an internal VBUS boost assist to help generate the required 5V VBUS from the available voltages on the board. Figure 17-3 shows how the internal VBUS components of the USB OTG module work in A-device and B-device configurations. Select the required polarity of the output signal based on the configuration of the external circuit with the PWMPOL bit (U1PWMCON<9>). Select the desired target voltage using the VBUSCHG bit (U1OTGCON<1>). Enable the PWM counter by setting the CNTEN bit to `1' (U1PWMCON<8>). Enable the PWM module by setting the PWMEN bit to `1' (U1PWMCON<15>). Enable the VBUS generation circuit (U1OTGCON<3> = 1). 4. 5. 6. 7. To enable voltage generation: 1. 2. Note: Verify that the USB module is powered (U1PWRC<0> = 1) and that the VBUS discharge is disabled (U1OTGCON<0> = 0). Set the PWM period (U1PWMRRS<7:0>) and duty cycle (U1PWMRRS<15:8>) as required. FIGURE 17-3: This section describes the general process for VBUS voltage generation and control. Please refer to the "PIC24F Family Reference Manual" for additional examples. USB VOLTAGE GENERATION AND CONNECTIONS BETWEEN AN A-DEVICE AND A B-DEVICE PIC24FJ256GB1XX PIC24FJ256GB1XX A-DEVICE (HOST) 5V BOOST ASSIST(1) 5V BOOST ASSIST XCVR VBUS (5V) D+ DGND ID D+ D- 3.3V REGULATOR D+ D- GND XCVR GND ID Note 1: USB SIE VBUS COMPARATORS RECEPTACLE 3.3V REGULATOR A PLUG RECEPTACLE VBUS COMPARATORS B PLUG USB SIE B-DEVICE ID Additional external components (not shown here) and software configuration are required for a host device to generate VBUS. For more information, refer to the "PIC24F Family Reference Manual". DS39897B-page 200 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 17.3 USB Interrupts 17.3.1 Unlike device level interrupts, the USB OTG interrupt status flags are not freely writable in software. All USB OTG flag bits are implemented as hardware set only bits. Additionally, these bits can only be cleared in software by writing a `1' to their locations (i.e., performing a MOV type instruction). Writing a `0' to a flag bit (i.e., a BCLR instruction) has no effect. The USB OTG module has many conditions that can be configured to cause an interrupt. All interrupt sources use the same interrupt vector. Figure 17-4 shows the interrupt logic for the USB module. There are two layers of interrupt registers in the USB module. The top level consists of overall USB status interrupts; these are enabled and flagged in the U1IE and U1IR registers, respectively. The second level consists of USB error conditions, which are enabled and flagged in the U1EIR and U1EIE registers. An interrupt condition in any of these triggers a USB Error Interrupt Flag (UERRIF) in the top level. FIGURE 17-4: CLEARING USB OTG INTERRUPTS Note: Throughout this data sheet, a bit that can only be cleared by writing a `1' to its location is referred to as "Write 1 to clear". In register descriptions, this function is indicated by the descriptor "K". USB OTG INTERRUPT FUNNEL Top Level (USB Status) Interrupts STALLIF STALLIE ATTACHIF ATTACHIE RESUMEIF RESUMEIE IDLEIF IDLEIE TRNIF TRNIE Second Level (USB Error) Interrupts SOFIF SOFIE BTSEF BTSEE DMAEF DMAEE URSTIF (DETACHIF) URSTIE (DETACHIE) BTOEF BTOEE Set USB1IF (UERRIF) DFN8EF DFN8EE UERRIE IDIF IDIE CRC16EF CRC16EE T1MSECIF TIMSECIE CRC5EF (EOFEF) CRC5EE (EOFEE) LSTATEIF PIDEF PIDEE LSTATEIE ACTVIF ACTVIE SESVDIF SESVDIE SESENDIF SESENDIE VBUSVDIF VBUSVDIE Top Level (USB OTG) Interrupts (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 201 PIC24FJ256GB110 FAMILY 17.4 Device Mode Operation 17.4.3 The following section describes how to perform a common Device mode task. In Device mode, USB transfers are performed at the transfer level. The USB module automatically performs the status phase of the transfer. 17.4.1 1. 2. 3. 4. 5. 6. 7. 8. 9. 2. 3. 4. 2. 3. Reset the Ping-Pong Buffer Pointers by setting, then clearing, the Ping-Pong Buffer Reset bit PPBRST (U1CON<1>). Disable all interrupts (U1IE and U1EIE = 00h). Clear any existing interrupt flags by writing FFh to U1IR and U1EIR. Verify that VBUS is present (non OTG devices only). Enable the USB module by setting the USBEN bit (U1CON<0>). Set the OTGEN bit (U1OTGCON<2>) to enable OTG operation. Enable the endpoint zero buffer to receive the first setup packet by setting the EPRXEN and EPHSHK bits for Endpoint 0 (U1EP0<3,0> = 1). Power up the USB module by setting the USBPWR bit (U1PWRC<0>). Enable the D+ pull-up resistor to signal an attach by setting DPPULUP (U1OTGCON<7>). 17.4.2 1. ENABLING DEVICE MODE 1. RECEIVING AN IN TOKEN IN DEVICE MODE Attach to a USB host and enumerate as described in Chapter 9 of the USB 2.0 specification. Create a data buffer, and populate it with the data to send to the host. In the appropriate (EVEN or ODD) Tx BD for the desired endpoint: a) Set up the status register (BDnSTAT) with the correct data toggle (DATA0/1) value and the byte count of the data buffer. b) Set up the address register (BDnADR) with the starting address of the data buffer. c) Set the UOWN bit of the status register to `1'. When the USB module receives an IN token, it automatically transmits the data in the buffer. Upon completion, the module updates the status register (BDnSTAT) and sets the Transfer Complete Interrupt Flag, TRNIF (U1IR<3>). 4. Attach to a USB host and enumerate as described in Chapter 9 of the USB 2.0 specification. Create a data buffer with the amount of data you are expecting from the host. In the appropriate (EVEN or ODD) Tx BD for the desired endpoint: a) Set up the status register (BDnSTAT) with the correct data toggle (DATA0/1) value and the byte count of the data buffer. b) Set up the address register (BDnADR) with the starting address of the data buffer. c) Set the UOWN bit of the status register to `1'. When the USB module receives an OUT token, it automatically receives the data sent by the host to the buffer. Upon completion, the module updates the status register (BDnSTAT) and sets the Transfer Complete Interrupt Flag, TRNIF (U1IR<3>). 17.5 Host Mode Operation The following sections describe how to perform common Host mode tasks. In Host mode, USB transfers are invoked explicitly by the host software. The host software is responsible for the Acknowledge portion of the transfer. Also, all transfers are performed using the Endpoint 0 control register (U1EP0) and buffer descriptors. 17.5.1 1. 2. 3. 4. 5. DS39897B-page 202 RECEIVING AN OUT TOKEN IN DEVICE MODE Preliminary ENABLE HOST MODE AND DISCOVER A CONNECTED DEVICE Enable Host mode by setting U1CON<3> (HOSTEN). This causes the Host mode control bits in other USB OTG registers to become available. Enable the D+ and D- pull-down resistors by setting DPPULDWN and DMPULDWN (U1OTGCON<5:4>). Disable the D+ and Dpull-up resistors by clearing DPPULUP and DMPULUP (U1OTGCON<7:6>). At this point, SOF generation begins with the SOF counter loaded with 12,000. Eliminate noise on the USB by clearing the SOFEN bit (U1CON<0>) to disable Start-Of-Frame packet generation. Enable the device attached interrupt by setting ATTACHIE (U1IE<6>). Wait for the device attached interrupt (U1IR<6> = 1). This is signaled by the USB device changing the state of D+ or D- from `0' to `1' (SE0 to J state). After it occurs, wait 100 ms for the device power to stabilize. (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 6. Check the state of the JSTATE and SE0 bits in U1CON. If the JSTATE bit (U1CON<7>) is `0', the connecting device is low speed. If the connecting device is low speed, set the low LSPDEN and LSPD bits (U1ADDR<7> and U1EP0<7>) to enable low-speed operation. 7. Reset the USB device by setting the RESET bit (U1CON<4>) for at least 50 ms, sending Reset signaling on the bus. After 50 ms, terminate the Reset by clearing RESET. 8. To keep the connected device from going into suspend, enable SOF packet generation to keep by setting the SOFEN bit. 9. Wait 10 ms for the device to recover from Reset. 10. Perform enumeration as described by Chapter 9 of the USB 2.0 specification. 17.5.2 1. 2. 3. 4. 5. 6. COMPLETE A CONTROL TRANSACTION TO A CONNECTED DEVICE Follow the procedure described in Section 17.5.1 "Enable Host Mode and Discover a Connected Device" to discover a device. Set up the Endpoint Control register for bidirectional control transfers by writing 0Dh to U1EP0 (this sets the EPCONDIS, EPTXEN, and EPHSHK bits). Place a copy of the device framework setup command in a memory buffer. See Chapter 9 of the USB 2.0 specification for information on the device framework command set. Initialize the buffer descriptor (BD) for the current (EVEN or ODD) Tx EP0, to transfer the eight bytes of command data for a device framework command (i.e., a GET DEVICE DESCRIPTOR): a) Set the BD data buffer address (BD0ADR) to the starting address of the 8-byte memory buffer containing the command. b) Write 8008h to BD0STAT (this sets the UOWN bit, and sets a byte count of 8). Set the USB device address of the target device in the address register (U1ADDR<6:0>). After a USB bus Reset, the device USB address will be zero. After enumeration, it will be set to another value between 1 and 127. Write D0h to U1TOK; this is a SETUP token to Endpoint 0, the target device's default control pipe. This initiates a SETUP token on the bus, followed by a data packet. The device handshake is returned in the PID field of BD0STAT after the packets are complete. When the USB module updates BD0STAT, a transfer done interrupt is asserted (the TRNIF flag is set). This completes the setup phase of the setup transaction as referenced in chapter 9 of the USB specification. (c) 2008 Microchip Technology Inc. 7. To initiate the data phase of the setup transaction (i.e., get the data for the GET DEVICE descriptor command), set up a buffer in memory to store the received data. 8. Initialize the current (EVEN or ODD) Rx or Tx (Rx for IN, Tx for OUT) EP0 BD to transfer the data. a) Write C040h to BD0STAT. This sets the UOWN, configures Data Toggle (DTS) to DATA1, and sets the byte count to the length of the data buffer (64 or 40h, in this case). b) Set BD0ADR to the starting address of the data buffer. 9. Write the token register with the appropriate IN or OUT token to Endpoint 0, the target device's default control pipe (e.g., write 90h to U1TOK for an IN token for a GET DEVICE DESCRIPTOR command). This initiates an IN token on the bus followed by a data packet from the device to the host. When the data packet completes, the BD0STAT is written and a transfer done interrupt is asserted (the TRNIF flag is set). For control transfers with a single packet data phase, this completes the data phase of the setup transaction as referenced in chapter 9 of the USB specification. If more data needs to be transferred, return to step 8. 10. To initiate the status phase of the setup transaction, set up a buffer in memory to receive or send the zero length status phase data packet. 11. Initialize the current (even or odd) Tx EP0 BD to transfer the status data.: a) Set the BDT buffer address field to the start address of the data buffer b) Write 8000h to BD0STAT (set UOWN bit, configure DTS to DATA0, and set byte count to 0). 12. Write the Token register with the appropriate IN or OUT token to Endpoint 0, the target device's default control pipe (e.g., write 01h to U1TOK for an OUT token for a GET DEVICE DESCRIPTOR command). This initiates an OUT token on the bus followed by a zero length data packet from the host to the device. When the data packet completes, the BD is updated with the handshake from the device, and a transfer done interrupt is asserted (the TRNIF flag is set). This completes the status phase of the setup transaction as described in chapter 9 of the USB specification. Note: Preliminary Only one control transaction can be performed per frame. DS39897B-page 203 PIC24FJ256GB110 FAMILY 17.5.3 1. 2. 3. 4. 5. 6. 7. SEND A FULL-SPEED BULK DATA TRANSFER TO A TARGET DEVICE Follow the procedure described in Section 17.5.1 "Enable Host Mode and Discover a Connected Device" and Section 17.5.2 "Complete a Control Transaction to a Connected Device" to discover and configure a device. To enable transmit and receive transfers with handshaking enabled, write 1Dh to U1EP0. If the target device is a low-speed device, also set the LSPD bit (U1EP0<7>). If you want the hardware to automatically retry indefinitely if the target device asserts a NAK on the transfer, clear the Retry Disable bit, RETRYDIS (U1EP0<6>). Set up the BD for the current (EVEN or ODD) Tx EP0 to transfer up to 64 bytes. Set the USB device address of the target device in the address register (U1ADDR<6:0>). Write an OUT token to the desired endpoint to U1TOK. This triggers the module's transmit state machines to begin transmitting the token and the data. Wait for the Transfer Done Interrupt Flag, TRNIF. This indicates that the BD has been released back to the microprocessor, and the transfer has completed. If the retry disable bit is set, the handshake (ACK, NAK, STALL or ERROR (0Fh)) is returned in the BD PID field. If a STALL interrupt occurs, the pending packet must be dequeued and the error condition in the target device cleared. If a detach interrupt occurs (SE0 for more than 2.5 s), then the target has detached (U1IR<0> is set). Once the transfer done interrupt occurs (TRNIF is set), the BD can be examined and the next data packet queued by returning to step 2. Note: USB speed, transceiver and pull-ups should only be configured during the module setup phase. It is not recommended to change these settings while the module is enabled. 17.6 17.6.1 OTG Operation SESSION REQUEST PROTOCOL (SRP) An OTG A-device may decide to power down the VBUS supply when it is not using the USB link through the Session Request Protocol (SRP). Software may do this by clearing VBUSON (U1OTGCON<3>). When the VBUS supply is powered down, the A-device is said to have ended a USB session. An OTG A-device or Embedded Host may re-power the VBUS supply at any time (initiate a new session). An OTG B-device may also request that the OTG A-device re-power the VBUS supply (initiate a new session). This is accomplished via Session Request Protocol (SRP). Prior to requesting a new session, the B-device must first check that the previous session has definitely ended. To do this, the B-device must check for two conditions: 1. VBUS supply is below the Session Valid voltage, and 2. Both D+ and D- have been low for at least 2 ms. The B-device will be notified of condition 1 by the SESENDIF (U1OTGIR<2>) interrupt. Software will have to manually check for condition 2. Note: When the A-device powers down the VBUS supply, the B-device must disconnect its pull-up resistor from power. If the device is self-powered, it can do this by clearing DPPULUP (U1OTGCON<7>) and DMPULUP (U1OTGCON<6>). The B-device may aid in achieving condition 1 by discharging the VBUS supply through a resistor. Software may do this by setting VBUSDIS (U1OTGCON<0>). After these initial conditions are met, the B-device may begin requesting the new session. The B-device begins by pulsing the D+ data line. Software should do this by setting DPPULUP (U1OTGCON<7>). The data line should be held high for 5 to 10 ms. The B-device then proceeds by pulsing the VBUS supply. Software should do this by setting VBUSCHG (UTOGCTRL<1>). When an A-device detects SRP signaling (either via the ATTACHIF (U1IR<6>) interrupt or via the SESVDIF (U1OTGIR<3>) interrupt), the A-device must restore the VBUS supply by setting VBUSON (U1OTGCON<3>). The B-device should not monitor the state of the VBUS supply while performing VBUS supply pulsing. When the B-device does detect that the VBUS supply has been restored (via the SESVDIF (U1OTGIR<3>) interrupt), the B-device must re-connect to the USB link by pulling up D+ or D- (via the DPPULUP or DMPULUP). The A-device must complete the SRP by driving USB Reset signaling. DS39897B-page 204 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 17.6.2 HOST NEGOTIATION PROTOCOL (HNP) In USB OTG applications, a Dual Role Device (DRD) is a device that is capable of being either a host or a peripheral. Any OTG DRD must support Host Negotiation Protocol (HNP). HNP allows an OTG B-device to temporarily become the USB host. The A-device must first enable the B-device to follow HNP. Refer to the On-The-Go Supplement to the USB 2.0 Specification for more information regarding HNP. HNP may only be initiated at full speed. After being enabled for HNP by the A-device, the B-device requests being the host any time that the USB link is in Suspend state, by simply indicating a disconnect. This can be done in software by clearing DPPULUP and DMPULUP. When the A-device detects the disconnect condition (via the URSTIF (U1IR<0>) interrupt), the A-device may allow the B-device to take over as Host. The A-device does this by signaling connect as a full-speed function. Software may accomplish this by setting DPPULUP. If the A-device responds instead with resume signaling, the A-device remains as host. When the B-device detects the connect condition (via ATTACHIF (U1IR<6>), the B-device becomes host. The B-device drives Reset signaling prior to using the bus. When the B-device has finished in its role as Host, it stops all bus activity and turns on its D+ pull-up resistor by setting DPPULUP. When the A-device detects a suspend condition (Idle for 3 ms), the A-device turns off its D+ pull-up. The A-device may also power-down VBUS supply to end the session. When the A-device detects the connect condition (via ATTACHIF), the A-device resumes host operation, and drives Reset signaling. (c) 2008 Microchip Technology Inc. 17.7 USB OTG Module Registers There are a total of 37 memory mapped registers associated with the USB OTG module. They can be divided into four general categories: * * * * USB OTG Module Control (12) USB Interrupt (7) USB Endpoint Management (16) USB VBUS Power Control (2) This total does not include the (up to) 128 BD registers in the BDT. Their prototypes, described in Register 17-1 and Register 17-2, are shown separately in Section 17.1 "USB Buffer Descriptors and the BDT". With the exception U1PWMCON and U1PWMRRS, all USB OTG registers are implemented in the Least Significant Byte of the register. Bits in the upper byte are unimplemented, and have no function. Note that some registers are instantiated only in Host mode, while other registers have different bit instantiations and functions in Device and Host modes. Registers described in the following sections are those that have bits with specific control and configuration features. The following registers are used for data or address values only: * U1BDTP1: Specifies the 256-word page in data RAM used for the BDT; 8-bit value with bit 0 fixed as `0' for boundary alignment * U1FRML and U1FRMH: Contains the 11-bit byte counter for the current data frame * U1PWMRRS: Contains the 8-bit value for PWM duty cycle (bits 15:8) and PWM period (bits 7:0) for the VBUS boost assist PWM module. Preliminary DS39897B-page 205 PIC24FJ256GB110 FAMILY 17.7.1 USB OTG MODULE CONTROL REGISTERS REGISTER 17-3: U1OTGSTAT: USB OTG STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R-0, HSC U-0 R-0, HSC U-0 R-0, HSC R-0, HSC U-0 R-0, HSC ID -- LSTATE -- SESVD SESEND -- VBUSVD bit 7 bit 0 Legend: U = Unimplemented bit, read as `0' R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as `0' bit 7 ID: ID Pin State Indicator bit 1 = No plug is attached, or a type B cable has been plugged into the USB receptacle 0 = A type A plug has been plugged into the USB receptacle bit 6 Unimplemented: Read as `0' bit 5 LSTATE: Line State Stable Indicator bit 1 = The USB line state (as defined by SE0 and JSTATE) has been stable for the previous 1 ms 0 = The USB line state has NOT been stable for the previous 1 ms bit 4 Unimplemented: Read as `0' bit 3 SESVD: Session Valid Indicator bit 1 = The VBUS voltage is above VA_SESS_VLD (as defined in the USB OTG Specification) on the A or B-device 0 = The VBUS voltage is below VA_SESS_VLD on the A or B-device bit 2 SESEND: B-Session End Indicator bit 1 = The VBUS voltage is below VB_SESS_END (as defined in the USB OTG Specification) on the B-device 0 = The VBUS voltage is above VB_SESS_END on the B-device bit 1 Unimplemented: Read as `0' bit 0 VBUSVD: A-VBUS Valid Indicator bit 1 = The VBUS voltage is above VA_VBUS_VLD (as defined in the USB OTG Specification) on the A-device 0 = The VBUS voltage is below VA_VBUS_VLD on the A-device DS39897B-page 206 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 17-4: U1OTGCON: USB ON-THE-GO CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R/W-0 R/W-0 DPPULUP DMPULUP R/W-0 R/W-0 DPPULDWN(1) DMPULDWN(1) R/W-0 R/W-0 VBUSON(1) OTGEN(1) R/W-0 R/W-0 VBUSCHG(1) VBUSDIS(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as `0' bit 7 DPPULUP: D+ Pull-Up Enable bit 1 = D+ data line pull-up resistor enabled 0 = D+ data line pull-up resistor disabled bit 6 DMPULUP: D- Pull-Up Enable bit 1 = D- data line pull-up resistor enabled 0 = D- data line pull-up resistor disabled bit 5 DPPULDWN: D+ Pull-Down Enable bit(1) 1 = D+ data line pull-down resistor enabled 0 = D+ data line pull-down resistor disabled bit 4 DMPULDWN: D- Pull-Down Enable bit(1) 1 = D- data line pull-down resistor enabled 0 = D- data line pull-down resistor disabled bit 3 VBUSON: VBUS Power-on bit(1) 1 = VBUS line powered 0 = VBUS line not powered bit 2 OTGEN: OTG Features Enable bit(1) 1 = USB OTG enabled; all D+/D- pull-ups and pull-downs bits are enabled 0 = USB OTG disabled; D+/D- pull-ups and pull-downs are controlled in hardware by the settings of the HOSTEN and USBEN bits (U1CON<3,0>) bit 1 VBUSCHG: VBUS Charge Select bit(1) 1 = VBUS line set to charge to 3.3V 0 = VBUS line set to charge to 5V bit 0 VBUSDIS: VBUS Discharge Enable bit(1) 1 = VBUS line discharged through a resistor 0 = VBUS line not discharged Note 1: These bits are only used in Host mode; do not use in Device mode. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 207 PIC24FJ256GB110 FAMILY REGISTER 17-5: U1PWRC: USB POWER CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R/W-0, HS U-0 U-0 R/W-0 U-0 U-0 R/W-0, HC R/W-0 UACTPND -- -- USLPGRD -- -- USUSPND USBPWR bit 7 bit 0 Legend: HS = Hardware Settable bit HC = Hardware Clearable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as `0' bit 7 UACTPND: USB Activity Pending bit 1 = Module should not be suspended at the moment (requires USLPGRD bit to be set) 0 = Module may be suspended or powered down bit 6-5 Unimplemented: Read as `0' bit 4 USLPGRD: Sleep/Suspend Guard bit 1 = Indicate to the USB module that it is about to be suspended or powered down 0 = No suspend bit 3-2 Unimplemented: Read as `0' bit 1 USUSPND: USB Suspend Mode Enable bit 1 = USB OTG module is in Suspend mode; USB clock is gated and the transceiver is placed in a low-power state 0 = Normal USB OTG operation bit 0 USBPWR: USB Operation Enable bit 1 = USB OTG module is enabled 0 = USB OTG module is disabled(1) Note 1: Do not clear this bit unless the HOSTEN, USBEN and OTGEN bits (U1CON<3,0> and U1OTGCON<2>) are all cleared. DS39897B-page 208 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 17-6: U1STAT: USB STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC R-0, HSC U-0 U-0 ENDPT3 ENDPT2 ENDPT1 ENDPT0 DIR PPBI(1) -- -- bit 7 bit 0 Legend: U = Unimplemented bit, read as `0' R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-8 Unimplemented: Read as `0' bit 7-4 ENDPT3:ENDPT0: Number of the Last Endpoint Activity bits (Represents the number of the BDT updated by the last USB transfer). 1111 = Endpoint 15 1110 = Endpoint 14 .... 0001 = Endpoint 1 0000 = Endpoint 0 bit 3 DIR: Last BD Direction Indicator bit 1 = The last transaction was a transmit transfer (Tx) 0 = The last transaction was a receive transfer (Rx) bit 2 PPBI: Ping-Pong BD Pointer Indicator bit(1) 1 = The last transaction was to the ODD BD bank 0 = The last transaction was to the EVEN BD bank bit 1-0 Unimplemented: Read as `0' Note 1: x = Bit is unknown This bit is only valid for endpoints with available EVEN and ODD BD registers. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 209 PIC24FJ256GB110 FAMILY REGISTER 17-7: U1CON: USB CONTROL REGISTER (DEVICE MODE) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 R-x, HSC R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 -- SE0 PKTDIS -- HOSTEN RESUME PPBRST USBEN bit 7 bit 0 Legend: U = Unimplemented bit, read as `0' R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-7 Unimplemented: Read as `0' bit 6 SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero active on the USB bus 0 = No single-ended zero detected bit 5 PKTDIS: Packet Transfer Disable bit 1 = SIE token and packet processing disabled; automatically set when a SETUP token is received 0 = SIE token and packet processing enabled bit 4 Unimplemented: Read as `0' bit 3 HOSTEN: Host Mode Enable bit 1 = USB host capability enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability disabled bit 2 RESUME: Resume Signaling Enable bit 1 = Resume signaling activated 0 = Resume signaling disabled bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the EVEN BD banks 0 = Ping-Pong Buffer Pointers not reset bit 0 USBEN: USB Module Enable bit 1 = USB module and supporting circuitry enabled (device attached); D+ pull-up is activated in hardware 0 = USB module and supporting circuitry disabled (device detached) DS39897B-page 210 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 17-8: U1CON: USB CONTROL REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R-x, HSC R-x, HSC R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 JSTATE SE0 TOKBUSY RESET HOSTEN RESUME PPBRST SOFEN bit 7 bit 0 Legend: U = Unimplemented bit, read as `0' R = Readable bit W = Writable bit HSC = Hardware Settable/Clearable bit -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as `0' bit 7 JSTATE: Live Differential Receiver J State Flag bit 1 = J state (differential `0' in low speed, differential `1' in full speed) detected on the USB 0 = No J state detected bit 6 SE0: Live Single-Ended Zero Flag bit 1 = Single-ended zero active on the USB bus 0 = No single-ended zero detected bit 5 TOKBUSY: Token Busy Status bit 1 = Token being executed by the USB module in On-The-Go state 0 = No token being executed bit 4 RESET: Module Reset bit 1 = USB Reset has been generated; for software Reset, application must set this bit for 10 ms, then clear it 0 = USB Reset terminated bit 3 HOSTEN: Host Mode Enable bit 1 = USB host capability enabled; pull-downs on D+ and D- are activated in hardware 0 = USB host capability disabled bit 2 RESUME: Resume Signaling Enable bit 1 = Resume signaling activated; software must set bit for 10 ms and then clear to enable remote wake-up 0 = Resume signaling disabled bit 1 PPBRST: Ping-Pong Buffers Reset bit 1 = Reset all Ping-Pong Buffer Pointers to the EVEN BD banks 0 = Ping-Pong Buffer Pointers not reset bit 0 SOFEN: Start-Of-Frame Enable bit 1 = Start-Of-Frame token sent every one 1 millisecond 0 = Start-Of-Frame token disabled (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 211 PIC24FJ256GB110 FAMILY REGISTER 17-9: U1ADDR: USB ADDRESS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R/W-0 (1) LSPDEN R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR6 ADDR5 ADDR4 ADDR3 ADDR2 ADDR1 ADDR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-8 Unimplemented: Read as `0' bit 7 LSPDEN: Low-Speed Enable Indicator bit(1) 1 = USB module operates at low speed 0 = USB module operates at full speed bit 6-0 ADDR6:ADDR0: USB Device Address bits Note 1: x = Bit is unknown Host mode only. In Device mode, this bit is unimplemented and read as `0'. REGISTER 17-10: U1TOK: USB TOKEN REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PID3 PID2 PID1 PID0 EP3 EP2 EP1 EP0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-8 Unimplemented: Read as `0' bit 7-4 PID3:PID0: Token Type Identifier bits 1101 = SETUP (TX) token type transaction(1) 1001 = IN (RX) token type transaction(1) 0001 = OUT (TX) token type transaction(1) bit 3-0 EP3:EP0: Token Command Endpoint Address bits This value must specify a valid endpoint on the attached device. Note 1: x = Bit is unknown All other combinations are reserved and are not to be used. DS39897B-page 212 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 17-11: U-0 -- bit 15 U1SOF: USB OTG START-OF-TOKEN THRESHOLD REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CNT7 CNT6 CNT5 CNT4 CNT3 CNT2 CNT1 CNT0 bit 7 bit 0 Legend: R = Readable bit -n = Value at POR bit 15-8 bit 7-0 W = Writable bit `1' = Bit is set U = Unimplemented bit, read as `0' `0' = Bit is cleared x = Bit is unknown Unimplemented: Read as `0' CNT7:CNT0: Start-Of-Frame Size bits; Value represents 10 + (packet size of n bytes). For example: 0100 1010 = 64-byte packet 0010 1010 = 32-byte packet 0001 0010 = 8-byte packet REGISTER 17-12: U1CNFG1: USB CONFIGURATION REGISTER 1 U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- U-0 -- bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 UTEYE UOEMON(1) -- USBSIDL -- -- PPB1 PPB0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as `0' bit 7 UTEYE: USB Eye Pattern Test Enable bit 1 = Eye pattern test enabled 0 = Eye pattern test disabled bit 6 UOEMON: USB OE Monitor Enable bit(1) 1 = OE signal active; it indicates intervals during which the D+/D- lines are driving 0 = OE signal inactive Unimplemented: Read as `0' bit 5 bit 4 bit 3-2 bit 1-0 Note 1: USBSIDL: USB OTG Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode Unimplemented: Read as `0' PPB1:PPB0: Ping-Pong Buffers Configuration bit 11 = EVEN/ODD ping-pong buffers enabled for Endpoints 1 to 15 10 = EVEN/ODD ping-pong buffers enabled for all endpoints 01 = EVEN/ODD ping-pong buffer enabled for OUT Endpoint 0 00 = EVEN/ODD ping-pong buffers disabled This bit is only active when the UTRDIS bit (U1CNFG2<0>) is set. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 213 PIC24FJ256GB110 FAMILY REGISTER 17-13: U1CNFG2: USB CONFIGURATION REGISTER 2 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 U-0 U-0 -- -- -- R/W-0 PUVBUS R/W-0 EXTI2CEN R/W-0 R/W-0 (1) UVBUSDIS R/W-0 (1) UVCMPDIS UTRDIS(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-5 Unimplemented: Read as `0' bit 4 PUVBUS: VBUS Pull-up Enable bit 1 = Pull-up on VBUS pin enabled 0 = Pull-up on VBUS pin disabled bit 3 EXTI2CEN: I2CTM Interface For External Module Control Enable bit 1 = External module(s) controlled via I2C interface 0 = External module(s) controller via dedicated pins bit 2 UVBUSDIS: On-Chip 5V Boost Regulator Builder Disable bit(1) 1 = On-chip boost regulator builder disabled; digital output control interface enabled 0 = On-chip boost regulator builder active bit 1 UVCMPDIS: On-Chip VBUS Comparator Disable bit(1) 1 = On-chip charge VBUS comparator disabled; digital input status interface enabled 0 = On-chip charge VBUS comparator active bit 0 UTRDIS: On-Chip Transceiver Disable bit(1) 1 = On-chip transceiver and VBUS detection disabled; digital transceiver interface enabled 0 = On-chip transceiver and VBUS detection active Note 1: Never change these bits while the USBPWR bit is set (U1PWRC<0> = 1). DS39897B-page 214 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 17.7.2 USB INTERRUPT REGISTERS REGISTER 17-14: U1OTGIR: USB OTG INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS U-0 R/K-0, HS IDIF T1MSECIF LSTATEIF ACTVIF SESVDIF SESENDIF -- VBUSVDIF bit 7 bit 0 Legend: U = Unimplemented bit, read as `0' R = Readable bit K = Write `1' to clear bit HS = Hardware Settable bit -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as `0' bit 7 IDIF: ID State Change Indicator bit 1 = Change in ID state detected 0 = No ID state change bit 6 T1MSECIF: 1 Millisecond Timer bit 1 = The 1 millisecond timer has expired 0 = The 1 millisecond timer has not expired bit 5 LSTATEIF: Line State Stable Indicator bit 1 = USB line state (as defined by the SE0 and JSTATE bits) has been stable for 1 ms, but different from last time 0 = USB line state has not been stable for 1 ms bit 4 ACTVIF: Bus Activity Indicator bit 1 = Activity on the D+/D- lines or VBUS detected 0 = No activity on the D+/D- lines or VBUS detected bit 3 SESVDIF: Session Valid Change Indicator bit 1 = VBUS has crossed VA_SESS_END (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_END bit 2 SESENDIF: B-Device VBUS Change Indicator bit 1 = VBUS change on B-device detected; VBUS has crossed VB_SESS_END (as defined in the USB OTG Specification)(1) 0 = VBUS has not crossed VA_SESS_END bit 1 Unimplemented: Read as `0' bit 0 VBUSVDIF A-Device VBUS Change Indicator bit 1 = VBUS change on A-device detected; VBUS has crossed VA_VBUS_VLD (as defined in the USB OTG Specification)(1) 0 = No VBUS change on A-device detected Note 1: Note: VBUS threshold crossings may be either rising or falling. Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 215 PIC24FJ256GB110 FAMILY REGISTER 17-15: U1OTGIE: USB OTG INTERRUPT ENABLE REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 R/W-0 IDIE T1MSECIE LSTATEIE ACTVIE SESVDIE SESENDIE -- VBUSVDIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-8 Unimplemented: Read as `0' bit 7 IDIE: ID Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 6 T1MSECIE: 1 Millisecond Timer Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 5 LSTATEIE: Line State Stable Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 4 ACTVIE: Bus Activity Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 3 SESVDIE: Session Valid Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 2 SESENDIE: B-Device Session End Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 1 Unimplemented: Read as `0' bit 0 VBUSVDIE: A-Device VBUS Valid Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled DS39897B-page 216 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 17-16: U1IR: USB INTERRUPT STATUS REGISTER (DEVICE MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R/K-0, HS U-0 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R-0 R/K-0, HS STALLIF -- RESUMEIF IDLEIF TRNIF SOFIF UERRIF URSTIF bit 7 bit 0 Legend: U = Unimplemented bit, read as `0' R = Readable bit K = Write `1' to clear bit HS = Hardware Settable bit -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as `0' bit 7 STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent bit 6 Unimplemented: Read as `0' bit 5 RESUMEIF: Resume Interrupt bit 1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential `1' for low speed, differential `0' for full speed) 0 = No K-state observed bit 4 IDLEIF: Idle Detect Interrupt bit 1 = Idle condition detected (constant Idle state of 3 ms or more) 0 = No Idle condition detected bit 3 TRNIF: Token Processing Complete Interrupt bit 1 = Processing of current token is complete; read U1STAT register for endpoint information 0 = Processing of current token not complete; clear U1STAT register or load next token from STAT (clearing this bit causes the STAT FIFO to advance) bit 2 SOFIF: Start-Of-Frame Token Interrupt bit 1 = A Start-Of-Frame token received by the peripheral or the Start-Of-Frame threshold reached by the host 0 = No Start-Of-Frame token received or threshold reached bit 1 UERRIF: USB Error Condition Interrupt bit (read-only) 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred bit 0 URSTIF: USB Reset Interrupt bit 1 = Valid USB Reset has occurred for at least 2.5 s; Reset state must be cleared before this bit can be reasserted 0 = No USB Reset has occurred. Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Note: Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 217 PIC24FJ256GB110 FAMILY REGISTER 17-17: U1IR: USB INTERRUPT STATUS REGISTER (HOST MODE ONLY) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R/K-0, HS R-0 R/K-0, HS STALLIF ATTACHIF RESUMEIF IDLEIF TRNIF SOFIF UERRIF DETACHIF bit 7 bit 0 Legend: U = Unimplemented bit, read as `0' R = Readable bit K = Write `1' to clear bit HS = Hardware Settable bit -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as `0' bit 7 STALLIF: STALL Handshake Interrupt bit 1 = A STALL handshake was sent by the peripheral device during the handshake phase of the transaction in Device mode 0 = A STALL handshake has not been sent bit 6 ATTACHIF: Peripheral Attach Interrupt bit 1 = A peripheral attachment has been detected by the module; set if the bus state is not SE0 and there has been no bus activity for 2.5 s 0 = No peripheral attachement detected bit 5 RESUMEIF: Resume Interrupt bit 1 = A K-state is observed on the D+ or D- pin for 2.5 s (differential `1' for low speed, differential `0' for full speed) 0 = No K-state observed bit 4 IDLEIF: Idle Detect Interrupt bit 1 = Idle condition detected (constant Idle state of 3 ms or more) 0 = No Idle condition detected bit 3 TRNIF: Token Processing Complete Interrupt bit 1 = Processing of current token is complete; read U1STAT register for endpoint information 0 = Processing of current token not complete; clear U1STAT register or load next token from U1STAT bit 2 SOFIF: Start-Of-Frame Token Interrupt bit 1 = A Start-Of-Frame token received by the peripheral or the Start-Of-Frame threshold reached by the host 0 = No Start-Of-Frame token received or threshold reached bit 1 UERRIF: USB Error Condition Interrupt bit 1 = An unmasked error condition has occurred; only error states enabled in the U1EIE register can set this bit 0 = No unmasked error condition has occurred bit 0 DETACHIF: Detach Interrupt bit 1 = A peripheral detachment has been detected by the module; Reset state must be cleared before this bit can be reasserted 0 = No peripheral detachment detected. Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Note: Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. DS39897B-page 218 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 17-18: U1IE: USB INTERRUPT ENABLE REGISTER (ALL USB MODES) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R/W-0 R/W-0 STALLIE ATTACHIE (1) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 RESUMEIE IDLEIE TRNIE SOFIE UERRIE R/W-0 URSTIE DETACHIE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as `0' bit 7 STALLIE: STALL Handshake Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 6 ATTACHIE: Peripheral Attach Interrupt bit (Host mode only)(1) 1 = Interrupt enabled 0 = Interrupt disabled bit 5 RESUMEIE: Resume Interrupt bit 1 = Interrupt enabled 0 = Interrupt disabled bit 4 IDLEIE: Idle Detect Interrupt bit 1 = Interrupt enabled 0 = Interrupt disabled bit 3 TRNIE: Token Processing Complete Interrupt bit 1 = Interrupt enabled 0 = Interrupt disabled bit 2 SOFIE: Start-of-Frame Token Interrupt bit 1 = Interrupt enabled 0 = Interrupt disabled bit 1 UERRIE: USB Error Condition Interrupt bit 1 = Interrupt enabled 0 = Interrupt disabled bit 0 URSTIE or DETACHIE: USB Reset Interrupt (Device mode) or USB Detach Interrupt (Host mode) Enable bit 1 = Interrupt enabled 0 = Interrupt disabled Note 1: Unimplemented in Device mode, read as `0'. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 219 PIC24FJ256GB110 FAMILY REGISTER 17-19: U1EIR: USB ERROR INTERRUPT STATUS REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R/K-0, HS U-0 BTSEF -- R/K-0, HS DMAEF R/K-0, HS R/K-0, HS BTOEF DFN8EF R/K-0, HS CRC16EF R/K-0, HS CRC5EF EOFEF R/K-0, HS PIDEF bit 7 bit 0 Legend: U = Unimplemented bit, read as `0' R = Readable bit K = Write `1' to clear bit HS = Hardware Settable bit -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as `0' bit 7 BTSEF: Bit Stuff Error Flag bit 1 = Bit stuff error has been detected 0 = No bit stuff error bit 6 Unimplemented: Read as `0' bit 5 DMAEF: DMA Error Flag bit 1 = A USB DMA error condition detected; the data size indicated by the BD byte count field is less than the number of received bytes. The received data is truncated. 0 = No DMA error bit 4 BTOEF: Bus Turnaround Time-out Error Flag bit 1 = Bus turnaround time-out has occurred 0 = No bus turnaround time-out bit 3 DFN8EF: Data Field Size Error Flag bit 1 = Data field was not an integral number of bytes 0 = Data field was an integral number of bytes bit 2 CRC16EF: CRC16 Failure Flag bit 1 = CRC16 failed 0 = CRC16 passed bit 1 For Device mode: CRC5EF: CRC5 Host Error Flag bit 1 = Token packet rejected due to CRC5 error 0 = Token packet accepted (no CRC5 error) For Host mode: EOFEF: End-Of-Frame Error Flag bit 1 = End-Of-Frame error has occurred 0 = End-Of-Frame interrupt disabled bit 0 PIDEF: PID Check Failure Flag bit 1 = PID check failed 0 = PID check passed. Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. Note: Individual bits can only be cleared by writing a `1' to the bit position as part of a word write operation on the entire register. Using Boolean instructions or bitwise operations to write to a single bit position will cause all set bits at the moment of the write to become cleared. DS39897B-page 220 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 17-20: U1EIE: USB ERROR INTERRUPT ENABLE REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R/W-0 U-0 BTSEE R/W-0 -- DMAEE R/W-0 R/W-0 BTOEE DFN8EE R/W-0 CRC16EE R/W-0 CRC5EE EOFEE R/W-0 PIDEE bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-8 Unimplemented: Read as `0' bit 7 BTSEE: Bit Stuff Error Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 6 Unimplemented: Read as `0' bit 5 DMAEE: DMA Error Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 4 BTOEE: Bus Turnaround Time-out Error Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 3 DFN8EE: Data Field Size Error Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 2 CRC16EE: CRC16 Failure Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 1 For Device mode: CRC5EE: CRC5 Host Error Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled For Host mode: EOFEE: End-of-Frame Error interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled bit 0 PIDEE: PID Check Failure Interrupt Enable bit 1 = Interrupt enabled 0 = Interrupt disabled (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 221 PIC24FJ256GB110 FAMILY 17.7.3 USB ENDPOINT MANAGEMENT REGISTERS REGISTER 17-21: U1EPn: USB ENDPOINT CONTROL REGISTERS (n = 0 TO 15) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 LSPD(1) RETRYDIS(1) -- EPCONDIS EPRXEN EPTXEN EPSTALL EPHSHK bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as `0' bit 7 LSPD: Low-Speed Direct Connection Enable bit (U1EP0 only)(1) 1 = Direct connection to a low-speed device enabled 0 = Direct connection to a low-speed device disabled bit 6 RETRYDIS: Retry Disable bit (U1EP0 only)(1) 1 = Retry NAK transactions disabled 0 = Retry NAK transactions enabled; retry done in hardware bit 5 Unimplemented: Read as `0' bit 4 EPCONDIS: Bidirectional Endpoint Control bit If EPTXEN and EPRXEN = 1: 1 = Disable Endpoint n from Control transfers; only Tx and Rx transfers allowed 0 = Enable Endpoint n for Control (SETUP) transfers; Tx and Rx transfers also allowed. For all other combinations of EPTXEN and EPRXEN: This bit is ignored. bit 3 EPRXEN: Endpoint Receive Enable bit 1 = Endpoint n receive enabled 0 = Endpoint n receive disabled bit 2 EPTXEN: Endpoint Transmit Enable bit 1 = Endpoint n transmit enabled 0 = Endpoint n transmit disabled bit 1 EPSTALL: Endpoint Stall Status bit 1 = Endpoint n was stalled 0 = Endpoint n was not stalled bit 0 EPHSHK: Endpoint Handshake Enable bit 1 = Endpoint handshake enabled 0 = Endpoint handshake disabled (typically used for isochronous endpoints) Note 1: These bits are available only for U1EP0, and only in Host mode. For all other U1EPn registers, these bits are always unimplemented and read as `0'. DS39897B-page 222 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 17.7.4 USB VBUS POWER CONTROL REGISTER REGISTER 17-22: U1PWMCON: USB VBUS PWM GENERATOR CONTROL REGISTER R/W-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 PWMEN -- -- -- -- -- PWMPOL CNTEN bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 PWMEN: PWM Enable bit 1 = PWM generator is enabled 0 = PWM generator is disabled; output is held in Reset state specified by PWMPOL bit 14-10 Unimplemented: Read as `0' bit 9 PWMPOL: PWM Polarity bit 1 = PWM output is active-low and resets high 0 = PWM output is active-high and resets low bit 8 CNTEN: PWM Counter Enable bit 1 = Counter is enabled 0 = Counter is disabled bit 7-0 Unimplemented: Read as `0' (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 223 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 224 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 18.0 Note: PARALLEL MASTER PORT (PMP) Key features of the PMP module include: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 13. Parallel Master Port (PMP)" (DS39713). The Parallel Master Port (PMP) module is a parallel 8-bit I/O module, specifically designed to communicate with a wide variety of parallel devices, such as communication peripherals, LCDs, external memory devices and microcontrollers. Because the interface to parallel peripherals varies significantly, the PMP is highly configurable. FIGURE 18-1: * Up to 16 Programmable Address Lines * Up to 2 Chip Select Lines * Programmable Strobe Options: - Individual Read and Write Strobes or; - Read/Write Strobe with Enable Strobe * Address Auto-Increment/Auto-Decrement * Programmable Address/Data Multiplexing * Programmable Polarity on Control Signals * Legacy Parallel Slave Port Support * Enhanced Parallel Slave Support: - Address Support - 4-Byte Deep Auto-Incrementing Buffer * Programmable Wait States * Selectable Input Voltage Levels PMP MODULE OVERVIEW Address Bus Data Bus Control Lines PIC24F Parallel Master Port PMA<0> PMALL PMA<1> PMALH Up to 16-Bit Address PMA<13:2> EEPROM PMA<14> PMCS1 PMA<15> PMCS2 PMBE PMRD PMRD/PMWR Microcontroller LCD FIFO Buffer PMWR PMENB PMD<7:0> PMA<7:0> PMA<15:8> (c) 2008 Microchip Technology Inc. Preliminary 8-Bit Data DS39897B-page 225 PIC24FJ256GB110 FAMILY REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0(1) R/W-0(1) R/W-0 R/W-0 R/W-0 PMPEN -- PSIDL ADRMUX1 ADRMUX0 PTBEEN PTWREN PTRDEN bit 15 bit 8 R/W-0 R/W-0 R/W-0(1) R/W-0(1) R/W-0(1) R/W-0 R/W-0 R/W-0 CSF1 CSF0 ALP CS2P CS1P BEP WRSP RDSP bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 PMPEN: Parallel Master Port Enable bit 1 = PMP enabled 0 = PMP disabled, no off-chip access performed bit 14 Unimplemented: Read as `0' bit 13 PSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-11 ADRMUX1:ADRMUX0: Address/Data Multiplexing Selection bits(1) 11 = Reserved 10 = All 16 bits of address are multiplexed on PMD<7:0> pins 01 = Lower 8 bits of address are multiplexed on PMD<7:0> pins, upper 3 bits are multiplexed on PMA<10:8> 00 = Address and data appear on separate pins bit 10 PTBEEN: Byte Enable Port Enable bit (16-Bit Master mode) 1 = PMBE port enabled 0 = PMBE port disabled bit 9 PTWREN: Write Enable Strobe Port Enable bit 1 = PMWR/PMENB port enabled 0 = PMWR/PMENB port disabled bit 8 PTRDEN: Read/Write Strobe Port Enable bit 1 = PMRD/PMWR port enabled 0 = PMRD/PMWR port disabled bit 7-6 CSF1:CSF0: Chip Select Function bits 11 = Reserved 10 = PMCS1 functions as chip set 01 = Reserved 00 = Reserved bit 5 ALP: Address Latch Polarity bit(1) 1 = Active-high (PMALL and PMALH) 0 = Active-low (PMALL and PMALH) bit 4 CS2P: Chip Select 2 Polarity bit(1) 1 = Active-high (PMCS2/PMCS2) 0 = Active-low (PMCS2/PMCS2) bit 3 CS1P: Chip Select 1 Polarity bit(1) 1 = Active-high (PMCS1/PMCS1) 0 = Active-low (PMCS1/PMCS1) Note 1: These bits have no effect when their corresponding pins are used as address lines. DS39897B-page 226 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 18-1: PMCON: PARALLEL PORT CONTROL REGISTER (CONTINUED) bit 2 BEP: Byte Enable Polarity bit 1 = Byte enable active-high (PMBE) 0 = Byte enable active-low (PMBE) bit 1 WRSP: Write Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Write strobe active-high (PMWR) 0 = Write strobe active-low (PMWR) For Master mode 1 (PMMODE<9:8> = 11): 1 = Enable strobe active-high (PMENB) 0 = Enable strobe active-low (PMENB) bit 0 RDSP: Read Strobe Polarity bit For Slave modes and Master mode 2 (PMMODE<9:8> = 00,01,10): 1 = Read strobe active-high (PMRD) 0 = Read strobe active-low (PMRD) For Master mode 1 (PMMODE<9:8> = 11): 1 = Read/write strobe active-high (PMRD/PMWR) 0 = Read/write strobe active-low (PMRD/PMWR) Note 1: These bits have no effect when their corresponding pins are used as address lines. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 227 PIC24FJ256GB110 FAMILY REGISTER 18-2: PMMODE: PARALLEL PORT MODE REGISTER R-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUSY IRQM1 IRQM0 INCM1 INCM0 MODE16 MODE1 MODE0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 WAITB1(1) WAITB0(1) WAITM3 WAITM2 WAITM1 WAITM0 WAITE1(1) WAITE0(1) bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 BUSY: Busy bit (Master mode only) 1 = Port is busy (not useful when the processor stall is active) 0 = Port is not busy bit 14-13 IRQM1:IRQM0: Interrupt Request Mode bits 11 = Interrupt generated when Read Buffer 3 is read or Write Buffer 3 is written (Buffered PSP mode) or on a read or write operation when PMA<1:0> = 11 (Addressable PSP mode only) 10 = No interrupt generated, processor stall activated 01 = Interrupt generated at the end of the read/write cycle 00 = No interrupt generated bit 12-11 INCM1:INCM0: Increment Mode bits 11 = PSP read and write buffers auto-increment (Legacy PSP mode only) 10 = Decrement ADDR<10:0> by 1 every read/write cycle 01 = Increment ADDR<10:0> by 1 every read/write cycle 00 = No increment or decrement of address bit 10 MODE16: 8/16-Bit Mode bit 1 = 16-bit mode: Data register is 16 bits, a read or write to the Data register invokes two 8-bit transfers 0 = 8-bit mode: Data register is 8 bits, a read or write to the Data register invokes one 8-bit transfer bit 9-8 MODE1:MODE0: Parallel Port Mode Select bits 11 = Master mode 1 (PMCS1, PMRD/PMWR, PMENB, PMBE, PMA<x:0> and PMD<7:0>) 10 = Master mode 2 (PMCS1, PMRD, PMWR, PMBE, PMA<x:0> and PMD<7:0>) 01 = Enhanced PSP, control signals (PMRD, PMWR, PMCS1, PMD<7:0> and PMA<1:0>) 00 = Legacy Parallel Slave Port, control signals (PMRD, PMWR, PMCS1 and PMD<7:0>) bit 7-6 WAITB1:WAITB0: Data Setup to Read/Write Wait State Configuration bits(1) 11 = Data wait of 4 TCY; multiplexed address phase of 4 TCY 10 = Data wait of 3 TCY; multiplexed address phase of 3 TCY 01 = Data wait of 2 TCY; multiplexed address phase of 2 TCY 00 = Data wait of 1 TCY; multiplexed address phase of 1 TCY bit 5-2 WAITM3:WAITM0: Read to Byte Enable Strobe Wait State Configuration bits 1111 = Wait of additional 15 TCY ... 0001 = Wait of additional 1 TCY 0000 = No additional wait cycles (operation forced into one TCY)(2) bit 1-0 WAITE1:WAITE0: Data Hold After Strobe Wait State Configuration bits(1) 11 = Wait of 4 TCY 10 = Wait of 3 TCY 01 = Wait of 2 TCY 00 = Wait of 1 TCY Note 1: 2: WAITB and WAITE bits are ignored whenever WAITM3:WAITM0 = 0000. A single-cycle delay is required between consecutive read and/or write operations. DS39897B-page 228 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 18-3: PMADDR: PARALLEL PORT ADDRESS REGISTER R/W-0 R/W-0 CS2 CS1 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<13:8> bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADDR<7:0> bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 CS2: Chip Select 2 bit 1 = Chip select 2 is active 0 = Chip select 2 is inactive bit 14 CS1: Chip Select 1 bit 1 = Chip select 1 is active 0 = Chip select 1 is inactive bit 13-0 ADDR13:ADDR0: Parallel Port Destination Address bits REGISTER 18-4: x = Bit is unknown PMAEN: PARALLEL PORT ENABLE REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN15 PTEN14 PTEN13 PTEN12 PTEN11 PTEN10 PTEN9 PTEN8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PTEN7 PTEN6 PTEN5 PTEN4 PTEN3 PTEN2 PTEN1 PTEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 PTEN15:PTEN14: PMCSx Strobe Enable bit 1 = PMA15 and PMA14 function as either PMA<15:14> or PMCS2 and PMCS1 0 = PMA15 and PMA14 function as port I/O bit 13-2 PTEN13:PTEN2: PMP Address Port Enable bits 1 = PMA<13:2> function as PMP address lines 0 = PMA<13:2> function as port I/O bit 1-0 PTEN1:PTEN0: PMALH/PMALL Strobe Enable bits 1 = PMA1 and PMA0 function as either PMA<1:0> or PMALH and PMALL 0 = PMA1 and PMA0 pads functions as port I/O (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 229 PIC24FJ256GB110 FAMILY REGISTER 18-5: PMSTAT: PARALLEL PORT STATUS REGISTER R-0 R/W-0, HS U-0 U-0 R-0 R-0 R-0 R-0 IBF IBOV -- -- IB3F IB2F IB1F IB0F bit 15 bit 8 R-1 R/W-0, HS U-0 U-0 R-1 R-1 R-1 R-1 OBE OBUF -- -- OB3E OB2E OB1E OB0E bit 7 bit 0 Legend: HS = Hardware Set bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 IBF: Input Buffer Full Status bit 1 = All writable input buffer registers are full 0 = Some or all of the writable input buffer registers are empty bit 14 IBOV: Input Buffer Overflow Status bit 1 = A write attempt to a full input byte register occurred (must be cleared in software) 0 = No overflow occurred bit 13-12 Unimplemented: Read as `0' bit 11-8 IB3F:IB0F Input Buffer x Status Full bits 1 = Input buffer contains data that has not been read (reading buffer will clear this bit) 0 = Input buffer does not contain any unread data bit 7 OBE: Output Buffer Empty Status bit 1 = All readable output buffer registers are empty 0 = Some or all of the readable output buffer registers are full bit 6 OBUF: Output Buffer Underflow Status bits 1 = A read occurred from an empty output byte register (must be cleared in software) 0 = No underflow occurred bit 5-4 Unimplemented: Read as `0' bit 3-0 OB3E:OB0E Output Buffer x Status Empty bit 1 = Output buffer is empty (writing data to the buffer will clear this bit) 0 = Output buffer contains data that has not been transmitted DS39897B-page 230 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 18-6: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 U-0 -- U-0 -- -- U-0 -- U-0 -- U-0 -- R/W-0 R/W-0 (1) RTSECSEL PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-2 Unimplemented: Read as `0' bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = PMP module inputs use Schmitt Trigger input buffers Note 1: x = Bit is unknown To enable the actual RTCC output, the RTCOE (RCFGCAL<10>)) bit must also be set. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 231 PIC24FJ256GB110 FAMILY FIGURE 18-2: LEGACY PARALLEL SLAVE PORT EXAMPLE Master PIC24F Slave PMD<7:0> FIGURE 18-3: PMD<7:0> PMCS1 PMCS1 PMRD PMRD PMWR PMWR Address Bus Data Bus Control Lines ADDRESSABLE PARALLEL SLAVE PORT EXAMPLE Master PIC24F Slave PMA<1:0> PMA<1:0> PMD<7:0> PMD<7:0> Write Address Decode Read Address Decode PMDOUT1L (0) PMDIN1L (0) PMCS1 PMCS1 PMDOUT1H (1) PMDIN1H (1) PMRD PMRD PMDOUT2L (2) PMDIN2L (2) PMWR PMWR PMDOUT2H (3) PMDIN2H (3) Address Bus Data Bus Control Lines TABLE 18-1: SLAVE MODE ADDRESS RESOLUTION PMA<1:0> Output Register (Buffer) Input Register (Buffer) 00 PMDOUT1<7:0> (0) PMDIN1<7:0> (0) 01 PMDOUT1<15:8> (1) PMDIN1<15:8> (1) 10 PMDOUT2<7:0> (2) PMDIN2<7:0> (2) 11 PMDOUT2<15:8> (3) PMDIN2<15:8> (3) FIGURE 18-4: MASTER MODE, DEMULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC24F PMA<13:0> PMD<7:0> PMCS1 PMCS2 DS39897B-page 232 Address Bus PMRD Data Bus PMWR Control Lines Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY FIGURE 18-5: MASTER MODE, PARTIALLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PIC24F PMA<13:8> PMD<7:0> PMA<7:0> PMCS1 Address Bus PMCS2 Multiplexed Data and Address Bus PMALL PMRD Control Lines PMWR FIGURE 18-6: MASTER MODE, FULLY MULTIPLEXED ADDRESSING (SEPARATE READ AND WRITE STROBES, TWO CHIP SELECTS) PMD<7:0> PMA<13:8> PIC24F PMCS1 PMCS2 PMALL PMALH Multiplexed Data and Address Bus PMRD Control Lines PMWR FIGURE 18-7: EXAMPLE OF A MULTIPLEXED ADDRESSING APPLICATION PIC24F PMD<7:0> PMALL 373 A<7:0> D<7:0> 373 PMALH A<15:8> A<15:0> D<7:0> CE OE WR PMCS1 FIGURE 18-8: Address Bus PMRD Data Bus PMWR Control Lines EXAMPLE OF A PARTIALLY MULTIPLEXED ADDRESSING APPLICATION PIC24F PMD<7:0> 373 PMALL PMA<10:8> A<7:0> D<7:0> A<10:8> D<7:0> CE OE PMCS1 WR Address Bus Data Bus PMRD Control Lines PMWR (c) 2008 Microchip Technology Inc. A<10:0> Preliminary DS39897B-page 233 PIC24FJ256GB110 FAMILY FIGURE 18-9: EXAMPLE OF AN 8-BIT MULTIPLEXED ADDRESS AND DATA APPLICATION PIC24F Parallel Peripheral PMD<7:0> PMALL AD<7:0> ALE PMCS1 CS Address Bus PMRD RD Data Bus PMWR WR Control Lines FIGURE 18-10: PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 8-BIT DATA) PIC24F PMA<n:0> Parallel EEPROM A<n:0> PMD<7:0> D<7:0> PMCS1 CE PMRD OE PMWR WR FIGURE 18-11: Address Bus Data Bus Control Lines PARALLEL EEPROM EXAMPLE (UP TO 15-BIT ADDRESS, 16-BIT DATA) PIC24F Parallel EEPROM PMA<n:0> A<n:1> PMD<7:0> D<7:0> PMBE A0 PMCS1 CE PMRD OE PMWR WR FIGURE 18-12: Address Bus Data Bus Control Lines LCD CONTROL EXAMPLE (BYTE MODE OPERATION) PIC24F PM<7:0> PMA0 PMRD/PMWR PMCS1 LCD Controller D<7:0> RS R/W E Address Bus Data Bus Control Lines DS39897B-page 234 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 19.0 Note: REAL-TIME CLOCK AND CALENDAR (RTCC) This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 29. Real-Time Clock and Calendar (RTCC)" (DS39696). FIGURE 19-1: RTCC BLOCK DIAGRAM RTCC Clock Domain 32.768 kHz Input from SOSC Oscillator CPU Clock Domain RCFGCAL RTCC Prescalers ALCFGRPT YEAR 0.5s RTCVAL RTCC Timer Alarm Event MTHDY WKDYHR MINSEC Comparator ALMTHDY Compare Registers with Masks ALRMVAL ALWDHR ALMINSEC Repeat Counter RTCC Interrupt RTCC Interrupt Logic Alarm Pulse RTCC Pin RTCOE (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 235 PIC24FJ256GB110 FAMILY 19.1 RTCC Module Registers TABLE 19-2: The RTCC module registers are organized into three categories: * RTCC Control Registers * RTCC Value Registers * Alarm Value Registers 19.1.1 ALRMPTR <1:0> To limit the register interface, the RTCC Timer and Alarm Time registers are accessed through corresponding register pointers. The RTCC Value register window (RTCVALH and RTCVALL) uses the RTCPTR bits (RCFGCAL<9:8>) to select the desired Timer register pair (see Table 19-1). By writing the RTCVALH byte, the RTCC Pointer value, RTCPTR<1:0> bits, decrement by one until they reach `00'. Once they reach `00', the MINUTES and SECONDS value will be accessible through RTCVALH and RTCVALL until the pointer value is manually changed. TABLE 19-1: RTCPTR <1:0> RTCVAL REGISTER MAPPING RTCC Value Register Window RTCVAL<15:8> RTCVAL<7:0> 00 MINUTES SECONDS 01 WEEKDAY HOURS 10 MONTH DAY 11 -- YEAR The Alarm Value register window (ALRMVALH and ALRMVALL) uses the ALRMPTR bits (ALCFGRPT<9:8>) to select the desired Alarm register pair (see Table 19-2). Alarm Value Register Window ALRMVAL<15:8> ALRMVAL<7:0> ALRMMIN 00 REGISTER MAPPING ALRMVAL REGISTER MAPPING ALRMSEC 01 ALRMWD ALRMHR 10 ALRMMNTH ALRMDAY 11 -- -- Considering that the 16-bit core does not distinguish between 8-bit and 16-bit read operations, the user must be aware that when reading either the ALRMVALH or ALRMVALL bytes will decrement the ALRMPTR<1:0> value. The same applies to the RTCVALH or RTCVALL bytes with the RTCPTR<1:0> being decremented. Note: 19.1.2 This only applies to read operations and not write operations. WRITE LOCK In order to perform a write to any of the RTCC Timer registers, the RTCWREN bit (RCFGCAL<13>) must be set (refer to Example 19-1). Note: To avoid accidental writes to the timer, it is recommended that the RTCWREN bit (RCFGCAL<13>) is kept clear at any other time. For the RTCWREN bit to be set, there is only 1 instruction cycle time window allowed between the unlock sequence and the setting of RTCWREN; therefore, it is recommended that code follow the procedure in Example 19-1. For applications written in C, the unlock sequence should be implemented using in-line assembly. By writing the ALRMVALH byte, the Alarm Pointer value, ALRMPTR<1:0> bits, decrement by one until they reach `00'. Once they reach `00', the ALRMMIN and ALRMSEC value will be accessible through ALRMVALH and ALRMVALL until the pointer value is manually changed. EXAMPLE 19-1: asm asm asm asm asm asm SETTING THE RTCWREN BIT volatile("disi #5"); volatile("mov #0x55, w7"); volatile("mov w7, _NVMKEY"); volatile("mov #0xAA, w8"); volatile("mov w8, _NVMKEY"); volatile("bset _RCFGCAL, #13"); DS39897B-page 236 //set the RTCWREN bit Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 19.1.3 RTCC CONTROL REGISTERS RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) REGISTER 19-1: R/W-0 RTCEN U-0 (2) R/W-0 -- RTCWREN R-0 RTCSYNC R-0 (3) HALFSEC R/W-0 R/W-0 R/W-0 RTCOE RTCPTR1 RTCPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CAL7 CAL6 CAL5 CAL4 CAL3 CAL2 CAL1 CAL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 RTCEN: RTCC Enable bit(2) 1 = RTCC module is enabled 0 = RTCC module is disabled bit 14 Unimplemented: Read as `0' bit 13 RTCWREN: RTCC Value Registers Write Enable bit 1 = RTCVALH and RTCVALL registers can be written to by the user 0 = RTCVALH and RTCVALL registers are locked out from being written to by the user bit 12 RTCSYNC: RTCC Value Registers Read Synchronization bit 1 = RTCVALH, RTCVALL and ALCFGRPT registers can change while reading due to a rollover ripple resulting in an invalid data read. If the register is read twice and results in the same data, the data can be assumed to be valid. 0 = RTCVALH, RTCVALL or ALCFGRPT registers can be read without concern over a rollover ripple bit 11 HALFSEC: Half-Second Status bit(3) 1 = Second half period of a second 0 = First half period of a second bit 10 RTCOE: RTCC Output Enable bit 1 = RTCC output enabled 0 = RTCC output disabled bit 9-8 RTCPTR1:RTCPTR0: RTCC Value Register Window Pointer bits Points to the corresponding RTCC Value registers when reading RTCVALH and RTCVALL registers; the RTCPTR<1:0> value decrements on every read or write of RTCVALH until it reaches `00'. RTCVAL<15:8>: 00 = MINUTES 01 = WEEKDAY 10 = MONTH 11 = Reserved RTCVAL<7:0>: 00 = SECONDS 01 = HOURS 10 = DAY 11 = YEAR Note 1: 2: 3: The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to `0' on a write to the lower half of the MINSEC register. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 237 PIC24FJ256GB110 FAMILY REGISTER 19-1: bit 7-0 Note 1: 2: 3: RCFGCAL: RTCC CALIBRATION AND CONFIGURATION REGISTER(1) (CONTINUED) CAL7:CAL0: RTC Drift Calibration bits 01111111 = Maximum positive adjustment; adds 508 RTC clock pulses every one minute ... 01111111 = Minimum positive adjustment; adds 4 RTC clock pulses every one minute 00000000 = No adjustment 11111111 = Minimum negative adjustment; subtracts 4 RTC clock pulses every one minute ... 10000000 = Maximum negative adjustment; subtracts 512 RTC clock pulses every one minute The RCFGCAL register is only affected by a POR. A write to the RTCEN bit is only allowed when RTCWREN = 1. This bit is read-only. It is cleared to `0' on a write to the lower half of the MINSEC register. REGISTER 19-2: PADCFG1: PAD CONFIGURATION CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- -- -- -- RTSECSEL(1) PMPTTL bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-2 Unimplemented: Read as `0' bit 1 RTSECSEL: RTCC Seconds Clock Output Select bit(1) 1 = RTCC seconds clock is selected for the RTCC pin 0 = RTCC alarm pulse is selected for the RTCC pin bit 0 PMPTTL: PMP Module TTL Input Buffer Select bit 1 = PMP module inputs (PMDx, PMCS1) use TTL input buffers 0 = PMP module inputs use Schmitt Trigger input buffers Note 1: x = Bit is unknown To enable the actual RTCC output, the RTCOE (RCFGCAL<10>)) bit must also be set. DS39897B-page 238 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 19-3: ALCFGRPT: ALARM CONFIGURATION REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ALRMEN CHIME AMASK3 AMASK2 AMASK1 AMASK0 ALRMPTR1 ALRMPTR0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ARPT7 ARPT6 ARPT5 ARPT4 ARPT3 ARPT2 ARPT1 ARPT0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 ALRMEN: Alarm Enable bit 1 = Alarm is enabled (cleared automatically after an alarm event whenever ARPT<7:0> = 00h and CHIME = 0) 0 = Alarm is disabled bit 14 CHIME: Chime Enable bit 1 = Chime is enabled; ARPT<7:0> bits are allowed to roll over from 00h to FFh 0 = Chime is disabled; ARPT<7:0> bits stop once they reach 00h bit 13-10 AMASK3:AMASK0: Alarm Mask Configuration bits 0000 = Every half second 0001 = Every second 0010 = Every 10 seconds 0011 = Every minute 0100 = Every 10 minutes 0101 = Every hour 0110 = Once a day 0111 = Once a week 1000 = Once a month 1001 = Once a year (except when configured for February 29th, once every 4 years) 101x = Reserved - do not use 11xx = Reserved - do not use bit 9-8 ALRMPTR1:ALRMPTR0: Alarm Value Register Window Pointer bits Points to the corresponding Alarm Value registers when reading ALRMVALH and ALRMVALL registers; the ALRMPTR<1:0> value decrements on every read or write of ALRMVALH until it reaches `00'. ALRMVAL<15:8>: 00 = ALRMMIN 01 = ALRMWD 10 = ALRMMNTH 11 = Unimplemented ALRMVAL<7:0>: 00 = ALRMSEC 01 = ALRMHR 10 = ALRMDAY 11 = Unimplemented bit 7-0 ARPT7:ARPT0: Alarm Repeat Counter Value bits 11111111 = Alarm will repeat 255 more times ... 00000000 = Alarm will not repeat The counter decrements on any alarm event. The counter is prevented from rolling over from 00h to FFh unless CHIME = 1. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 239 PIC24FJ256GB110 FAMILY 19.1.4 RTCVAL REGISTER MAPPINGS YEAR: YEAR VALUE REGISTER(1) REGISTER 19-4: U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x YRTEN3 YRTEN2 YRTEN1 YRTEN0 YRONE3 YRONE2 YRONE1 YRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as `0' bit 7-4 YRTEN3:YRTEN0: Binary Coded Decimal Value of Year's Tens Digit; Contains a value from 0 to 9 bit 3-0 YRONE3:YRONE0: Binary Coded Decimal Value of Year's Ones Digit; Contains a value from 0 to 9 Note 1: A write to the YEAR register is only allowed when RTCWREN = 1. REGISTER 19-5: MTHDY: MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R-x R-x R-x R-x R-x -- -- -- MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x -- -- DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as `0' bit 12 MTHTEN0: Binary Coded Decimal Value of Month's Tens Digit; Contains a value of 0 or 1 bit 11-8 MTHONE3:MTHONE0: Binary Coded Decimal Value of Month's Ones Digit; Contains a value from 0 to 9 bit 7-6 Unimplemented: Read as `0' bit 5-4 DAYTEN1:DAYTEN0: Binary Coded Decimal Value of Day's Tens Digit; Contains a value from 0 to 3 bit 3-0 DAYONE3:DAYONE0: Binary Coded Decimal Value of Day's Ones Digit; Contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN = 1. DS39897B-page 240 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY WKDYHR: WEEKDAY AND HOURS VALUE REGISTER(1) REGISTER 19-6: U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x -- -- -- -- -- WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x -- -- HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as `0' bit 10-8 WDAY2:WDAY0: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6 bit 7-6 Unimplemented: Read as `0' bit 5-4 HRTEN1:HRTEN0: Binary Coded Decimal Value of Hour's Tens Digit; Contains a value from 0 to 2 bit 3-0 HRONE3:HRONE0: Binary Coded Decimal Value of Hour's Ones Digit; Contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN = 1. REGISTER 19-7: MINSEC: MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x -- MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x -- SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as `0' bit 14-12 MINTEN2:MINTEN0: Binary Coded Decimal Value of Minute's Tens Digit; Contains a value from 0 to 5 bit 11-8 MINONE3:MINONE0: Binary Coded Decimal Value of Minute's Ones Digit; Contains a value from 0 to 9 bit 7 Unimplemented: Read as `0' bit 6-4 SECTEN2:SECTEN0: Binary Coded Decimal Value of Second's Tens Digit; Contains a value from 0 to 5 bit 3-0 SECONE3:SECONE0: Binary Coded Decimal Value of Second's Ones Digit; Contains a value from 0 to 9 (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 241 PIC24FJ256GB110 FAMILY 19.1.5 ALRMVAL REGISTER MAPPINGS REGISTER 19-8: ALMTHDY: ALARM MONTH AND DAY VALUE REGISTER(1) U-0 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x -- -- -- MTHTEN0 MTHONE3 MTHONE2 MTHONE1 MTHONE0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x -- -- DAYTEN1 DAYTEN0 DAYONE3 DAYONE2 DAYONE1 DAYONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-13 Unimplemented: Read as `0' bit 12 MTHTEN0: Binary Coded Decimal Value of Month's Tens Digit; Contains a value of 0 or 1 bit 11-8 MTHONE3:MTHONE0: Binary Coded Decimal Value of Month's Ones Digit; Contains a value from 0 to 9 bit 7-6 Unimplemented: Read as `0' bit 5-4 DAYTEN1:DAYTEN0: Binary Coded Decimal Value of Day's Tens Digit; Contains a value from 0 to 3 bit 3-0 DAYONE3:DAYONE0: Binary Coded Decimal Value of Day's Ones Digit; Contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN = 1. REGISTER 19-9: ALWDHR: ALARM WEEKDAY AND HOURS VALUE REGISTER(1) U-0 U-0 U-0 U-0 U-0 R/W-x R/W-x R/W-x -- -- -- -- -- WDAY2 WDAY1 WDAY0 bit 15 bit 8 U-0 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x -- -- HRTEN1 HRTEN0 HRONE3 HRONE2 HRONE1 HRONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-11 Unimplemented: Read as `0' bit 10-8 WDAY2:WDAY0: Binary Coded Decimal Value of Weekday Digit; Contains a value from 0 to 6 bit 7-6 Unimplemented: Read as `0' bit 5-4 HRTEN1:HRTEN0: Binary Coded Decimal Value of Hour's Tens Digit; Contains a value from 0 to 2 bit 3-0 HRONE3:HRONE0: Binary Coded Decimal Value of Hour's Ones Digit; Contains a value from 0 to 9 Note 1: A write to this register is only allowed when RTCWREN = 1. DS39897B-page 242 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 19-10: ALMINSEC: ALARM MINUTES AND SECONDS VALUE REGISTER U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x -- MINTEN2 MINTEN1 MINTEN0 MINONE3 MINONE2 MINONE1 MINONE0 bit 15 bit 8 U-0 R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x R/W-x -- SECTEN2 SECTEN1 SECTEN0 SECONE3 SECONE2 SECONE1 SECONE0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 Unimplemented: Read as `0' bit 14-12 MINTEN2:MINTEN0: Binary Coded Decimal Value of Minute's Tens Digit; Contains a value from 0 to 5 bit 11-8 MINONE3:MINONE0: Binary Coded Decimal Value of Minute's Ones Digit; Contains a value from 0 to 9 bit 7 Unimplemented: Read as `0' bit 6-4 SECTEN2:SECTEN0: Binary Coded Decimal Value of Second's Tens Digit; Contains a value from 0 to 5 bit 3-0 SECONE3:SECONE0: Binary Coded Decimal Value of Second's Ones Digit; Contains a value from 0 to 9 19.2 Calibration 3. The real-time crystal input can be calibrated using the periodic auto-adjust feature. When properly calibrated, the RTCC can provide an error of less than 3 seconds per month. This is accomplished by finding the number of error clock pulses for one minute and storing the value into the lower half of the RCFGCAL register. The 8-bit signed value loaded into the lower half of RCFGCAL is multiplied by four and will be either added or subtracted from the RTCC timer, once every minute. Refer to the steps below for RTCC calibration: 1. 2. Using another timer resource on the device, the user must find the error of the 32.768 kHz crystal. Once the error is known, it must be converted to the number of error clock pulses per minute and loaded into the RCFGCAL register. EQUATION 19-1: RTCC CALIBRATION Error (clocks per minute) =(Ideal Frequency - Measured Frequency) * 60 Ideal frequency = 32,768 Hz (c) 2008 Microchip Technology Inc. a) If the oscillator is faster then ideal (negative result form step 2), the RCFGCAL register value needs to be negative. This causes the specified number of clock pulses to be subtracted from the timer counter once every minute. b) If the oscillator is slower then ideal (positive result from step 2) the RCFGCAL register value needs to be positive. This causes the specified number of clock pulses to be subtracted from the timer counter once every minute. 4. Divide the number of error clocks per minute by 4 to get the correct CAL value and load the RCFGCAL register with the correct value. (Each 1-bit increment in CAL adds or subtracts 4 pulses). Writes to the lower half of the RCFGCAL register should only occur when the timer is turned off, or immediately after the rising edge of the seconds pulse. Note: Preliminary It is up to the user to include in the error value the initial error of the crystal, drift due to temperature and drift due to crystal aging. DS39897B-page 243 PIC24FJ256GB110 FAMILY 19.3 Alarm After each alarm is issued, the value of the ARPT bits is decremented by one. Once the value has reached 00h, the alarm will be issued one last time, after which the ALRMEN bit will be cleared automatically and the alarm will turn off. * Configurable from half second to one year * Enabled using the ALRMEN bit (ALCFGRPT<15>, Register 19-3) * One-time alarm and repeat alarm options available 19.3.1 Indefinite repetition of the alarm can occur if the CHIME bit = 1. Instead of the alarm being disabled when the value of the ARPT bits reaches 00h, it rolls over to FFh and continues counting indefinitely while CHIME is set. CONFIGURING THE ALARM The alarm feature is enabled using the ALRMEN bit. This bit is cleared when an alarm is issued. Writes to ALRMVAL should only take place when ALRMEN = 0. 19.3.2 At every alarm event, an interrupt is generated. In addition, an alarm pulse output is provided that operates at half the frequency of the alarm. This output is completely synchronous to the RTCC clock and can be used as a trigger clock to other peripherals. As shown in Figure 19-2, the interval selection of the alarm is configured through the AMASK bits (ALCFGRPT<13:10>). These bits determine which and how many digits of the alarm must match the clock value for the alarm to occur. Note: The alarm can also be configured to repeat based on a preconfigured interval. The amount of times this occurs once the alarm is enabled is stored in the ARPT bits, ARPT7:ARPT0 (ALCFGRPT<7:0>). When the value of the ARPT bits equals 00h and the CHIME bit (ALCFGRPT<14>) is cleared, the repeat function is disabled and only a single alarm will occur. The alarm can be repeated up to 255 times by loading ARPT7:ARPT0 with FFh. FIGURE 19-2: ALARM INTERRUPT Changing any of the registers, other then the RCFGCAL and ALCFGRPT registers and the CHIME bit while the alarm is enabled (ALRMEN = 1), can result in a false alarm event leading to a false alarm interrupt. To avoid a false alarm event, the timer and alarm values should only be changed while the alarm is disabled (ALRMEN = 0). It is recommended that the ALCFGRPT register and CHIME bit be changed when RTCSYNC = 0. ALARM MASK SETTINGS Alarm Mask Setting (AMASK3:AMASK0) Day of the Week Month Day Hours Minutes Seconds 0000 - Every half second 0001 - Every second 0010 - Every 10 seconds s 0011 - Every minute s s m s s m m s s 0100 - Every 10 minutes 0101 - Every hour 0110 - Every day 0111 - Every week d 1000 - Every month 1001 - Every year(1) Note 1: DS39897B-page 244 m m h h m m s s h h m m s s d d h h m m s s d d h h m m s s Annually, except when configured for February 29. Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 20.0 PROGRAMMABLE CYCLIC REDUNDANCY CHECK (CRC) GENERATOR Note: Consider the CRC equation: x16 + x12 + x5 + 1 To program this polynomial into the CRC generator, the CRC register bits should be set as shown in Table 20-1. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 30. Programmable Cyclic Redundancy Check (CRC)" (DS39714). TABLE 20-1: The programmable CRC generator offers the following features: Bit Name Bit Value PLEN3:PLEN0 1111 X15:X1 000100000010000 Note that for the value of X15:X1, the 12th bit and the 5th bit are set to `1', as required by the equation. The 0 bit required by the equation is always XORed. For a 16-bit polynomial, the 16th bit is also always assumed to be XORed; therefore, the X<15:1> bits do not have the 0 bit or the 16th bit. * User-programmable polynomial CRC equation * Interrupt output * Data FIFO The module implements a software configurable CRC generator. The terms of the polynomial and its length can be programmed using the X15:X1 bits (CRCXOR<15:1>) and the PLEN3:PLEN0 bits (CRCCON<3:0>), respectively. FIGURE 20-1: EXAMPLE CRC SETUP The topology of a standard CRC generator is shown in Figure 20-2. CRC SHIFTER DETAILS PLEN<3:0> 0 1 2 15 CRC Shift Register Hold XOR DOUT OUT IN BIT 0 p_clk X1 0 1 Hold OUT IN BIT 1 p_clk X2 Hold 0 1 OUT IN BIT 2 X3 X15 0 0 1 1 p_clk Hold OUT IN BIT 15 p_clk CRC Read Bus CRC Write Bus (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 245 PIC24FJ256GB110 FAMILY CRC GENERATOR RECONFIGURED FOR x16 + x12 + x5 + 1 FIGURE 20-2: XOR D Q D Q D Q D Q D Q SDOx BIT 0 BIT 4 BIT 5 BIT 12 BIT 15 p_clk p_clk p_clk p_clk p_clk CRC Read Bus CRC Write Bus 20.1 20.1.1 User Interface To empty words already written into a FIFO, the CRCGO bit must be set to `1' and the CRC shifter allowed to run until the CRCMPT bit is set. DATA INTERFACE To start serial shifting, a `1' must be written to the CRCGO bit. The module incorporates a FIFO that is 8 deep when the value of the PLEN bits (CRCCON<3:0>) > 7, and 16 deep, otherwise. The data for which the CRC is to be calculated must first be written into the FIFO. The smallest data element that can be written into the FIFO is one byte. For example, if PLEN = 5, then the size of the data is PLEN + 1 = 6. The data must be written as follows: data[5:0] = crc_input[5:0] data[7:6] = `bxx If a word is written when the CRCFUL bit is set, the VWORD Pointer will roll over to 0. The hardware will then behave as if the FIFO is empty. However, the condition to generate an interrupt will not be met; therefore, no interrupt will be generated (See Section 20.1.2 "Interrupt Operation"). At least one instruction cycle must pass after a write to CRCWDAT before a read of the VWORD bits is done. 20.1.2 Once data is written into the CRCWDAT MSb (as defined by PLEN), the value of the VWORD bits (CRCCON<12:8>) increments by one. The serial shifter starts shifting data into the CRC engine when CRCGO = 1 and VWORD > 0. When the MSb is shifted out, VWORD decrements by one. The serial shifter continues shifting until the VWORD reaches 0. Therefore, for a given value of PLEN, it will take (PLEN + 1) * VWORD number of clock cycles to complete the CRC calculations. When VWORD reaches 8 (or 16), the CRCFUL bit will be set. When VWORD reaches 0, the CRCMPT bit will be set. To continually feed data into the CRC engine, the recommended mode of operation is to initially "prime" the FIFO with a sufficient number of words so no interrupt is generated before the next word can be written. Once that is done, start the CRC by setting the CRCGO bit to `1'. From that point onward, the VWORD bits should be polled. If they read less than 8 or 16, another word can be written into the FIFO. DS39897B-page 246 Also, to get the correct CRC reading, it will be necessary to wait for the CRCMPT bit to go high before reading the CRCWDAT register. INTERRUPT OPERATION When the VWORD4:VWORD0 bits make a transition from a value of `1' to `0', an interrupt will be generated. 20.2 20.2.1 Operation in Power Save Modes SLEEP MODE If Sleep mode is entered while the module is operating, the module will be suspended in its current state until clock execution resumes. 20.2.2 IDLE MODE To continue full module operation in Idle mode, the CSIDL bit must be cleared prior to entry into the mode. If CSIDL = 1, the module will behave the same way as it does in Sleep mode; pending interrupt events will be passed on, even though the module clocks are not available. Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 20.3 Registers There are four registers used to control programmable CRC operation: * * * * CRCCON CRCXOR CRCDAT CRCWDAT REGISTER 20-1: CRCCON: CRC CONTROL REGISTER U-0 U-0 R/W-0 R-0 R-0 R-0 R-0 R-0 -- -- CSIDL VWORD4 VWORD3 VWORD2 VWORD1 VWORD0 bit 15 bit 8 R-0 R-1 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CRCFUL CRCMPT -- CRCGO PLEN3 PLEN2 PLEN1 PLEN0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-14 Unimplemented: Read as `0' bit 13 CSIDL: CRC Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-8 VWORD4:VWORD0: Pointer Value bits Indicates the number of valid words in the FIFO. Has a maximum value of 8 when PLEN3:PLEN0 > 7, or 16 when PLEN3:PLEN0 7. bit 7 CRCFUL: FIFO Full bit 1 = FIFO is full 0 = FIFO is not full bit 6 CRCMPT: FIFO Empty Bit 1 = FIFO is empty 0 = FIFO is not empty bit 5 Unimplemented: Read as `0' bit 4 CRCGO: Start CRC bit 1 = Start CRC serial shifter 0 = CRC serial shifter turned off bit 3-0 PLEN3:PLEN0: Polynomial Length bits Denotes the length of the polynomial to be generated minus 1. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 247 PIC24FJ256GB110 FAMILY REGISTER 20-2: CRCXOR: CRC XOR POLYNOMIAL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 X15 X14 X13 X12 X11 X10 X9 X8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 U-0 X7 X6 X5 X4 X3 X2 X1 -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-1 X15:X1: XOR of Polynomial Term Xn Enable bits bit 0 Unimplemented: Read as `0' DS39897B-page 248 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 21.0 Note: 10-BIT HIGH-SPEED A/D CONVERTER A block diagram of the A/D Converter is shown in Figure 21-1. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 17. 10-Bit A/D Converter" (DS39705). To perform an A/D conversion: 1. The 10-bit A/D Converter has the following key features: * * * * * * * * * * * Successive Approximation (SAR) conversion Conversion speeds of up to 500 ksps 16 analog input pins External voltage reference input pins Internal band gap reference inputs Automatic Channel Scan mode Selectable conversion trigger source 16-word conversion result buffer Selectable Buffer Fill modes Four result alignment options Operation during CPU Sleep and Idle modes 2. Configure the A/D module: a) Configure port pins as analog inputs and/or select band gap reference inputs (AD1PCFGL<15:0> and AD1PCFGH<1:0>). b) Select voltage reference source to match expected range on analog inputs (AD1CON2<15:13>). c) Select the analog conversion clock to match desired data rate with processor clock (AD1CON3<7:0>). d) Select the appropriate sample/conversion sequence (AD1CON1<7:5> and AD1CON3<12:8>). e) Select how conversion results are presented in the buffer (AD1CON1<9:8>). f) Select interrupt rate (AD1CON2<5:2>). g) Turn on A/D module (AD1CON1<15>). Configure A/D interrupt (if required): a) Clear the AD1IF bit. b) Select A/D interrupt priority. On all PIC24FJ256GB110 family devices, the 10-bit A/D Converter has 16 analog input pins, designated AN0 through AN15. In addition, there are two analog input pins for external voltage reference connections (VREF+ and VREF-). These voltage reference inputs may be shared with other analog input pins. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 249 PIC24FJ256GB110 FAMILY FIGURE 21-1: 10-BIT HIGH-SPEED A/D CONVERTER BLOCK DIAGRAM Internal Data Bus AVSS VREF+ VR Select AVDD VR+ 16 VR- VREF- Comparator VINH AN0 VINL VRS/H VR+ DAC AN1 AN2 AN5 MUX A AN4 10-Bit SAR VINH AN3 Conversion Logic Data Formatting AN6 ADC1BUF0: ADC1BUFF VINL AN7 AN8 AD1CON1 AD1CON2 AD1CON3 AN9 AN10 AD1CHS0 AN12 AN13 AN14 MUX B AN11 VINH AD1PCFGL AD1PCFGH AD1CSSL AD1CSSH VINL AN15 VBG VBG/2 DS39897B-page 250 Sample Control Control Logic Conversion Control Input MUX Control Pin Config Control Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 21-1: AD1CON1: A/D CONTROL REGISTER 1 R/W-0 U-0 R/W-0 U-0 U-0 U-0 R/W-0 R/W-0 ADON(1) -- ADSIDL -- -- -- FORM1 FORM0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0, HCS R/W-0, HCS SSRC2 SSRC1 SSRC0 -- -- ASAM SAMP DONE bit 7 bit 0 Legend: HCS = Hardware Clearable/Settable bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 ADON: A/D Operating Mode bit(1) 1 = A/D Converter module is operating 0 = A/D Converter is off bit 14 Unimplemented: Read as `0' bit 13 ADSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12-10 Unimplemented: Read as `0' bit 9-8 FORM1:FORM0: Data Output Format bits 11 = Signed fractional (sddd dddd dd00 0000) 10 = Fractional (dddd dddd dd00 0000) 01 = Signed integer (ssss sssd dddd dddd) 00 = Integer (0000 00dd dddd dddd) bit 7-5 SSRC2:SSRC0: Conversion Trigger Source Select bits 111 = Internal counter ends sampling and starts conversion (auto-convert) 110 = Reserved 101 = Reserved 100 = CTMU event ends sampling and starts conversion 011 = Timer5 compare ends sampling and starts conversion 010 = Timer3 compare ends sampling and starts conversion 001 = Active transition on INT0 pin ends sampling and starts conversion 000 = Clearing SAMP bit ends sampling and starts conversion bit 4-3 Unimplemented: Read as `0' bit 2 ASAM: A/D Sample Auto-Start bit 1 = Sampling begins immediately after last conversion completes. SAMP bit is auto-set. 0 = Sampling begins when SAMP bit is set bit 1 SAMP: A/D Sample Enable bit 1 = A/D sample/hold amplifier is sampling input 0 = A/D sample/hold amplifier is holding bit 0 DONE: A/D Conversion Status bit 1 = A/D conversion is done 0 = A/D conversion is NOT done Note 1: Values of ADC1BUFx registers will not retain their values once the ADON bit is cleared. Read out the conversion values from the buffer before disabling the module. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 251 PIC24FJ256GB110 FAMILY REGISTER 21-2: AD1CON2: A/D CONTROL REGISTER 2 R/W-0 R/W-0 R/W-0 r-0 U-0 R/W-0 U-0 U-0 VCFG2 VCFG1 VCFG0 r -- CSCNA -- -- bit 15 bit 8 R-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 BUFS -- SMPI3 SMPI2 SMPI1 SMPI0 BUFM ALTS bit 7 bit 0 Legend: U = Unimplemented bit, read as `0' R = Readable bit W = Writable bit r = Reserved bit' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-13 x = Bit is unknown VCFG2:VCFG0: Voltage Reference Configuration bits VCFG2:VCFG0 VR+ VR- 000 AVDD AVSS 001 External VREF+ pin AVSS 010 AVDD External VREF- pin 011 External VREF+ pin External VREF- pin 1xx AVDD AVSS bit 12 Reserved: Maintain as `0' bit 11 Unimplemented: Read as `0' bit 10 CSCNA: Scan Input Selections for CH0+ S/H Input for MUX A Input Multiplexer Setting bit 1 = Scan inputs 0 = Do not scan inputs bit 9-8 Unimplemented: Read as `0' bit 7 BUFS: Buffer Fill Status bit (valid only when BUFM = 1) 1 = A/D is currently filling buffer 08-0F, user should access data in 00-07 0 = A/D is currently filling buffer 00-07, user should access data in 08-0F bit 6 Unimplemented: Read as `0' bit 5-2 SMPI3:SMPI0: Sample/Convert Sequences Per Interrupt Selection bits 1111 = Interrupts at the completion of conversion for each 16th sample/convert sequence 1110 = Interrupts at the completion of conversion for each 15th sample/convert sequence ..... 0001 = Interrupts at the completion of conversion for each 2nd sample/convert sequence 0000 = Interrupts at the completion of conversion for each sample/convert sequence bit 1 BUFM: Buffer Mode Select bit 1 = Buffer configured as two 8-word buffers (ADC1BUFn<15:8> and ADC1BUFn<7:0>) 0 = Buffer configured as one 16-word buffer (ADC1BUFn<15:0>) bit 0 ALTS: Alternate Input Sample Mode Select bit 1 = Uses MUX A input multiplexer settings for first sample, then alternates between MUX B and MUX A input multiplexer settings for all subsequent samples 0 = Always uses MUX A input multiplexer settings DS39897B-page 252 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 21-3: AD1CON3: A/D CONTROL REGISTER 3 R/W-0 r-0 r-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADRC r r SAMC4 SAMC3 SAMC2 SAMC1 SAMC0 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ADCS7 ADCS6 ADCS5 ADCS4 ADCS3 ADCS2 ADCS1 ADCS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 ADRC: A/D Conversion Clock Source bit 1 = A/D internal RC clock 0 = Clock derived from system clock bit 14-13 Reserved: Maintain as `0' bit 12-8 SAMC4:SAMC0: Auto-Sample Time bits 11111 = 31 TAD ***** 00001 = 1 TAD 00000 = 0 TAD (not recommended) bit 7-0 ADCS7:ADCS0: A/D Conversion Clock Select bits 11111111 = 256 * TCY ****** 00000001 = 2 * TCY 00000000 = TCY (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 253 PIC24FJ256GB110 FAMILY REGISTER 21-4: AD1CHS0: A/D INPUT SELECT REGISTER R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NB -- -- CH0SB4(1) CH0SB3(1) CH0SB2(1) CH0SB1(1) CH0SB0(1) bit 15 bit 8 R/W-0 U-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CH0NA -- -- CH0SA4 CH0SA3 CH0SA2 CH0SA1 CH0SA0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 CH0NB: Channel 0 Negative Input Select for MUX B Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VR- bit 14-13 Unimplemented: Read as `0' bit 12-8 CH0SB4:CH0SB0: Channel 0 Positive Input Select for MUX B Multiplexer Setting bits(1) 10001 = Channel 0 positive input is internal band gap reference (VBG) 10000 = Channel 0 positive input is VBG/2 01111 = Channel 0 positive input is AN15 01110 = Channel 0 positive input is AN14 01101 = Channel 0 positive input is AN13 01100 = Channel 0 positive input is AN12 01011 = Channel 0 positive input is AN11 01010 = Channel 0 positive input is AN10 01001 = Channel 0 positive input is AN9 01000 = Channel 0 positive input is AN8 00111 = Channel 0 positive input is AN7 00110 = Channel 0 positive input is AN6 00101 = Channel 0 positive input is AN5 00100 = Channel 0 positive input is AN4 00011 = Channel 0 positive input is AN3 00010 = Channel 0 positive input is AN2 00001 = Channel 0 positive input is AN1 00000 = Channel 0 positive input is AN0 bit 7 CH0NA: Channel 0 Negative Input Select for MUX A Multiplexer Setting bit 1 = Channel 0 negative input is AN1 0 = Channel 0 negative input is VR- bit 6-5 Unimplemented: Read as `0' bit 4-0 CH0SA4:CH0SA0: Channel 0 Positive Input Select for MUX A Multiplexer Setting bits Implemented combinations are identical to those for CHOSB4:CHOSB0 (above). Note 1: Combinations not shown here are unimplemented; do not use. DS39897B-page 254 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 21-5: AD1PCFGL: A/D PORT CONFIGURATION REGISTER (LOW) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG15 PCFG14 PCFG13 PCFG12 PCFG11 PCFG10 PCFG9 PCFG8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 PCFG7 PCFG6 PCFG5 PCFG4 PCFG3 PCFG2 PCFG1 PCFG0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-0 x = Bit is unknown PCFG15:PCFG0: Analog Input Pin Configuration Control bits 1 = Pin for corresponding analog channel is configured in Digital mode; I/O port read enabled 0 = Pin configured in Analog mode; I/O port read disabled, A/D samples pin voltage REGISTER 21-6: AD1PCFGH: A/D PORT CONFIGURATION REGISTER (HIGH) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- -- -- -- PCFG17 PCFG16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-2 Unimplemented: Read as `0' bit 1 PCFG17: A/D Input Band Gap Scan Enable bit 1 = Internal band gap (VBG) channel enabled for input scan 0 = Analog channel disabled from input scan bit 0 PCFG16: A/D Input Half Band Gap Scan Enable bit 1 = Internal VBG/2 channel enabled for input scan 0 = Analog channel disabled from input scan (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 255 PIC24FJ256GB110 FAMILY REGISTER 21-7: AD1CSSL: A/D INPUT SCAN SELECT REGISTER (LOW) R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL15 CSSL14 CSSL13 CSSL12 CSSL11 CSSL10 CSSL9 CSSL8 bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CSSL7 CSSL6 CSSL5 CSSL4 CSSL3 CSSL2 CSSL1 CSSL0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-0 x = Bit is unknown CSSL15:CSSL0: A/D Input Pin Scan Selection bits 1 = Corresponding analog channel selected for input scan 0 = Analog channel omitted from input scan REGISTER 21-8: AD1CSSH: A/D INPUT SCAN SELECT REGISTER (HIGH) U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 R/W-0 R/W-0 -- -- -- -- -- -- CSSL17 CSSL16 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-2 Unimplemented: Read as `0' bit 1 CSSL17: A/D Input Band Gap Scan Selection bit 1 = Internal band gap (VBG) channel selected for input scan 0 = Analog channel omitted from input scan bit 0 CSSL16: A/D Input Half Band Gap Scan Selection bit 1 = Internal VBG/2 channel selected for input scan 0 = Analog channel omitted from input scan DS39897B-page 256 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY A/D CONVERSION CLOCK PERIOD(1) EQUATION 21-1: ADCS = TAD -1 TCY TAD = TCY * (ADCS + 1) Note 1: FIGURE 21-2: Based on TCY = 2 * TOSC; Doze mode and PLL are disabled. 10-BIT A/D CONVERTER ANALOG INPUT MODEL VDD Rs VA RIC 250 VT = 0.6V ANx CPIN 6-11 pF (Typical) VT = 0.6V Sampling Switch RSS 5 k (Typical) RSS ILEAKAGE 500 nA CHOLD = DAC capacitance = 4.4 pF (Typical) VSS Legend: CPIN = Input Capacitance = Threshold Voltage VT ILEAKAGE = Leakage Current at the pin due to various junctions = Interconnect Resistance RIC = Sampling Switch Resistance RSS = Sample/Hold Capacitance (from DAC) CHOLD Note: CPIN value depends on device package and is not tested. Effect of CPIN negligible if Rs 5 k. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 257 PIC24FJ256GB110 FAMILY FIGURE 21-3: A/D TRANSFER FUNCTION Output Code (Binary (Decimal)) 11 1111 1111 (1023) 11 1111 1110 (1022) 10 0000 0011 (515) 10 0000 0010 (514) 10 0000 0001 (513) 10 0000 0000 (512) 01 1111 1111 (511) 01 1111 1110 (510) 01 1111 1101 (509) 00 0000 0001 (1) DS39897B-page 258 Preliminary (VINH - VINL) VR+ 1024 1023*(VR+ - VR-) VR- + 1024 VR- + 512*(VR+ - VR-) 1024 VR- + Voltage Level VR+ - VR- 0 VR- 00 0000 0000 (0) (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 22.0 TRIPLE COMPARATOR MODULE Note: The comparator outputs may be directly connected to the CxOUT pins. When the respective COE equals `1', the I/O pad logic makes the unsynchronized output of the comparator available on the pin. This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated "PIC24F Family Reference Manual" chapter. A simplified block diagram of the module in shown in Figure 22-1. Diagrams of the possible individual comparator configurations are shown in Figure 22-2. Each comparator has its own control register, CMxCON (Register 22-1), for enabling and configuring its operation. The output and event status of all three comparators is provided in the CMSTAT register (Register 22-2). The triple comparator module provides three dual input comparators. The inputs to the comparator can be configured to use any one of four external analog inputs as well, as a voltage reference input from either the internal band gap reference divided by two (VBG/2) or the comparator voltage reference generator. FIGURE 22-1: TRIPLE COMPARATOR MODULE BLOCK DIAGRAM EVPOL1:EVPOL0 CCH1:CCH0 CREF CPOL VINCXINB CXINC CXIND VIN+ Trigger/Interrupt Logic CEVT COE C1 Input Select Logic C1OUT Pin COUT EVPOL1:EVPOL0 VBG/2 CPOL Trigger/Interrupt Logic CEVT COE VINVIN+ C2 COUT EVPOL1:EVPOL0 CXINA CVREF CPOL VINVIN+ Trigger/Interrupt Logic CEVT COE C3 COUT (c) 2008 Microchip Technology Inc. C2OUT Pin Preliminary C3OUT Pin DS39897B-page 259 PIC24FJ256GB110 FAMILY FIGURE 22-2: INDIVIDUAL COMPARATOR CONFIGURATIONS Comparator Off CON = 0, CREF = x, CCH1:CCH0 = xx COE VINVIN+ Cx Off (Read as `0') Comparator CxINB > CxINA Compare CON = 1, CREF = 0, CCH1:CCH0 = 00 CXINB CXINA VIN+ Comparator CxINC > CxINA Compare CON = 1, CREF = 0, CCH1:CCH0 = 01 COE VIN- CXINC Cx CxOUT Pin CXINA COE VINVIN+ VBG/2 Cx CxOUT Pin Comparator CxINB > CVREF Compare CON = 1, CREF = 1, CCH1:CCH0 = 00 CXINB CVREF CXINC Cx CxOUT Pin CVREF DS39897B-page 260 VIN+ CVREF Cx CxOUT Pin COE VINVIN+ Cx CxOUT Pin COE VINVIN+ Cx CxOUT Pin Comparator VBG > CVREF Compare CON = 1, CREF = 1, CCH1:CCH0 = 11 COE VIN- VIN+ Comparator CxINC > CVREF Compare CON = 1, CREF = 1, CCH1:CCH0 = 01 Comparator CxIND > CVREF Compare CON = 1, CREF = 1, CCH1:CCH0 = 10 CXIND CXINA COE VINVIN+ CXINA COE VIN- Comparator VBG > CxINA Compare CON = 1, CREF = 0, CCH1:CCH0 = 11 Comparator CxIND > CxINA Compare CON = 1, CREF = 0, CCH1:CCH0 = 10 CXIND CxOUT Pin VBG/2 Cx CxOUT Pin CVREF Preliminary COE VINVIN+ Cx CxOUT Pin (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 22-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) R/W-0 R/W-0 R/W-0 U-0 U-0 U-0 R/W-0 R-0 CON COE CPOL -- -- -- CEVT COUT bit 15 bit 8 R/W-0 R/W-0 U-0 R/W-0 U-0 U-0 R/W-0 R/W-0 EVPOL1 EVPOL0 -- CREF -- -- CCH1 CCH0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 CON: Comparator Enable bit 1 = Comparator is enabled 0 = Comparator is disabled bit 14 COE: Comparator Output Enable bit 1 = Comparator output is present on the CxOUT pin. 0 = Comparator output is internal only bit 13 CPOL: Comparator Output Polarity Select bit 1 = Comparator output is inverted 0 = Comparator output is not inverted bit 12-10 Unimplemented: Read as `0' bit 9 CEVT: Comparator Event bit 1 = Comparator event defined by to EVPOL1:EVPOL0 has occurred; subsequent triggers and interrupts are disabled until the bit is cleared 0 = Comparator event has not occurred bit 8 COUT: Comparator Output bit When CPOL = 0: 1 = VIN+ > VIN0 = VIN+ < VINWhen CPOL = 1: 1 = VIN+ < VIN0 = VIN+ > VIN- bit 7-6 EVPOL1:EVPOL0: Trigger/Event/Interrupt Polarity Select bits 11 = Trigger/event/interrupt generated on any change of the comparator output (while CEVT = 0) 10 = Trigger/event/interrupt generated on transition of the comparator output: If CPOL = 0 (non-inverted polarity): High-to-low transition only. If CPOL = 1 (inverted polarity): Low-to-high transition only. 01 = Trigger/event/interrupt generated on transition of comparator output: If CPOL = 0 (non-inverted polarity): Low-to-high transition only. If CPOL = 1 (inverted polarity): High-to-low transition only. 00 = Trigger/event/interrupt generation is disabled bit 5 Unimplemented: Read as `0' (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 261 PIC24FJ256GB110 FAMILY REGISTER 22-1: CMxCON: COMPARATOR x CONTROL REGISTERS (COMPARATORS 1 THROUGH 3) (CONTINUED) bit 4 CREF: Comparator Reference Select bits (non-inverting input) 1 = Non-inverting input connects to internal CVREF voltage 0 = Non-inverting input connects to CXINA pin bit 3-2 Unimplemented: Read as `0' bit 1-0 CCH1:CCH0: Comparator Channel Select bits 11 = Inverting input of comparator connects to VBG/2 10 = Inverting input of comparator connects to CXIND pin 01 = Inverting input of comparator connects to CXINC pin 00 = Inverting input of comparator connects to CXINB pin REGISTER 22-2: CMSTAT: COMPARATOR MODULE STATUS REGISTER R/W-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 CMIDL -- -- -- -- C3EVT C2EVT C1EVT bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 R-0 R-0 R-0 -- -- -- -- -- C3OUT C2OUT C1OUT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15 CMIDL: Comparator Stop in Idle Mode bit 1 = Discontinue operation of all comparators when device enters Idle mode 0 = Continue operation of all enabled comparators in Idle mode bit 14-11 Unimplemented: Read as `0' bit 10 C3EVT: Comparator 3 Event Status bit (read-only) Shows the current event status of Comparator 3 (CM3CON<9>). bit 9 C2EVT: Comparator 2 Event Status bit (read-only) Shows the current event status of Comparator 2 (CM2CON<9>). bit 8 C1EVT: Comparator 1 Event Status bit (read-only) Shows the current event status of Comparator 1 (CM1CON<9>). bit 7-3 Unimplemented: Read as `0' bit 2 C3OUT: Comparator 3 Output Status bit (read-only) Shows the current output of Comparator 3 (CM3CON<8>). bit 1 C2OUT: Comparator 2 Output Status bit (read-only) Shows the current output of Comparator 2 (CM2CON<8>). bit 0 C1OUT: Comparator 1 Output Status bit (read-only) Shows the current output of Comparator 1 (CM1CON<8>). DS39897B-page 262 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 23.0 Note: 23.1 COMPARATOR VOLTAGE REFERENCE This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the "PIC24F Family Reference Manual", "Section 20. Comparator Voltage Reference Module" (DS39709). Configuring the Comparator Voltage Reference voltage, each with 16 distinct levels. The range to be used is selected by the CVRR bit (CVRCON<5>). The primary difference between the ranges is the size of the steps selected by the CVREF Selection bits (CVR3:CVR0), with one range offering finer resolution. The comparator reference supply voltage can come from either VDD and VSS, or the external VREF+ and VREF-. The voltage source is selected by the CVRSS bit (CVRCON<4>). The settling time of the comparator voltage reference must be considered when changing the CVREF output. The voltage reference module is controlled through the CVRCON register (Register 23-1). The comparator voltage reference provides two ranges of output FIGURE 23-1: COMPARATOR VOLTAGE REFERENCE BLOCK DIAGRAM VREF+ AVDD CVRSS = 1 8R CVRSS = 0 CVR3:CVR0 R CVREN R R 16-to-1 MUX R 16 Steps R CVREF R R CVRR VREF- 8R CVRSS = 1 CVRSS = 0 AVSS (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 263 PIC24FJ256GB110 FAMILY REGISTER 23-1: CVRCON: COMPARATOR VOLTAGE REFERENCE CONTROL REGISTER U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CVREN CVROE CVRR CVRSS CVR3 CVR2 CVR1 CVR0 bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared x = Bit is unknown bit 15-8 Unimplemented: Read as `0' bit 7 CVREN: Comparator Voltage Reference Enable bit 1 = CVREF circuit powered on 0 = CVREF circuit powered down bit 6 CVROE: Comparator VREF Output Enable bit 1 = CVREF voltage level is output on CVREF pin 0 = CVREF voltage level is disconnected from CVREF pin bit 5 CVRR: Comparator VREF Range Selection bit 1 = CVRSRC range should be 0 to 0.625 CVRSRC with CVRSRC/24 step size 0 = CVRSRC range should be 0.25 to 0.719 CVRSRC with CVRSRC/32 step size bit 4 CVRSS: Comparator VREF Source Selection bit 1 = Comparator reference source CVRSRC = VREF+ - VREF0 = Comparator reference source CVRSRC = AVDD - AVSS bit 3-0 CVR3:CVR0: Comparator VREF Value Selection 0 CVR3:CVR0 15 bits When CVRR = 1: CVREF = (CVR<3:0>/ 24) * (CVRSRC) When CVRR = 0: CVREF = 1/4 * (CVRSRC) + (CVR<3:0>/32) * (CVRSRC) DS39897B-page 264 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 24.0 Note: CHARGE TIME MEASUREMENT UNIT (CTMU) 24.1 The CTMU module measures capacitance by generating an output pulse with a width equal to the time between edge events on two separate input channels. The pulse edge events to both input channels can be selected from four sources: two internal peripheral modules (OC1 and Timer1) and two external pins (CTEDG1 and CTEDG2). This pulse is used with the module's precision current source to calculate capacitance according to the relationship: This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the associated "PIC24F Family Reference Manual" chapter. The Charge Time Measurement Unit is a flexible analog module that provides accurate differential time measurement between pulse sources, as well as asynchronous pulse generation. Its key features include: * * * * * * dV C = I ------dT For capacitance measurements, the A/D Converter samples an external capacitor (CAPP) on one of its input channels after the CTMU output's pulse. A precision resistor (RPR) provides current source calibration on a second A/D channel. After the pulse ends, the converter determines the voltage on the capacitor. The actual calculation of capacitance is performed in software by the application. Four edge input trigger sources Polarity control for each edge source Control of edge sequence Control of response to edges Time measurement resolution of 1 nanosecond Accurate current source suitable for capacitive measurement Figure 24-1 shows the external connections used for capacitance measurements, and how the CTMU and A/D modules are related in this application. This example also shows the edge events coming from Timer1, but other configurations using external edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the "PIC24F Family Reference Manual". Together with other on-chip analog modules, the CTMU can be used to precisely measure time, measure capacitance, measure relative changes in capacitance, or generate output pulses that are independent of the system clock. The CTMU module is ideal for interfacing with capacitive-based sensors. The CTMU is controlled through two registers, CTMUCON and CTMUICON. CTMUCON enables the module, and controls edge source selection, edge source polarity selection, and edge sequencing. The CTMUICON register has controls the selection and trim of the current source. FIGURE 24-1: Measuring Capacitance TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR CAPACITANCE MEASUREMENT PIC24F Device Timer1 CTMU EDG1 Current Source EDG2 Output Pulse A/D Converter ANx ANY CAPP (c) 2008 Microchip Technology Inc. RPR Preliminary DS39897B-page 265 PIC24FJ256GB110 FAMILY 24.2 Measuring Time When the module is configured for pulse generation delay by setting the TGEN bit (CTMUCON<12>), the internal current source is connected to the B input of Comparator 2. A capacitor (CDELAY) is connected to the Comparator 2 pin, C2INB, and the comparator voltage reference, CVREF, is connected to C2INA. CVREF is then configured for a specific trip point. The module begins to charge CDELAY when an edge event is detected. When CDELAY charges above the CVREF trip point, a pulse is output on CTPLS. The length of the pulse delay is determined by the value of CDELAY and the CVREF trip point. Time measurements on the pulse width can be similarly performed, using the A/D module's internal capacitor (CAD) and a precision resistor for current calibration. Figure 24-2 shows the external connections used for time measurements, and how the CTMU and A/D modules are related in this application. This example also shows both edge events coming from the external CTEDG pins, but other configurations using internal edge sources are possible. A detailed discussion on measuring capacitance and time with the CTMU module is provided in the PIC24F Family Reference Manual. 24.3 Figure 24-3 shows the external connections for pulse generation, as well as the relationship of the different analog modules required. While CTEDG1 is shown as the input pulse source, other options are available. A detailed discussion on pulse generation with the CTMU module is provided in the "PIC24F Family Reference Manual". Pulse Generation and Delay The CTMU module can also generate an output pulse with edges that are not synchronous with the device's system clock. More specifically, it can generate a pulse with a programmable delay from an edge event input to the module. FIGURE 24-2: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR TIME MEASUREMENT TIME PIC24F Device CTMU CTEDG1 EDG1 CTEDG2 EDG2 Current Source Output Pulse A/D Converter ANx CAD RPR FIGURE 24-3: TYPICAL CONNECTIONS AND INTERNAL CONFIGURATION FOR PULSE DELAY GENERATION PIC24F Device CTEDG1 EDG1 CTMU CTPLS Current Source Comparator C2INB CDELAY DS39897B-page 266 C2 CVREF Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 24-1: CTMUCON: CTMU CONTROL REGISTER R/W-0 U-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 CTMUEN -- CTMUSIDL TGEN EDGEN EDGSEQEN IDISSEN CTTRIG bit 15 bit 8 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 EDG2POL EDG2SEL1 EDG2SEL0 EDG1POL EDG1SEL1 EDG1SEL0 EDG2STAT EDG1STAT bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15 CTMUEN: CTMU Enable bit 1 = Module is enabled 0 = Module is disabled bit 14 Unimplemented: Read as `0' bit 13 CTMUSIDL: Stop in Idle Mode bit 1 = Discontinue module operation when device enters Idle mode 0 = Continue module operation in Idle mode bit 12 TGEN: Time Generation Enable bit 1 = Enables edge delay generation 0 = Disables edge delay generation bit 10 EDGEN: Edge Enable bit 1 = Edges are not blocked 0 = Edges are blocked bit 10 EDGSEQEN: Edge Sequence Enable bit 1 = Edge 1 event must occur before Edge 2 event can occur 0 = No edge sequence is needed bit 9 IDISSEN: Analog Current Source Control bit 1 = Analog current source output is grounded 0 = Analog current source output is not grounded bit 8 CTTRIG: Trigger Control bit 1 = Trigger output is enabled 0 = Trigger output is disabled bit 7 EDG2POL: Edge 2 Polarity Select bit 1 = Edge 2 programmed for a positive edge response 0 = Edge 2 programmed for a negative edge response bit 6-5 EDG2SEL1:EDG2SEL0: Edge 2 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 4 EDG1POL: Edge 1 Polarity Select bit 1 = Edge 1 programmed for a positive edge response 0 = Edge 1 programmed for a negative edge response (c) 2008 Microchip Technology Inc. Preliminary x = Bit is unknown DS39897B-page 267 PIC24FJ256GB110 FAMILY REGISTER 24-1: CTMUCON: CTMU CONTROL REGISTER (CONTINUED) bit 3-2 EDG1SEL1:EDG1SEL0: Edge 1 Source Select bits 11 = CTED1 pin 10 = CTED2 pin 01 = OC1 module 00 = Timer1 module bit 1 EDG2STAT: Edge 2 Status bit 1 = Edge 2 event has occurred 0 = Edge 2 event has not occurred bit 0 EDG1STAT: Edge 1 Status bit 1 = Edge 1 event has occurred 0 = Edge 1 event has not occurred REGISTER 24-2: CTMUICON: CTMU CURRENT CONTROL REGISTER R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 ITRIM5 ITRIM4 ITRIM3 ITRIM2 ITRIM1 ITRIM0 IRNG1 IRNG0 bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 -- -- -- -- -- -- -- -- bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as `0' -n = Value at POR `1' = Bit is set `0' = Bit is cleared bit 15-10 ITRIM5:ITRIM0: Current Source Trim bits 011111 = Maximum positive change from nominal current 011110 ..... 000001 = Minimum positive change from nominal current 000000 = Nominal current output specified by IRNG1:IRNG0 111111 = Minimum negative change from nominal current ..... 100010 100001 = Maximum negative change from nominal current bit 9-8 IRNG1:IRNG0: Current Source Range Select bits 11 = 100 x Base current 10 = 10 x Base current 01 = Base current level (0.55 A nominal) 00 = Current source disabled bit 7-0 Unimplemented: Read as `0' DS39897B-page 268 Preliminary x = Bit is unknown (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 25.0 Note: SPECIAL FEATURES 25.1.1 This data sheet summarizes the features of this group of PIC24F devices. It is not intended to be a comprehensive reference source. For more information, refer to the following sections of the "PIC24F Family Reference Manual": * Section 9. "Watchdog Timer (WDT)" (DS39697) * Section 32. "High-Level Device Integration" (DS39719) * Section 33. "Programming and Diagnostics" (DS39716) PIC24FJ256GB110 family devices include several features intended to maximize application flexibility and reliability, and minimize cost through elimination of external components. These are: * * * * * * Flexible Configuration Watchdog Timer (WDT) Code Protection JTAG Boundary Scan Interface In-Circuit Serial Programming In-Circuit Emulation 25.1 In PIC24FJ256GB110 family devices, the configuration bytes are implemented as volatile memory. This means that configuration data must be programmed each time the device is powered up. Configuration data is stored in the three words at the top of the on-chip program memory space, known as the Flash Configuration Words. Their specific locations are shown in Table 25-1. These are packed representations of the actual device Configuration bits, whose actual locations are distributed among several locations in configuration space. The configuration data is automatically loaded from the Flash Configuration Words to the proper Configuration registers during device Resets. Note: Configuration data is reloaded on all types of device Resets. When creating applications for these devices, users should always specifically allocate the location of the Flash Configuration Word for configuration data. This is to make certain that program code is not stored in this address when the code is compiled. Configuration Bits The Configuration bits can be programmed (read as `0'), or left unprogrammed (read as `1'), to select various device configurations. These bits are mapped starting at program memory location F80000h. A detailed explanation of the various bit functions is provided in Register 25-1 through Register 25-5. The upper byte of all Flash Configuration Words in program memory should always be `1111 1111'. This makes them appear to be NOP instructions in the remote event that their locations are ever executed by accident. Since Configuration bits are not implemented in the corresponding locations, writing `1's to these locations has no effect on device operation. Note: Note that address F80000h is beyond the user program memory space. In fact, it belongs to the configuration memory space (800000h-FFFFFFh) which can only be accessed using table reads and table writes. TABLE 25-1: CONSIDERATIONS FOR CONFIGURING PIC24FJ256GB110 FAMILY DEVICES Performing a page erase operation on the last page of program memory clears the Flash Configuration Words, enabling code protection as a result. Therefore, users should avoid performing page erase operations on the last page of program memory. FLASH CONFIGURATION WORD LOCATIONS FOR PIC24FJ256GB110 FAMILY DEVICES Device PIC24FJ64GB1 Configuration Word Addresses 1 2 3 ABFEh ABFCh ABFAh PIC24FJ128GB1 157FEh 157FC 157FA PIC24FJ192GB1 20BFEh 20BFC 20BFA PIC24FJ256GB1 2ABFEh 2ABFC 2ABFA (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 269 PIC24FJ256GB110 FAMILY REGISTER 25-1: CW1: FLASH CONFIGURATION WORD 1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 U-1 -- -- -- -- -- -- -- -- bit 23 bit 16 r-x R/PO-1 R/PO-1 R/PO-1 R/PO-1 r-1 R/PO-1 R/PO-1 r JTAGEN GCP GWRP DEBUG r ICS1 ICS0 bit 15 bit 8 R/PO-1 R/PO-1 U-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 R/PO-1 FWDTEN WINDIS -- FWPSA WDTPS3 WDTPS2 WDTPS1 WDTPS0 bit 7 bit 0 Legend: r = Reserved bit R = Readable bit PO = Program Once bit -n = Value when device is unprogrammed U = Unimplemented bit, read as `0' `1' = Bit is set bit 23-16 Unimplemented: Read as `1' bit 15 Reserved: The value is unknown; program as `0' bit 14 JTAGEN: JTAG Port Enable bit(1) 1 = JTAG port is enabled 0 = JTAG port is disabled bit 13 GCP: General Segment Program Memory Code Protection bit 1 = Code protection is disabled 0 = Code protection is enabled for the entire program memory space bit 12 GWRP: General Segment Code Flash Write Protection bit 1 = Writes to program memory are allowed 0 = Writes to program memory are disabled bit 11 DEBUG: Background Debugger Enable bit 1 = Device resets into Operational mode 0 = Device resets into Debug mode bit 10 Reserved: Always maintain as `1' bit 9-8 ICS1:ICS0: Emulator Pin Placement Select bits 11 = Emulator functions are shared with PGEC1/PGED1 10 = Emulator functions are shared with PGEC2/PGED2 01 = Emulator functions are shared with PGEC3/PGED3 00 = Reserved; do not use bit 7 FWDTEN: Watchdog Timer Enable bit 1 = Watchdog Timer is enabled 0 = Watchdog Timer is disabled bit 6 WINDIS: Windowed Watchdog Timer Disable bit 1 = Standard Watchdog Timer enabled 0 = Windowed Watchdog Timer enabled; FWDTEN must be `1' bit 5 Unimplemented: Read as `1' bit 4 FWPSA: WDT Prescaler Ratio Select bit 1 = Prescaler ratio of 1:128 0 = Prescaler ratio of 1:32 Note 1: `0' = Bit is cleared The JTAGEN bit can only be modified using In-Circuit Serial ProgrammingTM (ICSPTM). It cannot be modified while programming the device through the JTAG interface. DS39897B-page 270 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 25-1: bit 3-0 Note 1: CW1: FLASH CONFIGURATION WORD 1 (CONTINUED) WDTPS3:WDTPS0: Watchdog Timer Postscaler Select bits 1111 = 1:32,768 1110 = 1:16,384 1101 = 1:8,192 1100 = 1:4,096 1011 = 1:2,048 1010 = 1:1,024 1001 = 1:512 1000 = 1:256 0111 = 1:128 0110 = 1:64 0101 = 1:32 0100 = 1:16 0011 = 1:8 0010 = 1:4 0001 = 1:2 0000 = 1:1 The JTAGEN bit can only be modified using In-Circuit Serial ProgrammingTM (ICSPTM). It cannot be modified while programming the device through the JTAG interface. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 271 PIC24FJ256GB110 FAMILY REGISTER 25-2: U-1 -- bit 23 CW2: FLASH CONFIGURATION WORD 2 U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- R/PO-1 IESO bit 15 R/PO-1 PLLDIV2 R/PO-1 PLLDIV1 R/PO-1 PLLDIV0 r-0 r R/PO-1 FNOSC2 R/PO-1 FNOSC1 R/PO-1 FNOSC0 bit 8 R/PO-1 FCKSM1 bit 7 R/PO-1 FCKSM0 R/PO-1 OSCIOFCN R/PO-1 IOL1WAY R/PO-1 DISUVREG r-1 r R/PO-1 POSCMD1 R/PO-1 POSCMD0 bit 0 Legend: R = Readable bit PO = Program-once bit -n = Value when device is unprogrammed bit 23-16 bit 15 bit 14-12 bit 11 bit 10-8 bit 7-6 bit 5 bit 4 U-1 -- bit 16 r = Reserved bit U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared Unimplemented: Read as `1' IESO: Internal External Switchover bit 1 = IESO mode (Two-Speed Start-up) enabled 0 = IESO mode (Two-Speed Start-up) disabled PLLDIV2:PLLDIV0: USB 96 MHz PLL Prescaler Select bits 111 = Oscillator input divided by 12 (48 MHz input) 110 = Oscillator input divided by 10 (40 MHz input) 101 = Oscillator input divided by 6 (24 MHz input) 100 = Oscillator input divided by 5 (20 MHz input) 011 = Oscillator input divided by 4 (16 MHz input) 010 = Oscillator input divided by 3 (12 MHz input) 001 = Oscillator input divided by 2 (8 MHz input) 000 = Oscillator input used directly (4 MHz input) Reserved: Always maintain as `0' FNOSC2:FNOSC0: Initial Oscillator Select bits 111 = Fast RC Oscillator with Postscaler (FRCDIV) 110 = Reserved 101 = Low-Power RC Oscillator (LPRC) 100 = Secondary Oscillator (SOSC) 011 = Primary Oscillator with PLL module (XTPLL, HSPLL, ECPLL) 010 = Primary Oscillator (XT, HS, EC) 001 = Fast RC Oscillator with postscaler and PLL module (FRCPLL) 000 = Fast RC Oscillator (FRC) FCKSM1:FCKSM0: Clock Switching and Fail-Safe Clock Monitor Configuration bits 1x = Clock switching and Fail-Safe Clock Monitor are disabled 01 = Clock switching is enabled, Fail-Safe Clock Monitor is disabled 00 = Clock switching is enabled, Fail-Safe Clock Monitor is enabled OSCIOFCN: OSCO Pin Configuration bit If POSCMD1:POSCMD0 = 11 or 00: 1 = OSCO/CLKO/RC15 functions as CLKO (FOSC/2) 0 = OSCO/CLKO/RC15 functions as port I/O (RC15) If POSCMD1:POSCMD0 = 10 or 01: OSCIOFCN has no effect on OSCO/CLKO/RC15. IOL1WAY: IOLOCK One-Way Set Enable bit 1 = The IOLOCK bit (OSCCON<6>)can be set once, provided the unlock sequence has been completed. Once set, the Peripheral Pin Select registers cannot be written to a second time. 0 = The IOLOCK bit can be set and cleared as needed, provided the unlock sequence has been completed DS39897B-page 272 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY REGISTER 25-2: bit 3 bit 2 bit 1-0 DISUVREG: Internal USB 3.3V Regulator Disable bit 1 = Regulator is disabled 0 = Regulator is enabled Reserved: Always maintain as `1' POSCMD1:POSCMD0: Primary Oscillator Configuration bits 11 = Primary oscillator disabled 10 = HS Oscillator mode selected 01 = XT Oscillator mode selected 00 = EC Oscillator mode selected REGISTER 25-3: U-1 -- bit 23 CW2: FLASH CONFIGURATION WORD 2 (CONTINUED) CW3: FLASH CONFIGURATION WORD 3 U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- U-1 -- bit 16 R/PO-1 WPEND bit 15 R/PO-1 WPCFG R/PO-1 WPDIS U-1 -- U-1 -- U-1 -- U-1 -- R/PO-1 WPFP8 bit 8 R/PO-1 WPFP7 bit 7 R/PO-1 WPFP6 R/PO-1 WPFP5 R/PO-1 WPFP4 R/PO-1 WPFP3 R/PO-1 WPFP2 R/PO-1 WPFP1 R/PO-1 WPFP0 bit 0 Legend: R = Readable bit PO = Program-once bit -n = Value when device is unprogrammed bit 23-16 bit 15 bit 14 bit 13 bit 12-9 bit 8-0 U = Unimplemented bit, read as `0' `1' = Bit is set `0' = Bit is cleared Unimplemented: Read as `1' WPEND: Segment Write Protection End Page Select bit 1 = Protected code segment lower boundary is at the bottom of program memory (000000h); upper boundary is the code page specified by WPFP8:WPFP0 0 = Protected code segment upper boundary is at the last page of program memory; lower boundary is the code page specified by WPFP8:WPFP0 WPCFG: Configuration Word Code Page Protection Select bit 1 = Last page (at the top of program memory) and Flash Configuration Words are not protected 0 = Last page and Flash Configuration Words are code protected WPDIS: Segment Write Protection Disable bit 1 = Segmented code protection disabled 0 = Segmented code protection enabled; protected segment defined by WPEND, WPCFG and WPFPx Configuration bits Unimplemented: Read as `1' WPFP8:WPFP0: Protected Code Segment Boundary Page bits Designates the 16 K word program code page that is the boundary of the protected code segment, starting with Page 0 at the bottom of program memory. If WPEND = 1: Last address of designated code page is the upper boundary of the segment. If WPEND = `0': First address of designated code page is the lower boundary of the segment. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 273 PIC24FJ256GB110 FAMILY REGISTER 25-4: DEVID: DEVICE ID REGISTER U -- bit 23 U -- U -- U -- U -- U -- U -- U -- bit 15 U -- R FAMID7 R FAMID6 R FAMID5 R FAMID4 R FAMID3 R FAMID2 bit 8 R FAMID0 R DEV5 R DEV4 R DEV3 R DEV2 R DEV1 R DEV0 bit 0 R FAMID1 bit 7 Legend: R = Read-only bit bit 23-14 bit 13-6 bit 5-0 U -- bit 16 U = Unimplemented bit Unimplemented: Read as `1' FAMID7:FAMID0: Device Family Identifier bits 01000000 = PIC24FJ256GB110 family DEV5:DEV0: Individual Device Identifier bits 000001 = PIC24FJ64GB106 000011 = PIC24FJ64GB108 000111 = PIC24FJ64GB110 001001 = PIC24FJ128GB106 001011 = PIC24FJ128GB108 001111 = PIC24FJ128GB110 010001 = PIC24FJ192GB106 010011 = PIC24FJ192GB108 010111 = PIC24FJ192GB110 011001 = PIC24FJ256GB106 011011 = PIC24FJ256GB108 011111 = PIC24FJ256GB110 REGISTER 25-5: DEVREV: DEVICE REVISION REGISTER U -- U -- U -- U -- U -- U -- U -- U -- bit 16 U -- U -- U -- U -- U -- U -- U -- R MAJRV2 bit 8 R MAJRV0 U -- U -- U -- R DOT2 R DOT1 bit 23 bit 15 R MAJRV1 bit 7 Legend: R = Read-only bit bit 23-9 bit 8-6 bit 5-3 bit 2-0 R DOT0 bit 0 U = Unimplemented bit Unimplemented: Read as `0' MAJRV2:MAJRV0: Major Revision Identifier bits Unimplemented: Read as `0' DOT2:DOT0: Minor Revision Identifier bits DS39897B-page 274 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 25.2 On-Chip Voltage Regulator FIGURE 25-1: All PIC24FJ256GB110 family devices power their core digital logic at a nominal 2.5V. This may create an issue for designs that are required to operate at a higher typical voltage, such as 3.3V. To simplify system design, all devices in the PIC24FJ256GB110 family incorporate an on-chip regulator that allows the device to run its core logic from VDD. Regulator Enabled (ENVREG tied to VDD): 3.3V PIC24FJ256GB VDD ENVREG The regulator is controlled by the ENVREG pin. Tying VDD to the pin enables the regulator, which in turn, provides power to the core from the other VDD pins. When the regulator is enabled, a low ESR capacitor (such as ceramic) must be connected to the VDDCORE/VCAP pin (Figure 25-1). This helps to maintain the stability of the regulator. The recommended value for the filter capacitor (CEFC) is provided in Section 28.1 "DC Characteristics". VDDCORE/VCAP CEFC (10 F typ) VSS Regulator Disabled (ENVREG tied to ground): If ENVREG is tied to VSS, the regulator is disabled. In this case, separate power for the core logic at a nominal 2.5V must be supplied to the device on the VDDCORE/VCAP pin to run the I/O pins at higher voltage levels, typically 3.3V. Alternatively, the VDDCORE/VCAP and VDD pins can be tied together to operate at a lower nominal voltage. Refer to Figure 25-1 for possible configurations. 25.2.1 CONNECTIONS FOR THE ON-CHIP REGULATOR 2.5V(1) 3.3V(1) PIC24FJ256GB VDD ENVREG VDDCORE/VCAP VSS VOLTAGE REGULATOR TRACKING MODE AND LOW-VOLTAGE DETECTION When it is enabled, the on-chip regulator provides a constant voltage of 2.5V nominal to the digital core logic. Regulator Disabled (VDD tied to VDDCORE): 2.5V(1) PIC24FJ256GB VDD The regulator can provide this level from a VDD of about 2.5V, all the way up to the device's VDDMAX. It does not have the capability to boost VDD levels below 2.5V. In order to prevent "brown out" conditions when the voltage drops too low for the regulator, the regulator enters Tracking mode. In Tracking mode, the regulator output follows VDD, with a typical voltage drop of 100 mV. When the device enters Tracking mode, it is no longer possible to operate at full speed. To provide information about when the device enters Tracking mode, the on-chip regulator includes a simple, Low-Voltage Detect circuit. When VDD drops below full-speed operating voltage, the circuit sets the Low-Voltage Detect Interrupt Flag, LVDIF (IFS4<8>). This can be used to generate an interrupt and put the application into a low-power operational mode, or trigger an orderly shutdown. Low-Voltage Detection is only available when the regulator is enabled. ENVREG VDDCORE/VCAP VSS Note 1: 25.2.2 These are typical operating voltages. Refer to Section 28.1 "DC Characteristics" for the full operating ranges of VDD and VDDCORE. ON-CHIP REGULATOR AND POR When the voltage regulator is enabled, it takes approximately 500 s for it to generate output. During this time, designated as TSTARTUP, code execution is disabled. TSTARTUP is applied every time the device resumes operation after any power-down, including Sleep mode. If the regulator is disabled, a separate Power-up Timer (PWRT) is automatically enabled. The PWRT adds a fixed delay of 64 ms nominal delay at device start-up. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 275 PIC24FJ256GB110 FAMILY 25.2.3 ON-CHIP REGULATOR AND BOR When the on-chip regulator is enabled, PIC24FJ256GB110 family devices also have a simple brown-out capability. If the voltage supplied to the regulator is inadequate to maintain the tracking level, the regulator Reset circuitry will generate a Brown-out Reset. This event is captured by the BOR flag bit (RCON<1>). The brown-out voltage specifications are provided in Section 7. Reset" (DS39712) in the "PIC24F Family Reference Manual". 25.2.4 POWER-UP REQUIREMENTS The on-chip regulator is designed to meet the power-up requirements for the device. If the application does not use the regulator, then strict power-up conditions must be adhered to. While powering up, VDDCORE must never exceed VDD by 0.3 volts. Note: 25.2.5 For more information, see Section 28.0 "Electrical Characteristics". VOLTAGE REGULATOR STANDBY MODE When enabled, the on-chip regulator always consumes a small incremental amount of current over IDD/IPD, including when the device is in Sleep mode, even though the core digital logic does not require power. To provide additional savings in applications where power resources are critical, the regulator automatically disables itself whenever the device goes into Sleep mode. This feature is controlled by the VREGS bit (RCON<8>). By default, this bit is cleared, which enables Standby mode. When waking up from Standby mode, the regulator will require around 190 s to wake-up. This extra time is needed to ensure that the regulator can source enough current to power the Flash memory. For applications which require a faster wake-up time, it is possible to disable regulator Standby mode. The VREGS bit (RCON<8>) can be set to turn off Standby mode so that the Flash stays powered when in Sleep mode and the device can wake-up in 10 s. When VREGS is set, the power consumption while in Sleep mode, will be approximately 40 A higher than power consumption when the regulator is allowed to enter Standby mode. DS39897B-page 276 25.3 Watchdog Timer (WDT) For PIC24FJ256GB110 family devices, the WDT is driven by the LPRC oscillator. When the WDT is enabled, the clock source is also enabled. The nominal WDT clock source from LPRC is 31 kHz. This feeds a prescaler that can be configured for either 5-bit (divide-by-32) or 7-bit (divide-by-128) operation. The prescaler is set by the FWPSA Configuration bit. With a 31 kHz input, the prescaler yields a nominal WDT time-out period (TWDT) of 1 ms in 5-bit mode, or 4 ms in 7-bit mode. A variable postscaler divides down the WDT prescaler output and allows for a wide range of time-out periods. The postscaler is controlled by the WDTPS3:WDTPS0 Configuration bits (CW1<3:0>), which allow the selection of a total of 16 settings, from 1:1 to 1:32,768. Using the prescaler and postscaler, time-out periods ranging from 1 ms to 131 seconds can be achieved. The WDT, prescaler and postscaler are reset: * On any device Reset * On the completion of a clock switch, whether invoked by software (i.e., setting the OSWEN bit after changing the NOSC bits), or by hardware (i.e., Fail-Safe Clock Monitor) * When a PWRSAV instruction is executed (i.e., Sleep or Idle mode is entered) * When the device exits Sleep or Idle mode to resume normal operation * By a CLRWDT instruction during normal execution If the WDT is enabled, it will continue to run during Sleep or Idle modes. When the WDT time-out occurs, the device will wake the device and code execution will continue from where the PWRSAV instruction was executed. The corresponding SLEEP or IDLE bits (RCON<3:2>) will need to be cleared in software after the device wakes up. The WDT Flag bit, WDTO (RCON<4>), is not automatically cleared following a WDT time-out. To detect subsequent WDT events, the flag must be cleared in software. Note: Preliminary The CLRWDT and PWRSAV instructions clear the prescaler and postscaler counts when executed. (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 25.3.1 WINDOWED OPERATION 25.3.2 The Watchdog Timer has an optional fixed-window mode of operation. In this Windowed mode, CLRWDT instructions can only reset the WDT during the last 1/4 of the programmed WDT period. A CLRWDT instruction executed before that window causes a WDT Reset, similar to a WDT time-out. Windowed WDT mode is enabled by programming the WINDIS Configuration bit (CW1<6>) to `0'. FIGURE 25-2: CONTROL REGISTER The WDT is enabled or disabled by the FWDTEN Configuration bit. When the FWDTEN Configuration bit is set, the WDT is always enabled. The WDT can be optionally controlled in software when the FWDTEN Configuration bit has been programmed to `0'. The WDT is enabled in software by setting the SWDTEN control bit (RCON<5>). The SWDTEN control bit is cleared on any device Reset. The software WDT option allows the user to enable the WDT for critical code segments and disable the WDT during non-critical segments for maximum power savings. WDT BLOCK DIAGRAM SWDTEN FWDTEN LPRC Control FWPSA WDTPS3:WDTPS0 Prescaler (5-bit/7-bit) LPRC Input 31 kHz Wake from Sleep WDT Counter Postscaler 1:1 to 1:32.768 1 ms/4 ms WDT Overflow Reset All Device Resets Transition to New Clock Source Exit Sleep or Idle Mode CLRWDT Instr. PWRSAV Instr. Sleep or Idle Mode 25.4 Program Verification and Code Protection 25.4.2 PIC24FJ256GB110 family devices provide two complimentary methods to protect application code from overwrites and erasures. These also help to protect the device from inadvertent configuration changes during run time. 25.4.1 GENERAL SEGMENT PROTECTION For all devices in the PIC24FJ256GB110 family, the on-chip program memory space is treated as a single block, known as the General Segment (GS). Code protection for this block is controlled by one Configuration bit, GCP. This bit inhibits external reads and writes to the program memory space. It has no direct effect in normal execution mode. Write protection is controlled by the GWRP bit in the Configuration Word. When GWRP is programmed to `0', internal write and erase operations to program memory are blocked. (c) 2008 Microchip Technology Inc. CODE SEGMENT PROTECTION In addition to global General Segment protection, a separate subrange of the program memory space can be individually protected against writes and erases. This area can be used for many purposes where a separate block of write and erase protected code is needed, such as bootloader applications. Unlike common boot block implementations, the specially protected segment in PIC24FJ256GB110 family devices can be located by the user anywhere in the program space, and configured in a wide range of sizes. Code segment protection provides an added level of protection to a designated area of program memory, by disabling the NVM safety interlock whenever a write or erase address falls within a specified range. They do not override General Segment protection controlled by the GCP or GWRP bits. For example, if GCP and GWRP are enabled, enabling segmented code protection for the bottom half of program memory does not undo General Segment protection for the top half. Preliminary DS39897B-page 277 PIC24FJ256GB110 FAMILY The size and type of protection for the segmented code range are configured by the WPFPx, WPEND, WPCFG and WPDIS bits in Configuration Word 3. Code segment protection is enabled by programming the WPDIS bit (= 0). The WPFP bits specify the size of the segment to be protected, by specifying the 512-word code page that is the start or end of the protected segment. The specified region is inclusive, therefore, this page will also be protected. The WPEND bit determines if the protected segment uses the top or bottom of the program space as a boundary. Programming WPEND (= 0) sets the bottom of program memory (000000h) as the lower boundary of the protected segment. Leaving WPEND unprogrammed (= 1) protects the specified page through the last page of implemented program memory, including the Configuration Word locations. A separate bit, WPCFG, is used to independently protect the last page of program space, including the Flash Configuration Words. Programming WPCFG (= 0) protects the last page regardless of the other bit settings. This may be useful in circumstances where write protection is needed for both a code segment in the bottom of memory, as well as the Flash Configuration Words. 25.4.3 CONFIGURATION REGISTER PROTECTION The Configuration registers are protected against inadvertent or unwanted changes or reads in two ways. The primary protection method is the same as that of the RP registers - shadow registers contain a complimentary value which is constantly compared with the actual value. To safeguard against unpredictable events, Configuration bit changes resulting from individual cell level disruptions (such as ESD events) will cause a parity error and trigger a device Reset. The data for the Configuration registers is derived from the Flash Configuration Words in program memory. When the GCP bit is set, the source data for device configuration is also protected as a consequence. Even if General Segment protection is not enabled, the device configuration can be protected by using the appropriate code cement protection setting. The various options for segment code protection are shown in Table 25-2. TABLE 25-2: SEGMENT CODE PROTECTION CONFIGURATION OPTIONS Segment Configuration Bits Write/Erase Protection of Code Segment WPDIS WPEND WPCFG 1 X 1 No additional protection enabled; all program memory protection configured by GCP and GWRP 1 X 0 Last code page protected, including Flash Configuration Words 0 1 0 Addresses from first address of code page defined by WPFP8:WPFP0 through end of implemented program memory (inclusive) protected, including Flash Configuration Words 0 0 0 Address 000000h through last address of code page defined by WPFP8:WPFP0 (inclusive) protected 0 1 1 Addresses from first address of code page defined by WPFP8:WPFP0 through end of implemented program memory (inclusive) protected, including Flash Configuration Words 0 0 1 Addresses from first address of code page defined by WPFP8:WPFP0 through end of implemented program memory (inclusive) protected DS39897B-page 278 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 25.5 JTAG Interface 25.7 PIC24FJ256GB110 family devices implement a JTAG interface, which supports boundary scan device testing as well as In-Circuit Serial Programming. 25.6 In-Circuit Serial Programming PIC24FJ256GB110 family microcontrollers can be serially programmed while in the end application circuit. This is simply done with two lines for clock (PGECx) and data (PGEDx) and three other lines for power, ground and the programming voltage. This allows customers to manufacture boards with unprogrammed devices and then program the microcontroller just before shipping the product. This also allows the most recent firmware or a custom firmware to be programmed. (c) 2008 Microchip Technology Inc. In-Circuit Debugger When MPLAB(R) ICD 2 is selected as a debugger, the in-circuit debugging functionality is enabled. This function allows simple debugging functions when used with MPLAB IDE. Debugging functionality is controlled through the PGECx (Emulation/Debug Clock) and PGEDx (Emulation/Debug Data) pins. To use the in-circuit debugger function of the device, the design must implement ICSP connections to MCLR, VDD, VSS and the PGECx/PGEDx pin pair designated by the ICS Configuration bits. In addition, when the feature is enabled, some of the resources are not available for general use. These resources include the first 80 bytes of data RAM and two I/O pins. Preliminary DS39897B-page 279 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 280 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 26.0 DEVELOPMENT SUPPORT 26.1 The PIC(R) microcontrollers are supported with a full range of hardware and software development tools: * Integrated Development Environment - MPLAB(R) IDE Software * Assemblers/Compilers/Linkers - MPASMTM Assembler - MPLAB C18 and MPLAB C30 C Compilers - MPLINKTM Object Linker/ MPLIBTM Object Librarian - MPLAB ASM30 Assembler/Linker/Library * Simulators - MPLAB SIM Software Simulator * Emulators - MPLAB ICE 2000 In-Circuit Emulator - MPLAB REAL ICETM In-Circuit Emulator * In-Circuit Debugger - MPLAB ICD 2 * Device Programmers - PICSTART(R) Plus Development Programmer - MPLAB PM3 Device Programmer - PICkitTM 2 Development Programmer * Low-Cost Demonstration and Development Boards and Evaluation Kits MPLAB Integrated Development Environment Software The MPLAB IDE software brings an ease of software development previously unseen in the 8/16-bit microcontroller market. The MPLAB IDE is a Windows(R) operating system-based application that contains: * A single graphical interface to all debugging tools - Simulator - Programmer (sold separately) - Emulator (sold separately) - In-Circuit Debugger (sold separately) * A full-featured editor with color-coded context * A multiple project manager * Customizable data windows with direct edit of contents * High-level source code debugging * Visual device initializer for easy register initialization * Mouse over variable inspection * Drag and drop variables from source to watch windows * Extensive on-line help * Integration of select third party tools, such as HI-TECH Software C Compilers and IAR C Compilers The MPLAB IDE allows you to: * Edit your source files (either assembly or C) * One touch assemble (or compile) and download to PIC MCU emulator and simulator tools (automatically updates all project information) * Debug using: - Source files (assembly or C) - Mixed assembly and C - Machine code MPLAB IDE supports multiple debugging tools in a single development paradigm, from the cost-effective simulators, through low-cost in-circuit debuggers, to full-featured emulators. This eliminates the learning curve when upgrading to tools with increased flexibility and power. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 281 PIC24FJ256GB110 FAMILY 26.2 MPASM Assembler 26.5 The MPASM Assembler is a full-featured, universal macro assembler for all PIC MCUs. The MPASM Assembler generates relocatable object files for the MPLINK Object Linker, Intel(R) standard HEX files, MAP files to detail memory usage and symbol reference, absolute LST files that contain source lines and generated machine code and COFF files for debugging. The MPASM Assembler features include: 26.3 Support for the entire dsPIC30F instruction set Support for fixed-point and floating-point data Command line interface Rich directive set Flexible macro language MPLAB IDE compatibility 26.6 MPLAB C18 and MPLAB C30 C Compilers The MPLAB C18 and MPLAB C30 Code Development Systems are complete ANSI C compilers for Microchip's PIC18 and PIC24 families of microcontrollers and the dsPIC30 and dsPIC33 family of digital signal controllers. These compilers provide powerful integration capabilities, superior code optimization and ease of use not found with other compilers. For easy source level debugging, the compilers provide symbol information that is optimized to the MPLAB IDE debugger. 26.4 MPLAB ASM30 Assembler produces relocatable machine code from symbolic assembly language for dsPIC30F devices. MPLAB C30 C Compiler uses the assembler to produce its object file. The assembler generates relocatable object files that can then be archived or linked with other relocatable object files and archives to create an executable file. Notable features of the assembler include: * * * * * * * Integration into MPLAB IDE projects * User-defined macros to streamline assembly code * Conditional assembly for multi-purpose source files * Directives that allow complete control over the assembly process MPLINK Object Linker/ MPLIB Object Librarian The MPLINK Object Linker combines relocatable objects created by the MPASM Assembler and the MPLAB C18 C Compiler. It can link relocatable objects from precompiled libraries, using directives from a linker script. MPLAB ASM30 Assembler, Linker and Librarian MPLAB SIM Software Simulator The MPLAB SIM Software Simulator allows code development in a PC-hosted environment by simulating the PIC MCUs and dsPIC(R) DSCs on an instruction level. On any given instruction, the data areas can be examined or modified and stimuli can be applied from a comprehensive stimulus controller. Registers can be logged to files for further run-time analysis. The trace buffer and logic analyzer display extend the power of the simulator to record and track program execution, actions on I/O, most peripherals and internal registers. The MPLAB SIM Software Simulator fully supports symbolic debugging using the MPLAB C18 and MPLAB C30 C Compilers, and the MPASM and MPLAB ASM30 Assemblers. The software simulator offers the flexibility to develop and debug code outside of the hardware laboratory environment, making it an excellent, economical software development tool. The MPLIB Object Librarian manages the creation and modification of library files of precompiled code. When a routine from a library is called from a source file, only the modules that contain that routine will be linked in with the application. This allows large libraries to be used efficiently in many different applications. The object linker/library features include: * Efficient linking of single libraries instead of many smaller files * Enhanced code maintainability by grouping related modules together * Flexible creation of libraries with easy module listing, replacement, deletion and extraction DS39897B-page 282 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 26.7 MPLAB ICE 2000 High-Performance In-Circuit Emulator 26.9 The MPLAB ICE 2000 In-Circuit Emulator is intended to provide the product development engineer with a complete microcontroller design tool set for PIC microcontrollers. Software control of the MPLAB ICE 2000 In-Circuit Emulator is advanced by the MPLAB Integrated Development Environment, which allows editing, building, downloading and source debugging from a single environment. The MPLAB ICE 2000 is a full-featured emulator system with enhanced trace, trigger and data monitoring features. Interchangeable processor modules allow the system to be easily reconfigured for emulation of different processors. The architecture of the MPLAB ICE 2000 In-Circuit Emulator allows expansion to support new PIC microcontrollers. The MPLAB ICE 2000 In-Circuit Emulator system has been designed as a real-time emulation system with advanced features that are typically found on more expensive development tools. The PC platform and Microsoft(R) Windows(R) 32-bit operating system were chosen to best make these features available in a simple, unified application. 26.8 MPLAB REAL ICE In-Circuit Emulator System MPLAB REAL ICE In-Circuit Emulator System is Microchip's next generation high-speed emulator for Microchip Flash DSC and MCU devices. It debugs and programs PIC(R) Flash MCUs and dsPIC(R) Flash DSCs with the easy-to-use, powerful graphical user interface of the MPLAB Integrated Development Environment (IDE), included with each kit. The MPLAB REAL ICE probe is connected to the design engineer's PC using a high-speed USB 2.0 interface and is connected to the target with either a connector compatible with the popular MPLAB ICD 2 system (RJ11) or with the new high-speed, noise tolerant, LowVoltage Differential Signal (LVDS) interconnection (CAT5). MPLAB ICD 2 In-Circuit Debugger Microchip's In-Circuit Debugger, MPLAB ICD 2, is a powerful, low-cost, run-time development tool, connecting to the host PC via an RS-232 or high-speed USB interface. This tool is based on the Flash PIC MCUs and can be used to develop for these and other PIC MCUs and dsPIC DSCs. The MPLAB ICD 2 utilizes the in-circuit debugging capability built into the Flash devices. This feature, along with Microchip's In-Circuit Serial ProgrammingTM (ICSPTM) protocol, offers costeffective, in-circuit Flash debugging from the graphical user interface of the MPLAB Integrated Development Environment. This enables a designer to develop and debug source code by setting breakpoints, single stepping and watching variables, and CPU status and peripheral registers. Running at full speed enables testing hardware and applications in real time. MPLAB ICD 2 also serves as a development programmer for selected PIC devices. 26.10 MPLAB PM3 Device Programmer The MPLAB PM3 Device Programmer is a universal, CE compliant device programmer with programmable voltage verification at VDDMIN and VDDMAX for maximum reliability. It features a large LCD display (128 x 64) for menus and error messages and a modular, detachable socket assembly to support various package types. The ICSPTM cable assembly is included as a standard item. In Stand-Alone mode, the MPLAB PM3 Device Programmer can read, verify and program PIC devices without a PC connection. It can also set code protection in this mode. The MPLAB PM3 connects to the host PC via an RS-232 or USB cable. The MPLAB PM3 has high-speed communications and optimized algorithms for quick programming of large memory devices and incorporates an SD/MMC card for file storage and secure data applications. MPLAB REAL ICE is field upgradeable through future firmware downloads in MPLAB IDE. In upcoming releases of MPLAB IDE, new devices will be supported, and new features will be added, such as software breakpoints and assembly code trace. MPLAB REAL ICE offers significant advantages over competitive emulators including low-cost, full-speed emulation, real-time variable watches, trace analysis, complex breakpoints, a ruggedized probe interface and long (up to three meters) interconnection cables. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 283 PIC24FJ256GB110 FAMILY 26.11 PICSTART Plus Development Programmer 26.13 Demonstration, Development and Evaluation Boards The PICSTART Plus Development Programmer is an easy-to-use, low-cost, prototype programmer. It connects to the PC via a COM (RS-232) port. MPLAB Integrated Development Environment software makes using the programmer simple and efficient. The PICSTART Plus Development Programmer supports most PIC devices in DIP packages up to 40 pins. Larger pin count devices, such as the PIC16C92X and PIC17C76X, may be supported with an adapter socket. The PICSTART Plus Development Programmer is CE compliant. A wide variety of demonstration, development and evaluation boards for various PIC MCUs and dsPIC DSCs allows quick application development on fully functional systems. Most boards include prototyping areas for adding custom circuitry and provide application firmware and source code for examination and modification. 26.12 PICkit 2 Development Programmer The PICkitTM 2 Development Programmer is a low-cost programmer and selected Flash device debugger with an easy-to-use interface for programming many of Microchip's baseline, mid-range and PIC18F families of Flash memory microcontrollers. The PICkit 2 Starter Kit includes a prototyping development board, twelve sequential lessons, software and HI-TECH's PICCTM Lite C compiler, and is designed to help get up to speed quickly using PIC(R) microcontrollers. The kit provides everything needed to program, evaluate and develop applications using Microchip's powerful, mid-range Flash memory family of microcontrollers. DS39897B-page 284 The boards support a variety of features, including LEDs, temperature sensors, switches, speakers, RS-232 interfaces, LCD displays, potentiometers and additional EEPROM memory. The demonstration and development boards can be used in teaching environments, for prototyping custom circuits and for learning about various microcontroller applications. In addition to the PICDEMTM and dsPICDEMTM demonstration/development board series of circuits, Microchip has a line of evaluation kits and demonstration software for analog filter design, KEELOQ(R) security ICs, CAN, IrDA(R), PowerSmart battery management, SEEVAL(R) evaluation system, Sigma-Delta ADC, flow rate sensing, plus many more. Check the Microchip web page (www.microchip.com) for the complete list of demonstration, development and evaluation kits. Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 27.0 Note: INSTRUCTION SET SUMMARY This chapter is a brief summary of the PIC24F instruction set architecture, and is not intended to be a comprehensive reference source. The PIC24F instruction set adds many enhancements to the previous PIC(R) MCU instruction sets, while maintaining an easy migration from previous PIC MCU instruction sets. Most instructions are a single program memory word. Only three instructions require two program memory locations. Each single-word instruction is a 24-bit word divided into an 8-bit opcode, which specifies the instruction type and one or more operands, which further specify the operation of the instruction. The instruction set is highly orthogonal and is grouped into four basic categories: * * * * Word or byte-oriented operations Bit-oriented operations Literal operations Control operations * A literal value to be loaded into a W register or file register (specified by the value of `k') * The W register or file register where the literal value is to be loaded (specified by `Wb' or `f') However, literal instructions that involve arithmetic or logical operations use some of the following operands: * The first source operand which is a register `Wb' without any address modifier * The second source operand which is a literal value * The destination of the result (only if not the same as the first source operand) which is typically a register `Wd' with or without an address modifier The control instructions may use some of the following operands: * A program memory address * The mode of the table read and table write instructions Table 27-1 shows the general symbols used in describing the instructions. The PIC24F instruction set summary in Table 27-2 lists all the instructions, along with the status flags affected by each instruction. Most word or byte-oriented W register instructions (including barrel shift instructions) have three operands: * The first source operand which is typically a register `Wb' without any address modifier * The second source operand which is typically a register `Ws' with or without an address modifier * The destination of the result which is typically a register `Wd' with or without an address modifier However, word or byte-oriented file register instructions have two operands: * The file register specified by the value `f' * The destination, which could either be the file register `f' or the W0 register, which is denoted as `WREG' Most bit-oriented instructions (including rotate/shift instructions) have two operands: The literal instructions that involve data movement may use some of the following operands: simple All instructions are a single word, except for certain double-word instructions, which were made double-word instructions so that all the required information is available in these 48 bits. In the second word, the 8 MSbs are `0's. If this second word is executed as an instruction (by itself), it will execute as a NOP. Most single-word instructions are executed in a single instruction cycle, unless a conditional test is true or the program counter is changed as a result of the instruction. In these cases, the execution takes two instruction cycles, with the additional instruction cycle(s) executed as a NOP. Notable exceptions are the BRA (unconditional/computed branch), indirect CALL/GOTO, all table reads and writes, and RETURN/RETFIE instructions, which are single-word instructions but take two or three cycles. Certain instructions that involve skipping over the subsequent instruction require either two or three cycles if the skip is performed, depending on whether the instruction being skipped is a single-word or two-word instruction. Moreover, double-word moves require two cycles. The double-word instructions execute in two instruction cycles. * The W register (with or without an address modifier) or file register (specified by the value of `Ws' or `f') * The bit in the W register or file register (specified by a literal value or indirectly by the contents of register `Wb') (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 285 PIC24FJ256GB110 FAMILY TABLE 27-1: SYMBOLS USED IN OPCODE DESCRIPTIONS Field Description #text Means literal defined by "text" (text) Means "content of text" [text] Means "the location addressed by text" { } Optional field or operation <n:m> Register bit field .b Byte mode selection .d Double-Word mode selection .S Shadow register select .w Word mode selection (default) bit4 4-bit bit selection field (used in word addressed instructions) {0...15} C, DC, N, OV, Z MCU Status bits: Carry, Digit Carry, Negative, Overflow, Sticky Zero Expr Absolute address, label or expression (resolved by the linker) f File register address {0000h...1FFFh} lit1 1-bit unsigned literal {0,1} lit4 4-bit unsigned literal {0...15} lit5 5-bit unsigned literal {0...31} lit8 8-bit unsigned literal {0...255} lit10 10-bit unsigned literal {0...255} for Byte mode, {0:1023} for Word mode lit14 14-bit unsigned literal {0...16383} lit16 16-bit unsigned literal {0...65535} lit23 23-bit unsigned literal {0...8388607}; LSB must be `0' None Field does not require an entry, may be blank PC Program Counter Slit10 10-bit signed literal {-512...511} Slit16 16-bit signed literal {-32768...32767} Slit6 6-bit signed literal {-16...16} Wb Base W register {W0..W15} Wd Destination W register { Wd, [Wd], [Wd++], [Wd--], [++Wd], [--Wd] } Wdo Destination W register { Wnd, [Wnd], [Wnd++], [Wnd--], [++Wnd], [--Wnd], [Wnd+Wb] } Wm,Wn Dividend, Divisor working register pair (direct addressing) Wn One of 16 working registers {W0..W15} Wnd One of 16 destination working registers {W0..W15} Wns One of 16 source working registers {W0..W15} WREG W0 (working register used in file register instructions) Ws Source W register { Ws, [Ws], [Ws++], [Ws--], [++Ws], [--Ws] } Wso Source W register { Wns, [Wns], [Wns++], [Wns--], [++Wns], [--Wns], [Wns+Wb] } DS39897B-page 286 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 27-2: INSTRUCTION SET OVERVIEW Assembly Mnemonic ADD ADDC AND ASR BCLR BRA BSET BSW BTG BTSC Assembly Syntax Description # of Words # of Cycles Status Flags Affected ADD f f = f + WREG 1 1 C, DC, N, OV, Z ADD f,WREG WREG = f + WREG 1 1 C, DC, N, OV, Z ADD #lit10,Wn Wd = lit10 + Wd 1 1 C, DC, N, OV, Z ADD Wb,Ws,Wd Wd = Wb + Ws 1 1 C, DC, N, OV, Z ADD Wb,#lit5,Wd Wd = Wb + lit5 1 1 C, DC, N, OV, Z ADDC f f = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC f,WREG WREG = f + WREG + (C) 1 1 C, DC, N, OV, Z ADDC #lit10,Wn Wd = lit10 + Wd + (C) 1 1 C, DC, N, OV, Z ADDC Wb,Ws,Wd Wd = Wb + Ws + (C) 1 1 C, DC, N, OV, Z ADDC Wb,#lit5,Wd Wd = Wb + lit5 + (C) 1 1 C, DC, N, OV, Z AND f f = f .AND. WREG 1 1 N, Z AND f,WREG WREG = f .AND. WREG 1 1 N, Z AND #lit10,Wn Wd = lit10 .AND. Wd 1 1 N, Z AND Wb,Ws,Wd Wd = Wb .AND. Ws 1 1 N, Z AND Wb,#lit5,Wd Wd = Wb .AND. lit5 1 1 N, Z ASR f f = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR f,WREG WREG = Arithmetic Right Shift f 1 1 C, N, OV, Z ASR Ws,Wd Wd = Arithmetic Right Shift Ws 1 1 C, N, OV, Z ASR Wb,Wns,Wnd Wnd = Arithmetic Right Shift Wb by Wns 1 1 N, Z ASR Wb,#lit5,Wnd Wnd = Arithmetic Right Shift Wb by lit5 1 1 N, Z BCLR f,#bit4 Bit Clear f 1 1 None BCLR Ws,#bit4 Bit Clear Ws 1 1 None BRA C,Expr Branch if Carry 1 1 (2) None BRA GE,Expr Branch if Greater than or Equal 1 1 (2) None BRA GEU,Expr Branch if Unsigned Greater than or Equal 1 1 (2) None BRA GT,Expr Branch if Greater than 1 1 (2) None BRA GTU,Expr Branch if Unsigned Greater than 1 1 (2) None BRA LE,Expr Branch if Less than or Equal 1 1 (2) None BRA LEU,Expr Branch if Unsigned Less than or Equal 1 1 (2) None BRA LT,Expr Branch if Less than 1 1 (2) None BRA LTU,Expr Branch if Unsigned Less than 1 1 (2) None BRA N,Expr Branch if Negative 1 1 (2) None BRA NC,Expr Branch if Not Carry 1 1 (2) None BRA NN,Expr Branch if Not Negative 1 1 (2) None BRA NOV,Expr Branch if Not Overflow 1 1 (2) None BRA NZ,Expr Branch if Not Zero 1 1 (2) None BRA OV,Expr Branch if Overflow 1 1 (2) None BRA Expr Branch Unconditionally 1 2 None BRA Z,Expr Branch if Zero 1 1 (2) None BRA Wn Computed Branch 1 2 None BSET f,#bit4 Bit Set f 1 1 None BSET Ws,#bit4 Bit Set Ws 1 1 None BSW.C Ws,Wb Write C bit to Ws<Wb> 1 1 None BSW.Z Ws,Wb Write Z bit to Ws<Wb> 1 1 None BTG f,#bit4 Bit Toggle f 1 1 None BTG Ws,#bit4 Bit Toggle Ws 1 1 None BTSC f,#bit4 Bit Test f, Skip if Clear 1 1 None (2 or 3) BTSC Ws,#bit4 Bit Test Ws, Skip if Clear 1 1 None (2 or 3) (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 287 PIC24FJ256GB110 FAMILY TABLE 27-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic BTSS BTST BTSTS Assembly Syntax Description # of Words # of Cycles Status Flags Affected BTSS f,#bit4 Bit Test f, Skip if Set 1 1 None (2 or 3) BTSS Ws,#bit4 Bit Test Ws, Skip if Set 1 1 None (2 or 3) BTST f,#bit4 Bit Test f 1 1 Z BTST.C Ws,#bit4 Bit Test Ws to C 1 1 C BTST.Z Ws,#bit4 Bit Test Ws to Z 1 1 Z BTST.C Ws,Wb Bit Test Ws<Wb> to C 1 1 C Z BTST.Z Ws,Wb Bit Test Ws<Wb> to Z 1 1 BTSTS f,#bit4 Bit Test then Set f 1 1 Z BTSTS.C Ws,#bit4 Bit Test Ws to C, then Set 1 1 C BTSTS.Z Ws,#bit4 Bit Test Ws to Z, then Set 1 1 Z CALL CALL lit23 Call Subroutine 2 2 None CALL Wn Call Indirect Subroutine 1 2 None CLR CLR f f = 0x0000 1 1 None CLR WREG WREG = 0x0000 1 1 None CLR Ws Ws = 0x0000 1 1 None Clear Watchdog Timer 1 1 WDTO, Sleep CLRWDT CLRWDT COM COM f f=f 1 1 N, Z COM f,WREG WREG = f 1 1 N, Z COM Ws,Wd Wd = Ws 1 1 N, Z CP f Compare f with WREG 1 1 C, DC, N, OV, Z CP Wb,#lit5 Compare Wb with lit5 1 1 C, DC, N, OV, Z CP Wb,Ws Compare Wb with Ws (Wb - Ws) 1 1 C, DC, N, OV, Z CP0 CP0 f Compare f with 0x0000 1 1 C, DC, N, OV, Z CP0 Ws Compare Ws with 0x0000 1 1 C, DC, N, OV, Z CPB CPB f Compare f with WREG, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,#lit5 Compare Wb with lit5, with Borrow 1 1 C, DC, N, OV, Z CPB Wb,Ws Compare Wb with Ws, with Borrow (Wb - Ws - C) 1 1 C, DC, N, OV, Z CPSEQ CPSEQ Wb,Wn Compare Wb with Wn, Skip if = 1 1 None (2 or 3) CPSGT CPSGT Wb,Wn Compare Wb with Wn, Skip if > 1 1 None (2 or 3) CPSLT CPSLT Wb,Wn Compare Wb with Wn, Skip if < 1 1 None (2 or 3) CPSNE CPSNE Wb,Wn Compare Wb with Wn, Skip if 1 1 None (2 or 3) DAW DAW Wn Wn = Decimal Adjust Wn 1 1 DEC DEC f f = f -1 1 1 C, DC, N, OV, Z DEC f,WREG WREG = f -1 1 1 C, DC, N, OV, Z CP C DEC Ws,Wd Wd = Ws - 1 1 1 C, DC, N, OV, Z DEC2 f f=f-2 1 1 C, DC, N, OV, Z DEC2 f,WREG WREG = f - 2 1 1 C, DC, N, OV, Z DEC2 Ws,Wd Wd = Ws - 2 1 1 C, DC, N, OV, Z DISI DISI #lit14 Disable Interrupts for k Instruction Cycles 1 1 None DIV DIV.SW Wm,Wn Signed 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.SD Wm,Wn Signed 32/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UW Wm,Wn Unsigned 16/16-bit Integer Divide 1 18 N, Z, C, OV DIV.UD Wm,Wn Unsigned 32/16-bit Integer Divide 1 18 N, Z, C, OV EXCH EXCH Wns,Wnd Swap Wns with Wnd 1 1 None FF1L FF1L Ws,Wnd Find First One from Left (MSb) Side 1 1 C FF1R FF1R Ws,Wnd Find First One from Right (LSb) Side 1 1 C DEC2 DS39897B-page 288 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 27-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic GOTO INC INC2 Assembly Syntax Description # of Words # of Cycles Status Flags Affected GOTO Expr Go to Address 2 2 None GOTO Wn Go to Indirect 1 2 None INC f f=f+1 1 1 C, DC, N, OV, Z INC f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC Ws,Wd Wd = Ws + 1 1 1 INC2 f f=f+2 1 1 C, DC, N, OV, Z INC2 f,WREG WREG = f + 2 1 1 C, DC, N, OV, Z C, DC, N, OV, Z INC2 Ws,Wd Wd = Ws + 2 1 1 IOR f f = f .IOR. WREG 1 1 N, Z IOR f,WREG WREG = f .IOR. WREG 1 1 N, Z IOR #lit10,Wn Wd = lit10 .IOR. Wd 1 1 N, Z IOR Wb,Ws,Wd Wd = Wb .IOR. Ws 1 1 N, Z IOR Wb,#lit5,Wd Wd = Wb .IOR. lit5 1 1 N, Z LNK LNK #lit14 Link Frame Pointer 1 1 None LSR LSR f f = Logical Right Shift f 1 1 C, N, OV, Z LSR f,WREG WREG = Logical Right Shift f 1 1 C, N, OV, Z LSR Ws,Wd Wd = Logical Right Shift Ws 1 1 C, N, OV, Z LSR Wb,Wns,Wnd Wnd = Logical Right Shift Wb by Wns 1 1 N, Z LSR Wb,#lit5,Wnd Wnd = Logical Right Shift Wb by lit5 1 1 N, Z MOV f,Wn Move f to Wn 1 1 None MOV [Wns+Slit10],Wnd Move [Wns+Slit10] to Wnd 1 1 None MOV f Move f to f 1 1 N, Z MOV f,WREG Move f to WREG 1 1 N, Z MOV #lit16,Wn Move 16-bit Literal to Wn 1 1 None MOV.b #lit8,Wn Move 8-bit Literal to Wn 1 1 None MOV Wn,f Move Wn to f 1 1 None MOV Wns,[Wns+Slit10] Move Wns to [Wns+Slit10] 1 1 MOV Wso,Wdo Move Ws to Wd 1 1 None MOV WREG,f Move WREG to f 1 1 N, Z MOV.D Wns,Wd Move Double from W(ns):W(ns+1) to Wd 1 2 None MOV.D Ws,Wnd Move Double from Ws to W(nd+1):W(nd) 1 2 None MUL.SS Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Signed(Ws) 1 1 None MUL.SU Wb,Ws,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(Ws) 1 1 None MUL.US Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Signed(Ws) 1 1 None MUL.UU Wb,Ws,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(Ws) 1 1 None MUL.SU Wb,#lit5,Wnd {Wnd+1, Wnd} = Signed(Wb) * Unsigned(lit5) 1 1 None MUL.UU Wb,#lit5,Wnd {Wnd+1, Wnd} = Unsigned(Wb) * Unsigned(lit5) 1 1 None MUL f W3:W2 = f * WREG 1 1 None NEG f f=f+1 1 1 C, DC, N, OV, Z NEG f,WREG WREG = f + 1 1 1 C, DC, N, OV, Z NEG Ws,Wd Wd = Ws + 1 1 1 C, DC, N, OV, Z NOP No Operation 1 1 None NOPR No Operation 1 1 None IOR MOV MUL NEG NOP POP POP f Pop f from Top-of-Stack (TOS) 1 1 None POP Wdo Pop from Top-of-Stack (TOS) to Wdo 1 1 None POP.D Wnd Pop from Top-of-Stack (TOS) to W(nd):W(nd+1) 1 2 None Pop Shadow Registers 1 1 All POP.S PUSH PUSH f Push f to Top-of-Stack (TOS) 1 1 None PUSH Wso Push Wso to Top-of-Stack (TOS) 1 1 None PUSH.D Wns Push W(ns):W(ns+1) to Top-of-Stack (TOS) 1 2 None Push Shadow Registers 1 1 None PUSH.S (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 289 PIC24FJ256GB110 FAMILY TABLE 27-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected PWRSAV PWRSAV #lit1 Go into Sleep or Idle mode 1 1 WDTO, Sleep RCALL RCALL Expr Relative Call 1 2 None RCALL Wn Computed Call 1 2 None REPEAT REPEAT #lit14 Repeat Next Instruction lit14 + 1 times 1 1 None REPEAT Wn Repeat Next Instruction (Wn) + 1 times 1 1 None RESET RESET Software Device Reset 1 1 None RETFIE RETFIE Return from Interrupt 1 3 (2) None RETLW RETLW Return with Literal in Wn 1 3 (2) None RETURN RETURN Return from Subroutine 1 3 (2) None RLC RLC f f = Rotate Left through Carry f 1 1 C, N, Z RLC f,WREG WREG = Rotate Left through Carry f 1 1 C, N, Z C, N, Z RLNC RRC RRNC #lit10,Wn RLC Ws,Wd Wd = Rotate Left through Carry Ws 1 1 RLNC f f = Rotate Left (No Carry) f 1 1 N, Z RLNC f,WREG WREG = Rotate Left (No Carry) f 1 1 N, Z N, Z RLNC Ws,Wd Wd = Rotate Left (No Carry) Ws 1 1 RRC f f = Rotate Right through Carry f 1 1 C, N, Z RRC f,WREG WREG = Rotate Right through Carry f 1 1 C, N, Z RRC Ws,Wd Wd = Rotate Right through Carry Ws 1 1 C, N, Z RRNC f f = Rotate Right (No Carry) f 1 1 N, Z RRNC f,WREG WREG = Rotate Right (No Carry) f 1 1 N, Z RRNC Ws,Wd Wd = Rotate Right (No Carry) Ws 1 1 N, Z SE SE Ws,Wnd Wnd = Sign-Extended Ws 1 1 C, N, Z SETM SETM f f = FFFFh 1 1 None SETM WREG WREG = FFFFh 1 1 None SETM Ws Ws = FFFFh 1 1 None SL f f = Left Shift f 1 1 C, N, OV, Z SL f,WREG WREG = Left Shift f 1 1 C, N, OV, Z SL Ws,Wd Wd = Left Shift Ws 1 1 C, N, OV, Z SL Wb,Wns,Wnd Wnd = Left Shift Wb by Wns 1 1 N, Z SL Wb,#lit5,Wnd Wnd = Left Shift Wb by lit5 1 1 N, Z SUB f f = f - WREG 1 1 C, DC, N, OV, Z SUB f,WREG WREG = f - WREG 1 1 C, DC, N, OV, Z SUB #lit10,Wn Wn = Wn - lit10 1 1 C, DC, N, OV, Z SUB Wb,Ws,Wd Wd = Wb - Ws 1 1 C, DC, N, OV, Z SUB Wb,#lit5,Wd Wd = Wb - lit5 1 1 C, DC, N, OV, Z SUBB f f = f - WREG - (C) 1 1 C, DC, N, OV, Z SL SUB SUBB SUBR SUBBR SWAP SUBB f,WREG WREG = f - WREG - (C) 1 1 C, DC, N, OV, Z SUBB #lit10,Wn Wn = Wn - lit10 - (C) 1 1 C, DC, N, OV, Z SUBB Wb,Ws,Wd Wd = Wb - Ws - (C) 1 1 C, DC, N, OV, Z SUBB Wb,#lit5,Wd Wd = Wb - lit5 - (C) 1 1 C, DC, N, OV, Z SUBR f f = WREG - f 1 1 C, DC, N, OV, Z SUBR f,WREG WREG = WREG - f 1 1 C, DC, N, OV, Z SUBR Wb,Ws,Wd Wd = Ws - Wb 1 1 C, DC, N, OV, Z SUBR Wb,#lit5,Wd Wd = lit5 - Wb 1 1 C, DC, N, OV, Z SUBBR f f = WREG - f - (C) 1 1 C, DC, N, OV, Z SUBBR f,WREG WREG = WREG - f - (C) 1 1 C, DC, N, OV, Z SUBBR Wb,Ws,Wd Wd = Ws - Wb - (C) 1 1 C, DC, N, OV, Z C, DC, N, OV, Z SUBBR Wb,#lit5,Wd Wd = lit5 - Wb - (C) 1 1 SWAP.b Wn Wn = Nibble Swap Wn 1 1 None SWAP Wn Wn = Byte Swap Wn 1 1 None DS39897B-page 290 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 27-2: INSTRUCTION SET OVERVIEW (CONTINUED) Assembly Mnemonic Assembly Syntax Description # of Words # of Cycles Status Flags Affected TBLRDH TBLRDH Ws,Wd Read Prog<23:16> to Wd<7:0> 1 2 TBLRDL TBLRDL Ws,Wd Read Prog<15:0> to Wd 1 2 None TBLWTH TBLWTH Ws,Wd Write Ws<7:0> to Prog<23:16> 1 2 None TBLWTL TBLWTL Ws,Wd Write Ws to Prog<15:0> 1 2 None ULNK ULNK Unlink Frame Pointer 1 1 None XOR XOR f f = f .XOR. WREG 1 1 N, Z XOR f,WREG WREG = f .XOR. WREG 1 1 N, Z XOR #lit10,Wn Wd = lit10 .XOR. Wd 1 1 N, Z XOR Wb,Ws,Wd Wd = Wb .XOR. Ws 1 1 N, Z XOR Wb,#lit5,Wd Wd = Wb .XOR. lit5 1 1 N, Z ZE Ws,Wnd Wnd = Zero-Extend Ws 1 1 C, Z, N ZE (c) 2008 Microchip Technology Inc. Preliminary None DS39897B-page 291 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 292 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 28.0 ELECTRICAL CHARACTERISTICS This section provides an overview of the PIC24FJ256GB110 family electrical characteristics. Additional information will be provided in future revisions of this document as it becomes available. Absolute maximum ratings for the PIC24FJ256GB110 family are listed below. Exposure to these maximum rating conditions for extended periods may affect device reliability. Functional operation of the device at these, or any other conditions above the parameters indicated in the operation listings of this specification, is not implied. Absolute Maximum Ratings() Ambient temperature under bias.............................................................................................................-40C to +100C Storage temperature .............................................................................................................................. -65C to +150C Voltage on VDD with respect to VSS ......................................................................................................... -0.3V to +4.0V Voltage on any combined analog and digital pin and MCLR, with respect to VSS ......................... -0.3V to (VDD + 0.3V) Voltage on any digital only pin with respect to VSS .................................................................................. -0.3V to +6.0V Voltage on VDDCORE with respect to VSS ................................................................................................. -0.3V to +3.0V Maximum current out of VSS pin ...........................................................................................................................300 mA Maximum current into VDD pin (Note 1)................................................................................................................250 mA Maximum output current sunk by any I/O pin..........................................................................................................25 mA Maximum output current sourced by any I/O pin ....................................................................................................25 mA Maximum current sunk by all ports .......................................................................................................................200 mA Maximum current sourced by all ports (Note 1)....................................................................................................200 mA Note 1: Maximum allowable current is a function of device maximum power dissipation (see Table 28-1). NOTICE: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at those or any other conditions above those indicated in the operation listings of this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 293 PIC24FJ256GB110 FAMILY 28.1 DC Characteristics FIGURE 28-1: PIC24FJ256GB110 FAMILY VOLTAGE-FREQUENCY GRAPH (INDUSTRIAL) 3.00V Voltage (VDDCORE)(1) 2.75V 2.75V 2.50V PIC24FJXXXGB1XX 2.25V 2.25V 2.00V 16 MHz 32 MHz Frequency For frequencies between 16 MHz and 32 MHz, FMAX = (64 MHz/V) * (VDDCORE - 2V) + 16 MHz. When the voltage regulator is disabled, VDD and VDDCORE must be maintained so that VDDCORE VDD 3.6V. Note 1: TABLE 28-1: THERMAL OPERATING CONDITIONS Rating Symbol Min Typ Max Unit Operating Junction Temperature Range TJ -40 -- +125 C Operating Ambient Temperature Range TA -40 -- +85 C PIC24FJ256GB110 family: Power Dissipation: Internal Chip Power Dissipation: PINT = VDD x (IDD - IOH) PD PINT + PI/O W PDMAX (TJ - TA)/JA W I/O Pin Power Dissipation: PI/O = ({VDD - VOH} x IOH) + (VOL x IOL) Maximum Allowed Power Dissipation TABLE 28-2: THERMAL PACKAGING CHARACTERISTICS Characteristic Symbol Typ Max Unit Notes Package Thermal Resistance, 14x14x1 mm TQFP JA 50.0 -- C/W (Note 1) Package Thermal Resistance, 12x12x1 mm TQFP JA 69.4 -- C/W (Note 1) Package Thermal Resistance, 10x10x1 mm TQFP JA 76.6 -- C/W (Note 1) Note 1: Junction to ambient thermal resistance, Theta-JA (JA) numbers are achieved by package simulations. DS39897B-page 294 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 28-3: DC CHARACTERISTICS: TEMPERATURE AND VOLTAGE SPECIFICATIONS DC CHARACTERISTICS Param Symbol No. Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units VDD 2.2 -- 3.6 V Regulator enabled VDD VDDCORE -- 3.6 V Regulator disabled 2.0 -- 2.75 V Regulator disabled Characteristic Conditions Operating Voltage DC10 Supply Voltage VDDCORE DC12 VDR RAM Data Retention Voltage(2) 1.5 -- -- V DC16 VPOR VDD Start VoltAge To ensure internal Power-on Reset Signal -- VSS -- V DC17 SVDD VDD Rise Rate to Ensure Internal Power-on Reset Signal .05 -- -- V/ms Note 1: 2: 0-3.3V in 0.1s 0-2.5V in 60 ms Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. This is the limit to which VDD can be lowered without losing RAM data. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 295 PIC24FJ256GB110 FAMILY TABLE 28-4: DC CHARACTERISTICS: OPERATING CURRENT (IDD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Operating Current (IDD)(2) DC20 0.83 1.2 mA -40C DC20a 0.83 1.2 mA +25C DC20b 0.83 1.2 mA +85C DC20d 1.1 1.6 mA -40C DC20e 1.1 1.6 mA +25C DC20f 1.1 1.6 mA +85C DC23 3.3 4.3 mA -40C DC23a 3.3 4.3 mA +25C DC23b 3.3 4.3 mA +85C DC23d 4.3 6 mA -40C DC23e 4.3 6 mA +25C DC23f 4.3 6 mA +85C DC24 18.2 24 mA -40C DC24a 18.2 24 mA +25C DC24b 18.2 24 mA +85C DC24d 18.2 24 mA -40C DC24e 18.2 24 mA +25C DC24f 18.2 24 mA +85C DC31 15.0 20 A -40C DC31a 15.0 20 A +25C DC31b 20.0 26 A +85C DC31d 57.0 75 A -40C DC31e 57.0 75 A +25C DC31f 95.0 124 A +85C Note 1: 2: 3: 4: 2.0V(3) 1 MIPS 3.3V(4) 2.0V(3) 4 MIPS 3.3V(4) 2.5V(3) 16 MIPS 3.3V(4) 2.0V(3) LPRC (31 kHz) 3.3V(4) Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The supply current is mainly a function of the operating voltage and frequency. Other factors, such as I/O pin loading and switching rate, oscillator type, internal code execution pattern and temperature, also have an impact on the current consumption. The test conditions for all IDD measurements are as follows: OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. CPU, SRAM, program memory and data memory are operational. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. DS39897B-page 296 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 28-5: DC CHARACTERISTICS: IDLE CURRENT (IIDLE) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Idle Current (IIDLE)(2) DC40 220 290 A -40C DC40a 220 290 A +25C DC40b 220 290 A +85C DC40d 300 390 A -40C DC40e 300 390 A +25C DC40f 300 420 A +85C DC43 0.85 1.1 mA -40C DC43a 0.85 1.1 mA +25C DC43b 0.87 1.2 mA +85C DC43d 1.1 1.4 mA -40C DC43e 1.1 1.4 mA +25C DC43f 1.1 1.4 mA +85C DC47 4.4 5.6 mA -40C DC47a 4.4 5.6 mA +25C DC47b 4.4 5.6 mA +85C DC47c 4.4 5.6 mA -40C DC47d 4.4 5.6 mA +25C DC47e 4.4 5.6 mA +85C DC50 1.1 1.4 mA -40C DC50a 1.1 1.4 mA +25C DC50b 1.1 1.4 mA +85C DC50d 1.4 1.8 mA -40C DC50e 1.4 1.8 mA +25C DC50f 1.4 1.8 mA +85C DC51 4.3 6.0 A -40C DC51a 4.5 6.0 A +25C DC51b 7.2 25 A +85C DC51d 38 50 A -40C DC51e 44 60 A +25C 70 110 A +85C DC51f Note 1: 2: 3: 4: 2.0V(3) 1 MIPS 3.3V(4) 2.0V(3) 4 MIPS 3.3V(4) 2.5V(3) 16 MIPS 3.3V(4) 2.0V(3) FRC (4 MIPS) 3.3V(4) 2.0V(3) LPRC (31 kHz) 3.3V(4) Data in "Typical" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IIDLE current is measured with the core off, OSCI driven with external square wave from rail to rail. All I/O pins are configured as inputs and pulled to VDD. MCLR = VDD; WDT and FSCM are disabled. No peripheral modules are operating and all of the Peripheral Module Disable (PMD) bits are set. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 297 PIC24FJ256GB110 FAMILY TABLE 28-6: DC CHARACTERISTICS: POWER-DOWN CURRENT (IPD) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial DC CHARACTERISTICS Parameter No. Typical(1) Max Units Conditions Power-Down Current (IPD)(2) DC60 0.1 1 A -40C DC60a 0.15 1 A +25C DC60b 3.7 18 A +85C DC60c 0.2 1.3 A -40C DC60d 0.25 1.3 A +25C DC60e 4.2 27 A +85C DC60f 3.6 9 A -40C DC60g 4.0 10 A +25C DC60h 11.0 36 A +85C DC61 1.75 3 A -40C DC61a 1.75 3 A +25C DC61b 1.75 3 A +85C DC61c 2.4 4 A -40C DC61d 2.4 4 A +25C DC61e 2.4 4 A +85C DC61f 2.8 5 A -40C DC61g 2.8 5 A +25C DC61h 2.8 5 A +85C DC62 2.5 7 A -40C DC62a 2.5 7 A +25C DC62b 3.0 7 A +85C DC62c 2.8 7 A -40C DC62d 3.0 7 A +25C DC62e 3.0 7 A +85C DC62f 3.5 10 A -40C DC62g 3.5 10 A +25C DC62h 4.0 10 A +85C Note 1: 2: 3: 4: 5: 2.0V(3) 2.5V(3) Base Power-Down Current(5) 3.3V(4) 2.0V(3) 2.5V(3) Watchdog Timer Current: IWDT(5) 3.3V(4) 2.0V(3) 2.5V(3) RTCC + Timer1 w/32 kHz Crystal: RTCC + ITI32(5) 3.3V(4) Data in the Typical column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Base IPD is measured with all peripherals and clocks shut down. All I/Os are configured as inputs and pulled high. WDT, etc., are all switched off, VREGS bit is clear, and the Peripheral Module Disable (PMD) bits for all unused peripherals are set. On-chip voltage regulator disabled (ENVREG tied to VSS). On-chip voltage regulator enabled (ENVREG tied to VDD). Low-Voltage Detect (LVD) and Brown-out Detect (BOD) are enabled. The current is the additional current consumed when the module is enabled. This current should be added to the base IPD current. DS39897B-page 298 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 28-7: DC CHARACTERISTICS: I/O PIN INPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial DC CHARACTERISTICS Param No. Sym VIL Characteristic Min Typ(1) Max Units Input Low Voltage(4) DI10 I/O Pins with ST Buffer VSS -- 0.2 VDD V DI11 I/O Pins with TTL Buffer VSS -- 0.15 VDD V DI15 MCLR VSS -- 0.2 VDD V DI16 OSC1 (XT mode) VSS -- 0.2 VDD V DI17 OSC1 (HS mode) VSS -- 0.2 VDD V DI18 I/O Pins with I2CTM Buffer: VSS -- 0.3 VDD V I/O Pins with SMBus Buffer: VSS -- 0.8 V I/O Pins with ST Buffer: with Analog Functions, Digital Only 0.8 VDD 0.8 VDD -- -- VDD 5.5 V V I/O Pins with TTL Buffer: with Analog Functions, Digital Only 0.25 VDD + 0.8 0.25 VDD + 0.8 -- -- VDD 5.5 V V DI19 VIH DI20 DI21 MCLR 0.8 VDD -- VDD V DI26 OSC1 (XT mode) 0.7 VDD -- VDD V DI27 OSC1 (HS mode) 0.7 VDD -- VDD V DI28 I/O Pins with I2C Buffer: with Analog Functions, Digital Only 0.7 VDD 0.7 VDD -- -- VDD 5.5 V V VDD 5.5 V V I/O Pins with SMBus Buffer: with Analog Functions, Digital Only DI30 ICNPU CNxx Pull-up Current IIL SMBus enabled Input High Voltage(4) DI25 DI29 Conditions Input Leakage 2.5V VPIN VDD 2.1 2.1 50 250 400 A VDD = 3.3V, VPIN = VSS Current(2,3) DI50 I/O Ports -- -- +1 A VSS VPIN VDD, Pin at high-impedance DI51 Analog Input Pins -- -- +1 A VSS VPIN VDD, Pin at high-impedance DI55 MCLR -- -- +1 A VSS VPIN VDD DI56 OSC1 -- -- +1 A VSS VPIN VDD, XT and HS modes Note 1: 2: 3: 4: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. The leakage current on the MCLR pin is strongly dependent on the applied voltage level. The specified levels represent normal operating conditions. Higher leakage current may be measured at different input voltages. Negative current is defined as current sourced by the pin. Refer to Table 1-4 for I/O pins buffer types. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 299 PIC24FJ256GB110 FAMILY TABLE 28-8: DC CHARACTERISTICS: I/O PIN OUTPUT SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial DC CHARACTERISTICS Param No. Sym VOL Characteristic I/O Ports DO16 OSC2/CLKO DO20 Note 1: OSC2/CLKO Units -- -- 0.4 V IOL = 8.5 mA, VDD = 3.6V -- -- 0.4 V IOL = 6.0 mA, VDD = 2.0V -- -- 0.4 V IOL = 8.5 mA, VDD = 3.6V -- -- 0.4 V IOL = 6.0 mA, VDD = 2.0V Conditions 3.0 -- -- V IOH = -3.0 mA, VDD = 3.6V 2.4 -- -- V IOH = -6.0 mA, VDD = 3.6V 1.65 -- -- V IOH = -1.0 mA, VDD = 2.0V 1.4 -- -- V IOH = -3.0 mA, VDD = 2.0V 2.4 -- -- V IOH = -6.0 mA, VDD = 3.6V 1.4 -- -- V IOH = -3.0 mA, VDD = 2.0V Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 28-9: DC CHARACTERISTICS: PROGRAM MEMORY Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial DC CHARACTERISTICS Param No. Max Output High Voltage I/O Ports DO26 Typ(1) Output Low Voltage DO10 VOH Min Sym Characteristic Min Typ(1) 10000 VMIN Max Units Conditions -- -- E/W -- 3.6 V VMIN = Minimum operating voltage 2.25 -- 3.6 V VMIN = Minimum operating voltage Program Flash Memory D130 EP Cell Endurance D131 VPR VDD for Read D132B VPEW VDD for Self-Timed Write D133A TIW Self-Timed Write Cycle Time -- 3 -- ms D133B TIE Self-Timed Page Erase Time 40 -- -- ms D134 TRETD Characteristic Retention 20 -- -- Year D135 IDDP -- 7 -- mA Note 1: Supply Current during Programming -40C to +85C Provided no other specifications are violated Data in "Typ" column is at 3.3V, 25C unless otherwise stated. TABLE 28-10: INTERNAL VOLTAGE REGULATOR SPECIFICATIONS Operating Conditions: -40C < TA < +85C (unless otherwise stated) Param Symbol No. Characteristics Min Typ Max Units Comments VRGOUT Regulator Output Voltage -- 2.5 -- V CEFC External Filter Capacitor Value 4.7 10 -- F TVREG -- 50 -- s ENVREG tied to VDD TPWRT -- 64 -- ms ENVREG tied to VSS DS39897B-page 300 Preliminary Series resistance < 3 Ohm recommended; < 5 Ohm required. (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 28.2 AC Characteristics and Timing Parameters The information contained in this section defines the PIC24FJ256GB110 family AC characteristics and timing parameters. TABLE 28-11: TEMPERATURE AND VOLTAGE SPECIFICATIONS - AC Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Operating voltage VDD range as described in Section 28.1 "DC Characteristics". AC CHARACTERISTICS FIGURE 28-2: LOAD CONDITIONS FOR DEVICE TIMING SPECIFICATIONS Load Condition 1 - for all pins except OSCO Load Condition 2 - for OSCO VDD/2 CL Pin RL VSS CL Pin RL = 464 CL = 50 pF for all pins except OSCO 15 pF for OSCO output VSS TABLE 28-12: CAPACITIVE LOADING REQUIREMENTS ON OUTPUT PINS Param Symbol No. Characteristic Min Typ(1) Max Units Conditions DO50 COSC2 OSCO/CLKO pin -- -- 15 pF In XT and HS modes when external clock is used to drive OSCI. DO56 CIO All I/O pins and OSCO -- -- 50 pF EC mode. DO58 CB SCLx, SDAx -- -- 400 pF In I2CTM mode. Note 1: Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 301 PIC24FJ256GB110 FAMILY FIGURE 28-3: EXTERNAL CLOCK TIMING Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 OSCI OS20 OS30 OS31 OS30 OS31 OS25 CLKO OS41 OS40 TABLE 28-13: EXTERNAL CLOCK TIMING REQUIREMENTS AC CHARACTERISTICS Param Sym No. OS10 Characteristic FOSC External CLKI Frequency (External clocks allowed only in EC mode) Oscillator Frequency Standard Operating Conditions: 2.50 to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units DC 4 -- -- 32 48 MHz MHz EC ECPLL 3 4 10 10 31 -- -- -- -- -- 10 8 32 32 33 MHz MHz MHz MHz kHz XT XTPLL HS HSPLL SOSC -- -- -- -- Conditions OS20 TOSC TOSC = 1/FOSC OS25 TCY 62.5 -- DC ns OS30 TosL, External Clock in (OSCI) TosH High or Low Time 0.45 x TOSC -- -- ns EC OS31 TosR, External Clock in (OSCI) TosF Rise or Fall Time -- -- 20 ns EC OS40 TckR CLKO Rise Time(3) -- 6 10 ns OS41 TckF CLKO Fall Time(3) -- 6 10 ns Note 1: 2: 3: Instruction Cycle Time(2) See parameter OS10 for FOSC value Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. Instruction cycle period (TCY) equals two times the input oscillator time base period. All specified values are based on characterization data for that particular oscillator type under standard operating conditions with the device executing code. Exceeding these specified limits may result in an unstable oscillator operation and/or higher than expected current consumption. All devices are tested to operate at "Min." values with an external clock applied to the OSCI/CLKI pin. When an external clock input is used, the "Max." cycle time limit is "DC" (no clock) for all devices. Measurements are taken in EC mode. The CLKO signal is measured on the OSCO pin. CLKO is low for the Q1-Q2 period (1/2 TCY) and high for the Q3-Q4 period (1/2 TCY). DS39897B-page 302 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 28-14: PLL CLOCK TIMING SPECIFICATIONS (VDD = 2.0V TO 3.6V) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial AC CHARACTERISTICS Param No. Sym Characteristic(1) OS50 FPLLI PLL Input Frequency Range(2) OS51 FSYS PLL Output Frequency Range OS52 TLOCK PLL Start-up Time (Lock Time) OS53 DCLK Note 1: 2: CLKO Stability (Jitter) Min Typ(2) Max Units 4 -- 32 MHz 95.76 -- 96.24 MHz -- -- 200 s -0.25 -- 0.25 % Conditions ECPLL, HSPLL, XTPLL modes These parameters are characterized but not tested in manufacturing. Data in "Typ" column is at 3.3V, 25C unless otherwise stated. Parameters are for design guidance only and are not tested. TABLE 28-15: AC CHARACTERISTICS: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ Max Units Conditions -2 -- 2 % +25C 3.0V VDD 3.6V -5 -- 5 % -40C TA +85C 3.0V VDD 3.6V Internal FRC Accuracy @ 8 MHz(1) F20 FRC Note 1: Frequency calibrated at 25C and 3.3V. OSCTUN bits can be used to compensate for temperature drift. TABLE 28-16: INTERNAL RC ACCURACY AC CHARACTERISTICS Param No. Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ Max Units -20 -- 20 % Conditions LPRC @ 31 kHz(1) F21 Note 1: -40C TA +85C 3.0V VDD 3.6V Change of LPRC frequency as VDD changes. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 303 PIC24FJ256GB110 FAMILY FIGURE 28-4: CLKO AND I/O TIMING CHARACTERISTICS I/O Pin (Input) DI35 DI40 I/O Pin (Output) New Value Old Value DO31 DO32 Note: Refer to Figure 28-2 for load conditions. TABLE 28-17: CLKO AND I/O TIMING REQUIREMENTS AC CHARACTERISTICS Param No. Sym Characteristic Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C for Industrial Min Typ(1) Max Units DO31 TIOR Port Output Rise Time -- 10 25 ns DO32 TIOF Port Output Fall Time -- 10 25 ns DI35 TINP INTx pin High or Low Time (output) 20 -- -- ns DI40 TRBP CNx High or Low Time (input) 2 -- -- TCY Note 1: Conditions Data in "Typ" column is at 3.3V, 25C unless otherwise stated. DS39897B-page 304 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY TABLE 28-18: ADC MODULE SPECIFICATIONS Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions Device Supply AD01 AVDD Module VDD Supply Greater of VDD - 0.3 or 2.0 -- Lesser of VDD + 0.3 or 3.6 V AD02 AVSS Module VSS Supply VSS - 0.3 -- VSS + 0.3 V AD05 VREFH Reference Voltage High AVSS + 1.7 AVDD V AD06 VREFL Reference Voltage Low AD07 VREF Absolute Reference Voltage AD10 VINH-VINL Full-Scale Input Span Reference Inputs -- AVSS -- AVDD - 1.7 V AVSS - 0.3 -- AVDD + 0.3 V Analog Input VREFL -- VREFH V -- AVDD + 0.3 V AVDD/2 V (Note 2) AD11 VIN Absolute Input Voltage AVSS - 0.3 AD12 VINL Absolute VINL Input Voltage AVSS - 0.3 -- AD13 -- Leakage Current -- 0.00 1 0.610 A VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V, Source Impedance = 2.5 k AD17 RIN Recommended Impedance of Analog Voltage Source -- -- 2.5K 10-bit ADC Accuracy AD20b Nr Resolution -- 10 -- bits AD21b INL Integral Nonlinearity -- 1 <2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD22b DNL Differential Nonlinearity -- 0.5 <1 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD23b GERR Gain Error -- 1 3 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD24b EOFF Offset Error -- 1 2 LSb VINL = AVSS = VREFL = 0V, AVDD = VREFH = 3V AD25b -- Monotonicity(1) -- -- -- -- Note 1: 2: Guaranteed The ADC conversion result never decreases with an increase in the input voltage and has no missing codes. Measurements taken with external VREF+ and VREF- used as the ADC voltage reference. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 305 PIC24FJ256GB110 FAMILY TABLE 28-19: ADC CONVERSION TIMING REQUIREMENTS(1) Standard Operating Conditions: 2.0V to 3.6V (unless otherwise stated) Operating temperature -40C TA +85C AC CHARACTERISTICS Param No. Symbol Characteristic Min. Typ Max. Units Conditions TCY = 75 ns, AD1CON3 in default state Clock Parameters AD50 TAD ADC Clock Period 75 -- -- ns AD51 tRC ADC Internal RC Oscillator Period -- 250 -- ns AD55 tCONV Conversion Time -- 12 -- TAD AD56 FCNV Throughput Rate -- -- 500 ksps AD57 tSAMP Sample Time -- 1 -- TAD AD61 tPSS Sample Start Delay from setting Sample bit (SAMP) -- 3 TAD Conversion Rate AVDD > 2.7V Clock Parameters Note 1: 2 Because the sample caps will eventually lose charge, clock rates below 10 kHz can affect linearity performance, especially at elevated temperatures. DS39897B-page 306 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY 29.0 PACKAGING INFORMATION 29.1 Package Marking Information 64-Lead TQFP (10x10x1 mm) Example XXXXXXXXXX XXXXXXXXXX XXXXXXXXXX YYWWNNN PIC24FJ256 GB106-I/ PT e3 0820017 80-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN PIC24FJ256GB 108-I/PT e3 0820017 100-Lead TQFP (12x12x1 mm) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN PIC24FJ256GB 110-I/PT e3 0820017 100-Lead TQFP (14x14x1 mm) Example XXXXXXXXXXXX XXXXXXXXXXXX YYWWNNN Legend: XX...X Y YY WW NNN e3 * Note: PIC24FJ256GB 110-I/PF e3 0820017 Customer-specific information Year code (last digit of calendar year) Year code (last 2 digits of calendar year) Week code (week of January 1 is week `01') Alphanumeric traceability code Pb-free JEDEC designator for Matte Tin (Sn) This package is Pb-free. The Pb-free JEDEC designator ( e3 ) can be found on the outer packaging for this package. In the event the full Microchip part number cannot be marked on one line, it will be carried over to the next line, thus limiting the number of available characters for customer-specific information. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 307 PIC24FJ256GB110 FAMILY 29.2 Package Details The following sections give the technical details of the packages. /HDG3ODVWLF7KLQ4XDG)ODWSDFN 37 [[PP%RG\PP>74)3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ D D1 E e E1 N b NOTE 1 123 NOTE 2 A c A2 A1 L L1 8QLWV 'LPHQVLRQ/LPLWV 1XPEHURI/HDGV 0,//,0(7(56 0,1 1 120 0$; /HDG3LWFK H 2YHUDOO+HLJKW $ %6& 0ROGHG3DFNDJH7KLFNQHVV $ 6WDQGRII $ )RRW/HQJWK / )RRWSULQW / 5() )RRW$QJOH 2YHUDOO:LGWK ( %6& 2YHUDOO/HQJWK ' %6& 0ROGHG3DFNDJH:LGWK ( %6& 0ROGHG3DFNDJH/HQJWK ' %6& /HDG7KLFNQHVV F /HDG:LGWK E 0ROG'UDIW$QJOH7RS 0ROG'UDIW$QJOH%RWWRP 1RWHV 3LQYLVXDOLQGH[IHDWXUHPD\YDU\EXWPXVWEHORFDWHGZLWKLQWKHKDWFKHGDUHD &KDPIHUVDWFRUQHUVDUHRSWLRQDOVL]HPD\YDU\ 'LPHQVLRQV'DQG(GRQRWLQFOXGHPROGIODVKRUSURWUXVLRQV0ROGIODVKRUSURWUXVLRQVVKDOOQRWH[FHHGPPSHUVLGH 'LPHQVLRQLQJDQGWROHUDQFLQJSHU$60(<0 %6& %DVLF'LPHQVLRQ7KHRUHWLFDOO\H[DFWYDOXHVKRZQZLWKRXWWROHUDQFHV 5() 5HIHUHQFH'LPHQVLRQXVXDOO\ZLWKRXWWROHUDQFHIRULQIRUPDWLRQSXUSRVHVRQO\ 0LFURFKLS 7HFKQRORJ\ 'UDZLQJ &% DS39897B-page 308 Preliminary (c) 2008 Microchip Technology Inc. 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PIC24FJ256GB110 FAMILY /HDG3ODVWLF7KLQ4XDG)ODWSDFN 37 [[PP%RG\PP>74)3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ (c) 2008 Microchip Technology Inc. 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PIC24FJ256GB110 FAMILY /HDG3ODVWLF7KLQ4XDG)ODWSDFN 3) [[PP%RG\PP>74)3@ 1RWH )RUWKHPRVWFXUUHQWSDFNDJHGUDZLQJVSOHDVHVHHWKH0LFURFKLS3DFNDJLQJ6SHFLILFDWLRQORFDWHGDW KWWSZZZPLFURFKLSFRPSDFNDJLQJ (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 315 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 316 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY APPENDIX A: REVISION HISTORY Revision A (October 2007) Original data sheet for the PIC24FJ256GB110 family of devices. Revision B (March 2008) Changes to Section 28.0 "Electrical Characteristics" and minor edits to text throughout document. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 317 PIC24FJ256GB110 FAMILY NOTES: DS39897B-page 318 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY INDEX A PSV Operation............................................................ 54 Reset System ............................................................. 61 RTCC........................................................................ 235 Shared I/O Port Structure ......................................... 121 SPI Master, Frame Master Connection .................... 177 SPI Master, Frame Slave Connection ...................... 177 SPI Master/Slave Connection (Enhanced Buffer Modes)................................. 176 SPI Master/Slave Connection (Standard Mode)............................................... 176 SPI Slave, Frame Master Connection ...................... 177 SPI Slave, Frame Slave Connection ........................ 177 SPIx Module (Enhanced Mode)................................ 171 SPIx Module (Standard Mode) ................................. 170 System Clock Diagram ............................................. 109 Triple Comparator Module........................................ 259 UART (Simplified)..................................................... 187 USB OTG Interrupt Funnel ....................................... 201 USB OTG Module..................................................... 196 USB PLL................................................................... 116 USB Voltage Generation and Connections .............. 200 Watchdog Timer (WDT)............................................ 277 A/D Converter Analog Input Model ................................................... 257 Transfer Function...................................................... 258 AC Characteristics ADC Conversion Timing ........................................... 306 CLKO and I/O Timing................................................ 304 AC Characteristics Internal RC Accuracy ................................................ 303 Alternate Interrupt Vector Table (AIVT) .............................. 67 Assembler MPASM Assembler................................................... 282 B Block Diagram CRC Shifter Details................................................... 245 Block Diagrams 10-Bit High-Speed A/D Converter............................. 250 16-Bit Asynchronous Timer3 and Timer5 ................. 151 16-Bit Synchronous Timer2 and Timer4 ................... 151 16-Bit Timer1 Module................................................ 147 32-Bit Timer2/3 and Timer4/5 ................................... 150 Accessing Program Space Using Table Operations ................................................ 53 Addressable PMP Example ...................................... 232 Addressing for Table Registers................................... 55 BDT Mapping for Endpoint Buffering Modes ............ 197 CALL Stack Frame...................................................... 51 Comparator Voltage Reference ................................ 263 CPU Programmer's Model .......................................... 27 CRC Generator Configured for Polynomial............... 246 CTMU Connections and Internal Configuration for Capacitance Measurement.......................... 265 CTMU Typical Connections and Internal Configuration for Pulse Delay Generation ........ 266 CTMU Typical Connections and Internal Configuration for Time Measurement ............... 266 Data Access From Program Space Address Generation ............................................ 52 I2C Module ................................................................ 180 Individual Comparator Configuration ........................ 260 Input Capture ............................................................ 155 LCD Control .............................................................. 234 Legacy PMP Example............................................... 232 On-Chip Regulator Connections ............................... 275 Output Compare (16-Bit Mode)................................. 160 Output Compare (Double-Buffered 16-Bit PWM Mode) ........................................... 162 PCI24FJ256GB110 Family (General) ......................... 14 PIC24F CPU Core ...................................................... 26 PMP 8-Bit Multiplexed Address and Data Application................................................ 234 PMP EEPROM (8-Bit Data) ...................................... 234 PMP Master Mode, Demultiplexed Addressing ........................................................ 232 PMP Master Mode, Fully Multiplexed Addressing ........................................................ 233 PMP Master Mode, Partially Multiplexed Addressing ........................................................ 233 PMP Module Overview ............................................. 225 PMP Multiplexed Addressing .................................... 233 PMP Parallel EEPROM (16-Bit Data) ....................... 234 PMP Partially Multiplexed Addressing ...................... 233 (c) 2008 Microchip Technology Inc. C C Compilers MPLAB C18.............................................................. 282 MPLAB C30.............................................................. 282 Charge Time Measurement Unit. See CTMU. Code Examples Basic Clock Switching Example ............................... 115 Configuring UART1 Input and Output Functions (PPS) ............................................... 127 Erasing a Program Memory Block.............................. 58 I/O Port Read/Write .................................................. 122 Initiating a Programming Sequence ........................... 59 Loading the Write Buffers ........................................... 59 Single-Word Flash Programming ............................... 60 Code Protection ................................................................ 277 Code Segment Protection ........................................ 277 Configuration Options....................................... 278 Configuration Protection ........................................... 278 Configuration Bits ............................................................. 269 Core Features....................................................................... 9 CPU Arithmetic Logic Unit (ALU) ........................................ 29 Control Registers........................................................ 28 Core Registers............................................................ 27 Programmer's Model .................................................. 25 CRC Setup Example ......................................................... 245 User Interface ........................................................... 246 CTMU Measuring Capacitance............................................ 265 Measuring Time........................................................ 266 Pulse Delay and Generation..................................... 266 Customer Change Notification Service............................. 323 Customer Notification Service .......................................... 323 Customer Support............................................................. 323 Preliminary DS39897B-page 319 PIC24FJ256GB110 FAMILY I2C D Data Memory Address Space............................................................ 33 Memory Map ............................................................... 33 Near Data Space ........................................................ 34 SFR Space.................................................................. 34 Software Stack ............................................................ 51 Space Organization .................................................... 34 DC Characteristics I/O Pin Input Specifications ....................................... 299 I/O Pin Output Specifications .................................... 300 Program Memory ...................................................... 300 Development Support ....................................................... 281 Device Features (Summary) 100-Pin........................................................................ 13 64-Pin.......................................................................... 11 80-Pin.......................................................................... 12 Doze Mode........................................................................ 120 E Electrical Characteristics A/D Specifications ..................................................... 305 Absolute Maximum Ratings ...................................... 293 Current Specifications ....................................... 296-298 External Clock ........................................................... 302 Load Conditions and Requirements for Specifications.................................................... 301 PLL Clock Specifications .......................................... 303 Thermal Conditions ................................................... 294 V/F Graph ................................................................. 294 Voltage Regulator Specifications .............................. 300 Voltage Specifications............................................... 295 Electrical Characteristics Internal RC Accuracy ................................................ 303 ENVREG Pin..................................................................... 275 Equations A/D Conversion Clock Period ................................... 257 Baud Rate Reload Calculation .................................. 181 Calculating the PWM Period ..................................... 163 Calculation for Maximum PWM Resolution............... 163 Relationship Between Device and SPI Clock Speed............................................... 178 RTCC Calibration ...................................................... 243 UART Baud Rate with BRGH = 0 ............................. 188 Errata .................................................................................... 7 F Flash Configuration Words.................................. 32, 269-273 Flash Program Memory....................................................... 55 and Table Instructions................................................. 55 Enhanced ICSP Operation.......................................... 56 JTAG Operation .......................................................... 56 Programming Algorithm .............................................. 58 RTSP Operation.......................................................... 56 Single-Word Programming.......................................... 60 I I/O Ports Analog Port Pins Configuration ................................. 122 Input Change Notification.......................................... 122 Open-Drain Configuration ......................................... 122 Parallel (PIO) ............................................................ 121 Peripheral Pin Select ................................................ 123 Pull-ups and Pull-downs ........................................... 122 DS39897B-page 320 Clock Rates .............................................................. 181 Reserved Addresses ................................................ 181 Setting Baud Rate as Bus Master............................. 181 Slave Address Masking ............................................ 181 Idle Mode .......................................................................... 120 Input Capture 32-Bit Mode .............................................................. 156 Synchronous and Trigger Modes.............................. 155 Input Capture with Dedicated Timers ............................... 155 Instruction Set Overview................................................................... 287 Summary .................................................................. 285 Instruction-Based Power-Saving Modes................... 119, 120 Inter-Integrated Circuit. See I2C. ...................................... 179 Internet Address ............................................................... 323 Interrupt Vector Table (IVT) ................................................ 67 Interrupts and Reset Sequence .................................................. 67 Control and Status Registers...................................... 70 Implemented Vectors.................................................. 69 Setup and Service Procedures ................................. 108 Trap Vectors ............................................................... 68 Vector Table ............................................................... 68 IrDA Support ..................................................................... 189 J JTAG Interface.................................................................. 279 M Microchip Internet Web Site.............................................. 323 MPLAB ASM30 Assembler, Linker, Librarian ................... 282 MPLAB ICD 2 In-Circuit Debugger ................................... 283 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator .................................... 283 MPLAB Integrated Development Environment Software .............................................. 281 MPLAB PM3 Device Programmer .................................... 283 MPLAB REAL ICE In-Circuit Emulator System ................ 283 MPLINK Object Linker/MPLIB Object Librarian ................ 282 N Near Data Space ................................................................ 34 O Oscillator Configuration Clock Selection ......................................................... 110 Clock Switching ........................................................ 114 Sequence ......................................................... 115 Initial Configuration on POR ..................................... 110 USB Operation ......................................................... 116 Special Considerations..................................... 117 Output Compare 32-Bit Mode .............................................................. 159 Synchronous and Trigger Modes.............................. 159 Output Compare with Dedicated Timers........................... 159 P Packaging ......................................................................... 307 Details....................................................................... 308 Marking ..................................................................... 307 Parallel Master Port. See PMP. ........................................ 225 Peripheral Enable bits....................................................... 120 Peripheral Module Disable bits ......................................... 120 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY Peripheral Pin Select (PPS) .............................................. 123 Available Peripherals and Pins ................................. 123 Configuration Control ................................................ 126 Considerations for Use ............................................. 127 Input Mapping ........................................................... 124 Mapping Exceptions.................................................. 126 Output Mapping ........................................................ 125 Peripheral Priority ..................................................... 123 Registers........................................................... 128-146 PICSTART Plus Development Programmer ..................... 284 Pinout Descriptions ....................................................... 15-23 POR and On-Chip Voltage Regulator................................ 275 Power-Saving Clock Frequency and Clock Switching...................... 119 Power-Saving Features .................................................... 119 Power-up Requirements ................................................... 276 Product Identification System ........................................... 325 Program Memory Access Using Table Instructions................................. 53 Address Construction.................................................. 51 Address Space............................................................ 31 Flash Configuration Words ......................................... 32 Memory Maps ............................................................. 31 Organization................................................................ 32 Program Space Visibility ............................................. 54 Program Space Visibility (PSV) .......................................... 54 Pulse-Width Modulation (PWM) Mode .............................. 162 Pulse-Width Modulation. See PWM. PWM Duty Cycle and Period .............................................. 163 R Reader Response ............................................................. 324 Reference Clock Output.................................................... 117 Register Maps A/D Converter ............................................................. 45 Comparators ............................................................... 48 CPU Core.................................................................... 35 CRC ............................................................................ 48 CTMU.......................................................................... 45 I2C............................................................................... 41 ICN.............................................................................. 36 Input Capture .............................................................. 39 Interrupt Controller ...................................................... 37 NVM ............................................................................ 50 Output Compare ......................................................... 40 Pad Configuration ....................................................... 44 Parallel Master/Slave Port .......................................... 47 Peripheral Pin Select .................................................. 49 PMD ............................................................................ 50 PORTA........................................................................ 43 PORTB........................................................................ 43 PORTC ....................................................................... 43 PORTD ....................................................................... 43 PORTE........................................................................ 44 PORTF........................................................................ 44 PORTG ....................................................................... 44 RTCC .......................................................................... 48 SPI .............................................................................. 42 System ........................................................................ 50 Timers ......................................................................... 38 UART .......................................................................... 42 USB OTG.................................................................... 46 (c) 2008 Microchip Technology Inc. Registers AD1CHS0 (A/D Input Select).................................... 254 AD1CON1 (A/D Control 1)........................................ 251 AD1CON2 (A/D Control 2)........................................ 252 AD1CON3 (A/D Control 3)........................................ 253 AD1CSSH (A/D Input Scan Select, High)................. 256 AD1CSSL (A/D Input Scan Select, Low) .................. 256 AD1PCFGH (A/D Port Configuration, High) ............. 255 AD1PCFGL (A/D Port Configuration, Low)............... 255 ALCFGRPT (Alarm Configuration) ........................... 239 ALMINSEC (Alarm Minutes and Seconds Value) ................................................ 243 ALMTHDY (Alarm Month and Day Value) ................ 242 ALWDHR (Alarm Weekday and Hours Value) ......... 242 BDnSTAT Prototype (Buffer Descriptor n Status, CPU Mode) ...................... 199 BDnSTAT Prototype (Buffer Descriptor n Status, USB Mode) ...................... 198 CLKDIV (Clock Divider) ............................................ 113 CMSTAT (Comparator Status) ................................. 262 CMxCON (Comparator x Control) ............................ 261 CORCON (CPU Control) ............................................ 29 CORCON (CPU Core Control) ................................... 71 CRCCON (CRC Control) .......................................... 247 CRCXOR (CRC XOR Polynomial) ........................... 248 CTMUCON (CTMU Control)..................................... 267 CTMUICON (CTMU Current Control) ....................... 268 CVRCON (Comparator Voltage Reference Control) ........................................... 264 CW1 (Flash Configuration Word 1) .......................... 270 CW2 (Flash Configuration Word 2) .......................... 272 CW3 (Flash Configuration Word 3) .......................... 273 DEVID (Device ID).................................................... 274 DEVREV (Device Revision)...................................... 274 I2CxCON (I2Cx Control)........................................... 182 I2CxMSK (I2C Slave Mode Address Mask).............. 186 I2CxSTAT (I2Cx Status) ........................................... 184 ICxCON1 (Input Capture x Control 1)....................... 157 ICxCON2 (Input Capture x Control 2)....................... 158 IECn (Interrupt Enable Control 0-5)...................... 80-86 IFSn (Interrupt Flag Status 0-5)............................ 74-79 INTCON1 (Interrupt Control 1) ................................... 72 INTCON2 (Interrupt Control 2) ................................... 73 IPCn (Interrupt Priority Control 0-23).................. 87-107 MINSEC (RTCC Minutes and Seconds Value) ................................................ 241 MTHDY (RTCC Month and Day Value).................... 240 NVMCON (Flash Memory Control)............................. 57 OCxCON1 (Output Compare x Control 1) ................ 165 OCxCON2 (Output Compare x Control 2) ................ 166 OSCCON (Oscillator Control)................................... 111 OSCTUN (FRC Oscillator Tune) .............................. 114 PADCFG1 (Pad Configuration Control).................... 231 PADCFG1 (Pad Configuration) ................................ 238 PMADDR (PMP Address)......................................... 229 PMAEN (PMP Enable) ............................................. 229 PMMODE (Parallel Port Mode) ................................ 228 PMPCON (PMP Control) .......................................... 226 PMSTAT (PMP Status)............................................. 230 RCFGCAL (RTCC Calibration and Configuration) ................................................... 237 RCON (Reset Control)................................................ 62 REFOCON (Reference Oscillator Control) ............... 118 RPINRn (PPS Input Mapping 0-29).................. 128-138 RPORn (PPS Output Mapping 0-15)................ 138-146 Preliminary DS39897B-page 321 PIC24FJ256GB110 FAMILY SPIxCON1 (SPIx Control 1) ...................................... 174 SPIxCON2 (SPIx Control 2) ...................................... 175 SPIxSTAT (SPIx Status) ........................................... 172 SR (ALU STATUS) ............................................... 28, 71 T1CON (Timer1 Control)........................................... 148 TxCON (Timer2 and Timer4 Control)........................ 152 TyCON (Timer3 and Timer5 Control)........................ 153 U1ADDR (USB Address) .......................................... 212 U1CNFG1 (USB Configuration 1) ............................. 213 U1CNFG2 (USB Configuration 2) ............................. 214 U1CON (USB Control, Device Mode) ....................... 210 U1CON (USB Control, Host Mode)........................... 211 U1EIE (USB Error Interrupt Enable) ......................... 221 U1EIR (USB Error Interrupt Status) .......................... 220 U1EPn (USB Endpoint n Control) ............................. 222 U1IE (USB Interrupt Enable)..................................... 219 U1IR (USB Interrupt Status, Device Mode) .............. 217 U1IR (USB Interrupt Status, Host Mode) .................. 218 U1OTGCON (USB OTG Control) ............................. 207 U1OTGIE (USB OTG Interrupt Enable) .................... 216 U1OTGIR (USB OTG Interrupt Status) ..................... 215 U1OTGSTAT (USB OTG Status).............................. 206 U1PWMCON USB (VBUS PWM Generator Control) ............................................ 223 U1PWRC (USB Power Control) ................................ 208 U1SOF (USB OTG Start-Of-Token Threshold)......................................................... 213 U1STAT (USB Status) .............................................. 209 U1TOK (USB Token) ................................................ 212 UxMODE (UARTx Mode) .......................................... 190 UxSTA (UARTx Status and Control) ......................... 192 WKDYHR (RTCC Weekday and Hours Value) ..................................................... 241 YEAR (RTCC Year Value) ........................................ 240 Resets BOR (Brown-out Reset) .............................................. 61 Clock Source Selection ............................................... 63 CM (Configuration Mismatch Reset) ........................... 61 Delay Times ................................................................ 64 Device Times .............................................................. 63 IOPUWR (Illegal Opcode Reset) ................................ 61 MCLR (Pin Reset) ....................................................... 61 POR (Power-on Reset) ............................................... 61 RCON Flags Operation ............................................... 63 SFR States.................................................................. 65 SWR (RESET Instruction)........................................... 61 TRAPR (Trap Conflict Reset)...................................... 61 UWR (Uninitialized W Register Reset)........................ 61 WDT (Watchdog Timer Reset).................................... 61 Revision History ................................................................ 317 RTCC Alarm Configuration .................................................. 244 Calibration ................................................................. 243 Register Mapping ...................................................... 236 DS39897B-page 322 S Selective Peripheral Power Control .................................. 120 Serial Peripheral Interface. See SPI. SFR Space ......................................................................... 34 Sleep Mode....................................................................... 119 Software Simulator (MPLAB SIM) .................................... 282 Software Stack.................................................................... 51 Special Features................................................................. 10 SPI T Timer1............................................................................... 147 Timer2/3 and Timer4/5 ..................................................... 149 Timing Diagrams CLKO and I/O Timing ............................................... 304 External Clock........................................................... 302 U UART ................................................................................ 187 Baud Rate Generator (BRG) .................................... 188 Operation of UxCTS and UxRTS Pins...................... 189 Receiving .................................................................. 189 Transmitting 8-Bit Data Mode................................................ 189 9-Bit Data Mode................................................ 189 Break and Sync Sequence ............................... 189 Universal Asynchronous Receiver Transmitter. See UART. Universal Serial Bus. See USB OTG. USB On-The-Go (OTG) ...................................................... 10 USB OTG Buffer Descriptors and BDT...................................... 197 Device Mode Operation ............................................ 202 DMA Interface........................................................... 198 Host Mode Operation................................................ 202 Interrupts .................................................................. 201 OTG Operation ......................................................... 204 Registers .......................................................... 205-223 VBUS Voltage Generation ......................................... 200 V VDDCORE/VCAP Pin ........................................................... 275 Voltage Regulator (On-Chip) ............................................ 275 and BOR ................................................................... 276 Standby Mode .......................................................... 276 Tracking Mode .......................................................... 275 W Watchdog Timer (WDT).................................................... 276 Control Register........................................................ 277 Windowed Operation ................................................ 277 WWW Address ................................................................. 323 WWW, On-Line Support ....................................................... 7 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY THE MICROCHIP WEB SITE CUSTOMER SUPPORT Microchip provides online support via our WWW site at www.microchip.com. This web site is used as a means to make files and information easily available to customers. Accessible by using your favorite Internet browser, the web site contains the following information: Users of Microchip products can receive assistance through several channels: * Product Support - Data sheets and errata, application notes and sample programs, design resources, user's guides and hardware support documents, latest software releases and archived software * General Technical Support - Frequently Asked Questions (FAQ), technical support requests, online discussion groups, Microchip consultant program member listing * Business of Microchip - Product selector and ordering guides, latest Microchip press releases, listing of seminars and events, listings of Microchip sales offices, distributors and factory representatives * * * * * Distributor or Representative Local Sales Office Field Application Engineer (FAE) Technical Support Development Systems Information Line Customers should contact their distributor, representative or field application engineer (FAE) for support. Local sales offices are also available to help customers. A listing of sales offices and locations is included in the back of this document. Technical support is available through the web site at: http://support.microchip.com CUSTOMER CHANGE NOTIFICATION SERVICE Microchip's customer notification service helps keep customers current on Microchip products. Subscribers will receive e-mail notification whenever there are changes, updates, revisions or errata related to a specified product family or development tool of interest. To register, access the Microchip web site at www.microchip.com, click on Customer Change Notification and follow the registration instructions. (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 323 PIC24FJ256GB110 FAMILY READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip product. If you wish to provide your comments on organization, clarity, subject matter, and ways in which our documentation can better serve you, please FAX your comments to the Technical Publications Manager at (480) 792-4150. Please list the following information, and use this outline to provide us with your comments about this document. To: Technical Publications Manager RE: Reader Response Total Pages Sent ________ From: Name Company Address City / State / ZIP / Country Telephone: (_______) _________ - _________ FAX: (______) _________ - _________ Application (optional): Would you like a reply? Y N Device: PIC24FJ256GB110 Family Literature Number: DS39897B Questions: 1. What are the best features of this document? 2. How does this document meet your hardware and software development needs? 3. Do you find the organization of this document easy to follow? If not, why? 4. What additions to the document do you think would enhance the structure and subject? 5. What deletions from the document could be made without affecting the overall usefulness? 6. Is there any incorrect or misleading information (what and where)? 7. How would you improve this document? DS39897B-page 324 Preliminary (c) 2008 Microchip Technology Inc. PIC24FJ256GB110 FAMILY PRODUCT IDENTIFICATION SYSTEM To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office. PIC 24 FJ 256 GB1 10 T - I / PT - XXX Examples: a) Microchip Trademark Architecture Flash Memory Family b) Program Memory Size (KB) Product Group PIC24FJ64GB106-I/PT: PIC24F device with USB On-The-Go, 64-Kbyte program memory, 64-pin, Industrial temp.,TQFP package. PIC24FJ256GB110-I/PT: PIC24F device with USB On-The-Go, 256-Kbyte program memory, 100-pin, Industrial temp.,TQFP package. Pin Count Tape and Reel Flag (if applicable) Temperature Range Package Pattern Architecture 24 = 16-bit modified Harvard without DSP Flash Memory Family FJ = Flash program memory Product Group GB1 = General purpose microcontrollers with USB On-The-Go Pin Count 06 08 10 = 64-pin = 80-pin = 100-pin Temperature Range I = -40C to +85C (Industrial) Package PF PT = 100-lead (14x14x1 mm) TQFP (Thin Quad Flatpack) = 64-lead, 80-lead, 100-lead (12x12x1 mm) TQFP (Thin Quad Flatpack) Pattern Three-digit QTP, SQTP, Code or Special Requirements (blank otherwise) ES = Engineering Sample (c) 2008 Microchip Technology Inc. Preliminary DS39897B-page 325 WORLDWIDE SALES AND SERVICE AMERICAS ASIA/PACIFIC ASIA/PACIFIC EUROPE Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: http://support.microchip.com Web Address: www.microchip.com Asia Pacific Office Suites 3707-14, 37th Floor Tower 6, The Gateway Harbour City, Kowloon Hong Kong Tel: 852-2401-1200 Fax: 852-2401-3431 India - Bangalore Tel: 91-80-4182-8400 Fax: 91-80-4182-8422 India - New Delhi Tel: 91-11-4160-8631 Fax: 91-11-4160-8632 Austria - Wels Tel: 43-7242-2244-39 Fax: 43-7242-2244-393 Denmark - Copenhagen Tel: 45-4450-2828 Fax: 45-4485-2829 India - Pune Tel: 91-20-2566-1512 Fax: 91-20-2566-1513 France - Paris Tel: 33-1-69-53-63-20 Fax: 33-1-69-30-90-79 Japan - Yokohama Tel: 81-45-471- 6166 Fax: 81-45-471-6122 Germany - Munich Tel: 49-89-627-144-0 Fax: 49-89-627-144-44 Atlanta Duluth, GA Tel: 678-957-9614 Fax: 678-957-1455 Boston Westborough, MA Tel: 774-760-0087 Fax: 774-760-0088 Chicago Itasca, IL Tel: 630-285-0071 Fax: 630-285-0075 Dallas Addison, TX Tel: 972-818-7423 Fax: 972-818-2924 Detroit Farmington Hills, MI Tel: 248-538-2250 Fax: 248-538-2260 Kokomo Kokomo, IN Tel: 765-864-8360 Fax: 765-864-8387 Los Angeles Mission Viejo, CA Tel: 949-462-9523 Fax: 949-462-9608 Santa Clara Santa Clara, CA Tel: 408-961-6444 Fax: 408-961-6445 Toronto Mississauga, Ontario, Canada Tel: 905-673-0699 Fax: 905-673-6509 Australia - Sydney Tel: 61-2-9868-6733 Fax: 61-2-9868-6755 China - Beijing Tel: 86-10-8528-2100 Fax: 86-10-8528-2104 Korea - Daegu Tel: 82-53-744-4301 Fax: 82-53-744-4302 China - Chengdu Tel: 86-28-8665-5511 Fax: 86-28-8665-7889 China - Hong Kong SAR Tel: 852-2401-1200 Fax: 852-2401-3431 Korea - Seoul Tel: 82-2-554-7200 Fax: 82-2-558-5932 or 82-2-558-5934 China - Nanjing Tel: 86-25-8473-2460 Fax: 86-25-8473-2470 Malaysia - Kuala Lumpur Tel: 60-3-6201-9857 Fax: 60-3-6201-9859 China - Qingdao Tel: 86-532-8502-7355 Fax: 86-532-8502-7205 Malaysia - Penang Tel: 60-4-227-8870 Fax: 60-4-227-4068 China - Shanghai Tel: 86-21-5407-5533 Fax: 86-21-5407-5066 Philippines - Manila Tel: 63-2-634-9065 Fax: 63-2-634-9069 China - Shenyang Tel: 86-24-2334-2829 Fax: 86-24-2334-2393 Singapore Tel: 65-6334-8870 Fax: 65-6334-8850 China - Shenzhen Tel: 86-755-8203-2660 Fax: 86-755-8203-1760 Taiwan - Hsin Chu Tel: 886-3-572-9526 Fax: 886-3-572-6459 China - Wuhan Tel: 86-27-5980-5300 Fax: 86-27-5980-5118 Taiwan - Kaohsiung Tel: 886-7-536-4818 Fax: 886-7-536-4803 China - Xiamen Tel: 86-592-2388138 Fax: 86-592-2388130 Taiwan - Taipei Tel: 886-2-2500-6610 Fax: 886-2-2508-0102 China - Xian Tel: 86-29-8833-7252 Fax: 86-29-8833-7256 Thailand - Bangkok Tel: 66-2-694-1351 Fax: 66-2-694-1350 Italy - Milan Tel: 39-0331-742611 Fax: 39-0331-466781 Netherlands - Drunen Tel: 31-416-690399 Fax: 31-416-690340 Spain - Madrid Tel: 34-91-708-08-90 Fax: 34-91-708-08-91 UK - Wokingham Tel: 44-118-921-5869 Fax: 44-118-921-5820 China - Zhuhai Tel: 86-756-3210040 Fax: 86-756-3210049 01/02/08 DS39897B-page 326 Preliminary (c) 2008 Microchip Technology Inc.