SGLS126A − JULY 2002 − REVISED FEBRUARY 2003
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265
features
DControlled Baseline
− One Assembly/Test Site, One Fabrication
Site
DExtended Temperature Performance of
−55°C to 125°C
DEnhanced Diminishing Manufacturing
Sources (DMS) Support
DEnhanced Product Change Notification
DQualification Pedigree†
DHigh-Speed 6 MSPS ADC
D4 Single-Ended or 2 Differential Inputs
DSimultaneous Sampling of 4 Single-Ended
Signals or 2 Differential Signals or
Combination of Both
DDifferential Nonlinearity Error: ±1 LSB
DIntegral Nonlinearity Error: ±1.8 LSB
DSignal-to-Noise and Distortion Ratio: 68 dB
at fI = 2 MHz
DAuto-Scan Mode for 2, 3, or 4 Inputs
D3-V or 5-V Digital Interface Compatible
DLow Power: 216 mW Max
D5-V Analog Single Supply Operation
†Component qualification in accordance with JEDEC and industry
standards to ensure reliable operation over an extended
temperature range. This includes, but is not limited to, Highly
Accelerated Stress Test (HAST) or biased 85/85, temperature
cycle, autoclave or unbiased HAST, electromigration, bond
intermetallic life, and mold compound life. Such qualification
testing should not be viewed as justifying use of this component
beyond specified performance and environmental limits.
DInternal Voltage References . . . 50 PPM/°C
and ±5% Accuracy
DGlueless DSP Interface
DParallel µC/DSP Interface
DIntegrated FIFO
DAvailable in TSSOP Package
applications
DRadar Applications
DCommunications
DControl Applications
DHigh-Speed DSP Front-End
DSelected Military Applications
description
The THS1206 is a CMOS, low-power, 12-bit,
6 MSPS analog-to-digital converter (ADC). The
speed, resolution, bandwidth, and single-supply
operation are suited for applications in radar,
imaging, high-speed acquisition, and communications. A multistage pipelined architecture with output error
correction logic provides for no missing codes over the full operating temperature range. Internal control
registers are used to program the ADC into the desired mode. The THS1206 consists of four analog inputs,
which are sampled simultaneously. These inputs can be selected individually and configured to single-ended
or differential inputs. An integrated 16 word deep FIFO allows the storage of data in order to take the load off
of the processor connected to the ADC. Internal reference voltages for the ADC (1.5 V and 3.5 V) are provided.
Copyright 2002 − 2003, Texas Instruments Incorporated
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Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.
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D0
D1
D2
D3
D4
D5
BVDD
BGND
D6
D7
D8
D9
D10/RA0
D11/RA1
CONV_CLK (CONVST)
DATA_AV
AINP
AINM
BINP
BINM
REFIN
REFOUT
REFP
REFM
AGND
AVDD
CS0
CS1
WR (R/W)
RD
DVDD
DGND
DA PACKAGE
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