100k 1M 10M 200M
FREQUENCY (Hz)
4.0
GAIN (dB)
2.0
VO= 0.2VPP
AV= +2
RF= RL= 2k
±5
±2.5V
±1.5V
6.0
8.0
0.0
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LMH664x Low Power, 130 MHz, 75 mA Rail-to-Rail Output Amplifiers
1 Features 3 Description
The LMH664X family true single supply voltage
1(VS= ±5 V, TA= 25°C, RL=2kΩ, AV= +1. feedback amplifiers offer high speed (130 MHz), low
Typical Values Unless Specified). distortion (−62 dBc), and exceptionally high output
•−3 dB BW (AV= +1) 130 MHz current (approximately 75 mA) at low cost and with
• Supply Voltage Range 2.7 V to 12.8 V reduced power consumption when compared against
existing devices with similar performance.
• Slew Rate, (AV=−1) 130V/µs(1)
• Supply Current (no load) 2.7 mA/amp Input common mode voltage range extends to 0.5 V
below V−and 1 V from V+. Output voltage range
• Output Short Circuit Current +115 mA to 145 mA extends to within 40 mV of either supply rail, allowing
• Linear Output Current ±75 mA wide dynamic range especially desirable in low
• Input Common Mode Volt. 0.5 V Beyond V−,1V voltage applications. The output stage is capable of
from V+approximately 75 mA in order to drive heavy loads.
Fast output Slew Rate (130 V/µs) ensures large
• Output Voltage Swing 40 mV from Rails peak-to-peak output swings can be maintained even
• Input Voltage Noise (100 kHz) 17nV/√Hz at higher speeds, resulting in exceptional full power
• Input Current Noise (100 kHz) 0.9pA/√Hz bandwidth of 40 MHz with a 3 V supply. These
characteristics, along with low cost, are ideal features
• THD (5MHz, RL= 2kΩ, VO= 2VPP, AV= +2) −62 for a multitude of industrial and commercial
dBc applications.
• Settling Time 68 ns
• Fully Characterized for 3 V, 5 V, and ±5 V Device Information(1)
• Overdrive Recovery 100 ns PART NUMBER PACKAGE BODY SIZE (NOM)
• Output Short Circuit Protected(2) SOT-23 (5) 2.90 mm × 1.60 mm
LMH6642 SOIC (8) 4.90 mm × 3.91 mm
• No Output Phase Reversal with CMVR Exceeded SOIC (8)
LMH6643 3.00 mm × 3.00 mm
(1) Slew rate is the average of the rising and falling slew rates VSSOP (8)
(2) Output short circuit duration is infinite for VS< 6 V at room SOIC (14) 8.64 mm × 3.91 mm
temperature and below. For VS> 6 V, allowable short circuit LMH6644 TSSOP (14) 5.00 mm × 4.40 mm
duration is 1.5 ms.
(1) For all available packages, see the orderable addendum at
the end of the datasheet.
2 Applications Closed Loop Gain vs. Frequency
• Active Filters for Various Supplies
• CD/DVD ROM
• ADC Buffer Amp
• Portable Video
• Current Sense Buffer
1
An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
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Table of Contents
8.2 Functional Block Diagram....................................... 21
1 Features.................................................................. 18.3 Feature Description................................................. 21
2 Applications ........................................................... 18.4 Device Functional Modes........................................ 21
3 Description............................................................. 19 Application and Implementation ........................ 22
4 Revision History..................................................... 29.1 Application Information............................................ 22
5 Description (continued)......................................... 39.2 Typical Application.................................................. 22
6 Pin Configuration and Functions......................... 410 Power Supply Recommendations ..................... 24
7 Specifications......................................................... 511 Layout................................................................... 25
7.1 Absolute Maximum Ratings ...................................... 511.1 Layout Guidelines ................................................. 25
7.2 Handling Ratings....................................................... 511.2 Layout Example .................................................... 25
7.3 Recommended Operating Conditions....................... 512 Device and Documentation Support................. 26
7.4 Thermal Information.................................................. 512.1 Related Links ........................................................ 26
7.5 3V Electrical Characteristics.................................... 612.2 Trademarks........................................................... 26
7.6 5V Electrical Characteristics.................................... 812.3 Electrostatic Discharge Caution............................ 26
7.7 ±5V Electrical Characteristics................................ 10 12.4 Glossary................................................................ 26
7.8 Typical Performance Characteristics ...................... 12 13 Mechanical, Packaging, and Orderable
8 Detailed Description............................................ 21 Information ........................................................... 26
8.1 Overview................................................................. 21
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision P (March 2013) to Revision Q Page
• Added, revised, or updated the following sections: Device Information Table, Application and Implementation; Power
Supply Recommendations; Device and Documentation Support; Mechanical, Packaging, and Ordering Information ........ 1
• Changed "Junction Temperature Range" to "Operating Temperature Range"...................................................................... 5
• Deleted TJ= 25°C for Electrical Characteristics tables.......................................................................................................... 6
• Changed from "RL" to "Rf" ..................................................................................................................................................... 6
• Deleted TJ= 25°C for Typical Performance Characteristics ................................................................................................ 12
Changes from Revision O (March 2013) to Revision P Page
• Changed layout of National Data Sheet to TI format ............................................................................................................. 1
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5 Description (continued)
Careful attention has been paid to ensure device stability under all operating voltages and modes. The result is a
very well behaved frequency response characteristic (0.1dB gain flatness up the 12 MHz under 150 Ωload and
AV= +2) with minimal peaking (typically 2dB maximum) for any gain setting and under both heavy and light
loads. This along with fast settling time (68ns) and low distortion allows the device to operate well in an ADC
buffer as well as high frequency filter applications.
This device family offers professional quality video performance with low DG (0.01%) and DP (0.01°)
characteristics. Differential Gain and Differential Phase characteristics are also well maintained under heavy
loads (150 Ω) and throughout the output voltage range. The LMH664X family is offered in single (LMH6642),
dual (LMH6643), and quad (LMH6644) options.
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OUT A
+±+±
+±+±
1
2
3
4
5
6
7 8
9
10
11
12
13
14
±IN A
+IN A
V+
+IN B
±IN B
OUT B
OUT D
±IN D
+IN D
V±
+IN C
±IN C
OUT C
A D
B C
OUT B
1
2
3
4 5
6
7
8
OUT A
-IN A
+IN A
V-
V+
-IN B
+IN B
-+
+-
A
B
V+
1
2
3
4 5
6
7
8
N/C
-IN
+IN
V-
OUTPUT
N/C
N/C
+
-
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6 Pin Configuration and Functions
5-Pin SOT-23 (LMH6642) 8-Pin SOIC (LMH6642)
Package DBV05A Package D08A
Top View Top View
8-Pin SOIC and VSSOP (LMH6643) 14-Pin SOIC and 14-Pin TSSOP (LMH6644)
Package DGK08A Package D14A, PW14A
Top View Top View
Pin Functions
PIN
LMH6642 LMH6643 LMH6644 I/O DESCRIPTION
NAME D14A and
DBV05A D08A DGK08A PW14A
-IN 4 2 I Inverting Input
+IN 3 3 I Non-inverting Input
-IN A 2 2 I ChA Inverting Input
+IN A 3 3 I ChA Non-inverting Input
-IN B 6 6 I ChB Inverting Input
+IN B 5 5 I ChB Non-inverting Input
-IN C 9 I ChC Inverting Input
+IN C 10 I ChC Non-inverting Input
-IN D 13 I ChD Inverting Input
+IN D 12 I ChD Non-inverting Input
N/C 1,5,8 –– No connection
OUT A 1 1 O ChA Output
OUT B 7 7 O ChB Output
OUT C 8 O ChC Output
OUT D 14 O ChD Output
OUTPUT 1 6 O Output
V-2 4 4 11 I Negative Supply
V+5 7 8 4 I Positive Supply
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7 Specifications
7.1 Absolute Maximum Ratings(1)(2)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
VIN Differential ±2.5 V
Output Short Circuit Duration See (3) and (4)
Supply Voltage (V+- V−) 13.5 V
V++0.8
Voltage at Input/Output pins V
V−−0.8
Input Current ±10 mA
Junction Temperature(5) +150 °C
Infrared or Convection Reflow (20 sec) 235 °C
Soldering Information Wave Soldering Lead Temp.(10 sec) 260 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) If Military/Aerospace specified devices are required, please contact the TI Sales Office/Distributors for availability and specifications.
(3) Applies to both single-supply and split-supply operation. Continuous short circuit operation at elevated ambient temperature can result in
exceeding the maximum allowed junction temperature of 150°C.
(4) Output short circuit duration is infinite for VS< 6V at room temperature and below. For VS> 6V, allowable short circuit duration is 1.5ms.
(5) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/ RθJA . All numbers apply for packages soldered directly onto a PC board.
7.2 Handling Ratings MIN MAX UNIT
Tstg Storage temperature range −65 +150 °C
Human body model (HBM), per ANSI/ESDA/JEDEC JS-001, 2000
all pins(2)
Electrostatic
V(ESD) Machine model (MM)(3) 200 V
discharge(1) Charged device model (CDM), per JEDEC specification 1000
JESD22-C101, all pins(4)
(1) Human body model, 1.5 kΩin series with 100 pF. Machine Model, 0 Ωin series with 200 pF.
(2) JEDEC document JEP155 states that 2000-V HBM allows safe manufacturing with a standard ESD control process.
(3) JEDEC document JEP157 states that 200-V MM allows safe manufacturing with a standard ESD control process.
(4) JEDEC document JEP157 states that 1000-V CDM allows safe manufacturing with a standard ESD control process.
7.3 Recommended Operating Conditions(1)
over operating free-air temperature range (unless otherwise noted) MIN MAX UNIT
Supply Voltage (V+– V−) 2.7 12.8 V
Operating Temperature Range(2) −40 +85 °C
(1) Absolute Maximum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for
which the device is intended to be functional, but specific performance is not ensured. For ensured specifications and the test
conditions, see the Electrical Characteristics.
(2) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board.
7.4 Thermal Information LMH6642 LMH6643 LMH6644
THERMAL METRIC(1) DBV05A D08A DGK08A D14A PW14A UNIT
5 PINS 8 PINS 8 PINS 14 PINS 14 PINS
RθJA Junction-to-ambient Thermal Resistance(2) 265 190 235 145 155 °C/W
(1) For more information about traditional and new thermal metrics, see the IC Package Thermal Metrics application report, SPRA953.
(2) The maximum power dissipation is a function of TJ(MAX), RθJA, and TA. The maximum allowable power dissipation at any ambient
temperature is PD= (TJ(MAX) - TA)/ RθJA. All numbers apply for packages soldered directly onto a PC board.
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7.5 3V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+= 3V, V−= 0V, VCM = VO= V+/2, VID (input differential voltage) as noted
(where applicable) and RL= 2kΩto V+/2.
PARAMETER TEST CONDITIONS AT V+= 3V, V−= 0V, UNIT
TEMPERATURE VCM = VO= V+/2, VID
EXTREMES RL= 2 kΩto V+/2
MIN TYP MAX MIN(1) TYP(2) MAX(1)
BW −3dB BW AV= +1, VOUT = 200mVPP 80 115 MHz
AV= +2, −1, VOUT = 200mVPP 46
BW0.1dB 0.1dB Gain AV= +2, RL= 150Ωto V+/2, MHz
19
Flatness Rf = 402Ω, VOUT = 200mVPP
PBW Full Power AV= +1, −1dB, VOUT = 1VPP MHz
40
Bandwidth
enInput-Referred f = 100kHz 17 nV/√Hz
Voltage Noise f = 1kHz 48
inInput-Referred f = 100kHz 0.90 pA/√Hz
Current Noise f = 1kHz 3.3
THD Total Harmonic f = 5MHz, VO= 2VPP, AV=−1, −48 dBc
Distortion RL= 100Ωto V+/2
DG Differential Gain VCM = 1V, NTSC, AV= +2 0.17%
RL=150Ωto V+/2
RL=1kΩto V+/2 0.03%
DP Differential VCM = 1V, NTSC, AV= +2 0.05
Phase RL=150Ωto V+/2 deg
RL=1kΩto V+/2 0.03
CT Rej. Cross-Talk f = 5MHz, Receiver: dB
47
Rejection Rf= Rg= 510Ω, AV= +2
TSSettling Time VO= 2VPP, ±0.1%, 8pF Load, ns
68
VS= 5V
SR Slew Rate (3) AV=−1, VI= 2VPP 90 120 V/µs
VOS Input Offset For LMH6642 and LMH6644 ±7 ±1 ±5 mV
Voltage For LMH6643 ±7 ±1 ±3.4
TC VOS Input Offset See (4) µV/°C
±5
Average Drift
IBInput Bias See (5) −3.25 −1.50 −2.60 µA
Current
IOS Input Offset 1000 20 800 nA
Current
RIN Common Mode MΩ
3
Input Resistance
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Slew rate is the average of the rising and falling slew rates.
(4) Offset voltage average drift determined by dividing the change in VOS at temperature extremes by the total temperature change.
(5) Positive current corresponds to current flowing into the device.
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3V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+= 3V, V−= 0V, VCM = VO= V+/2, VID (input differential voltage) as noted
(where applicable) and RL= 2kΩto V+/2.
PARAMETER TEST CONDITIONS AT V+= 3V, V−= 0V, UNIT
TEMPERATURE VCM = VO= V+/2, VID
EXTREMES RL= 2 kΩto V+/2
MIN TYP MAX MIN(1) TYP(2) MAX(1)
CIN Common Mode pF
Input 2
Capacitance
CMVR Input Common- CMRR ≥50dB −0.1 −0.5 −0.2
Mode Voltage V
1.6 1.8 2.0
Range
CMRR Common Mode VCM Stepped from 0V to 1.5V dB
72 95
Rejection Ratio
AVOL Large Signal VO= 0.5V to 2.5V 75 80 96
Voltage Gain RL= 2kΩto V+/2 dB
VO= 0.5V to 2.5V 70 74 82
RL= 150Ωto V+/2
VOOutput Swing RL= 2kΩto V+/2, VID = 200mV 2.90 2.98 V
High RL= 150Ωto V+/2, VID = 200mV 2.80 2.93
Output Swing RL= 2kΩto V+/2, VID =−200mV 25 75 mV
Low RL= 150Ωto V+/2, VID =−200mV 75 150
ISC Output Short Sourcing to V+/2 35 50 95
Circuit Current VID = 200mV (6) mA
Sinking to V+/2 40 55 110
VID =−200mV (6)
IOUT Output Current VOUT = 0.5V from either supply ±65 mA
+PSRR Positive Power V+= 3.0V to 3.5V, VCM = 1.5V dB
Supply 75 85
Rejection Ratio
ISSupply Current No Load 4.50 2.70 4.00 mA
(per channel)
(6) Short circuit test is a momentary test. See Note 7 under 5 V Electrical Characteristics.
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7.6 5V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+= 5V, V−= 0V, VCM = VO= V+/2, VID (input differential voltage) as noted
(where applicable) and RL= 2kΩto V+/2. V+= 5V, V−= 0V, UNIT
AT TEMPERATURE VCM = VO= V+/2, VID
EXTREMES
PARAMETER TEST CONDITIONS RL= 2kΩto V+/2
MIN TYP MAX MIN(1) TYP(2) MAX(1)
BW −3dB BW AV= +1, VOUT = 200mVPP 90 120 MHz
AV= +2, −1, VOUT = 200mVPP 46
BW0.1dB 0.1dB Gain AV= +2, RL= 150Ωto V+/2, MHz
15
Flatness Rf= 402Ω, VOUT = 200mVPP
PBW Full Power AV= +1, −1dB, VOUT = 2VPP MHz
22
Bandwidth
enInput-Referred f = 100kHz 17 nV/√Hz
Voltage Noise f = 1kHz 48
inInput-Referred f = 100kHz 0.90 pA/√Hz
Current Noise f = 1kHz 3.3
THD Total Harmonic f = 5MHz, VO= 2VPP, AV= +2 dBc
−60
Distortion
DG Differential Gain NTSC, AV= +2 0.16%
RL=150Ωto V+/2
RL= 1kΩto V+/2 0.05%
DP Differential NTSC, AV= +2 0.05
Phase RL= 150Ωto V+/2 deg
RL= 1kΩto V+/2 0.01
CT Rej. Cross-Talk f = 5MHz, Receiver: 47 dB
Rejection Rf= Rg= 510Ω, AV= +2
TSSettling Time VO= 2VPP, ±0.1%, 8pF Load 68 ns
SR Slew Rate (3) AV=−1, VI= 2VPP 95 125 V/µs
VOS Input Offset For LMH6642 and LMH6644 ±7 ±1 ±5 mV
Voltage For LMH6643 ±7 ±1 ±3.4
TC VOS Input Offset See (4) µV/°C
±5
Average Drift
IBInput Bias See (5) −3.25 −1.70 −2.60 µA
Current
IOS Input Offset 1000 20 800 nA
Current
RIN Common Mode MΩ
Input 3
Resistance
CIN Common Mode pF
Input 2
Capacitance
CMVR Input Common- CMRR ≥50dB −0.1 −0.5 −0.2
Mode Voltage V
3.6 3.8 4.0
Range
CMRR Common Mode VCM Stepped from 0V to 3.5V dB
72 95
Rejection Ratio
AVOL Large Signal VO= 0.5V to 4.50V 82 86 98
Voltage Gain RL= 2kΩto V+/2 dB
VO= 0.5V to 4.25V 72 76 82
RL= 150Ωto V+/2
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Slew rate is the average of the rising and falling slew rates.
(4) Offset voltage average drift determined by dividing the change in VOS at temperature extremes by the total temperature change.
(5) Positive current corresponds to current flowing into the device.
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5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+= 5V, V−= 0V, VCM = VO= V+/2, VID (input differential voltage) as noted
(where applicable) and RL= 2kΩto V+/2. V+= 5V, V−= 0V, UNIT
AT TEMPERATURE VCM = VO= V+/2, VID
EXTREMES
PARAMETER TEST CONDITIONS RL= 2kΩto V+/2
MIN TYP MAX MIN(1) TYP(2) MAX(1)
VOOutput Swing RL= 2kΩto V+/2, VID = 200mV 4.90 4.98 V
High RL= 150Ωto V+/2, VID = 200mV 4.65 4.90
Output Swing RL= 2kΩto V+/2, VID =−200mV 25 100 mV
Low RL= 150Ωto V+/2, VID =−200mV 100 150
ISC Output Short Sourcing to V+/2 40 55 115
Circuit Current VID = 200mV (6)(7) mA
Sinking to V+/2 55 70 140
VID =−200mV (6)(7)
IOUT Output Current VO= 0.5V from either supply ±70 mA
+PSRR Positive Power V+= 4.0V to 6V dB
Supply 79 90
Rejection Ratio
ISSupply Current No Load 5.00 2.70 4.25 mA
(per channel)
(6) Short circuit test is a momentary test. See Note 7.
(7) Output short circuit duration is infinite for VS< 6V at room temperature and below. For VS> 6V, allowable short circuit duration is 1.5ms.
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7.7 ±5V Electrical Characteristics
Unless otherwise specified, all limits ensured for V+= 5V, V−=−5V, VCM = VO= 0V, VID (input differential voltage) as noted
(where applicable) and RL= 2kΩto ground. AT TEMPERATURE V+= 5V, V−=−5V, UNIT
EXTREMES VCM = VO= 0V, VID
PARAMETER TEST CONDITIONS MIN TYP MAX MIN(1) TYP(2) MAX(1)
BW −3dB BW AV= +1, VOUT = 200mVPP 95 130 MHz
AV= +2, −1, VOUT = 200mVPP 46
BW0.1dB 0.1dB Gain AV= +2, RL= 150Ωto V+/2, MHz
12
Flatness Rf= 806Ω, VOUT = 200mVPP
PBW Full Power AV= +1, −1dB, VOUT = 2VPP MHz
24
Bandwidth
enInput-Referred f = 100kHz 17 nV/√Hz
Voltage Noise f = 1kHz 48
inInput-Referred f = 100kHz 0.90 pA/√Hz
Current Noise f = 1kHz 3.3
THD Total Harmonic f = 5MHz, VO= 2VPP, AV= +2 dBc
−62
Distortion
DG Differential Gain NTSC, AV= +2 0.15%
RL= 150Ωto V+/2
RL= 1kΩto V+/2 0.01%
DP Differential NTSC, AV= +2 0.04
Phase RL= 150Ωto V+/2 deg
RL= 1kΩto V+/2 0.01
CT Rej. Cross-Talk f = 5MHz, Receiver: 47 dB
Rejection Rf= Rg= 510Ω, AV= +2
TSSettling Time VO= 2VPP, ±0.1%, 8pF Load, ns
68
VS= 5V
SR Slew Rate (3) AV=−1, VI= 2VPP 100 135 V/µs
VOS Input Offset For LMH6642 and LMH6644 ±7 ±1 ±5 mV
Voltage For LMH6643 ±7 ±1 ±3.4
TC VOS Input Offset See (4) µV/°C
±5
Average Drift
IBInput Bias See (5) −3.25 −1.60 −2.60 µA
Current
IOS Input Offset 1000 20 800 nA
Current
RIN Common Mode MΩ
Input 3
Resistance
CIN Common Mode pF
Input 2
Capacitance
CMVR Input Common- CMRR ≥50dB −5.1 −5.5 −5.2
Mode Voltage V
3.6 3.8 4.0
Range
CMRR Common Mode VCM Stepped from −5V to 3.5V dB
74 95
Rejection Ratio
(1) All limits are ensured by testing or statistical analysis.
(2) Typical values represent the most likely parametric norm.
(3) Slew rate is the average of the rising and falling slew rates.
(4) Offset voltage average drift determined by dividing the change in VOS at temperature extremes by the total temperature change.
(5) Positive current corresponds to current flowing into the device.
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±5V Electrical Characteristics (continued)
Unless otherwise specified, all limits ensured for V+= 5V, V−=−5V, VCM = VO= 0V, VID (input differential voltage) as noted
(where applicable) and RL= 2kΩto ground. AT TEMPERATURE V+= 5V, V−=−5V, UNIT
EXTREMES VCM = VO= 0V, VID
PARAMETER TEST CONDITIONS MIN TYP MAX MIN(1) TYP(2) MAX(1)
AVOL Large Signal VO=−4.5V to 4.5V, 84 88 96
Voltage Gain RL= 2kΩdB
VO=−4.0V to 4.0V, 74 78 82
RL= 150Ω
VOOutput Swing RL= 2kΩ, VID = 200mV 4.90 4.96 V
High RL= 150Ω, VID = 200mV 4.65 4.80
Output Swing RL= 2kΩ, VID =−200mV −4.96 −4.90 V
Low RL= 150Ω, VID =−200mV −4.80 −4.65
ISC Output Short Sourcing to Ground 35 60 115
Circuit Current VID = 200mV (6)(7) mA
Sinking to Ground 65 85 145
VID =−200mV (6)(7)
IOUT Output Current VO= 0.5V from either supply ±75 mA
PSRR Power Supply (V+, V−) = (4.5V, −4.5V) to (5.5V, dB
78 90
Rejection Ratio −5.5V)
ISSupply Current No Load 5.50 2.70 4.50 mA
(per channel)
(6) Short circuit test is a momentary test. See (7).
(7) Output short circuit duration is infinite for VS< 6V at room temperature and below. For VS> 6V, allowable short circuit duration is 1.5ms.
Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 11
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10k 100k 1M 10M 100M 500M
-4
-2
0
GAIN (dB)
FREQUENCY (Hz)
VS = ±5V
RL = 2k
AV = +1
VOUT = 0.2VPP
-40°C
85°C
25°C
100k 1M 10M 200M
FREQUENCY (Hz)
6.5
GAIN (dB)
6.0
AV = +2
RF = 2k
RL = 150
VO = 0.2VPP
±1.5V
5.5
7.0
5.0
±2.5V
±5V
AV = +1
AV = +5
AV = +10
AV = +2
10k 100k 1M 10M 100M 500M
-3
-2
-1
0
+1
+2
+3
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
VS = ±1.5V
RL = 2k
VOUT = 0.2VPP
10k 100k 1M 10M 100M 500M
-6
-4
-2
0
GAIN (dB)
FREQUENCY (Hz)
-40°C
25°C
85°C
VS = ±1.5V
RL = 2k
AV = +1
VO = 0.2VPP
10k 100k 1M 10M 100M 500
M
-3
-2
-1
0
+1
+2
+3
NORMALIZED GAIN (dB)
FREQUENCY (Hz)
VS = ±5V
RL = 2k
VOUT = 0.2VPP
AV = +5
AV = +1
AV = +2
AV = +10
100k 1M 10M 200M
FREQUENCY (Hz)
-2
-1
0
GAIN (dB)
-3
VS = ±2.5V
VS = ±5V
VS = ±1.5V
VS = ±1.5V
VS = ±2.5V
VS = ±5V
AV = +1
RL = 2k
VOUT = 0.2VPP
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7.8 Typical Performance Characteristics
V+= +5, V−=−5V, RF= RL= 2 kΩ. Unless otherwise specified.
Figure 1. Closed Loop Frequency Response Figure 2. Closed Loop Gain vs. Frequency
for Various Supplies for Various Gain
Figure 4. Closed Loop Frequency Response
Figure 3. Closed Loop Gain vs. Frequency for Various Temperature
for Various Gain
Figure 5. Closed Loop Gain vs. Frequency Figure 6. Closed Loop Frequency Response
for Various Supplies for Various Temperature
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100k 1M 10M 100M
FREQUENCY (Hz)
0
1
2
3
VOUT (VPP)
VS = 3V
AV = -1
RL = 2k
RL = 100:
100K 1M 10M 100M
FREQUENCY (Hz)
0
1
2
3
4
5
VOUT (VPP)
VS = 5V
AV = -1
Rf = 2k
RL = 2K to VS/2
100K 1M 10M 200M
FREQUENCY (Hz)
-0.1
+0.1
GAIN (dB)
0
VO = 0.4VPP
AV = +2
RF = 806:
RL = 150:
±5V
±2.5V
±1.5V
+0.2
+0.3
PHASE (deg)
-155
-65
-20
+25
±1.5V
±2.5V
±5V
GAIN
PHASE
-110
100K 1M 10M 200M
FREQUENCY (Hz)
0
2
4
6
GAIN (dB)
±5V
±1.5V
±2.5V
VO = 0.4VPP
AV = +2
RF = 806:
RL 150:
100k 1M 10M 200M
FREQUENCY (Hz)
4.0
GAIN (dB)
2.0
VO= 0.2VPP
AV= +2
RF= RL= 2k
±5
±2.5V
±1.5V
6.0
8.0
0.0
100k 1M 10M 200M
FREQUENCY (Hz)
4.0
GAIN (dB)
2.0
AV = +2
RF = RL = 2k
±5V
4VPP
±2.5V
2VPP
6.0
8.0
0.0
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Typical Performance Characteristics (continued)
V+= +5, V−=−5V, RF= RL= 2 kΩ. Unless otherwise specified.
Figure 7. Large Signal Frequency Response Figure 8. Closed Loop Small Signal Frequency Response
for Various Supplies
Figure 9. Closed Loop Frequency Response Figure 10. ±0.1dB Gain Flatness
for Various Supplies for Various Supplies
Figure 11. VOUT (VPP) for THD < 0.5% Figure 12. VOUT (VPP) for THD < 0.5%
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0.0 1.0 2.0 3.0 4.0 5.0
-20
-30
-40
-50
-60
-70
-80
-90
HD2 (dBc)
VOUT (VPP)
VS = 5V, AV = +2
RL = 2k: & 100: to VS/2
100:,1MHz
100:5MHz 2k:, 5MHz
2k:, 10MHz
100:, 10MHz
10k 100k 1M 10M 150M
FREQUENCY (Hz)
-20
0
20
40
60
80
GAIN (dB)
PHASE (Deg)
40
20
0
60
VS = ±5V
RL = 2k -40°C
85°C
25°C
GAIN
PHASE
100k 1M 10M 100M
FREQUENCY (Hz)
0
4
7
10
VOUT (VPP)
VS = ±5V
AV = -1
RL = 100:
8
9
6
5
3
2
1
RL =
2K
FREQUENCY (Hz)
10k 100k 1M 10M 150M
-20
0
20
40
60
80
GAIN (dB)
PHASE (Deg)
40
20
0
60
VS = ±1.5V
RL= 2k
-40°C
85°C
25°C
PHASE
GAIN
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Typical Performance Characteristics (continued)
V+= +5, V−=−5V, RF= RL= 2 kΩ. Unless otherwise specified.
Figure 14. Open Loop Gain/Phase
Figure 13. VOUT (VPP) for THD < 0.5% for Various Temperature
Figure 16. HD2 (dBc) vs. Output Swing
Figure 15. Open Loop Gain/Phase
for Various Temperature
Figure 18. HD2 vs. Output Swing
Figure 17. HD3 (dBc) vs. Output Swing
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25°C
85°C
110 100 1K
ISINK (mA)
0.01
0.1
1
10
VOUT FROM V- (V)
-40°C
VS=±1.5V
110 100 1k
ISOURCE (mA)
0.01
0.1
1
10
VOUT FROM V+ (V)
85°C
25°C
-40°C
VS = ±1.5V
±0.1% SETTLING TIME
0.5 1 1.5 2
INPUT STEP AMPLITUDE (VPP)
0
10
20
30
40
50
60
70
80
VS = 5V
AV = -1
Rf = RL = 2k
CL = 8pF
10 100 1K 10K 100K
FREQUENCY (Hz)
1
10
100
1k
1M
100
10
1
0.1
Hz)
en (nV/
Hz)
in (pA/
CURRENT
VOLTAGE
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SNOS966Q –MAY 2001–REVISED SEPTEMBER 2014
Typical Performance Characteristics (continued)
V+= +5, V−=−5V, RF= RL= 2 kΩ. Unless otherwise specified.
Figure 19. HD3 vs. Output Swing Figure 20. THD (dBc) vs. Output Swing
Figure 22. Input Noise vs. Frequency
Figure 21. Settling Time vs. Input Step Amplitude
(Output Slew and Settle Time)
Figure 23. VOUT from V+vs. ISOURCE Figure 24. VOUT from V−vs. ISINK
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0 20 40 60 80 100 120
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
VOUT FROM V+ (V)
ISOURCING (mA)
VS = ±2.5V
25°C
85°C
-40°C
0 20 40 60 80 100 120
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
0.8
0.9
1
VOUT FROM V- (V)
ISINK(mA)
25°C
85°C
-40°C
VS = ±2.5
VS (V)
2 3 4 5 6 7 8 9 10
0
180
ISC (mA)
20
40
60
80
100
120
140
160
-40°C, Source
25°C, Source
85°C, Source
-40°C, Sink
25°C, Sink
85°C, Sink
23 4 5 6 7 8 9 10
VS (V)
20
40
60
80
100
120
140
160
VOUT FROM SUPPLY (mV)
-40°C, Sourcing
25°C, Sourcing
85°C, Sourcing
25°C, Sinking
85°C, Sinking
-40°C, Sinking
RL = 150:
110 100 1k
ISOURCE (mA)
0.01
0.1
1
10
VOUT FROM V+ (V)
85°
C
25°C
-40°C
85°C
-40°C
VS = ±5V
110 100 1k
ISINK (mA)
0.01
0.1
1
10
VOUT FROM V- (V)
85°C
25°C
-40°C
VS = ±5V
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Typical Performance Characteristics (continued)
V+= +5, V−=−5V, RF= RL= 2 kΩ. Unless otherwise specified.
Figure 25. VOUT from V+vs. ISOURCE Figure 26. VOUT from V−vs. ISINK
Figure 27. Swing vs. VSFigure 28. Short Circuit Current (to VS/2) vs. VS
Figure 29. Output Sinking Saturation Voltage vs. IOUT Figure 30. Output Sourcing Saturation Voltage vs. IOUT
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0 1 2 3 4 5
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
VOS (mV)
VOUT (V)
VS = 5V
RL = 150: to V+/2
-40°C
25°C
85°C
-2 0 2 4 6 8 10
VCM (V)
-2
-1.5
-1
-0.5
0
0.5
1.0
1.5
2
VOS (mV)
-40°C
25°C
85°C
VS = 10V
30
40
50
60
70
100
CMRR (dB)
100 1k 10k 100k 1M
FREQUENCY (Hz)
80
90
10M
VS = 5V
AV = +6
1k 100k 10M
FREQUENCY (Hz)
0.01
1
1000
ZOUT (:)
100M
1M
10k
100
10
0.1
AV = +1
10k 100k 1M 10M 100M
FREQUENCY (Hz)
0
10
20
30
40
50
60
70
80
90
PSRR (dB)
+ PSRR
- PSRR
VS = 5V
AV = +10
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Typical Performance Characteristics (continued)
V+= +5, V−=−5V, RF= RL= 2 kΩ. Unless otherwise specified.
Figure 31. Closed Loop Output Impedance Figure 32. PSRR vs. Frequency
vs. Frequency AV= +1
Figure 33. CMRR vs. Frequency Figure 34. Crosstalk Rejection vs. Frequency
(Output to Output)
Figure 36. VOS vs. VCM (Typical Unit)
Figure 35. VOS vs. VOUT (Typical Unit)
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2 4 6 8 10 12
0
5
10
15
20
25
30
35
40
45
50
IOS (nA)
VS (V)
-40°C
25°C
85°C
-2 0 2 4 6 8 10
VCM (V)
-0.5
0.5
1
1.5
2
2.5
3
3.5
4
IS (mA) (PER CHANNEL)
-40°C
25°C
85°C
VS = 10V
0
2 4 6 8 10 12
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
VOS (mV)
VS (V)
Unit #1
Unit #2
Unit #3
85°C
53 7 9
-1000
2 4 6 8 10 12
-1900
-1800
-1700
-1600
-1500
-1400
-1300
-1200
-1100
IB (nA)
VS (V)
-40°C
25°C
85°C
2 4 6 8 10 12
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
VOS (mV)
VS (V)
Unit #1
Unit #2
Unit #3
-40°C
2 4 6 8 10 11
-1
-0.8
-0.6
-0.4
-0.2
0
0.2
0.4
0.6
0.8
1
VOS (mV)
VS (V)
Unit #1
Unit #2
Unit #3
25°C
9
7
5
3
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Typical Performance Characteristics (continued)
V+= +5, V−=−5V, RF= RL= 2 kΩ. Unless otherwise specified.
Figure 37. VOS vs. VS(for 3 Representative Units) Figure 38. VOS vs. VS(for 3 Representative Units)
Figure 40. IBvs. VS
Figure 39. VOS vs. VS(for 3 Representative Units)
Figure 42. ISvs. VCM
Figure 41. IOS vs. VS
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40 mV/DIV 10.0 ns/DIV
VS = ±5V
VO = 100mVPP
AV = +1, RL = 2k
40 mV/DIV 10 ns/DIV
VS = 3V
VO = 100mVPP
RL = 2k to VS/2
AV = +1
400 mV/DIV 40.0 nS/DIV
VS=±1.5V
VO=2VPP
AV= -1
RL=2k
4 /DIV
VS = ±5V
VO = 8VPP
RL= 2k
AV = +2
AV = +1
200.0 ns/DIV
2 4 6 8 10 12
1
2
3
4
IS (mA) (PER CHANNEL)
VS (V)
85°C
-40°C
25°C
VS = 3V
VO = 100mVPP
RL = 2k to VS/2
AV = -1
40 mV/DIV 20 ns/DIV
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Typical Performance Characteristics (continued)
V+= +5, V−=−5V, RF= RL= 2 kΩ. Unless otherwise specified.
Figure 43. ISvs. VSFigure 44. Small Signal Step Response
Figure 45. Large Signal Step Response Figure 46. Large Signal Step Response
Figure 47. Small Signal Step Response Figure 48. Small Signal Step Response
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2 V/DIV 100 ns/DIV
AV = -1 VS = ±5V
VOUT = 8VPP RL = 2K:
2 V/DIV
VS = ±5V
VO = 8VPP
AV = +2
RL = 2k
40.0 ns/DIV
VS = ±5V
VO = 2VPP
RL = 2k
AV = -1
400 mV/DIV 20 ns/DIV
VS = ±5V
VO = 200mVPP
AV = +2,
RL = 2k
40 mV/DIV 20.0 ns/DIV
VS = ±5V
VO = 100mVPP
RL = 2k
AV = -1
20 ns/DIV
40 mV/DIV
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Typical Performance Characteristics (continued)
V+= +5, V−=−5V, RF= RL= 2 kΩ. Unless otherwise specified.
Figure 49. Small Signal Step Response Figure 50. Small Signal Step Response
Figure 52. Large Signal Step Response
Figure 51. Large Signal Step Response
Figure 53. Large Signal Step Response
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IN+ IN-
R R
V-
V+
V+V+
V-
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8 Detailed Description
8.1 Overview
The LMH664X family is based on proprietary VIP10 dielectrically isolated bipolar process. This device family
architecture features the following:
• Complimentary bipolar devices with exceptionally high ft(∼8 GHz) even under low supply voltage (2.7 V) and
low bias current.
• A class A-B “turn-around” stage with improved noise, offset, and reduced power dissipation compared to
similar speed devices (patent pending).
• Common Emitter push-push output stage capable of 75 mA output current (at 0.5 V from the supply rails)
while consuming only 2.7 mA of total supply current per channel. This architecture allows output to reach
within mV of either supply rail.
• Consistent performance over the entire operating supply voltage range with little variation for the most
important specifications (for example, BW, SR, IOUT, and so forth)
• Significant power saving (∼40%) compared to competitive devices on the market with similar performance.
8.2 Functional Block Diagram
Figure 54. Input Equivalent Circuit
8.3 Feature Description
The LMH664X family is a drop-in replacement for the AD805X family of high speed Op Amps in most
applications. In addition, the LMH664X will typically save about 40% on power dissipation, due to lower supply
current, when compared to competition. All AD805X family’s specified parameters are included in the list of
LMH664X ensured specifications in order to ensure equal or better level of performance. However, as in most
high performance parts, due to subtleties of applications, it is strongly recommended that the performance of the
part to be evaluated is tested under actual operating conditions to ensure full compliance to all specifications.
8.4 Device Functional Modes
With 3-V supplies and a common mode input voltage range that extends 0.5 V below V−, the LMH664X find
applications in low voltage/low power applications. Even with 3-V supplies, the −3dB BW (@ AV= +1) is typically
115 MHz with a tested limit of 80 MHz. Production testing guarantees that process variations will not compromise
speed. High frequency response is exceptionally stable, confining the typical −3dB BW over the industrial
temperature range to ±2.5%.
As seen in Typical Performance Characteristics, the LMH664X output current capability (∼75 mA) is enhanced
compared to AD805X. This enhancement increases the output load range, adding to the LMH664X’s versatility.
Since LMH664X is capable of high output current, device junction temperature should not to exceed the Absolute
Maximum Ratings.
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+
-
Vbias
Cd10
-
200pF
Photodiode Rd
C1
100nF Q1
2N3904
R5
510:
R2
1.8k:
D1
1N4148
R3
1k:
R11
910
:R10
1k:
-1mAPP
Cf
5pF
Rf
1k:
VCC =
+5V
Rbias
Photodiode
Equivalent
Circuit
Id×100k:
Vout
+5V
x
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9 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
9.1 Application Information
This device family was designed to avoid output phase reversal. With input overdrive, the output is kept near
supply rail (or as closed to it as mandated by the closed loop gain setting and the input voltage). See Figure 56.
However, if the input voltage range of −0.5 V to 1 V from V+is exceeded by more than a diode drop, the internal
ESD protection diodes will start to conduct. The current in the diodes should be kept at or below 10 mA.
Output overdrive recovery time is less than 100 ns as can be seen in Figure 57.
9.2 Typical Application
Figure 55. Single Supply Photodiode I-V Converter
9.2.1 Design Requirements
The circuit shown in Figure 55 is used to amplify the current from a photodiode into a voltage output. In this
circuit, the emphasis is on achieving high bandwidth and the transimpedance gain setting is kept relatively low.
Because of its high slew rate limit and high speed, the LMH664X family lends itself well to such an application.
This circuit achieves approximately 1V/mA of transimpedance gain and capable of handling up to 1mApp from
the photodiode. Q1, in a common base configuration, isolates the high capacitance of the photodiode (Cd) from
the Op Amp input in order to maximize speed. Input is AC coupled through C1 to ease biasing and allow single
supply operation. With 5-V single supply, the device input/output is shifted to near half supply using a voltage
divider from VCC. Note that Q1 collector does not have any voltage swing and the Miller effect is minimized. D1,
tied to Q1 base, is for temperature compensation of Q1’s bias point. Q1 collector current was set to be large
enough to handle the peak-to-peak photodiode excitation and not too large to shift the U1 output too far from
mid-supply.
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SQRT GBWP/(2SRF CIN)
fP =
CF =SQRT (CIN)/(2SGBWP RF)
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Typical Application (continued)
9.2.1.1 Input and Output Topology
All input / output pins are protected against excessive voltages by ESD diodes connected to V+and V-rails (see
Figure 54). These diodes start conducting when the input / output pin voltage approaches 1Vbe beyond V+or V-
to protect against over voltage. These diodes are normally reverse biased. Further protection of the inputs is
provided by the two resistors (R in Figure 54), in conjunction with the string of anti-parallel diodes connected
between both bases of the input stage. The combination of these resistors and diodes reduces excessive
differential input voltages approaching 2Vbe. This occurs most commonly when the device is used as a
comparator (or with little or no feedback) and the device inputs no longer follow each other. In such a case, the
diodes may conduct. As a consequence, input current increases and the differential input voltage is clamped. It is
important to make sure that the subsequent current flow through the device input pins does not violate the
Absolute Maximum Ratings of the device. To limit the current through this protection circuit, extra series resistors
can be placed. Together with the built-in series resistors of several hundred ohms, these external resistors can
limit the input current to a safe number (that is, less than 10mA). Be aware that these input series resistors may
impact the switching speed of the device and could slow down the device.
9.2.1.2 Single Supply, Low Power Photodiode Amplifier
The circuit shown in Figure 55 is used to amplify the current from a photodiode into a voltage output. In this
circuit, the emphasis is on achieving high bandwidth and the transimpedance gain setting is kept relatively low.
Because of its high slew rate limit and high speed, the LMH664X family lends itself well to such an application.
This circuit achieves approximately 1V/mA of transimpedance gain and capable of handling up to 1mApp from the
photodiode. Q1, in a common base configuration, isolates the high capacitance of the photodiode (Cd) from the
Op Amp input in order to maximize speed. Input is AC coupled through C1 to ease biasing and allow single
supply operation. With 5V single supply, the device input/output is shifted to near half supply using a voltage
divider from VCC. Note that Q1 collector does not have any voltage swing and the Miller effect is minimized. D1,
tied to Q1 base, is for temperature compensation of Q1’s bias point. Q1 collector current was set to be large
enough to handle the peak-to-peak photodiode excitation and not too large to shift the U1 output too far from
mid-supply.
No matter how low an Rfis selected, there is a need for Cfin order to stabilize the circuit. The reason for this is
that the Op Amp input capacitance and Q1 equivalent collector capacitance together (CIN) will cause additional
phase shift to the signal fed back to the inverting node. Cfwill function as a zero in the feedback path counter-
acting the effect of the CIN and acting to stabilized the circuit. By proper selection of Cfsuch that the Op Amp
open loop gain is equal to the inverse of the feedback factor at that frequency, the response is optimized with a
theoretical 45° phase margin.
where
• GBWP is the Gain Bandwidth Product of the Op Amp (1)
Optimized as such, the I-V converter will have a theoretical pole, fp, at:
(2)
With Op Amp input capacitance of 3pF and an estimate for Q1 output capacitance of about 3pF as well, CIN = 6
pF. From the typical performance plots, LMH6642/6643 family GBWP is approximately 57 MHz. Therefore, with
Rf= 1k, from Equation 1 and Equation 2:
Cf=∼4.1 pF and fp= 39 MHz (3)
For this example, optimum Cfwas empirically determined to be around 5 pF. This time domain response is
shown in Figure 58 below showing about 9 ns rise/fall times, corresponding to about 39 MHz for fp. The overall
supply current from the +5 V supply is around 5 mA with no load.
Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 23
Product Folder Links: LMH6642 LMH6643 LMH6644
200 mV/DIV 20 ns/DIV
VIN (1 V/DIV)
VOUT (2 V/DIV)
VS=±5V, VIN=5VPP
AV=+5, RF=RL=2k
2 V/DIV 100 ns/DIV
VOUT (VPP)
1V/DIV 200 ns/DIV
VS = ±2.5V
AV = +1
V+
V-
Output
Input
LMH6642
,
LMH6643
,
LMH6644
SNOS966Q –MAY 2001–REVISED SEPTEMBER 2014
www.ti.com
Typical Application (continued)
9.2.2 Detailed Design Procedure
No matter how low an Rf is selected, there is a need for Cfin order to stabilize the circuit. The reason for this is
that the Op Amp input capacitance and Q1 equivalent collector capacitance together (CIN) will cause additional
phase shift to the signal fed back to the inverting node. Cfwill function as a zero in the feedback path
counteracting the effect of the CIN and acting to stabilized the circuit. By proper selection of Cfsuch that the Op
Amp open loop gain is equal to the inverse of the feedback factor at that frequency, the response is optimized
with a theoretical 45° phase margin where GBWP is the Gain Bandwidth Product of the Op Amp, Optimized as
such, the I-V converter will have a theoretical pole, fp, at: (2) With Op Amp input capacitance of 3pF and an
estimate for Q1 output capacitance of about 3pF as well, CIN = 6 pF. From the typical performance plots,
LMH6642/6643 family GBWP is approximately 57 MHz. Therefore, with Rf = 1k, from Equation 2 and
Equation 3 : Cf=∼4.1 pF and fp = 39 MHz.
Single Supply Photodiode I-V Converter For this example, optimum Cfwas empirically determined to be around 5
pF. This time domain response is shown in Figure 58 showing about 9 ns rise/fall times, corresponding to about
39 MHz for fp. The overall supply current from the +5 V supply is around 5 mA with no load.
9.2.3 Application Curves
Figure 56. Input and Output Shown with CMVR Exceeded Figure 57. Overload Recovery Waveform
Figure 58. Converter Step Response (1VPP, 20 ns/DIV)
10 Power Supply Recommendations
The LMH664x device family can operate off a single supply or with dual supplies. The input CM capability of the
parts (CMVR) extends all the way down to the V- rail to simplify single supply applications. Supplies should be
decoupled with low inductance, often ceramic, capacitors to ground less than 0.5 inches from the device pins.
The use of ground plane is recommended, and as in most high speed devices, it is advisable to remove ground
plane close to device sensitive pins such as the inputs.
24 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMH6642 LMH6643 LMH6644
LMH6642
,
LMH6643
,
LMH6644
www.ti.com
SNOS966Q –MAY 2001–REVISED SEPTEMBER 2014
11 Layout
11.1 Layout Guidelines
Generally, a good high frequency layout will keep power supply and ground traces away from the inverting input
and output pins. Parasitic capacitances on these nodes to ground will cause frequency response peaking and
possible circuit oscillations (see Application Note OA-15, "Frequent Faux Pas in Applying Wideband Current
Feedback Amplifiers", SNOA367, for more information). Texas Instruments suggests the following evaluation
boards as a guide for high frequency layout and as an aid in device testing and characterization:
Table 1. Printed Circuit Board Layout And Component Values
DEVICE PACKAGE EVALUATION BOARD PN
LMH6642MF 5-Pin SOT-23 LMH730216
LMH6642MA 8-Pin SOIC LMH730227
LMH6643MA 8-Pin SOIC LMH730036
LMH6643MM 8-Pin VSSOP LMH730123
LMH6644MA 14-Pin SOIC LMH730231
LMH6644MT 14-Pin TSSOP LMH730131
Another important parameter in working with high speed/high performance amplifiers, is the component values
selection. Choosing external resistors that are large in value will effect the closed loop behavior of the stage
because of the interaction of these resistors with parasitic capacitances. These capacitors could be inherent to
the device or a by-product of the board layout and component placement. Either way, keeping the resistor values
lower, will diminish this interaction to a large extent. On the other hand, choosing very low value resistors could
load down nodes and will contribute to higher overall power dissipation.
11.2 Layout Example
Figure 59. LMH6642/LMH6643/LMH6644 Layer 1 Figure 60. LMH6642/LMH6643/LMH6644 Layer 2
Copyright © 2001–2014, Texas Instruments Incorporated Submit Documentation Feedback 25
Product Folder Links: LMH6642 LMH6643 LMH6644
LMH6642
,
LMH6643
,
LMH6644
SNOS966Q –MAY 2001–REVISED SEPTEMBER 2014
www.ti.com
12 Device and Documentation Support
12.1 Related Links
The table below lists quick access links. Categories include technical documents, support and community
resources, tools and software, and quick access to sample or buy.
Table 2. Related Links
TECHNICAL TOOLS & SUPPORT &
PARTS PRODUCT FOLDER SAMPLE & BUY DOCUMENTS SOFTWARE COMMUNITY
LMH6642 Click here Click here Click here Click here Click here
LMH6643 Click here Click here Click here Click here Click here
LMH6644 Click here Click here Click here Click here Click here
12.2 Trademarks
All trademarks are the property of their respective owners.
12.3 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
12.4 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
13 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
26 Submit Documentation Feedback Copyright © 2001–2014, Texas Instruments Incorporated
Product Folder Links: LMH6642 LMH6643 LMH6644
PACKAGE OPTION ADDENDUM
www.ti.com 19-Oct-2017
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead/Ball Finish
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LMH6642MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
42MA
LMH6642MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
42MA
LMH6642MF NRND SOT-23 DBV 5 1000 TBD Call TI Call TI -40 to 85 A64A
LMH6642MF/NOPB ACTIVE SOT-23 DBV 5 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A64A
LMH6642MFX/NOPB ACTIVE SOT-23 DBV 5 3000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A64A
LMH6643MA NRND SOIC D 8 95 TBD Call TI Call TI -40 to 85 LMH66
43MA
LMH6643MA/NOPB ACTIVE SOIC D 8 95 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
43MA
LMH6643MAX/NOPB ACTIVE SOIC D 8 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH66
43MA
LMH6643MM NRND VSSOP DGK 8 1000 TBD Call TI Call TI -40 to 85 A65A
LMH6643MM/NOPB ACTIVE VSSOP DGK 8 1000 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A65A
LMH6643MMX/NOPB ACTIVE VSSOP DGK 8 3500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 A65A
LMH6644MA/NOPB ACTIVE SOIC D 14 55 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH6644MA
LMH6644MAX/NOPB ACTIVE SOIC D 14 2500 Green (RoHS
& no Sb/Br) CU SN Level-1-260C-UNLIM -40 to 85 LMH6644MA
LMH6644MT/NOPB ACTIVE TSSOP PW 14 94 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 LMH66
44MT
LMH6644MTX/NOPB ACTIVE TSSOP PW 14 2500 Green (RoHS
& no Sb/Br) CU NIPDAU | CU SN Level-1-260C-UNLIM -40 to 85 LMH66
44MT
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
PACKAGE OPTION ADDENDUM
www.ti.com 19-Oct-2017
Addendum-Page 2
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish
value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LMH6642MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6642MF SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6642MF/NOPB SOT-23 DBV 5 1000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6642MFX/NOPB SOT-23 DBV 5 3000 178.0 8.4 3.2 3.2 1.4 4.0 8.0 Q3
LMH6643MAX/NOPB SOIC D 8 2500 330.0 12.4 6.5 5.4 2.0 8.0 12.0 Q1
LMH6643MM VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMH6643MM/NOPB VSSOP DGK 8 1000 178.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMH6643MMX/NOPB VSSOP DGK 8 3500 330.0 12.4 5.3 3.4 1.4 8.0 12.0 Q1
LMH6644MAX/NOPB SOIC D 14 2500 330.0 16.4 6.5 9.35 2.3 8.0 16.0 Q1
LMH6644MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
LMH6644MTX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Aug-2017
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LMH6642MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6642MF SOT-23 DBV 5 1000 210.0 185.0 35.0
LMH6642MF/NOPB SOT-23 DBV 5 1000 210.0 185.0 35.0
LMH6642MFX/NOPB SOT-23 DBV 5 3000 210.0 185.0 35.0
LMH6643MAX/NOPB SOIC D 8 2500 367.0 367.0 35.0
LMH6643MM VSSOP DGK 8 1000 210.0 185.0 35.0
LMH6643MM/NOPB VSSOP DGK 8 1000 210.0 185.0 35.0
LMH6643MMX/NOPB VSSOP DGK 8 3500 367.0 367.0 35.0
LMH6644MAX/NOPB SOIC D 14 2500 367.0 367.0 35.0
LMH6644MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0
LMH6644MTX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 24-Aug-2017
Pack Materials-Page 2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
www.ti.com
PACKAGE OUTLINE
C
TYP
0.22
0.08
0.25
3.0
2.6
2X 0.95
1.9
1.45 MAX
TYP
0.15
0.00
5X 0.5
0.3
TYP
0.6
0.3
TYP
8
0
1.9
A
3.05
2.75
B
1.75
1.45
(1.1)
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES:
1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing
per ASME Y14.5M.
2. This drawing is subject to change without notice.
3. Refernce JEDEC MO-178.
0.2 C A B
1
34
5
2
INDEX AREA
PIN 1
GAGE PLANE
SEATING PLANE
0.1 C
SCALE 4.000
www.ti.com
EXAMPLE BOARD LAYOUT
0.07 MAX
ARROUND 0.07 MIN
ARROUND
5X (1.1)
5X (0.6)
(2.6)
(1.9)
2X (0.95)
(R0.05) TYP
4214839/C 04/2017
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
NOTES: (continued)
4. Publication IPC-7351 may have alternate designs.
5. Solder mask tolerances between and around signal pads can vary based on board fabrication site.
SYMM
LAND PATTERN EXAMPLE
EXPOSED METAL SHOWN
SCALE:15X
PKG
1
34
5
2
SOLDER MASK
OPENING
METAL UNDER
SOLDER MASK
SOLDER MASK
DEFINED
EXPOSED METAL
METAL
SOLDER MASK
OPENING
NON SOLDER MASK
DEFINED
(PREFERRED)
SOLDER MASK DETAILS
EXPOSED METAL
www.ti.com
EXAMPLE STENCIL DESIGN
(2.6)
(1.9)
2X(0.95)
5X (1.1)
5X (0.6)
(R0.05) TYP
SOT-23 - 1.45 mm max heightDBV0005A
SMALL OUTLINE TRANSISTOR
4214839/C 04/2017
NOTES: (continued)
6. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate
design recommendations.
7. Board assembly site may have different recommendations for stencil design.
SOLDER PASTE EXAMPLE
BASED ON 0.125 mm THICK STENCIL
SCALE:15X
SYMM
PKG
1
34
5
2
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Mouser Electronics
Authorized Distributor
Click to View Pricing, Inventory, Delivery & Lifecycle Information:
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LMH6642MA/NOPB LMH6642MAX/NOPB LMH6642MF LMH6642MF/NOPB LMH6642MFX/NOPB