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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,

intellectual property matters and other important disclaimers. PRODUCTION DATA.

LMR24220

SNVS737F –OCTOBER 2011–REVISED JUNE 2019

LMR24220 42-V

, 2-A Step-Down Voltage Regulator in DSBGA Package

1 Features

1• Input Voltage Range of 4.5 V to 42 V

• Output Voltage Range of 0.8 V to 24 V

• Output Current up to 2 A

• Integrated Low RDS(ON) Synchronous MOSFETs

for High Efficiency

• Up to 1-MHz Switching Frequency

• Low Shutdown IQ, 25 µA Typical

• Programmable Soft Start

• No Loop Compensation Required

• COT Architecture with ERM

• Tiny Overall Solution Reduces System Cost

• Integrated Synchronous MOSFETs Provides High

Efficiency at Low Output Voltages

• COT with ERM Architecture

• Stable with Low ESR Capacitors

• 28-Bump DSBGA (3.676 × 2.48 × 0.60 mm

maximum) Packaging

• Create a custom design using the LMR24220 with

the WEBENCH®Power Designer

2 Applications

• Point-of-Load Conversions from 5-V, 12-V, and

24-V Rails

• Space Constrained Applications

• Industrial Distributed Power Applications

• Power Meters

3 Description

The LMR24220 synchronously rectified buck

converter features all required functions to implement

a highly efficient and cost effective buck regulator. It

is capable of supplying 2-A to loads with an output

voltage as low as 0.8 V. Dual N-channel synchronous

MOSFET switches allow a low component count, thus

reducing complexity and minimizing board size.

Different from most other COT regulators, the

LMR24220 does not rely on output capacitor ESR for

stability. The device is designed to work exceptionally

well with ceramic and other very low ESR output

capacitors. It requires no loop compensation, results

in a fast load-transient response and simple circuit

implementation. The operating frequency remains

nearly constant with line variations due to the inverse

relationship between the input voltage and the on-

time. The operating frequency can be externally

programmed up to 1 MHz. Protection features include

VCC undervoltage lockout, output overvoltage

protection, thermal shutdown, and gate drive

undervoltage lockout. The LMR24220 is available in

the small DSBGA low profile chip-scale package.

Device Information(1)

PART NUMBER PACKAGE BODY SIZE (MAX)

LMR24220 DSBGA (28) 3.676 mm × 2.48 mm

(1) For all available packages, see the orderable addendum at

the end of the data sheet.

Typical Application

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Table of Contents

1 Features.................................................................. 1

2 Applications ........................................................... 1

3 Description............................................................. 1

4 Revision History..................................................... 2

5 Pin Configuration and Functions......................... 3

6 Specifications......................................................... 4

6.1 Absolute Maximum Ratings ...................................... 4

6.2 Recommended Operating Ratings............................ 4

6.3 Electrical Characteristics........................................... 5

6.4 Typical Characteristics.............................................. 6

7 Detailed Description.............................................. 9

7.1 Overview................................................................... 9

7.2 Functional Block Diagram......................................... 9

7.3 Feature Description................................................. 10

8 Application and Implementation ........................ 14

8.1 Application Information............................................ 14

8.2 Typical Application ................................................. 14

9 Layout................................................................... 18

9.1 Layout Guidelines ................................................... 18

9.2 Package Considerations......................................... 18

9.3 Thermal Derating .................................................... 19

10 Device and Documentation Support................. 20

10.1 Device Support...................................................... 20

10.2 Receiving Notification of Documentation Updates 20

10.3 Community Resources.......................................... 20

10.4 Trademarks........................................................... 20

10.5 Electrostatic Discharge Caution............................ 20

10.6 Glossary................................................................ 20

11 Mechanical, Packaging, and Orderable

Information........................................................... 21

4 Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

Changes from Revision E (April 2013) to Revision F Page

• Editorial changes only; add WEBENCH links ........................................................................................................................ 1

Changes from Revision D (April 2013) to Revision E Page

• Changed layout of National Semiconductor data sheet to TI format...................................................................................... 1

VIN VIN BST SW AGND RON EN

SW SW SW SW AGND AGND AGND

SW SW SW SW VCC AGND SS

PGND PGND PGND VCC AGND FB

A B C D E F G

1PGND

Top Mark

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5 Pin Configuration and Functions

YPA Package

28-Bump DSGBA

Top View

Pin Descriptions

PIN DESCRIPTION

NO. NAME

A2, A3, B2,

B3, C2, C3,

D2, D3, D4

SW Switching node Internally connected to the source of the main MOSFET and the drain of the

synchronous MOSFET. Connect to the inductor.

A4, B4 VIN Input supply voltage Supply pin to the device. Nominal input range is 4.5 V to 42 V.

C4 BST Connection for

bootstrap capacitor Connect a 33-nF capacitor from the SW pin to this pin. An internal diode charges the

capacitor during the main MOSFET off-time.

E3, E4, F1,

F2, F3, G3 AGND Analog Ground Ground for all internal circuitry other than the PGND pin.

G2 SS Soft start An 8-µA internal current source charges an external capacitor to provide the soft- start

function.

G1 FB Feedback Internally connected to the regulation and over-voltage comparators. The regulation

setting is 0.8V at this pin. Connect to feedback resistors.

G4 EN Enable Connect a voltage higher than 1.26 V to enable the regulator. Leaving this input open

circuit will enable the device at internal UVLO level.

F4 RON On-time control An external resistor from the VIN pin to this pin sets the main MOSFET on-time.

E1, E2 VCC Start-up regulator

Output Nominally regulated to 6 V. Connect a capacitor of not less than 680 nF between the

VCC and AGND pins for stable operation.

A1, B1, C1,

D1 PGND Power ground Synchronous MOSFET source connection. Tie to a ground plane.

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(1) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and

specifications.

(2) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which

operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.

(3) The human body model is a 100pF capacitor discharged through a 1.5kΩresistor into each pin.

6 Specifications

6.1 Absolute Maximum Ratings

See notes(1)(2)

VIN, RON to AGND -0.3V to 43.5V

SW to AGND -0.3V to 43.5V

SW to AGND (Transient) -2V (< 100ns)

VIN to SW -0.3V to 43.5V

BST to SW -0.3V to 7V

All Other Inputs to AGND -0.3V to 7V

ESD Rating Human Body Model(3) ±2kV

Storage Temperature Range -65°C to +150°C

Junction Temperature (TJ) 150°C

(1) Absolute Maximum Ratings are limits beyond which damage to the device may occur. Operating Ratings are conditions under which

operation of the device is intended to be functional. For ensured specifications and test conditions, see the Electrical Characteristics.

(2) θJA calculations were performed in general accordance with JEDEC standards JESD51–1 to JESD51–11.

6.2 Recommended Operating Ratings

See note(1)

Supply Voltage Range (VIN) 4.5V to 42V

Junction Temperature Range (TJ)−40°C to +125°C

Thermal Resistance (θJA) 28-ball DSBGA(2) 50°C/W

For soldering specifications see SNOA549

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(1) Min and Max limits are 100% production tested at 25°C. Limits over the operating temperature range are specified through correlation

using Statistical Quality Control (SQC) methods. Limits are used to calculate Average Outgoing Quality Level (AOQL).

(2) VCC provides self bias for the internal gate drive and control circuits. Device thermal limitations limit external loading.

6.3 Electrical Characteristics

Specifications with standard type are for TJ= 25°C only; limits in boldface type apply over the full Operating Junction

Temperature (TJ) range. Minimum and maximum limits are ensured through test, design, or statistical correlation. Typical

values represent the most likely parametric norm at TJ= 25°C, and are provided for reference purposes only. Unless

otherwise stated the following conditions apply: VIN = 18 V, VOUT = 3.3 V.(1)

PARAMETER TEST CONDITIONS MIN TYP MAX UNIT

START-UP REGULATOR, VCC

VCC VCC output voltage CCC = 680nF, no load 5.0 6.0 7.2 V

VIN - VCC VIN - VCC dropout voltage ICC = 20mA 350 mV

IVCCL VCC current limit(2) VCC = 0V 40 65 mA

VCC-UVLO VCC under-voltage lockout threshold

(UVLO) VIN increasing 3.55 3.75 3.95 V

VCC-UVLO-HYS VCC UVLO hysteresis VIN decreasing – DSBGA

package 150 mV

tVCC-UVLO-D VCC UVLO filter delay 3 µs

IIN IIN operating current No switching, VFB = 1V 0.7 1mA

IIN-SD IIN operating current, Device shutdown VEN = 0V 25 40 µA

SWITCHING CHARACTERISTICS

RDS-UP-ON Main MOSFET RDS(on) 0.18 0.375 Ω

RDS- DN-ON Syn. MOSFET RDS(on) 0.11 0.225 Ω

VG-UVLO Gate drive voltage UVLO VBST - VSW increasing 3.3 4.2 V

SOFT START

ISS SS pin source current VSS = 0.5V 11 µA

CURRENT LIMIT

ICL Syn. MOSFET current limit threshold LMR24220 2.156 2.8 3.4 A

ON/OFF TIMER

ton ON timer pulse width VIN = 10V, RON = 100 kΩ1.38 µs

VIN = 30V, RON = 100 kΩ0.47

ton-MIN ON timer minimum pulse width 150 ns

toff OFF timer pulse width 260 ns

ENABLE INPUT

VEN EN Pin input threshold VEN rising 1.13 1.18 1.23 V

VEN-HYS Enable threshold hysteresis VEN falling 90 mV

REGULATION AND OVERVOLTAGE COMPARATOR

VFB In-regulation feedback voltage VSS ≥0.8V

TJ=−40°C to +125°C 0.784 0.8 0.816 V

VFB-OV Feedback overvoltage threshold 0.888 0.920 0.945 V

IFB FB pin current 5 nA

THERMAL SHUTDOWN

TSD Thermal shutdown temperature TJrising 165 °C

TSD-HYS Thermal shutdown temperature

hysteresis TJfalling 20 °C

0 10 20 30 40 50

100

200

300

400

500

600

700

SWITCHING FREQENCY (kHZ)

VIN(v)

Ron = 12.4k; L = 2.2H, Io = 0.5A

Ron = 12.4k; L = 2.2H, Io = 2A

Ron = 49.9k; L = 3.3H, Io = 0.5A

Ron = 49.9k; L = 3.3H, Io = 2A

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6.4 Typical Characteristics

Unless otherwise specified all curves are taken at VIN = 18 V with the configuration in the typical application circuit for

VOUT = 3.3 V (Figure 25) TA= 25°C.

Figure 1. VCC vs ICC Figure 2. VCC vs VIN

Figure 3. ton vs VIN

VOUT = 0.8 V

Figure 4. Switching Frequency, ƒSW vs VIN

Figure 5. VFB vs Temperature Figure 6. RDS(on) vs Temperature

5V/DIV

2V/DIV

1A/DIV

TIME (2 ms/DIV)

VIN

2V/DIV

1A/DIV

TIME (2 ms/DIV)

VEN

0.0 0.4 0.8 1.2 1.6 2.0

100

EFFICIENCY (%)

LOAD CURRENT (A)

VIN = 4.5V

VIN = 9V

VIN = 12v

VIN = 24V

VIN = 42v

0.0 0.4 0.8 1.2 1.6 2.0

-0.3

-0.2

-0.1

0.0

0.1

0.2

0.3

0.4

0.5

0.6

ûVOUT(%)

LOAD CURRENT (A)

VIN = 4.5V

VIN = 9V

VIN = 12V

VIN = 24V

VIN = 42V

0.0 0.4 0.8 1.2 1.6 2.0

100

EFFICIENCY (%)

LOAD CURRENT (A)

VIN = 4.5V

VIN = 9V

VIN = 12V

VIN = 24V

VIN = 42V

0.0 0.4 0.8 1.2 1.6 2.0

-0.8

-0.6

-0.4

-0.2

0.0

0.2

0.4

0.6

0.8

ûVOUT(%)

LOAD CURRENT (A)

VIN = 4.5V

VIN = 9V

VIN = 12V

VIN = 24V

VIN = 42V

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Typical Characteristics (continued)

Unless otherwise specified all curves are taken at VIN = 18 V with the configuration in the typical application circuit for

VOUT = 3.3 V (Figure 25) TA= 25°C.

VOUT = 3.3 V

Figure 7. Efficiency vs Load Current

VOUT = 3.3 V

Figure 8. VOUT Regulation vs Load Current

VOUT = 0.8 V

Figure 9. Efficiency vs Load Current

VOUT = 0.8 V

Figure 10. VOUT Regulation vs Load Current

VOUT = 3.3 V, 2 A Loaded

Figure 11. Power Up

VOUT = 3.3 V, 2 A Loaded

Figure 12. Start-up With Enable

50 mV/DIV

20V/DIV

500 mA/DIV

TIME (5 Ps/DIV)

VSW

'VO

5V/DIV

1A/DIV

TIME (50 Ps/DIV)

VSW

20 mV/DIV

5V/DIV

1A/DIV

TIME (2 Ps/DIV)

VSW

'VO

2V/DIV

5V/DIV

1A/DIV

TIME (50 Ps/DIV)

VEN

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Typical Characteristics (continued)

Unless otherwise specified all curves are taken at VIN = 18 V with the configuration in the typical application circuit for

VOUT = 3.3 V (Figure 25) TA= 25°C.

VOUT = 3.3 V, 2 A Loaded

Figure 13. Shutdown Transient VOUT = 3.3 V, 2 A Loaded

Figure 14. Continuous Mode Operation

VOUT = 3.3 V, 0.5 A Loaded

Figure 15. Discontinuous Mode Operation

VOUT = 3.3 V, 0.5 A to 2 A Loaded

Figure 16. DCM to CCM Transition

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7 Detailed Description

7.1 Overview

The LMR24220 step-down switching regulator features all required functions to implement a cost effective,

efficient buck power converter capable of supplying 2 A to a load. It contains dual N-channel main and

synchronous MOSFETs. The constant on-time (COT) regulation scheme requires no loop compensation, results

in fast load transient response and simple circuit implementation. The regulator can function properly even with

an all ceramic output capacitor network and does not rely on the ESR of the output capacitor for stability. The

operating frequency remains constant with line variations due to the inverse relationship between the input

voltage and the on-time. The valley current limit detection circuit, with the limit set internally at 2.8 A, inhibits the

main MOSFET until the inductor current level subsides.

The LMR24220 can be applied in numerous applications and can operate efficiently for inputs as high as 42 V.

Protection features include output over-voltage protection, thermal shutdown, VCC undervoltage lockout, and

gate-drive undervoltage lockout. The LMR24220 is available in a small DSBGA chip-scale package.

7.2 Functional Block Diagram

VOUT

1.3 x 10-10 x RON

fSW =

(VIN ± VOUT) x RON2

VOUT (VIN - 1) x L x 1.18 x 1020 x IOUT

fSW =

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7.3 Feature Description

7.3.1 CoT Control Circuit Overview

COT control is based on a comparator and a one-shot on-timer, with the output voltage feedback (feeding to the

FB pin) compared with an internal reference of 0.8 V. If the voltage of the FB pin is below the reference, the main

MOSFET is turned on for a fixed on-time determined by a programming resistor RON and the input voltage VIN,

upon which the on-time varies inversely. Following the on-time, the main MOSFET remains off for a minimum of

260 ns. Then, if the voltage of the FB pin is below the reference, the main MOSFET is turned on again for

another on-time period. The switching continues to achieve regulation.

The regulator will operate in the discontinuous conduction mode (DCM) at a light load, and the continuous

conduction mode (CCM) with a heavy load. In the DCM, the current through the inductor starts at zero and

ramps up to a peak during the on-time, and then ramps back to zero before the end of the off-time. It remains

zero and the load current is supplied entirely by the output capacitor. The next on-time period starts when the

voltage at the FB pin falls below the internal reference. The operating frequency in the DCM is lower and varies

larger with the load current as compared with the CCM. Conversion efficiency is maintained since conduction

loss and switching loss are reduced with the reduction in the load and the switching frequency respectively. The

operating frequency in the DCM can be calculated approximately as follows:

(1)

In the CCM, the current flows through the inductor in the entire switching cycle, and never reaches zero during

the off-time. The operating frequency remains relatively constant with load and line variations. The CCM

operating frequency can be calculated approximately as follows:

(2)

Consider Equation 4 and Equation 5 when choosing the switching frequency.

The output voltage is set by two external resistors RFB1 and RFB2. The regulated output voltage is:

VOUT = 0.8V x (RFB1 + RFB2)/RFB2 (3)

7.3.2 Start-up Regulator (VCC)

A start-up regulator is integrated within the LMR24220. The input pin VIN can be connected directly to a line

voltage up to 42 V. The VCC output regulates at 6 V, and is current limited to 65 mA. Upon power up, the

regulator sources current into an external capacitor CVCC, which is connected to the VCC pin. For stability, CVCC

must be at least 680 nF. When the voltage on the VCC pin is higher than the UVLO threshold of 3.75 V, the main

MOSFET is enabled, and the SS pin is released to allow the soft-start capacitor CSS to charge.

The minimum input voltage is determined by the dropout voltage of the regulator and the VCC UVLO falling

threshold (≊3.7 V). If VIN is less than ≊4 V, the regulator shuts off, and VCC goes to zero.

7.3.3 Regulation Comparator

The feedback voltage at the FB pin is compared to a 0.8-V internal reference. In normal operation (the output

voltage is regulated), an on-time period is initiated when the voltage at the FB pin falls below 0.8V. The main

MOSFET stays on for the on-time, causing the output voltage and consequently the voltage of the FB pin to rise

above 0.8 V. After the on-time period, the main MOSFET stays off until the voltage of the FB pin falls below 0.8

V again. Bias current at the FB pin is nominally 5 nA.

7.3.4 Zero Coil Current Detect

The current of the synchronous MOSFET is monitored by a zero coil current detection circuit, which inhibits the

synchronous MOSFET when its current reaches zero until the next on-time. This circuit enables the DCM

operation, which improves the efficiency at a light load.

ILR = (VIN - VOUT) x ton

fSW(MAX) = VOUT

VIN(MAX) x 150 ns

VIN

1.3 x 10-10 x RON

ton =

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Feature Description (continued)

7.3.5 Overvoltage Comparator

The voltage at the FB pin is compared to a 0.92-V internal reference. If it rises above 0.92 V, the on-time is

immediately terminated. This condition is known as overvoltage protection (OVP). It can occur if the input voltage

or the output load changes suddenly. Once the OVP is activated, the main MOSFET remains off until the voltage

at the FB pin falls below 0.92 V. The synchronous MOSFET stays on to discharge the inductor until the inductor

current reduces to zero, and then switches off.

7.3.6 On-Time Timer, Shutdown

The on-time of the LMR24220 main MOSFET is determined by the resistor RON and the input voltage VIN. It is

calculated as follows:

(4)

The inverse relationship of ton and VIN gives a nearly constant frequency as VIN is varied. Select RON so that the

on-time at maximum VIN is greater than 150 ns. The on-timer has a limiter to ensure a minimum of 150 ns for ton.

This limits the maximum operating frequency, which is governed by Equation 5:

(5)

The LMR24220 can be remotely shutdown by pulling the voltage of the EN pin below 1 V. In this shutdown

mode, the SS pin is internally grounded, the on-timer is disabled, and bias currents are reduced. Releasing the

EN pin allows normal operation to resume because the EN pin is internally pulled up.

Figure 17. Shutdown Implementation

7.3.7 Current Limit

Current limit detection is carried out during the off-time by monitoring the re-circulating current through the

synchronous MOSFET. Referring to Functional Block Diagram, when the main MOSFET is turned off, the

inductor current flows through the load, the PGND pin and the internal synchronous MOSFET. If this current

exceeds 2.8 A, the current limit comparator toggles, and as a result disabling the start of the next on-time period.

The next switching cycle starts when the re-circulating current falls back below 2.8 A (and the voltage at the FB

pin is below 0.8 V). The inductor current is monitored during the on-time of the synchronous MOSFET. As long

as the inductor current exceeds 2.8 A, the main MOSFET will remain inhibited to achieve current limit. The

operating frequency is lower during current limit due to a longer off-time.

Figure 18 shows an inductor current waveform. On average, the output current IOUT is the same as the inductor

current IL, which is the average of the rippled inductor current. In case of current limit (the current limit portion of

Figure 18), the next on-time does not initiate until the current drops below 2.8 A (assume the voltage at the FB

pin is lower than 0.8 V). During each on-time the current ramps up an amount equal to:

(6)

During current limit, the LMR24220 operates in a constant current mode with an average output current IOUT(CL)

equal to 2.8 A + ILR / 2.

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Feature Description (continued)

However, due to thermal limitations, the device may not support load currents greater than 2 A for extended

periods.

Figure 18. Inductor Current - Current Limit Operation

7.3.8 N-Channel MOSFET and Driver

The LMR24220 integrates an N-channel main MOSFET and an associated floating high voltage main MOSFET

gate driver. The gate drive circuit works in conjunction with an external bootstrap capacitor CBST and an internal

high voltage diode. CBST connecting between the BST and SW pins powers the main MOSFET gate driver during

the main MOSFET on-time. During each off-time, the voltage of the SW pin falls to approximately –1 V, and CBST

charges from VCC through the internal diode. The minimum off-time of 260 ns provides enough time for charging

CBST in each cycle.

7.3.9 Soft Start

The soft-start feature allows the converter to gradually reach a steady state operating point, thereby reducing

start-up stresses and current surges. Upon turnon, after VCC reaches the undervoltage threshold, an 8 µA

internal current source charges up an external capacitor CSS connecting to the SS pin. The ramping voltage at

the SS pin (and the non-inverting input of the regulation comparator as well) ramps up the output voltage VOUT in

a controlled manner.

The soft start time duration to reach steady-state operation is given by Equation 7:

tSS = VREF × CSS / 8µA = 0.8 V × CSS / 8 µA (7)

This equation can be rearranged as follows:

CSS= tSS × 8 µA / 0.8 V (8)

Use of a 4.7-nF capacitor results in a 0.5-ms soft-start duration. This is a recommended value. Note that high

values of CSS capacitance cause more output voltage drop when a load transient goes across the DCM-CCM

boundary. If a fast load transient response is desired for steps between DCM and CCM mode the softstart

capacitor value should be less than 18 nF (which corresponds to a soft-start time of 1.8 ms).

An internal switch grounds the SS pin if any of the following three cases happens: (i) VCC is below the UVLO

threshold; (ii) a thermal shutdown occurs; or (iii) the EN pin is grounded. Alternatively, the output voltage can be

shut off by connecting the SS pin to ground using an external switch. Releasing the switch allows the SS pin to

ramp up and the output voltage to return to normal. The shutdown configuration is shown in Figure 19.

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Feature Description (continued)

Figure 19. Alternate Shutdown Implementation

7.3.10 Thermal Protection

The junction temperature of the LMR24220 should not exceed the maximum limit. Thermal protection is

implemented by an internal thermal shutdown circuit, which activates (typically) at 165°C to make the controller

enter a low power reset state by disabling the main MOSFET, disabling the on-timer, and grounding the SS pin.

Thermal protection helps prevent catastrophic failures from accidental device overheating. When the junction

temperature falls back below 145°C (typical hysteresis = 20°C), the SS pin is released, and normal operation

resumes.

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8 Application and Implementation

NOTE

Information in the following applications sections is not part of the TI component

specification, and TI does not warrant its accuracy or completeness. TI’s customers are

responsible for determining suitability of components for their purposes. Customers should

validate and test their design implementation to confirm system functionality.

8.1 Application Information

The LMR24220 synchronously rectified buck converter features all required functions to implement a highly

efficient and cost effective buck regulator. It is capable of supplying 2-A to loads with an output voltage as low as

0.8 V. Dual N-channel synchronous MOSFET switches allow a low component count, thus reducing complexity

and minimizing board size

8.2 Typical Application

Figure 20. Typical Application Schematic

8.2.1 Detailed Design Procedure

8.2.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR24220 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

L = ILR x fSW x VIN

VOUT x (VIN - VOUT)

1.3 x 10-10

VIN(MAX) x 150 ns

RON t

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Typical Application (continued)

8.2.1.2 External Components

The following guidelines can be used to select external components.

RFB1 and RFB2: Choose these resistors from standard values in the range of 1 kΩto 10 kΩ, satisfying the

following ratio:

RFB1 / RFB2 = (VOUT / 0.8 V) – 1 (9)

For VOUT = 0.8 V, the FB pin can be connected to the output directly with a pre-load resistor drawing more than

20 µA. This is needed because the converter operation needs a minimum inductor current ripple to maintain

good regulation when no load is connected.

RON:Equation 2 can be used to select RON if a desired operating frequency is selected. But the minimum value of

RON is determined by the minimum on-time. It can be calculated as follows:

(10)

If RON calculated from Equation 2 is smaller than the minimum value determined in Equation 10, select a lower

frequency to re-calculate RON by Equation 2. Alternatively, VIN(MAX) can also be limited in order to keep the

frequency unchanged. The relationship of VIN(MAX) and RON is shown in Figure 21.

On the other hand, the minimum off-time of 260 ns can limit the maximum duty ratio.

Figure 21. Maximum VIN for Selected RON

L: The main parameter affected by the inductor is the amplitude of inductor current ripple (ILR). Once ILR is

selected, L can be determined by:

where

• VIN is the maximum input voltage and

• fSW is determined from Equation 2. (11)

If the output current IOUT is determined, by assuming that IOUT = IL, the higher and lower peak of ILR can be

determined. Beware that the higher peak of ILR must not be larger than the saturation current of the inductor and

current limits of the main and synchronous MOSFETs. Also, the lower peak of ILR must be positive if CCM

operation is required.

CIN = 'VIN

IOUT x ton

LMR24220

SNVS737F –OCTOBER 2011–REVISED JUNE 2019

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Product Folder Links: LMR24220

Typical Application (continued)

Figure 22. Inductor Selection for VOUT = 3.3 V Figure 23. Inductor Selection for VOUT = 0.8 V

Figure 22 and Figure 23 show curves on inductor selection for various VOUT and RON. For small RON, according

to Equation 10, VIN is limited. Some curves are therefore limited as shown in the figures.

CVCC:The capacitor on the VCC output provides not only noise filtering and stability, but also prevents false

triggering of the VCC UVLO at the main MOSFET on/off transitions. CVCC should be no smaller than 680 nF for

stability, and should be a good-quality, low ESR, ceramic capacitor.

COUT and COUT3:COUT must generally be no smaller than 10 µF. Experimentation is usually necessary to

determine the minimum value for COUT, as the nature of the load may require a larger value. A load which

creates significant transients requires a larger COUT than a fixed load.

COUT3 is a small value ceramic capacitor located close to the LMR24220 to further suppress high frequency noise

at VOUT. A 100-nF capacitor is recommended.

CIN and CIN3:The function of CIN is to supply most of the main MOSFET current during the on-time, and limit the

voltage ripple at the VIN pin, assuming that the voltage source connecting to the VIN pin has finite output

impedance. If the voltage source’s dynamic impedance is high (effectively a current source), CIN supplies the

average input current, but not the ripple current.

At the maximum load current, when the main MOSFET turns on, the current to the VIN pin suddenly increases

from zero to the lower peak of the inductor’s ripple current and ramps up to the higher peak value. It then drops

to zero at turnoff. The average current during the on-time is the load current. For a worst case calculation, CIN

must be capable of supplying this average load current during the maximum on-time. CIN is calculated from:

where

• IOUT is the load current

• ton is the maximum on-time, and

•ΔVIN is the allowable ripple voltage at VIN. (12)

The purpose of CIN3 is to help avoid transients and ringing due to long lead inductance at the VIN pin. A low ESR

0.1-µF ceramic chip capacitor located close to the LMR24220 is recommended.

CBST:TI recommends a 33-nF, high-quality ceramic capacitor with low ESR for CBST because it supplies a surge

current to charge the main MOSFET gate driver at turnon. Low ESR also helps ensure a complete recharge

during each off-time.

CSS:The capacitor at the SS pin determines the soft-start time; that is, the time for the reference voltage at the

regulation comparator and the output voltage to reach their final value. The time is determined from Equation 13:

50 mV/DIV

1A/DIV

TIME (500 Ps/DIV)

'VO

tSS = 8 PA

CSS x 0.8V

LMR24220

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SNVS737F –OCTOBER 2011–REVISED JUNE 2019

Product Folder Links: LMR24220

Typical Application (continued)

(13)

CFB:If the output voltage is higher than 1.6 V, use a CFB in the DCM to reduce the output ripple. The

recommended value for CFB is 10 nF.

8.2.2 Application Curve

VOUT = 3.3 V, 0.2 A to 2 A Load

Figure 24. Load Transient

LMR24220

SNVS737F –OCTOBER 2011–REVISED JUNE 2019

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Product Folder Links: LMR24220

9 Layout

9.1 Layout Guidelines

The LMR24220 regulation, overvoltage, and current limit comparators are very fast and may respond to short

duration noise pulses. Layout is therefore critical for optimum performance. It must be as neat and compact as

possible, and all external components must be as close to their associated pins of the LMR24220 as possible

(refer to Functional Block Diagram). The loop formed by CIN, the main and synchronous MOSFET internal to the

LMR24220, and the PGND pin must be as small as possible. The connection from the PGND pin to CIN must be

as short and direct as possible. Add vias to connect the ground of CIN to a ground plane, located as close as

possible to the capacitor. Connect the bootstrap capacitor CBST as close as possible to the SW and BST

pins—the connecting traces should be thick. The feedback resistors and capacitor RFB1, RFB2, and CFB must be

close to the FB pin. A long trace running from VOUT to RFB1 is generally acceptable since this is a low impedance

node. Ground RFB2 directly to the AGND pin. Connect the output capacitor COUT close to the load and tied

directly to the ground plane. Connect the inductor L close to the SW pin with as short a trace as possible to

reduce the potential for EMI (electromagnetic interference) generation. If it is expected that the internal

dissipation of the LMR24220 will produce excessive junction temperature during normal operation, making good

use of the PC board’s ground plane can help considerably to dissipate heat. Additionally, the use of thick traces,

where possible, can help conduct heat away from the LMR24220. Judicious positioning of the PC board within

the end product, along with the use of any available air flow (forced or natural convection) can help reduce the

junction temperature.

9.2 Package Considerations

The die has exposed edges and can be sensitive to ambient light. For applications with direct high intensitiy

ambient red, infrared, LED or natural light it is recommended to have the device shielded from the light source to

avoid abnormal behavior.

Figure 25. Typical Application Schematic For VOUT = 3.3 V

0 25 50 75 100 125

0.0

0.4

0.8

1.2

1.6

2.0

2.4

MAXIMUM IOUT(A)

AMBIENT TEMPERATURE (°C)

LMR24220

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SNVS737F –OCTOBER 2011–REVISED JUNE 2019

Product Folder Links: LMR24220

Package Considerations (continued)

Figure 26. Typical Application Schematic For VOUT = 0.8 V

9.3 Thermal Derating

Temperature rise increases with frequency, load current, input voltage and smaller board dimensions. On a

typical board, the LMR24220 is capable of supplying 2 A below an ambient temperature of 50°C under worst

case operation with input voltage of 42 V. Figure 27 shows a thermal derating curve for the output current without

thermal shutdown against ambient temperature up to 125°C. Obtaining 2-A output current is possible at higher

temperature by increasing the PCB ground plane area, adding air flow or reducing the input voltage or operating

frequency

θJA = 40°C/W, VOUT = 3.3 V, ƒSW = 500 kHz

(tested on the evaluation board)

Figure 27. Thermal Derating Curve

LMR24220

SNVS737F –OCTOBER 2011–REVISED JUNE 2019

www.ti.com

Product Folder Links: LMR24220

10 Device and Documentation Support

10.1 Device Support

10.1.1 Development Support

10.1.1.1 Custom Design With WEBENCH® Tools

Click here to create a custom design using the LMR24220 device with the WEBENCH® Power Designer.

1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.

2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.

3. Compare the generated design with other possible solutions from Texas Instruments.

The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time

pricing and component availability.

In most cases, these actions are available:

• Run electrical simulations to see important waveforms and circuit performance

• Run thermal simulations to understand board thermal performance

• Export customized schematic and layout into popular CAD formats

• Print PDF reports for the design, and share the design with colleagues

Get more information about WEBENCH tools at www.ti.com/WEBENCH.

10.2 Receiving Notification of Documentation Updates

To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper

right corner, click on Alert me to register and receive a weekly digest of any product information that has

changed. For change details, review the revision history included in any revised document.

10.3 Community Resources

The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective

contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of

Use.

TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration

among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help

solve problems with fellow engineers.

Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and

contact information for technical support.

10.4 Trademarks

E2E is a trademark of Texas Instruments.

WEBENCH is a registered trademark of Texas Instruments.

All other trademarks are the property of their respective owners.

10.5 Electrostatic Discharge Caution

This integrated circuit can be damaged by ESD. Texas Instruments recommends that all integrated circuits be handled with

appropriate precautions. Failure to observe proper handling and installation procedures can cause damage.

ESD damage can range from subtle performance degradation to complete device failure. Precision integrated circuits may be more

susceptible to damage because very small parametric changes could cause the device not to meet its published specifications.

10.6 Glossary

SLYZ022 —TI Glossary.

This glossary lists and explains terms, acronyms, and definitions.

LMR24220

www.ti.com

SNVS737F –OCTOBER 2011–REVISED JUNE 2019

Product Folder Links: LMR24220

11 Mechanical, Packaging, and Orderable Information

The following pages include mechanical, packaging, and orderable information. This information is the most

current data available for the designated devices. This data is subject to change without notice and revision of

this document. For browser-based versions of this data sheet, refer to the left-hand navigation.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 1

PACKAGING INFORMATION

Orderable Device Status

(1)

Package Type Package

Drawing Pins Package

Qty Eco Plan

(2)

Lead finish/

Ball material

(6)

MSL Peak Temp

(3)

Op Temp (°C) Device Marking

(4/5)

Samples

LMR24220TL/NOPB ACTIVE DSBGA YPA 28 250 RoHS & Green SNAGCU Level-1-260C-UNLIM -20 to 125 SJ6B

LMR24220TLX/NOPB ACTIVE DSBGA YPA 28 1000 RoHS & Green SNAGCU Level-1-260C-UNLIM -20 to 125 SJ6B

(1) The marketing status values are defined as follows:

ACTIVE: Product device recommended for new designs.

LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.

NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.

PREVIEW: Device has been announced but is not in production. Samples may or may not be available.

OBSOLETE: TI has discontinued the production of the device.

(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance

do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may

reference these types of products as "Pb-Free".

RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.

Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based

flame retardants must also meet the <=1000ppm threshold requirement.

(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.

(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.

(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation

of the previous line and the two combined represent the entire Device Marking for that device.

(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two

lines if the finish value exceeds the maximum column width.

Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information

provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and

continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.

TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.

In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.

PACKAGE OPTION ADDENDUM

www.ti.com 10-Dec-2020

Addendum-Page 2

TAPE AND REEL INFORMATION

*All dimensions are nominal

Device Package

Type Package

Drawing Pins SPQ Reel

Diameter

(mm)

Reel

Width

W1 (mm)

(mm) B0

(mm) K0

(mm) P1

(mm) W

(mm) Pin1

Quadrant

LMR24220TL/NOPB DSBGA YPA 28 250 178.0 12.4 2.64 3.84 0.76 8.0 12.0 Q1

LMR24220TLX/NOPB DSBGA YPA 28 1000 178.0 12.4 2.64 3.84 0.76 8.0 12.0 Q1

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Jun-2019

Pack Materials-Page 1

*All dimensions are nominal

Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)

LMR24220TL/NOPB DSBGA YPA 28 250 210.0 185.0 35.0

LMR24220TLX/NOPB DSBGA YPA 28 1000 210.0 185.0 35.0

PACKAGE MATERIALS INFORMATION

www.ti.com 18-Jun-2019

Pack Materials-Page 2

MECHANICAL DATA

YPA0028

www.ti.com

TLC28XXX (Rev A)

. All linear dimensions are in millimeters. Dimensioning and tolerancing per ASME Y14.5M-1994.

B. This drawing is subject to change without notice.

4215064/A 12/12

NOTES:

0.600

±0.075

D: Max =

E: Max =

3.676 mm, Min =

2.48 mm, Min =

3.615 mm

2.419 mm

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