LM2653 www.ti.com SNVS050E - NOVEMBER 1999 - REVISED APRIL 2013 LM2653 1.5A High Efficiency Synchronous Switching Regulator Check for Samples: LM2653 FEATURES DESCRIPTION * * * * * * * The LM2653 switching regulator provides high efficient power conversion over a 100:1 load range (1.5A to 15 mA). This feature makes the LM2653 an ideal fit in battery-powered applications. 1 2 * * * * * * Efficiency up to 97% 4V to 14V Input Voltage Range 1.5V to 5.0V Adjustable Output Voltage 0.1 Switch On Resistance 300 kHz Fixed Frequency Internal Oscillator 7 A Shutdown Current Patented Current Sensing for Current Mode Control Input Undervoltage Lockout Output Overvoltage Shutdown Protection Output Undervoltage Shutdown Protection Adjustable Soft-Start Adjustable PGOOD Delay Current Limit and Thermal Shutdown APPLICATIONS * * * * * * * * Webpad Personal Digital Assistants (PDAs) Computer Peripherals Battery-Powered Devices Notebook Computer Video Supply Handheld Scanners GXM I/O and Core Voltage High Efficiency 5V Conversion Synchronous rectification is used to achieve up to 97% efficiency. At light loads, the LM2653 enters a low power hysteretic or "sleep" mode to keep the efficiency high. In many applications, the efficiency still exceeds 80% at 15 mA load. A shutdown pin is available to disable the LM2653 and reduce the supply current to 7A. All the power, control, and drive functions are integrated within the ICs. The ICs contain patented current sensing circuity for current mode control. This feature eliminates the external current sensing resistor required by other current-mode DC-DC converters. The ICs have a 300 kHz fixed frequency internal oscillator. The high oscillator frequency allows the use of extremely small, low profile components. Protection features include thermal shutdown, input undervoltage lockout, adjustable soft-start, cycle by cycle current limit, output overvoltage and undervoltage protections. Typical Application Efficiency vs Load Current (VIN = 5V, VOUT = 3.3V) Figure 1. Figure 2. 1 2 Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet. All trademarks are the property of their respective owners. PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of the Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. Copyright (c) 1999-2013, Texas Instruments Incorporated LM2653 SNVS050E - NOVEMBER 1999 - REVISED APRIL 2013 www.ti.com These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam during storage or handling to prevent electrostatic damage to the MOS gates. Absolute Maximum Ratings (1) (2) (3) Input Voltage 15V PGOOD Pin Voltage 15V -0.4V VFB 5V Feedback Pin Voltage Power Dissipation (TA =25C) (4) 893 mW Junction Temperature Range -40C TJ +125C Storage Temperature Range -65C to +150C Lead Temperature PW Package Vapor Phase (60 sec.) 215C Infrared (15 sec.) 220C Maximum Junction Temperature 150C ESD Susceptibility (1) Human Body Model (3) 1 kV Absolute Maxmum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but device parameter specifications may not be specified under these conditions. For specified specifications and test conditions, see Electrical Characteristics. If Military/Aerospace specified devices are required, please contact the TI Sales Office/ Distributors for availability and specifications. The human body model is a 100 pF capacitor discharged through a 1.5 k resistor into each pin. The maximum allowable power dissipation is calculated by using PDMAX = (TJMAX - TA)/JA, where TJMAX is the maximum junction temperature, TA is the ambient temperature, and JA is the junction-to-ambient thermal resistance of the specified package. The 893 mW rating results from using 150C, 25C, and 140C/W for TJMAX, TA, and JA respectively. A JA of 140C/W represents the worstcase condition of no heat sinking of the 16-pin TSSOP package. Heat sinking allows the safe dissipation of more power. The Absolute Maximum power dissipation must be derated by 7.14 mW per C above 25C ambient. The LM2653 actively limits its junction temperatures to about 165C. (2) (3) (4) Operating Ratings (1) 4V VIN 14V Supply Voltage (1) Absolute Maxmum Ratings indicate limits beyond which damage to the device may occur. Operating Ratings indicate conditions for which the device is intended to be functional, but device parameter specifications may not be specified under these conditions. For specified specifications and test conditions, see Electrical Characteristics. Electrical Characteristics Specifications with standard typeface are for TJ = 25C, and those in boldface type apply over full Operating Temperature Range. VIN = 10V unless otherwise specified. Symbol VFB Parameter Feedback Voltage Conditions ILOAD = 900 mA Typical (1) Limit (2) 1.238 1.200 1.263 VOUT VINUV VIN = 4V to 12V ILOAD = 900 mA 0.2 % Output Voltage Load Regulation ILOAD = 10 mA to 1.5A VIN = 5V 1.3 % Output Voltage Load Regulation ILOAD = 200 mA to 1.5A VIN = 5V 0.3 % VIN Undervoltage Lockout Threshold Voltage Rising Edge 3.8 Hysteresis for the Input Undervoltage Lockout ICL Switch Current Limit (1) (2) 2 V V(min) V(max) Output Voltage Line Regulation VUV_HYST ISM Units 3.95 210 VIN = 5V VOUT = 2.5V Sleep Mode Threshold Current VIN = 5V, VOUT = 2.5V mV 2.0 1.55 2.60 100 V V(max) A A(min) A(max) mA All limits specified at room temperature (standard typeface) and at temperature extremes (bold typeface). All room temperature limits are 100% production tested. All limits at temperature extremes are specified via correlation using standard Statistical Quality Control (SQC) methods. All limits are used to calculate Average Outgoing Quality Level (AOQL). Typical numbers are at 25C and represent the most likely norm. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM2653 LM2653 www.ti.com SNVS050E - NOVEMBER 1999 - REVISED APRIL 2013 Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25C, and those in boldface type apply over full Operating Temperature Range. VIN = 10V unless otherwise specified. Symbol Parameter Conditions Typical VHYST Sleep Mode Feedback Voltage Hysteresis 24 IQ Quiescent Current 1.7 IQSD Quiescent Current in Shutdown Mode Shutdown Pin Pulled Low High-Side or Low-Side MOSFET ON Resistance ISWITCH = 1A RSW(ON) High-Side or Low-Side Switch On Resistance (MOSFET ON Resistance + Bonding Wire Resitstance) ISWITCH = 1A IL RDS(ON) VBOOT (1) Limit (2) mV 2.0 mA mA(max) 12/20 A A(max) 130 m m (max) 7 75 110 m Switch Leakage Current--High Side 130 nA Switch Leakge Current--Low Side 130 nA Bootstrap Regulator Voltage IBOOT = 1 mA 6.75 6.45/6.40 6.95/7.00 GM Error Amplifier Transconductance AV Error Amplifier Voltage Gain IEA_SOURCE Error Amplifier Source Current VIN = 3.6V, VFB = 1.17V, VCOMP = 2V Error Amplifier Sink Current VIN = 3.6V, VFB = 1.31V, VCOMP = 2V IEA_SINK VEAH 100 VIN = 4V, VFB = 1.31V VD Body Diode Voltage IDIODE = 1.5A FOSC Oscillator Frequency Measured at Switch Pin VIN = 4V 300 VIN = 4V 95 ISS VOUTUV Soft-Start Current Voltage at the SS Pin = 1.4V VOUT Undervoltage Lockout Threshold Voltage ILDELAY 30 A A(min) 2.50/2.40 V V(min) 1.35/1.50 V V(max) 2.70 1.25 1 V 280/255 330/345 kHz kHz(min) kHz(max) 92 % %(min) 7 14 A A(min) A(max) 76 84 %VOUT %VOUT(min) %VOUT(max) 11 81 Hysteresis for VOUTUV VOUTOV A A(min) 65 Error Amplifier Output Swing Lower Limit Maximum Duty Cycle 25/15 40 VIN = 4V, VFB = 1.17V DMAX V V(min) V(max) mho 1250 Error Amplifier Output Swing Upper Limit VEAL Units 5 VOUT Overvoltage Lockout Threshold Voltage %VOUT 108 106 114 %VOUT %VOUT(min) %VOUT(max) Hysteresis for VOUTOV 3 %VOUT LDELAY Pin Source Current 5 A SOURCE IPGOODSINK PGOOD Pin Sink Current VPGOOD = 0.4V IPGOODLEAKA PGOOD Pin Leakage Current VPGOOD = 5V 50 15 Shutdown Pin Current Shutdown Pin Pulled Low 2.2 mA(max) nA GE ISHUTDOWN 0.8/0.5 3.7/4.0 A A(min) A(max) Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM2653 3 LM2653 SNVS050E - NOVEMBER 1999 - REVISED APRIL 2013 www.ti.com Electrical Characteristics (continued) Specifications with standard typeface are for TJ = 25C, and those in boldface type apply over full Operating Temperature Range. VIN = 10V unless otherwise specified. Symbol VSHUTDOWN Parameter Shutdown Pin Threshold Voltage Conditions Rising Edge Typical (1) Limit 0.6 0.3 0.9 (2) Units V V(min) V(max) TSD Thermal Shutdown Temperature 165 C TSD_HYST Thermal Shutdown Hysteresis Temperature 25 C 4 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM2653 LM2653 www.ti.com SNVS050E - NOVEMBER 1999 - REVISED APRIL 2013 Typical Performance Characteristics Efficiency vs Load Current (VIN = 5V, VOUT = 2.5V) lQ vs VIN Figure 3. Figure 4. IQSD vs Input Voltage IQSD vs Junction Temperature Figure 5. Figure 6. Frequency vs Junction Temperature RSW(ON) vs Input Voltage Figure 7. Figure 8. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM2653 5 LM2653 SNVS050E - NOVEMBER 1999 - REVISED APRIL 2013 www.ti.com Typical Performance Characteristics (continued) RSW(ON) vs Junction Temperature Current Limit vs Input Voltage (VOUT = 2.5V) Figure 9. Figure 10. Current Limit vs Junction Temperature (VOUT = 2.5V) Reference Voltage vs Junction Temperature Figure 11. Figure 12. Sleep Mode Threshold vs Output Voltage (VIN = 5V) Figure 13. 6 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM2653 LM2653 www.ti.com SNVS050E - NOVEMBER 1999 - REVISED APRIL 2013 CONNECTION DIAGRAM Figure 14. 16-Lead TSSOP (PW) See Package Number PW0016A PIN DESCRIPTIONS Pin Name Function 1-2 SW Switched-node connection, which is connected with the source of the internal high-side MOSFET. 3-5 VIN Main power supply input pin. Connected to the drain of the high-side MOSFET. 6 VCB Bootstrap capacitor connection for high-side gate drive. 7 AVIN Input voltage for control and driver circuits. 8 SD(SS) Shutdown and Soft-start control pin. Pulling this pin below 0.3V shuts off the regulator. A capacitor connected from this pin to ground provides a control ramp of the input current. Do not drive this pin with an external source or erroneous operation may result. 9 FB 10 COMP Output voltage feedback input. Connected to the output voltage. 11 PGOOD A constant monitor on the output voltage. PGOOD will go low if the output voltage exceeds 110% or goes below 80% of its nominal. 12 LDELAY A capacitor between this pin to ground sets the delay from the output voltage reaches 80% of its nominal to when the undervoltage latch protection is enabled and PGOOD pin goes low. 13 AGND Low-noise analog ground. 14-16 PGND Power ground. Compensation network connection. Connected to the output of the voltage error amplifier. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM2653 7 LM2653 SNVS050E - NOVEMBER 1999 - REVISED APRIL 2013 www.ti.com Block Diagram Figure 15. 8 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM2653 LM2653 www.ti.com SNVS050E - NOVEMBER 1999 - REVISED APRIL 2013 OPERATION The LM2653 operates in a constant frequency (300 kHz), current-mode PWM for moderate to heavy loads; and it automatically switches to hysteretic mode for light loads. In hysteretic mode, the switching frequency is reduced to keep the efficiency high. MAIN OPERATION When the load current is higher than the sleep mode threshold, the part is always operating in PWM mode. At the beginning of each switching cycle, the high-side switch is turned on, the current from the high-side switch is sensed and compared with the output of the error amplifier (COMP pin). When the sensed current reaches the COMP pin voltage level, the high-side switch is turned off; after 40 ns (deadtime), the low-side switch is turned on. At the end of the switching cycle, the low-side switch is turned off; and the same cycle repeats. The current of the top switch is sensed by a patented internal circuitry. This unique technique gets rid of the external sense resistor, saves cost and size, and improves noise immunity of the sensed current. A feedforward from the input voltage is added to reduce the variation of the current limit over the input voltage range. When the load current decreases below the sleep mode theshold, the output voltage will rise slightly, this rise is sensed by the hysteretic mode comparator which makes the part go into the hysteretic mode with both the high and low side switches off. The output voltage starts to drop until it hits the low threshold of the hysteretic comparator, and the part immediately goes back to the PWM operation. The output voltage keeps increasing until it reaches the top hysteretic threshold, then both the high and low side switches turn off again, and th same cycle repeats. PROTECTIONS The cycle-by-cycle current limit circuitry turns off the high-side MOSFET whenever the current in MOSFET reaches 2A. A second level current limit is accomplished by the undervoltage protection: if the load pulls the output voltage down below 80% of its nominal value, the undervoltage latch protection will wait for a period of time (set by the capacitor at the LDELAY pin, see LDELAY CAPACITOR for more information). If the output voltage is still below 80% of its nominal after the waiting period, the latch protection will be enabled. In the latch protection mode, the low-side MOSFET is on and the high-side MOSFET is off. The latch protection will also be enabled immediately whenever the output voltage exceeds the overvoltage threshold (110% of its nominal). Both protections are disabled during start-up.(See SOFT-START CAPACITOR and LDELAY CAPACITOR for more information.) Toggling the input supply voltage or the shutdown pin can reset the device from the latched protection mode. PGOOD FLAG The PGOOD flag goes low whenever the overvoltage or undervoltage latch protection is enabled. Design Procedure This section presents guidelines for selecting external components. INPUT CAPACITOR A low ESR aluminum, tantalum, or ceramic capacitor is needed between the input pin and power ground. This capacitor prevents large voltage transients from appearing at the input. The capacitor is selected based on the RMS current and voltage requirements. The RMS current is given by: (1) The RMS current reaches its maximum (IOUT/2) when VIN equals 2VOUT. For an aluminum or ceramic capacitor, the voltage rating should be at least 25% higher than the maximum input voltage. If a tantalum capacitor is used, the voltage rating required is about twice the maximum input voltage. The tantalum capacitor should be surge current tested by the manufacturer to prevent shorted by the inrush current. It is also recommended to put a small ceramic capacitor (0.1 F) between the input pin and ground pin to reduce high frequency spikes. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM2653 9 LM2653 SNVS050E - NOVEMBER 1999 - REVISED APRIL 2013 www.ti.com INDUCTOR The most critical parameters for the inductor are the inductance, peak current and the DC resistance. The inductance is related to the peak-to-peak inductor ripple current, the input and the output voltages: (2) A higher value of ripple current reduces inductance, but increases the conductance loss, core loss, current stress for the inductor and switch devices. It also requires a bigger output capacitor for the same output voltage ripple requirement. A reasonable value is setting the ripple current to be 30% of the DC output current. Since the ripple current increases with the input voltage, the maximum input voltage is always used to determine the inductance. The DC resistance of the inductor is a key parameter for the efficiency. Lower DC resistance is available with a bigger winding area. A good tradeoff between the efficiency and the core size is letting the inductor copper loss equal 2% of the output power. OUTPUT CAPACITOR The selection of COUT is driven by the maximum allowable output voltage ripple. The output ripple in the constant frequency, PWM mode is approximated by: (3) The ESR term usually plays the dominant role in determining the voltage ripple. A low ESR aluminum electrolytic or tantalum capacitor (such as Nichicon PL series, Sanyo OS-CON, Sprague 593D, 594D, AVX TPS, and CDE polymer aluminum) is recommended. An electrolytic capacitor is not recommended for temperatures below -25C since its ESR rises dramatically at cold temperature. A tantalum capacitor has a much better ESR specification at cold temperature and is preferred for low temperature applications. The output voltage ripple in constant frequency mode has to be less than the sleep mode voltage hysteresis to avoid entering the sleep mode at full load: VRIPPLE < 20mV * VOUT /VFB (4) BOOST CAPACITOR A 0.1 F ceramic capacitor is recommended for the boost capacitor. The typical voltage across the boost capacitor is 6.7V. SOFT-START CAPACITOR A soft-start capacitor is used to provide the soft-start feature. When the input voltage is first applied, or when the SD(SS) pin is allowed to go high, the soft-start capacitor is charged by a current source (approximately 2 A). When the SD(SS) pin voltage reaches 0.6V (shutdown threshold), the internal regulator circuitry starts to operate. The current charging the soft-start capacitor increases from 2 A to approximately 10 A. With the SD(SS) pin voltage between 0.6V and 1.3V, the level of the current limit is zero, which means the output voltage is still zero. When the SD(SS) pin voltage increases beyond 1.3V, the current limit starts to increase. The switch duty cycle, which is controlled by the level of the current limit, starts with narrow pulses and gradually gets wider. At the same time, the output voltage of the converter increases towards the nominal value, which brings down the output voltage of the error amplifier. When the output of the error amplifier is less than the current limit voltage, it takes over the control of the duty cycle. The converter enters the normal current-mode PWM operation. The SD(SS) pin voltage is eventually charged up to about 2V. The soft-start time can be estimated as: TSS = CSS * 0.6V/2 A + CSS * (2V-0.6V)/10 A (5) During start-up, the internal circuit is monitoring the soft-start voltage. When the softstart voltage reaches 2V, the undervoltage and overvoltage protections are enabled. If the output voltage doesn't rise above 80% of the normal value before the soft-start reaches 2V. The undervoltage protection will kick in and shut the device down. You can avoid this by either increasing the value of the soft-start capacitor, or using a LDELAY capacitor. 10 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM2653 LM2653 www.ti.com SNVS050E - NOVEMBER 1999 - REVISED APRIL 2013 LDELAY CAPACITOR As mentioned in the Operation section, the LDELAY capacitor sets the time delay between the output voltage goes below 80% of its nominal value and the undervoltage latch protection is enabled. Charging the CDELAY by a 5 A current source up to 2V sets the delay time. Therefore, TDELAY = CDELAY * 2V/5A. The undervoltage protection is disabled by tying the LDELAY pin to the ground. R1 and R2 (PROGRAMMING OUTPUT VOLTAGE) Use the following formula to select the appropriate resistor values: VOUT = VREF(1 + R1/R2) where * VREF = 1.238V (6) Select resistors between 10k and 100k. (1% or higher accuracy metal film resistors for R1 and R2.) COMPENSATION COMPONENTS In the control to output transfer function, the first pole Fp1 can be estimated as 1/(2ROUTCOUT); The ESR zero Fz1 of the output capacitor is 1/(2ESRCOUT); Also, there is a high frequency pole Fp2 in the range of 45kHz to 150kHz: Fp2 = Fs/(n(1-D)) where * * D = VOUT/VIN n = 1+0.348L/(VIN-VOUT) (L is in Hs and VIN and VOUT in volts) (7) The total loop gain G is approximately 500/IOUT where IOUT is in amperes. A Gm amplifier is used inside the LM2653. The output resistor Ro of the Gm amplifier is about 80k. Cc1 and RC together with Ro give a lag compensation to roll off the gain: Fpc1 = 1/(2Cc1(Ro+Rc)), Fzc1 = 1/2Cc1Rc. (8) In some applications, the ESR zero Fz1 cannot be cancelled by Fp2. Then, Cc2 is needed to introduce Fpc2 to cancel the ESR zero, Fp2 = 1/(2Cc2RoRc). The rule of thumb is to have more than 45 phase margin at the crossover frequency (G=1). If COUT is higher than 68F, Cc1 = 2.2nF, and Rc = 15K are good choices for most applications. If the ESR zero is too low to be cancelled by Fp2, add Cc2. If the transient response to a step load is important, choose RC to be higher than 10k. EXTERNAL SCHOTTKY DIODE A Schottky diode D1 is recommended to prevent the intrinsic body diode of the low-side MOSFET from conducting during the deadtime in PWM operation and hysteretic mode when both MOSFETs are off. If the body diode turns on, there is extra power dissipation in the body diode because of the reverse-recovery current and higher forward voltage; the high-side MOSFET also has more switching loss since the negative diode reverserecovery current appears as the high-side MOSFET turn-on current in addition to the load current. These losses degrade the efficiency by 1-2%. The improved efficiency and noise immunity with the Schottky diode become more obvious with increasing input voltage and load current. The breakdown voltage rating of D1 is preferred to be 25% higher than the maximum input voltage. Since D1 is only on for a short period of time, the average current rating for D1 only requires being higher than 30% of the maximum output current. It is important to place D1 very close to the drain and source of the low-side MOSFET, extra parasitic inductance in the parallel loop will slow the turn-on of D1 and direct the current through the body diode of the low-side MOSFET. Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM2653 11 LM2653 SNVS050E - NOVEMBER 1999 - REVISED APRIL 2013 www.ti.com PCB Layout Considerations Layout is critical to reduce noises and ensure specified performance. The important guidelines are listed as follows: 1. Minimize the parasitic inductance in the loop of input capacitors and the internal MOSFETs by connecting the input capacitors to VIN and PGND pins with short and wide traces. This is important because the rapidly switching current, together with wiring inductance can generate large voltage spikes that may result in noise problems. 2. Minimize the trace from the center of the output resistor divider to the FB pin and keep it away from noise sources to avoid noise pick up. For applications require tight regulation at the output, a dedicated sense trace (separated from the power trace) is recommended to connect the top of the resistor divider to the output. 3. If the Schottky diode D1 is used, minimize the traces connecting D1 to SW and PGND pins. Figure 16. Schematic for the Typical Board Layout Typical PC Board Layout: (2X Size) Figure 17. Component Placement Guide 12 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM2653 LM2653 www.ti.com SNVS050E - NOVEMBER 1999 - REVISED APRIL 2013 Figure 18. Component Side PC Board Layout Figure 19. Solder Side PC Board Layout Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM2653 13 LM2653 SNVS050E - NOVEMBER 1999 - REVISED APRIL 2013 www.ti.com REVISION HISTORY Changes from Revision D (April 2013) to Revision E * 14 Page Changed layout of National Data Sheet to TI format .......................................................................................................... 13 Submit Documentation Feedback Copyright (c) 1999-2013, Texas Instruments Incorporated Product Folder Links: LM2653 PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 PACKAGING INFORMATION Orderable Device Status (1) Package Type Package Pins Package Drawing Qty Eco Plan Lead/Ball Finish MSL Peak Temp (2) (6) (3) Op Temp (C) Device Marking (4/5) LM2653MTC-ADJ NRND TSSOP PW 16 92 TBD Call TI Call TI -40 to 125 2653MT C-ADJ LM2653MTC-ADJ/NOPB ACTIVE TSSOP PW 16 92 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 2653MT C-ADJ LM2653MTCX-ADJ/NOPB ACTIVE TSSOP PW 16 2500 Green (RoHS & no Sb/Br) SN Level-1-260C-UNLIM -40 to 125 2653MT C-ADJ (1) The marketing status values are defined as follows: ACTIVE: Product device recommended for new designs. LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect. NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design. PREVIEW: Device has been announced but is not in production. Samples may or may not be available. OBSOLETE: TI has discontinued the production of the device. (2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may reference these types of products as "Pb-Free". RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption. Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based flame retardants must also meet the <=1000ppm threshold requirement. (3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature. (4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device. (5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation of the previous line and the two combined represent the entire Device Marking for that device. (6) Lead/Ball Finish - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead/Ball Finish values may wrap to two lines if the finish value exceeds the maximum column width. Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals. TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release. Addendum-Page 1 Samples PACKAGE OPTION ADDENDUM www.ti.com 6-Feb-2020 In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis. Addendum-Page 2 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 TAPE AND REEL INFORMATION *All dimensions are nominal Device Package Package Pins Type Drawing LM2653MTCX-ADJ/NOPB TSSOP PW 16 SPQ Reel Reel A0 Diameter Width (mm) (mm) W1 (mm) 2500 330.0 12.4 Pack Materials-Page 1 6.95 B0 (mm) K0 (mm) P1 (mm) 5.6 1.6 8.0 W Pin1 (mm) Quadrant 12.0 Q1 PACKAGE MATERIALS INFORMATION www.ti.com 6-Nov-2015 *All dimensions are nominal Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm) LM2653MTCX-ADJ/NOPB TSSOP PW 16 2500 367.0 367.0 35.0 Pack Materials-Page 2 PACKAGE OUTLINE PW0016A TSSOP - 1.2 mm max height SCALE 2.500 SMALL OUTLINE PACKAGE SEATING PLANE C 6.6 TYP 6.2 A 0.1 C PIN 1 INDEX AREA 14X 0.65 16 1 2X 5.1 4.9 NOTE 3 4.55 8 9 B 0.30 0.19 0.1 C A B 16X 4.5 4.3 NOTE 4 1.2 MAX (0.15) TYP SEE DETAIL A 0.25 GAGE PLANE 0.15 0.05 0 -8 0.75 0.50 DETAIL A A 20 TYPICAL 4220204/A 02/2017 NOTES: 1. All linear dimensions are in millimeters. Any dimensions in parenthesis are for reference only. Dimensioning and tolerancing per ASME Y14.5M. 2. This drawing is subject to change without notice. 3. This dimension does not include mold flash, protrusions, or gate burrs. Mold flash, protrusions, or gate burrs shall not exceed 0.15 mm per side. 4. This dimension does not include interlead flash. Interlead flash shall not exceed 0.25 mm per side. 5. Reference JEDEC registration MO-153. www.ti.com EXAMPLE BOARD LAYOUT PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE SYMM 16X (1.5) (R0.05) TYP 1 16 16X (0.45) SYMM 14X (0.65) 8 9 (5.8) LAND PATTERN EXAMPLE EXPOSED METAL SHOWN SCALE: 10X SOLDER MASK OPENING METAL UNDER SOLDER MASK METAL SOLDER MASK OPENING EXPOSED METAL EXPOSED METAL 0.05 MAX ALL AROUND NON-SOLDER MASK DEFINED (PREFERRED) 0.05 MIN ALL AROUND SOLDER MASK DEFINED SOLDER MASK DETAILS 15.000 4220204/A 02/2017 NOTES: (continued) 6. Publication IPC-7351 may have alternate designs. 7. Solder mask tolerances between and around signal pads can vary based on board fabrication site. www.ti.com EXAMPLE STENCIL DESIGN PW0016A TSSOP - 1.2 mm max height SMALL OUTLINE PACKAGE 16X (1.5) SYMM (R0.05) TYP 1 16X (0.45) 16 SYMM 14X (0.65) 8 9 (5.8) SOLDER PASTE EXAMPLE BASED ON 0.125 mm THICK STENCIL SCALE: 10X 4220204/A 02/2017 NOTES: (continued) 8. Laser cutting apertures with trapezoidal walls and rounded corners may offer better paste release. IPC-7525 may have alternate design recommendations. 9. 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