This is information on a product in full production.
December 2016 DocID027180 Rev 5 1/133
STM8AL31E8x STM8AL3LE8x
Automotive 8-bit ultra-low-power MCU, 64 KB Flash, EEPROM,
RTC, AES, LCD, timers, USARTs, I2C, SPIs, ADC, DAC, COMPs
Datasheet - production data
Features
•AEC-Q100 grade 1 qualified
•Operating conditions
– Operating power supply range 1.8 V to
3.6 V (down to 1.65 V at power down)
– Temp. range: -40 to 85 or 125 °C
•Low-power features
– 5 low-power modes: Wait, Low-power run
(5.9 µA), Low-power wait (3 µA), Active-
halt with full RTC (1.4 µA), Halt (400 nA)
– Consumption: 200 µA/MHz+330 µA
– Fast wake up from Halt mode (4.7 µs)
– Ultra-low leakage per I/0: 50 nA
•Advanced STM8 core
– Harvard architecture and 3-stage pipeline
– Max freq: 16 MHz, 16 CISC MIPS peak
– Up to 40 external interrupt sources
•Reset and supply management
– Low power, ultra safe BOR reset with 5
programmable thresholds
– Ultra-low-power POR/PDR
– Programmable voltage detector (PVD)
•Clock management
– 32 kHz and 1-16 MHz crystal oscillators
– Internal 16 MHz factory-trimmed RC and
38 kHz low consumption RC
– Clock security system
•Low-power RTC
– BCD calendar with alarm interrupt,
– Digital calibration with +/- 0.5ppm accuracy
– Advanced anti-tamper detection
•DMA
– 4 ch. for ADC, encryption hardware
accelerator (AES), DACs, SPIs, I2C,
USARTs, Timers, 1 ch. for memory-to-
memory
•LCD: 8x40 or 4x44 w/ step-up converter
•12-bit ADC up to 1 Msps /
28 channels,
– Temp. sensor and internal ref.
voltage
•Memories
– Up to 64 Kbytes of Flash with up to
2 Kbytes of data EEPROM with ECC and
RWW
– Flexible write/read protection modes
– Up to 4 Kbytes of RAM
•2x12-bit DAC (dual mode) with output buffer
•2 ultra-low-power comparators
– 1 with fixed threshold and 1 rail to rail
– Wakeup capability
•Timers
– Three 16-bit timers with 2 channels (IC,
OC, PWM), quadrature encoder
– One 16-bit advanced control timer with 3
channels, supporting motor control
– One 8-bit timer with 7-bit prescaler
– One window and one independent
watchdog
– Beeper timer with 1, 2 or 4 kHz frequencies
•Communication interfaces
– Two synchronous serial interface (SPI)
–Fast I
2C 400 kHz SMBus and PMBus
– Three USARTs (IrDA, LIN 1.3, LIN2.0)
•Up to 67 I/Os, all mappable on interrupt vectors
•Fast on-chip programming and non-intrusive
debugging with SWIM, Bootloader using
USART
•96-bit unique ID
LQFP80 LQFP64 LQFP48
14x14 mm 10x10 mm 7x7 mm
www.st.com
DocID027180 Rev 5 3/133
STM8AL31E8x STM8AL3LE8x Contents
5
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10
2 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
2.1 STM8AL ultra-low-power 8-bit family benefits . . . . . . . . . . . . . . . . . . . . . .11
2.2 Device overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13
3 Functional overview . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
3.1 Low-power modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
3.2 Central processing unit STM8 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.1 Advanced STM8 Core . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.2.2 Interrupt controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
3.3 Reset and supply management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.1 Power supply scheme . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.2 Power supply supervisor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
3.3.3 Voltage regulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.4 Clock management . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
3.5 Low-power real-time clock . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
3.6 LCD (Liquid crystal display) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.7 Memories . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.8 DMA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
3.9 Analog-to-digital converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.10 Digital-to-analog converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.11 Ultra-low-power comparators . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
3.12 System configuration controller and routing interface . . . . . . . . . . . . . . . 22
3.13 AES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14 Timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
3.14.1 16-bit advanced control timer (TIM1) . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.14.2 16-bit general purpose timers (TIM2, TIM3, TIM5) . . . . . . . . . . . . . . . . 23
3.14.3 8-bit basic timer (TIM4) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15 Watchdog timers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15.1 Window watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
3.15.2 Independent watchdog timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Contents STM8AL31E8x STM8AL3LE8x
4/133 DocID027180 Rev 5
3.16 Beeper . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.1 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.2 I2C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
3.17.3 USART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.18 Infrared (IR) interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
3.19 Development support . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
4 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
5 Memory and register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.1 Memory mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
5.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
6 Interrupt vector mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
7 Option byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
8 Unique ID . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
9 Electrical parameters . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.1 Parameter conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.1.1 Minimum and maximum values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.1.2 Typical values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.1.3 Typical curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.1.4 Loading capacitor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
9.1.5 Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.2 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
9.3 Operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.3.1 General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
9.3.2 Embedded reset and power control block characteristics . . . . . . . . . . 70
9.3.3 Supply current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
9.3.4 Clock and timing characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
9.3.5 Memory characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
9.3.6 I/O current injection characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.3.7 I/O port pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
9.3.8 Communication interfaces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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9.3.9 LCD controller (STM8AL3LE8x only) . . . . . . . . . . . . . . . . . . . . . . . . . . 105
9.3.10 Embedded reference voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
9.3.11 Temperature sensor . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
9.3.12 Comparator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
9.3.13 12-bit DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
9.3.14 12-bit ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
9.3.15 EMC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
9.4 Thermal characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .119
10 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
10.1 LQFP80 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 120
10.2 LQFP64 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
10.3 LQFP48 package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
11 Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
12 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
List of tables STM8AL31E8x STM8AL3LE8x
6/133 DocID027180 Rev 5
List of tables
Table 1. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Table 2. High-density STM8AL3xE8x low-power device features and peripheral counts. . . . . . . . . 13
Table 3. Timer feature comparison. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Table 4. Legend/abbreviation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 5. High-density STM8AL3xE8x pin description. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30
Table 6. Flash and RAM boundary addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 7. Factory conversion registers. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 8. I/O port hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40
Table 9. General hardware register map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Table 10. CPU/SWIM/debug module/interrupt controller registers. . . . . . . . . . . . . . . . . . . . . . . . . . . 58
Table 11. Interrupt mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
Table 12. Option byte addresses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62
Table 13. Option byte description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63
Table 14. Unique ID registers (96 bits) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65
Table 15. Voltage characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Table 16. Current characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 17. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 18. Operating lifetime (OLF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68
Table 19. General operating conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 69
Table 20. Embedded reset and power control block characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . 70
Table 21. Total current consumption in Run mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 72
Table 22. Total current consumption in Wait mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75
Table 23. Total current consumption and timing in low-power run mode at VDD = 1.65 V
to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
Table 24. Total current consumption in low-power wait mode at VDD = 1.65 V to 3.6 V . . . . . . . . . . 78
Table 25. Total current consumption and timing in Active-halt mode
at VDD = 1.65 V to 3.6 V . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
Table 26. Typical current consumption in Active-halt mode, RTC clocked by LSE external crystal. . 80
Table 27. Total current consumption and timing in Halt mode at VDD = 1.65 to 3.6 V . . . . . . . . . . . 82
Table 28. Peripheral current consumption . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
Table 29. Current consumption under external reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 30. HSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85
Table 31. LSE external clock characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 32. HSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86
Table 33. LSE oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Table 34. HSI oscillator characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Table 35. LSI oscillator characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 36. RAM and hardware registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Table 37. Flash program memory/data EEPROM memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 38. Flash program memory. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 39. Data memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91
Table 40. I/O current injection susceptibility . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 92
Table 41. I/O static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 93
Table 42. Output driving current (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 43. Output driving current (true open drain ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
Table 44. Output driving current (PA0 with high sink LED driver capability). . . . . . . . . . . . . . . . . . . . 96
Table 45. NRST pin characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Table 46. SPI1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 100
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Table 47. I2C characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103
Table 48. LCD characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 105
Table 49. Reference voltage characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
Table 50. TS characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 51. Comparator 1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
Table 52. Comparator 2 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 108
Table 53. DAC characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
Table 54. DAC accuracy . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 110
Table 55. DAC output on PB4-PB5-PB6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111
Table 56. ADC1 characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
Table 57. ADC1 accuracy with VDDA = 3.3 V to 2.5 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 58. ADC1 accuracy with VDDA = 2.4 V to 3.6 V. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 59. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V. . . . . . . . . . . . . . . . . . . . . . . . . . . 114
Table 60. EMS data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117
Table 61. EMI data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 62. ESD absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 118
Table 63. Electrical sensitivities . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 64. Thermal characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119
Table 65. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121
Table 66. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124
Table 67. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 128
Table 68. STM8AL31E8x STM8AL3LE8x ordering information scheme . . . . . . . . . . . . . . . . . . . . . 131
Table 69. Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
List of figures STM8AL31E8x STM8AL3LE8x
8/133 DocID027180 Rev 5
List of figures
Figure 1. High-density STM8AL3xE8x device block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Figure 2. Clock tree diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Figure 3. STM8AL31E8A 80-pin package pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 4. STM8AL3LE8A 80-pin package pinout (with LCD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
Figure 5. STM8AL31E89 64-pin pinout (without LCD). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 6. STM8AL3LE89 64-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28
Figure 7. STM8AL31E88 48-pin pinout (without LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 8. STM8AL3LE88 48-pin pinout (with LCD) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29
Figure 9. Memory map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39
Figure 10. Pin loading conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66
Figure 11. Pin input voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
Figure 12. Power supply thresholds. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71
Figure 13. Typical IDD(RUN) from RAM vs. VDD (HSI clock source), fCPU =16 MHz(1) . . . . . . . . . . . . . 73
Figure 14. Typical IDD(RUN) from Flash vs. VDD (HSI clock source), fCPU = 16 MHz(1) . . . . . . . . . . . . 74
Figure 15. Typical IDD(Wait) from RAM vs. VDD (HSI clock source), fCPU = 16 MHz(1) . . . . . . . . . . . . . 76
Figure 16. Typical IDD(Wait) from Flash (HSI clock source), fCPU = 16 MHz(1) . . . . . . . . . . . . . . . . . . . 76
Figure 17. Typical IDD(LPR) vs. VDD (LSI clock source), all peripherals OFF . . . . . . . . . . . . . . . . . . . . 77
Figure 18. Typical IDD(LPW) vs. VDD (LSI clock source), all peripherals OFF(1) . . . . . . . . . . . . . . . . . . 78
Figure 19. Typical IDD(AH) vs. VDD (LSI clock source) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81
Figure 20. Typical IDD(Halt) vs. VDD (internal reference voltage OFF) . . . . . . . . . . . . . . . . . . . . . . . . 82
Figure 21. HSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
Figure 22. LSE oscillator circuit diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88
Figure 23. Typical HSI frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 89
Figure 24. Typical LSI clock source frequency vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90
Figure 25. Typical VIL and VIH vs. VDD (standard I/Os) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 26. Typical VIL and VIH vs. VDD (true open drain I/Os). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94
Figure 27. Typical pull-up resistance RPU vs. VDD with VIN=VSS. . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 28. Typical pull-up current Ipu vs. VDD with VIN=VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 95
Figure 29. Typical VOL @ VDD = 3.0 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 30. Typical VOL @ VDD = 1.8 V (high sink ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 31. Typical VOL @ VDD = 3.0 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 32. Typical VOL @ VDD = 1.8 V (true open drain ports) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 33. Typical VDD - VOH @ VDD = 3.0 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 34. Typical VDD - VOH @ VDD = 1.8 V (high sink ports). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 97
Figure 35. Typical NRST pull-up resistance RPU vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
Figure 36. Typical NRST pull-up current Ipu vs. VDD . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 37. Recommended NRST pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
Figure 38. SPI1 timing diagram - slave mode and CPHA=0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 39. SPI1 timing diagram - slave mode and CPHA=1(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 101
Figure 40. SPI1 timing diagram - master mode(1) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 102
Figure 41. Typical application with I2C bus and timing diagram(1)) . . . . . . . . . . . . . . . . . . . . . . . . . . 104
Figure 42. ADC1 accuracy characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 43. Typical connection diagram using the ADC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 115
Figure 44. Power supply and reference decoupling (VREF+ not connected to VDDA). . . . . . . . . . . . . 116
Figure 45. Power supply and reference decoupling (VREF+ connected to VDDA) . . . . . . . . . . . . . . 116
Figure 46. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 120
Figure 47. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 122
DocID027180 Rev 5 9/133
STM8AL31E8x STM8AL3LE8x List of figures
9
Figure 48. LQFP80 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
Figure 49. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . 124
Figure 50. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
Figure 51. LQFP64 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126
Figure 52. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline . . . . . . . . . . . . . . . . . . 127
Figure 53. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
recommended footprint . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
Figure 54. LQFP48 marking example (package top view). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
Introduction STM8AL31E8x STM8AL3LE8x
10/133 DocID027180 Rev 5
1 Introduction
This document describes the features, pinout, mechanical data and ordering information of
the high-density STM8AL31E8x and STM8AL3LE8x devices (microcontrollers with 64 Kbyte
Flash memory density). These devices are referred to as high-density devices in
STM8L051/L052 Value Line, STM8L151/L152, STM8L162, STM8AL31, STM8AL3L MCU
lines reference manual (RM0031) and in the STM8L and STM8AL Flash programming
manual (PM0054).
For more details on the whole STMicroelectronics ultra-low-power family please refer to
Section 3: Functional overview on page 14.
For information on the debug module and SWIM (single wire interface module), refer to the
STM8 SWIM communication protocol and debug module user manual (UM0470).
For information on the STM8 core, please refer to the STM8 CPU programming manual
(PM0044).
DocID027180 Rev 5 11/133
STM8AL31E8x STM8AL3LE8x Description
61
2 Description
The high-density STM8AL3xE8x ultra-low-power devices feature an enhanced STM8 CPU
core providing increased processing power (up to 16 MIPS at 16 MHz) while maintaining the
advantages of a CISC architecture with improved code density, a 24-bit linear addressing
space and an optimized architecture for low-power operations.
The family includes an integrated debug module with a hardware interface (SWIM) which
allows non-intrusive in-application debugging and ultrafast Flash programming.
All high-density STM8AL3xE8x microcontrollers feature embedded data EEPROM and low-
power low-voltage single-supply program Flash memory.
The devices incorporate an extensive range of enhanced I/Os and peripherals, a 12-bit
ADC, two DACs, two comparators, a real-time clock, AES, 8x40 or 4x44-segment LCD, four
16-bit timers, one 8-bit timer, as well as standard communication interfaces such as two
SPIs, an I2C interface, and three USARTs. One 8x40 or 4x44-segment LCD is available on
the STM8AL3LE8x devices. The modular design of the peripheral set allows the same
peripherals to be found in different ST microcontroller families including 32-bit families. This
makes any transition to a different family very easy, and simplified even more by the use of
a common set of development tools.
2.1 STM8AL ultra-low-power 8-bit family benefits
High-density STM8AL3xE8x devices are part of the STM8AL automotive ultra-low-power 8-
bit family providing the following benefits:
•Integrated system
– 64 Kbytes of high-density embedded Flash program memory
– 2 Kbytes of data EEPROM
– 4 Kbytes of RAM
– Internal high-speed and low-power low speed RC.
– Embedded reset
•Ultra-low-power consumption
– 1 µA in Active-halt mode
– Clock gated system and optimized power management
– Capability to execute from RAM for Low-power wait mode and Low-power run
mode
•Advanced features
– Up to 16 MIPS at 16 MHz CPU clock frequency
– Direct memory access (DMA) for memory-to-memory or peripheral-to-memory
access.
•Short development cycles
– Application scalability across a common family product architecture with
compatible pinout, memory map and modular peripherals.
– Wide choice of development tools
Description STM8AL31E8x STM8AL3LE8x
12/133 DocID027180 Rev 5
STM8AL ultra-low-power microcontrollers operates either from 1.8 to 3.6 V (down to 1.65 V
at power-down) or from 1.65 to 3.6 V. They are available in the -40 to +85 °C and -40 to
+125 °C temperature ranges.
These features make the STM8AL ultra-low-power microcontroller families suitable for a
wide range of applications.
The devices are offered in one 48-pin package. Different sets of peripherals are included
depending on the device. Refer to Section 3 for an overview of the complete range of
peripherals proposed in this family.
All STM8AL ultra-low-power products are based on the same architecture with the same
memory mapping and a coherent pinout.
Figure 1 shows the block diagram of the high-density STM8AL3xE8x families.
DocID027180 Rev 5 13/133
STM8AL31E8x STM8AL3LE8x Description
61
2.2 Device overview
Table 2. High-density STM8AL3xE8x low-power device features and peripheral counts
Features STM8AL3xx8 STM8AL3xx9 STM8AL3xxA
Flash (Kbyte) 64
Data EEPROM (Kbyte) 2
AES 1
LCD 8x28 or 4x32(1) 8x36 or 4x40(1) 8x40 or 4x44(1)
Timers
Basic 1
(8-bit)
1
(8-bit)
1
(8-bit)
General purpose 3
(16-bit)
3
(16-bit)
3
(16-bit)
Advanced control 1
(16-bit)
1
(16-bit)
1
(16-bit)
Communication
interfaces
SPI 2 2 2
I2C 1 1 1
USART 3 3 3
GPIOs 41(2) 54(2) 68(2)
12-bit synchronized ADC
(number of channels)
1
(25)
1
(28)
1
(28)
12-Bit DAC
Number of channels
2
2
2
2
2
2
Comparators (COMP1/COMP2) 2 2 2
Others
RTC, window watchdog, independent watchdog,
16-MHz and 38-kHz internal RC, 1- to 16-MHz and 32-kHz external
oscillator
CPU frequency 16 MHz
Operating voltage 1.8 to 3.6 V (down to 1.65 V at power-down) with BOR
Operating temperature -40 to +85 °C / -40 to +125 °C
Packages LQFP48 LQFP64 LQFP80
1. STM8AL3LE8x versions only.
2. The number of GPIOs given in this table includes the NRST/PA1 pin but the application can use the NRST/PA1 pin as
general purpose output only (PA1).
Functional overview STM8AL31E8x STM8AL3LE8x
14/133 DocID027180 Rev 5
3 Functional overview
Figure 1. High-density STM8AL3xE8x device block diagram
1. Legend: AF: alternate function
ADC: Analog-to-digital converter
AES: Advanced encryption standard hardware accelerator
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DocID027180 Rev 5 15/133
STM8AL31E8x STM8AL3LE8x Functional overview
61
BOR: Brownout reset
DMA: Direct memory access
DAC: Digital-to-analog converter
I²C: Inter-integrated circuit multimaster interface
IWDG: Independent watchdog
LCD: Liquid crystal display
POR/PDR: Power on reset / power-down reset
RTC: Real-time clock
SPI: Serial peripheral interface
SWIM: Single wire interface module
USART: Universal synchronous asynchronous receiver transmitter
WWDG: Window watchdog
3.1 Low-power modes
The high-density STM8AL3xE8x devices support five low-power modes to achieve the best
compromise between low-power consumption, short startup time and available wakeup
sources:
•Wait mode: CPU clock is stopped, but selected peripherals keep running. An internal
or external interrupt or a Reset is used to exit the microcontroller from Wait mode (WFE
or WFI mode).
•Low-power run mode: The CPU and the selected peripherals are running. Execution
is done from RAM with a low speed oscillator (LSI or LSE). Flash memory and data
EEPROM are stopped and the voltage regulator is configured in ultra-low-power mode.
The microcontroller enters Low-power run mode by software and exits from this mode
by software or by a reset.
All interrupts must be masked and are not used to exit the microcontroller from this
mode.
•Low-power wait mode: This mode is entered when executing a Wait for event in Low-
power run mode. It is similar to Low-power run mode except that the CPU clock is
stopped. The wakeup from this mode is triggered by a Reset or by an internal or
external event (peripheral event generated by the timers, serial interfaces, DMA
controller (DMA1), comparators and I/O ports). When the wakeup is triggered by an
event, the system goes back to Low-power run mode.
All interrupts must be masked and arenot used to exit the microcontroller from this
mode.
•Active-halt mode: CPU and peripheral clocks are stopped, except RTC. The wakeup
is triggered by RTC interrupts, external interrupts or reset.
•Halt mode: CPU and peripheral clocks are stopped, the device remains powered on.
The RAM content is preserved. The wakeup is triggered by an external interrupt or
reset. A few peripherals have also a wakeup from Halt capability. Switching off the
internal reference voltage reduces power consumption. Through software configuration
it is also possible to wake up the device without waiting for the internal reference
voltage wakeup time to have a fast wakeup time of 5 µs.
Functional overview STM8AL31E8x STM8AL3LE8x
16/133 DocID027180 Rev 5
3.2 Central processing unit STM8
3.2.1 Advanced STM8 Core
The 8-bit STM8 core is designed for code efficiency and performance with an Harvard
architecture and a 3-stage pipeline.
It contains 6 internal registers which are directly addressable in each execution context, 20
addressing modes including indexed indirect and relative addressing, and 80 instructions.
Architecture and registers
•Harvard architecture
•3-stage pipeline
•32-bit wide program memory bus - single cycle fetching most instructions
•X and Y 16-bit index registers - enabling indexed addressing modes with or without
offset and read-modify-write type data manipulations
•8-bit accumulator
•24-bit program counter - 16 Mbyte linear memory space
•16-bit stack pointer - access to a 64 Kbyte level stack
•8-bit condition code register - 7 condition flags for the result of the last instruction
Addressing
•20 addressing modes
•Indexed indirect addressing mode for lookup tables located anywhere in the address
space
•Stack pointer relative addressing mode for local variables and parameter passing
Instruction set
•80 instructions with 2-byte average instruction size
•Standard data movement and logic/arithmetic functions
•8-bit by 8-bit multiplication
•16-bit by 8-bit and 16-bit by 16-bit division
•Bit manipulation
•Data transfer between stack and accumulator (push/pop) with direct stack access
•Data transfer using the X and Y registers or direct memory-to-memory transfers
3.2.2 Interrupt controller
The high-density STM8AL3xE8x devices feature a nested vectored interrupt controller:
•Nested interrupts with 3 software priority levels
•32 interrupt vectors with hardware priority
•Up to 40 external interrupt sources on 11 vectors
•Trap and reset interrupts
DocID027180 Rev 5 17/133
STM8AL31E8x STM8AL3LE8x Functional overview
61
3.3 Reset and supply management
3.3.1 Power supply scheme
The device requires a 1.65 V to 3.6 V operating supply voltage (VDD). The external power
supply pins must be connected as follows:
•VSS1, VDD1, VSS2, VDD2, VSS3, VDD3, VSS4, VDD4= 1.65 to 3.6 V: external power supply
for I/Os and for the internal regulator. Provided externally through VDD pins, the
corresponding ground pin is VSS. VSS1/VSS2/VSS3/VSS4 and VDD1/VDD2/VDD3/VDD4
must not be left unconnected.
•VSSA, VDDA = 1.65 to 3.6 V: external power supplies for analog peripherals (minimum
voltage to be applied to VDDA is 1.8 V when the ADC1 is used). VDDA and VSSA must
be connected to VDD and VSS, respectively.
•VREF+, VREF- (for ADC1): external reference voltage for ADC1. Must be provided
externally through VREF+ and VREF- pin.
•VREF+ (for DAC1/2): external voltage reference for DAC1 and DAC2 must be provided
externally through VREF+.
3.3.2 Power supply supervisor
The device has an integrated ZEROPOWER power-on reset (POR)/power-down reset
(PDR), coupled with a brownout reset (BOR) circuitry. At power-on, BOR is always active,
and ensures proper operation starting from 1.8 V. As soon as the 1.8 V BOR threshold is
reached, the option byte loading process starts, either to confirm or modify the default
thresholds, or to disable BOR permanently. In this latter case, the VDD min value at power
down is 1.65 V.
Five BOR thresholds are available through option byte, starting from 1.8 V to 3 V. To reduce
the power consumption in Halt mode, it is possible to automatically switch off the internal
reference voltage (and consequently the BOR) in Halt mode. The device remains in reset
state when VDD is below a specified threshold, VPOR/PDR or VBOR, without the need for any
external reset circuit.
The device features an embedded programmable voltage detector (PVD) that monitors the
VDD/VDDA power supply and compares it to the VPVD threshold. This PVD offers 7 different
levels between 1.85 V and 3.05 V, chosen by software, with a step around 200 mV. An
interrupt is generated when VDD/VDDA drops below the VPVD threshold and/or when
VDD/VDDA is higher than the VPVD threshold. The interrupt service routine generates then a
warning message and/or put the MCU into a safe state. The PVD is enabled by software.
Functional overview STM8AL31E8x STM8AL3LE8x
18/133 DocID027180 Rev 5
3.3.3 Voltage regulator
The high-density STM8AL3xE8x devices embed an internal voltage regulator for generating
the 1.8 V power supply for the core and peripherals.
This regulator has two different modes:
•Main voltage regulator mode (MVR) for Run, Wait for interrupt (WFI) and Wait for event
(WFE) modes.
•Low-power voltage regulator mode (LPVR) for Halt, Active-halt, Low-power run and
Low-power wait modes.
When entering Halt or Active-halt modes, the system automatically switches from the MVR
to the LPVR in order to reduce current consumption.
3.4 Clock management
The clock controller distributes the system clock (SYSCLK) coming from different oscillators
to the core and the peripherals. It also manages clock gating for low-power modes and
ensures clock robustness.
Features
•Clock prescaler: to get the best compromise between speed and current
consumption, the clock frequency to the CPU and peripherals has to be adjusted by a
programmable prescaler
•Safe clock switching: Clock sources are adaptable safely on the fly in run mode
through a configuration register.
•Clock management: To reduce power consumption, the clock controller stops the
clock to the core, individual peripherals or memory.
•System clock sources: 4 different clock sources are available to drive the system
clock:
– 1-16 MHz High speed external crystal (HSE)
– 16 MHz High speed internal RC oscillator (HSI)
– 32.768 Low speed external crystal (LSE)
– 38 kHz Low speed internal RC (LSI)
•RTC and LCD clock sources: the above four sources are available to clock the RTC
and the LCD, whatever the system clock.
•Startup clock: After reset, the microcontroller restarts by default with an internal
2 MHz clock (HSI/8). The prescaler ratio and clock source is adjustable by the
application program as soon as the code execution starts.
•Clock security system (CSS): This feature is enabled by software. If a HSE clock
failure occurs, the system clock is automatically switched to HSI.
•Configurable main clock output (CCO): This outputs an external clock for use by the
application.
DocID027180 Rev 5 19/133
STM8AL31E8x STM8AL3LE8x Functional overview
61
Figure 2. Clock tree diagram
1. The HSE clock source is either an external crystal/ceramic resonator or an external source (HSE bypass).
Refer to Section HSE clock in STM8L051/L052 Value Line, STM8L151/L152, STM8L162, STM8AL31,
STM8AL3L MCU lines reference manual (RM0031).
2. The LSE clock source is either an external crystal/ceramic resonator or a external source (LSE bypass).
Refer to Section LSE clock in STM8L051/L052 Value Line, STM8L151/L152, STM8L162, STM8AL31,
STM8AL3L MCU lines reference manual (RM0031).
3.5 Low-power real-time clock
The real-time clock (RTC) is an independent binary coded decimal (BCD) timer/counter.
Six byte locations contain the second, minute, hour (12/24 hour), week day, date, month,
year, in BCD (binary coded decimal) format. Correction for 28, 29 (leap year), 30, and 31
day months are made automatically. The subsecond field is also readable in binary format.
The calendar is adjustable from 1 to 32767 RTC clock pulses. This allows to make a
synchronization to a master clock.
The RTC offers a digital calibration which allows an accuracy of +/-0.5ppm.
It provides a programmable alarm and programmable periodic interrupts with wakeup from
Halt capability.
•Periodic wakeup time using the 32.768 kHz LSE with the lowest resolution (of 61 µs) is
from min. 122 µs to max. 3.9 s. With a different resolution, the wakeup time reaches
36 hours
•Periodic alarms based on the calendar are generated from LSE period to every year
A clock security system detects a failure on LSE, and provides an interrupt with wakeup
capability. The RTC clock automatically switches to LSI in case of LSE failure.
The RTC also provides 3 anti-tamper detection pins. This detection embeds a
programmable filter and wakes-up the MCU.
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Functional overview STM8AL31E8x STM8AL3LE8x
20/133 DocID027180 Rev 5
3.6 LCD (Liquid crystal display)
The LCD is only available on STM8AL3LE8x devices.
The liquid crystal display drives up to 8 common terminals and up to 40 segment terminals
to drive up to 320 pixels. This LCD is configurable to drive up to 4 common and 44
segments (up to 176 pixels).
•Internal step-up converter to guarantee contrast control whatever VDD.
•Static 1/2, 1/3, 1/4, 1/8 duty supported.
•Static 1/2, 1/3, 1/4 bias supported.
•Phase inversion to reduce power consumption and EMI.
•Up to 8 pixels programmable to blink.
•The LCD controller operating in Halt mode.
Note: Unnecessary segments and common pins can be used as general I/O pins.
3.7 Memories
The high-density STM8AL3xE8x devices have the following main features:
•4 Kbytes of RAM
•The non-volatile memory is divided into three arrays:
– 64 Kbytes of medium-density embedded Flash program memory
– 2 Kbytes of Data EEPROM
– Option byte.
The memory supports the read-while-write (RWW): it is possible to execute the code from
the program matrix while programming/erasing the data matrix.
The option byte protects part of the Flash program memory from write and readout piracy.
3.8 DMA
A 4-channel direct memory access controller (DMA1) offers a memory-to-memory and
peripherals-from/to-memory transfer capability. The 4 channels are shared between the
following IPs with DMA capability: ADC1, DAC1,DAC2, AES, I2C1, SPI1, SPI2, USART1,
USART2, USART3, and the 5 Timers.
DocID027180 Rev 5 21/133
STM8AL31E8x STM8AL3LE8x Functional overview
61
3.9 Analog-to-digital converter
•12-bit analog-to-digital converter (ADC1) with 28 channels (including 4 fast channel),
temperature sensor and internal reference voltage
•Conversion time down to 1 µs with fSYSCLK= 16 MHz
•Programmable resolution
•Programmable sampling time
•Single and continuous mode of conversion
•Scan capability: automatic conversion performed on a selected group of analog inputs
•Analog watchdog: interrupt generation when the converted voltage is outside the
programmed threshold
•Triggered by timer
Note: ADC1 can be served by DMA1.
3.10 Digital-to-analog converter
•12-bit DAC with 2 buffered outputs (two digital signals are converted into two analog
voltage signal outputs)
•Synchronized update capability using timers
•DMA capability for each channel
•External triggers for conversion
•Noise-wave generation
•Triangular-wave generation
•Dual DAC channels with independent or simultaneous conversions
•Input reference voltage VREF+ for better resolution
Note: DAC can be served by DMA1.
3.11 Ultra-low-power comparators
The high-density STM8AL3xE8x devices embed two comparators (COMP1 and COMP2)
sharing the same current bias and voltage reference. The voltage reference is an internal or
external (coming from an I/O).
•One comparator with fixed threshold (COMP1).
•One comparator rail to rail with fast or slow mode (COMP2). The threshold is one of the
following:
– DAC output
– External I/O
– Internal reference voltage or internal reference voltage submultiple (1/4, 1/2, 3/4)
The two comparators are usable together to offer a window function. They wake up from
Halt mode.
Functional overview STM8AL31E8x STM8AL3LE8x
22/133 DocID027180 Rev 5
3.12 System configuration controller and routing interface
The system configuration controller provides the capability to remap some alternate
functions on different I/O ports. TIM4 and ADC1 DMA channels can also be remapped.
The highly flexible routing interface allows application software to control the routing of
different I/Os to the TIM1 timer input captures. It also controls the routing of internal analog
signals to ADC1, COMP1, COMP2, DAC1 and the internal reference voltage VREFINT
. It also
provides a set of registers for efficiently managing the charge transfer acquisition sequence.
3.13 AES
The AES Hardware Accelerator can be used to encipher and decipher data using the AES
algorithm (compatible with FIPS PUB 197, 2001 Nov 26).
• Key scheduler
• Key derivation for decryption
• 128-bit data block processed
• 128-bit key length
• 892 clock cycles to encrypt/decrypt one 128-bit block
AES data flow can be served by the DMA1 controller
3.14 Timers
The high-density STM8AL3xE8x devices contain one advanced control timer (TIM1), three
16-bit general purpose timers (TIM2,TIM3 and TIM5) and one 8-bit basic timer (TIM4).
All the timers are served by DMA1.
Table 3 compares the features of the advanced control, general-purpose and basic timers.
Table 3. Timer feature comparison
Timer Counter
resolution
Counter
type Prescaler factor
DMA1
request
generation
Capture/compare
channels
Complementary
outputs
TIM1
16-bit up/down
Any integer
from 1 to 65536
Yes
3 + 1 3
TIM2
Any power of 2
from 1 to 128 2
None
TIM3
TIM5
TIM4 8-bit up Any power of 2
from 1 to 32768 0
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STM8AL31E8x STM8AL3LE8x Functional overview
61
3.14.1 16-bit advanced control timer (TIM1)
This is a high-end timer designed for a wide range of control applications. With its
complementary outputs, dead-time control and center-aligned PWM capability, the field of
applications is extended to motor control, lighting and half-bridge driver.
•16-bit up, down and up/down autoreload counter with 16-bit prescaler
•3 independent capture/compare channels (CAPCOM) configurable as input capture,
output compare, PWM generation (edge and center aligned mode) and single pulse
mode output
•1 additional capture/compare channel which is not connected to an external I/O
•Synchronization module to control the timer with external signals
•Break input to force timer outputs into a defined state
•3 complementary outputs with adjustable dead time
•Encoder mode
•Interrupt capability on various events (capture, compare, overflow, break, trigger)
3.14.2 16-bit general purpose timers (TIM2, TIM3, TIM5)
•16-bit autoreload (AR) up/down-counter
•7-bit prescaler adjustable to fixed power of 2 ratios (1…128)
•2 individually configurable capture/compare channels
•PWM mode
•Interrupt capability on various events (capture, compare, overflow, break, trigger)
•Synchronization with other timers or external signals (external clock, reset, trigger and
enable)
3.14.3 8-bit basic timer (TIM4)
The 8-bit timer consists of an 8-bit up auto-reload counter driven by a programmable
prescaler. This timer is used for timebase generation with interrupt generation on timer
overflow or for DAC trigger generation.
3.15 Watchdog timers
The watchdog system is based on two independent timers providing maximum security to
the applications.
3.15.1 Window watchdog timer
The window watchdog (WWDG) is used to detect the occurrence of a software fault, usually
generated by external interferences or by unexpected logical conditions, which cause the
application program to abandon its normal sequence.
3.15.2 Independent watchdog timer
The independent watchdog peripheral (IWDG) is used to resolve processor malfunctions
due to hardware or software failures.
Functional overview STM8AL31E8x STM8AL3LE8x
24/133 DocID027180 Rev 5
It is clocked by the internal LSI RC clock source, and thus stays active even in case of a
CPU clock failure.
3.16 Beeper
The beeper function outputs a signal on the BEEP pin for sound generation. The signal is in
the range of 1, 2 or 4 kHz.
3.17 Communication interfaces
3.17.1 SPI
The serial peripheral interfaces (SPI1 and SPI2) provide half/ full duplex synchronous serial
communication with external devices.
•Maximum speed: 8 Mbit/s (fSYSCLK/2) both for master and slave
•Full duplex synchronous transfers
•Simplex synchronous transfers on 2 lines with a possible bidirectional data line
•Master or slave operation - selectable by hardware or software
•Hardware CRC calculation
•Slave/master selection input pin
Note: SPI1 and SPI2 can be served by the DMA1 Controller.
3.17.2 I2C
The I2C bus interface (I2C1) provides multi-master capability, and controls all I²C bus-
specific sequencing, protocol, arbitration and timing.
•Master, slave and multi-master capability
•Standard mode up to 100 kHz and fast speed modes up to 400 kHz.
•7-bit and 10-bit addressing modes.
•SMBus 2.0 and PMBus support
•Hardware CRC calculation
Note: I2C1 can be served by the DMA1 Controller.
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STM8AL31E8x STM8AL3LE8x Functional overview
61
3.17.3 USART
The USART interfaces (USART1, USART2 and USART3) allow full duplex, asynchronous
communications with external devices requiring an industry standard NRZ asynchronous
serial data format. It offers a very wide range of baud rates.
•1 Mbit/s full duplex SCI
•SPI1 emulation
•High precision baud rate generator
•Smartcard emulation
•IrDA SIR encoder decoder
•Single wire half duplex mode
Note: USART1, USART2 and USART3 can be served by the DMA1 Controller.
USART interfaces are used to implement LIN slave communication, with LIN Break
detection on the framing error flag (FE in USART_SR register) with a value of 0 in the
USART data register (USART_DR).
3.18 Infrared (IR) interface
The high-density STM8AL3xE8x devices contain an infrared interface which is used with an
IR LED for remote control functions. Two timer output compare channels are used to
generate the infrared remote control signals.
3.19 Development support
Development tools
Development tools for the STM8 microcontrollers include:
•The STice emulation system offering tracing and code profiling
•The STVD high-level language debugger including C compiler, assembler and
integrated development environment
•The STVP Flash programming software
The STM8 also comes with starter kits, evaluation boards and low-cost in-circuit
debugging/programming tools.
Single wire data interface (SWIM) and debug module
The debug module with its single wire data interface (SWIM) permits non-intrusive real-time
in-circuit debugging and fast memory programming.
The Single wire interface is used for direct access to the debugging module and memory
programming. The interface is activated in all device operation modes.
The non-intrusive debugging module features a performance close to a full-featured
emulator. Beside memory and peripherals, CPU operation is also monitored in real-time by
means of shadow registers.
DocID027180 Rev 5 27/133
STM8AL31E8x STM8AL3LE8x Pin description
61
4 Pin description
Figure 3. STM8AL31E8A 80-pin package pinout (without LCD)
1. Pin 22 is reserved and must be tied to VDD.
2. The above figure shows the package top view.
Figure 4. STM8AL3LE8A 80-pin package pinout (with LCD)
1. The above figure shows the package top view.
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Pin description STM8AL31E8x STM8AL3LE8x
28/133 DocID027180 Rev 5
Figure 5. STM8AL31E89 64-pin pinout (without LCD)
1. Pin 18 is reserved and must be tied to VDD.
2. The above figure shows the package top view.
Figure 6. STM8AL3LE89 64-pin pinout (with LCD)
1. The above figure shows the package top view.
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DocID027180 Rev 5 29/133
STM8AL31E8x STM8AL3LE8x Pin description
61
Figure 7. STM8AL31E88 48-pin pinout (without LCD)
1. Pin 13 is reserved and must be tied to VDD.
2. The above figure shows the package top view.
Figure 8. STM8AL3LE88 48-pin pinout (with LCD)
1. The above figure shows the package top view.
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Pin description STM8AL31E8x STM8AL3LE8x
30/133 DocID027180 Rev 5
Table 4. Legend/abbreviation
Type I= input, O = output, S = power supply
Level
FT: Five-volt tolerant
Output HS = high sink/source (20 mA)
Port and control
configuration
Input float = floating, wpu = weak pull-up
Output T = true open drain, OD = open drain, PP = push pull
Reset state
Bold X (pin state after reset release).
Unless otherwise specified, the pin state is the same during the reset phase (i.e.
“under reset”) and after internal reset release (i.e. at reset state).
Table 5. High-density STM8AL3xE8x pin description
Pin
number
Pin name
Type
I/O level
Input Output
Main function
(after reset)
Default alternate function
LQFP80
LQFP64
LQFP48
floating
wpu
Ext. interrupt
High sink/source
OD
PP
1 - - PH0/LCD SEG 36 (3) I/O FT(5) XXXHSXXPort H0 LCD segment 36
2 - - PH1/LCD SEG 37 (3) I/O FT(5) XXXHSXXPort H1 LCD segment 37
3 - - PH2/LCD SEG 38 (3) I/O FT(5) XXXHSXXPort H2 LCD segment 38
4 - - PH3/LCD SEG 39 (3) I/O FT(5) XXXHSXXPort H3 LCD segment 39
622NRST/PA1
(1) I/O - - X-HSX XReset PA1
733
PA2/OSC_IN/
[USART1_TX](2)/
[SPI1_MISO] (2)
I/O - XXXHSXXPort A2
HSE oscillator input /
[USART1 transmit] / [SPI1
master in- slave out] /
844
PA3/OSC_OUT/[USART1
_RX](2)/[SPI1_MOSI](2) I/O - XXXHSXXPort A3
HSE oscillator output /
[USART1 receive]/ [SPI1
master out/slave in]/
955
PA4/TIM2_BKIN/
[TIM2_ETR](2)
LCD_COM0(3)/ADC1_IN2
COMP1_INP
I/O FT(5) XXXHSXXPort A4
Timer 2 - break input /
/[Timer 2 - trigger] /
LCD COM 0 / ADC1 input
2/Comparator 1 positive
input
10 6 6
PA5/TIM3_BKIN/
[TIM3_ETR](2)/
LCD_COM1(3)/ADC1_IN1/
COMP1_INP
I/O FT(5) XXXHSXXPort A5
Timer 3 - break input /
[Timer 3 - trigger] /
LCD_COM 1 /
ADC1 input 1/Comparator 1
positive input
11 7 7
PA6/ADC1_TRIG/
LCD_COM2(3)/ADC1_IN0/
COMP1_INP
I/O FT(5) XXXHSXXPort A6
ADC1 - trigger / LCD_COM2
/ ADC1 input 0/Comparator
1 positive input
DocID027180 Rev 5 31/133
STM8AL31E8x STM8AL3LE8x Pin description
61
12 8 8 PA7/LCD_SEG0(3)/
TIM5_CH1 I/O FT(5) XXXHSXXPort A7 LCD segment 0 / TIM5
channel 1
39 31 24
PB0(4)/TIM2_CH1/
LCD_SEG10(3)/
ADC1_IN18/
COMP1_INP
I/O FT(5) XXXHSXXPort B0
Timer 2 - channel 1 / LCD
segment 10 /
ADC1_IN18/Comparator 1
positive input
40 32 25
PB1/TIM3_CH1/
LCD_SEG11(3)/
ADC1_IN17/
COMP1_INP
I/O FT(5) XXXHSXXPort B1
Timer 3 - channel 1 / LCD
segment 11 /
ADC1_IN17/Comparator 1
positive input
41 33 26
PB2/ TIM2_CH2/
LCD_SEG12(3)/
ADC1_IN16/
COMP1_INP
I/O FT(5) XXXHSXXPort B2
Timer 2 - channel 2 / LCD
segment 12 /
ADC1_IN16/Comparator 1
positive input
42 34 27
PB3/TIM2_ETR/
LCD_SEG13(3)/
ADC1_IN15/COMP1_INP
I/O FT(5) XXXHSXXPort B3
Timer 2 - trigger / LCD
segment 13
/ADC1_IN15/Comparator 1
positive input
43 35 -
PB4(4)/SPI1_NSS/
LCD_SEG14(3)/
ADC1_IN14/COMP1_INP
I/O FT(5) XXXHSXXPort B4
SPI1 master/slave select /
LCD segment 14 /
ADC1_IN14/Comparator 1
positive input
--28
PB4(4)/SPI1_NSS/
LCD_SEG14(3)/
ADC1_IN14/DAC_OUT2/
COMP1_INP
I/O FT(5) XXXHSXXPort B4
SPI1 master/slave select /
LCD segment 14 /
ADC1_IN14 /
DAC channel 2
output/Comparator 1
positive input
44 36 -
PB5/SPI1_SCK/
LCD_SEG15(3)/
ADC1_IN13
COMP1_INP
I/O FT(5) XXXHSXXPort B5
SPI1 clock / LCD segment
15 /
ADC1_IN13/Comparator 1
positive input
--29
PB5/SPI1_SCK/
LCD_SEG15(3)/
ADC1_IN13/DAC_OUT2/
COMP1_INP
I/O FT(5) XXXHSXXPort B5
[SPI1 clock] / LCD segment
15 / ADC1_IN13 / DAC
channel 2
output/Comparator 1
positive input
Table 5. High-density STM8AL3xE8x pin description (continued)
Pin
number
Pin name
Type
I/O level
Input Output
Main function
(after reset)
Default alternate function
LQFP80
LQFP64
LQFP48
floating
wpu
Ext. interrupt
High sink/source
OD
PP
Pin description STM8AL31E8x STM8AL3LE8x
32/133 DocID027180 Rev 5
45 37 -
PB6/SPI1_MOSI/
LCD_SEG16(3)/
ADC1_IN12/COMP1_INP
I/O FT(5) XXXHSXXPort B6
SPI1 master out/slave in/
LCD segment 16 /
ADC1_IN12/Comparator 1
positive input
--30
PB6/SPI1_MOSI/
LCD_SEG16(3)/
ADC1_IN12/DAC_OUT2/
COMP1_INP
I/O FT(5) XXXHSXXPort B6
SPI1 master out/
slave in / LCD segment 16 /
ADC1_IN12 / DAC channel
2 output/Comparator 1
positive input
46 38 31
PB7/SPI1_MISO/
LCD_SEG17(3)/
ADC1_IN11/COMP1_INP
I/O FT(5) XXXHSXXPort B7
SPI1 master in- slave out/
LCD segment 17 /
ADC1_IN11/Comparator 1
positive input
65 53 37 PC0/I2C1_SDA I/O FT(5) XXT
(6) -Port C0 I2C1 data
66 54 38 PC1/I2C1_SCL I/O FT(5) XXT
(6) -Port C1 I2C1 clock
69 57 41
PC2/USART1_RX/
LCD_SEG22/ADC1_IN6/
COMP1_INP/VREFINT
I/O FT(5) XXXHSXXPort C2
USART1 receive /
LCD segment 22 /
ADC1_IN6/Comparator 1
positive input/Internal
reference voltage output
--42
PC3/USART1_TX/
LCD_SEG23(3)/
ADC1_IN5
I/O FT(5) XXXHSXXPort C3
USART1 transmit /
LCD segment 23 /
ADC1_IN5
70 58 -
PC3/USART1_TX/
LCD_SEG23(3)/
ADC1_IN5/COMP2_INM/
COMP1_INP
I/O FT(5) XXXHSXXPort C3
USART1 transmit /
LCD segment 23 /
ADC1_IN5 /
Comparator 2 negative input
/Comparator 1 input positive
71 59 43
PC4/USART1_CK/
I2C1_SMB/CCO/
LCD_SEG24(3)/
ADC1_IN4/COMP2_INM/
COMP1_INP
I/O FT(5) XXXHSXXPort C4
USART1 synchronous clock
/ I2C1_SMB / Configurable
clock output / LCD segment
24 / ADC1_IN4 /
Comparator 2 negative input
/ Comparator 1 positive
input
72 60 44
PC5/OSC32_IN
/[SPI1_NSS](2)/
[USART1_TX](2)
I/O FT(5) XXXHSXXPort C5
LSE oscillator input / [SPI1
master/slave select] /
[USART1 transmit]
Table 5. High-density STM8AL3xE8x pin description (continued)
Pin
number
Pin name
Type
I/O level
Input Output
Main function
(after reset)
Default alternate function
LQFP80
LQFP64
LQFP48
floating
wpu
Ext. interrupt
High sink/source
OD
PP
DocID027180 Rev 5 33/133
STM8AL31E8x STM8AL3LE8x Pin description
61
73 61 45
PC6/OSC32_OUT/
[SPI1_SCK](2)/
[USART1_RX](2)
I/O FT(5) XXXHSXXPort C6 LSE oscillator output / [SPI1
clock] / [USART1 receive]
74 62 -
PC7/LCD_SEG25(3)/
ADC1_IN3/COMP2_INM/
COMP1_INP
I/O FT(5) XXXHSXXPort C7
LCD segment 25
/ADC1_IN3/ Comparator
negative input / Comparator
1 positive input
--46
PC7/LCD_SEG25(3)/
ADC1_IN3/USART3_CK/
COMP2_INM/
COMP1_INP
I/O FT(5) XXXHSXXPort C7
LCD segment 25
/ADC1_IN3/ USART3
synchronous clock/
Comparator 2 negative input
/ Comparator 1 positive
input
29 25 20
PD0/TIM3_CH2/
[ADC1_TRIG](2)/
LCD_SEG7(3)/
ADC1_IN22/COMP2_INP
I/O FT(5) XXXHSXXPort D0
Timer 3 - channel 2 /
[ADC1_Trigger] / LCD
segment 7 / ADC1_IN22 /
Comparator 2 positive input
2
30 26 21
PD1/TIM3_ETR/
LCD_COM3(3)/
ADC1_IN21/COMP1_INP/
COMP2_INP
I/O FT(5) XXXHSXXPort D1
Timer 3 - trigger /
LCD_COM3 / ADC1_IN21 /
comparator 1 positive input/
comparator 2 positive input
31 27 22
PD2/TIM1_CH1
/LCD_SEG8(3)/
ADC1_IN20/COMP1_INP
I/O FT(5) XXXHSXXPort D2
Timer 1 - channel 1 / LCD
segment 8 /
ADC1_IN20/Comparator 1
positive input
32 28 23
PD3/ TIM1_ETR/
LCD_SEG9(3)/
ADC1_IN19/
COMP1_INP
I/O FT(5) XXXHSXXPort D3
Timer 1 - trigger / LCD
segment 9 /
ADC1_IN19/Comparator 1
positive input
57 45 -
PD4/TIM1_CH2
/LCD_SEG18(3)/
ADC1_IN10/
COMP1_INP
I/O FT(5) XXXHSXXPort D4
Timer 1 - channel 2 / LCD
segment 18 /
ADC1_IN10/Comparator 1
positive input
--33
PD4/TIM1_CH2
/LCD_SEG18(3)/
ADC1_IN10/SPI2_MISO/
COMP1_INP
I/O FT(5) XXXHSXXPort D4
Timer 1 - channel 2 / LCD
segment 18 /
ADC1_IN10/SPI2 master
in/slave out/Comparator 1
positive input
Table 5. High-density STM8AL3xE8x pin description (continued)
Pin
number
Pin name
Type
I/O level
Input Output
Main function
(after reset)
Default alternate function
LQFP80
LQFP64
LQFP48
floating
wpu
Ext. interrupt
High sink/source
OD
PP
Pin description STM8AL31E8x STM8AL3LE8x
34/133 DocID027180 Rev 5
58 46 -
PD5/TIM1_CH3
/LCD_SEG19(3)/
ADC1_IN9/
COMP1_INP
I/O FT(5) XXXHSXXPort D5
Timer 1 - channel 3 / LCD
segment 19 /
ADC1_IN9/Comparator 1
positive input
--34
PD5/TIM1_CH3
/LCD_SEG19(3)/
ADC1_IN9/SPI2_MOSI/
COMP1_INP
I/O FT(5) XXXHSXXPort D5
Timer 1 - channel 3 / LCD
segment 19 / ADC1_IN9/
SPI2 master out/slave
in/Comparator 1 positive
input
59 47
PD6/TIM1_BKIN
/LCD_SEG20(3)/
ADC1_IN8/RTC_CALIB/
COMP1_INP/VREFINT
I/O FT(5) XXXHSXXPort D6
Timer 1 - break input / LCD
segment 20 / ADC1_IN8 /
RTC calibration/Comparator
1 positive input/Internal
reference voltage output
--35
PD6/TIM1_BKIN
/LCD_SEG20(3)/
ADC1_IN8/RTC_CALIB/
SPI2_SCK/COMP1_INP/
VREFINT
I/O FT(5) XXXHSXXPort D6
Timer 1 - break input / LCD
segment 20 / ADC1_IN8 /
RTC calibration/SPI2
clock/Comparator 1 positive
input/Internal reference
voltage output
60 48 -
PD7/TIM1_CH1N
/LCD_SEG21(3)/
ADC1_IN7/RTC_ALARM/
COMP1_INP/VREFINT
I/O FT(5) XXXHSXXPort D7
Timer 1 - inverted channel 1/
LCD segment 21 /
ADC1_IN7 / RTC
alarm/Comparator 1 positive
input/Internal reference
voltage output
--36
PD7/TIM1_CH1N
/LCD_SEG21(3)/
ADC1_IN7/RTC_ALARM/
SPI2_NSS/COMP1_INP/V
REFINT
I/O FT(5) XXXHSXXPort D7
Timer 1 - inverted channel 1/
LCD segment 21 /
ADC1_IN7 / RTC alarm
/SPI2 master/slave
select/Comparator 1 positive
input/Internal reference
voltage output
61 49 - PG4/LCD_SEG32/
SPI2_NSS I/O FT(5) XXXHSXXPort G4 LCD segment 32 / SPI2
master/slave select
62 50 - PG5/LCD_SEG33/
SPI2_SCK I/O FT(5) XXXHSXXPort G5 LCD segment 33 / SPI2
clock
63 51 - PG6/LCD_SEG34/
SPI2_MOSI I/O FT(5) XXXHSXXPort G6 LCD segment 34 / SPI2
master out- slave in
Table 5. High-density STM8AL3xE8x pin description (continued)
Pin
number
Pin name
Type
I/O level
Input Output
Main function
(after reset)
Default alternate function
LQFP80
LQFP64
LQFP48
floating
wpu
Ext. interrupt
High sink/source
OD
PP
DocID027180 Rev 5 35/133
STM8AL31E8x STM8AL3LE8x Pin description
61
64 52 - PG7/LCD_SEG35/
SPI2_MISO I/O FT(5) XXXHSXXPort G7 LCD segment 35 / SPI2
master in- slave out
23 - - PE0/LCD_SEG1(3)/
TIM5_CH2 I/O FT(5) XXXHSXXPort E0 LCD segment 1 /Timer 5
channel 2
-1914
PE0/LCD_SEG1(3)/
TIM5_CH2/RTC_TAMP1 I/O FT(5) XXXHSXXPort E0 LCD segment 1 /Timer 5
channel 2 / RTC tamper 1
24 - - PE1/TIM1_CH2N
/LCD_SEG2(3) I/O FT(5) XXXHSXXPort E1 Timer 1 - inverted channel 2
/ LCD segment 2
-2015
PE1/TIM1_CH2N
/LCD_SEG2(3)/
RTC_TAMP2
I/O FT(5) XXXHSXXPort E1
Timer 1 - inverted channel 2
/ LCD segment 2 /
RTC tamper 2
25 - - PE2/TIM1_CH3N
/LCD_SEG3(3) I/O FT(5) XXXHSXXPort E2 Timer 1 - inverted channel 3
/ LCD segment 3
-2116
PE2/TIM1_CH3N
/LCD_SEG3(3)/
RTC_TAMP3
I/O FT(5) XXXHSXXPort E2
Timer 1 - inverted channel 3
/ LCD segment 3 /
RTC tamper 3
26 - - PE3/LCD_SEG4(3) I/O FT(5) XXXHSXXPort E3 LCD segment 4
-2217
PE3/LCD_SEG4(3)/
USART2_RX I/O FT(5) XXXHSXXPort E3 LCD segment 4/
USART2 receive
27 - - PE4/LCD_SEG5(3)/
DAC_TRIG1 I/O FT(5) XXXHSXXPort E4 LCD segment 5/
DAC 1 trigger
-2318
PE4/LCD_SEG5(3)/
DAC_TRIG2/USART2_TX I/O FT(5) XXXHSXXPort E4
LCD segment 5/
DAC 2 trigger/
USART2 transmit
28 - -
PE5/LCD_SEG6(3)/
ADC1_IN23/COMP1_INP/
COMP2_INP
I/O FT(5) XXXHSXXPort E5
LCD segment 6 /
ADC1_IN23/Comparator 1
positive input/Comparator 2
positive input
-2419
PE5/LCD_SEG6(3)/
ADC1_IN23/COMP1_INP/
COMP2_INP/
USART2_CK
I/O FT(5) XXXHSXXPort E5
LCD segment 6 /
ADC1_IN23/ Comparator 1
positive input/ Comparator 2
positive input/USART2
synchronous clock
--47
PE6/LCD_SEG26(3)/
PVD_IN/TIM5_BKIN/
USART3_TX
I/O FT(5) XXXHSXXPort E6
LCD segment 26 /PVD_IN
/TIM5 break input / USART3
transmit
Table 5. High-density STM8AL3xE8x pin description (continued)
Pin
number
Pin name
Type
I/O level
Input Output
Main function
(after reset)
Default alternate function
LQFP80
LQFP64
LQFP48
floating
wpu
Ext. interrupt
High sink/source
OD
PP
Pin description STM8AL31E8x STM8AL3LE8x
36/133 DocID027180 Rev 5
75 63 - PE6/LCD_SEG26(3)/
PVD_IN/TIM5_BKIN I/O FT(5) XXXHSXXPort E6 LCD segment 26 /PVD_IN
/TIM5 break input
76 64 - PE7/LED_SEG27/
TIM5_ETR I/O FT(5) XXXHSXXPort E7 LCD segment 27/
TIM5 trigger
--48
PE7/LED_SEG27/
TIM5_ETR/
USART3_RX
I/O FT(5) XXXHSXXPort E7 LCD segment 27/TIM5 trig-
ger/USART3 receive
77 - - PI0/RTC_TAMP1/
[SPI2_NSS]/[TIM3_CH1 I/O FT(5) XXXHSXXPort I0
RTC tamper 1 output
[SPI2 master/slave select]
[TIM3 channel 1]
78 - - PI1/RTC_TAMP2/
[SPI2_SCK] I/O FT(5) XXXHSXXPort I1 RTC tamper 2 output
[SPI2 clock]
79 - - PI2/RTC_TAMP3/
[SPI2_MOSI] I/O FT(5) XXXHSXXPort I2 RTC tamper 3 output
[SPI2 master out- slave in]
80 - - PI3/TIM5_CH1/
[SPI2_MISO]/[TIM3_CH2] I/O FT(5) XXXHSXXPort I3
TIM5 Channel 1
[SPI2 master in- slave out]
[TIM3 channel 2]
--32
PF0/ADC1_IN24/
DAC_OUT1 I/O - XXXHSXXPort F0 ADC1_IN24 / DAC 1 output
-39-
PF0/ADC1_IN24/
DAC_OUT1
[USART3_TX]
I/O - XXXHSXXPort F0
ADC1_IN24 /
DAC 1 output/
[USART3 transmit]
49 - -
PF0/ADC1_IN24/
DAC_OUT1/
[USART3_TX]/[SPI1_MIS
O]
I/O - XXXHSXXPort F0
ADC1_IN24 / DAC 1 output/
[USART3 transmit]
[SPI1 master in- slave out]
50 - -
PF1/ADC1_IN25/
DAC_OUT2/
[USART3_RX]/
[SPI1_MOSI]
I/O - XXXHSXXPort F1
ADC1_IN25/
DAC channel 2 output/
[USART3 receive]
[SPI1 master out- slave in]
-40-
PF1/ADC1_IN25/
DAC_OUT2/
[USART3_RX]
I/O - XXXHSXXPort F1
ADC1_IN25/
DAC channel 2 output/
[USART3 receive]
51 - -
PF2/ADC1_IN26/
[SPI1_SCK]/
[USART3_SCK]
I/O - XXXHSXXPort F2
ADC1_IN26
[SPI1 clock]
[USART3 clock]
52 - - PF3/ADC1_IN27/
[SPI1_NSS] I/O - XXXHSXXPort F3 ADC1_IN26
[SPI1 master/slave select]
Table 5. High-density STM8AL3xE8x pin description (continued)
Pin
number
Pin name
Type
I/O level
Input Output
Main function
(after reset)
Default alternate function
LQFP80
LQFP64
LQFP48
floating
wpu
Ext. interrupt
High sink/source
OD
PP
DocID027180 Rev 5 37/133
STM8AL31E8x STM8AL3LE8x Pin description
61
53 41 - PF4/LCD_COM4 I/O FT(5) XXXHSXXPort F4 LCD COM4
54 42 - PF5/LCD_COM5 I/O FT(5) XXXHSXXPort F5 LCD COM5
55 43 - PF6/LCD_COM6 I/O FT(5) XXXHSXXPort F6 LCD COM6
56 44 - PF7/LCD_COM7 I/O FT(5) XXXHSXXPort F7 LCD COM7
22 18 13 VLCD(7) S- ------LCD booster external capacitor
15 11 10 VDD1 S- -- - - - - Digital power supply
14 10 - VSS1 ---- - - - - I/O ground
16 12 11 VDDA S- -- - - - - Analog supply voltage
17 13 12 VREF+/VREF+_DAC S- ------
ADC1 and DAC1/2 positive voltage
reference
18 14 -
PG0/LCD SEG
28(3)/USART3_RX/
[TIM2_BKIN]
I/O FT(5) XXXHSXXPort G0
LCD segment 28/
USART3 receive /
[Timer 2 - break input]
19 15 -
PG1/LCD SEG
29(3)/USART3_TX/
[TIM3_BKIN]
I/O FT(5) XXXHSXXPort G1
LCD segment 29/
USART3 transmit /
[Timer 3 -break input]
20 16 - PG2/LCD_SEG 30(3)/
USART3_CK I/O FT(5) XXXHSXXPort G2
LCD segment 30/
USART 3 synchronous
clock
21 17 - PG3/LCD SEG 31 (3)/
[TIM3_ETR] I/O FT(5) XXXHSXXPort G3 LCD segment 31/
[Timer 3 - trigger]
33 - - PH4/USART2_RX I/O FT(5) XXXHSXXPort H4 USART2 receive
34 - - PH5/USART2_TX I/O FT(5) XXXHSXXPort H5 USART2 transmit
35 - - PH6/USART2_CK/
TIM5_CH1 I/O FT(5) XXXHSXXPort H6 USART2 synchronous
clock/ Timer 5 - channel 1
36 - - PH7/TIM5_CH2 I/O FT(5) XXXHSXXPort H7 Timer 5 - channel 2
--9V
SS/VSSA/VREF- S- ------
I/O ground / Analog ground voltage /
ADC1 negative voltage reference
13 9 - VSSA/VREF- S- ------
Analog ground voltage /
ADC1 negative voltage reference
37 29 - VDD3 S - - - - - - - IOs supply voltage
38 30 - VSS3 S - - - - - - - IOs ground voltage
Table 5. High-density STM8AL3xE8x pin description (continued)
Pin
number
Pin name
Type
I/O level
Input Output
Main function
(after reset)
Default alternate function
LQFP80
LQFP64
LQFP48
floating
wpu
Ext. interrupt
High sink/source
OD
PP
Pin description STM8AL31E8x STM8AL3LE8x
38/133 DocID027180 Rev 5
Note: The slope control of all GPIO pins, except true open drain pins, are programmable. By
default the slope control is limited to 2 MHz.
System configuration options
As shown in Table 5: High-density STM8AL3xE8x pin description, some alternate functions
can be remapped on different I/O ports by programming one of the two remapping registers
described in the “Routing interface (RI) and system configuration controller” section in
STM8L051/L052 Value Line, STM8L151/L152, STM8L162, STM8AL31, STM8AL3L MCU
lines reference manual (RM0031).
511
PA0(8)/[USART1_CK](2)/
SWIM/BEEP/IR_TIM (9) I/O - X XXHSX XPort A0
[USART1 synchronous
clock](2) / SWIM input and
output /
Beep output / Infrared Timer
output
68 56 40 VSS2 S- -- - - - - IOs ground voltage
67 55 39 VDD2 S- -- - - - - IOs supply voltage
48 - - VSS4 S- -- - - - - IOs ground voltage
47 - - VDD4 S- -- - - - - IOs supply voltage
1. At power-up, the PA1/NRST pin is a reset input pin with pull-up. To be used as a general purpose pin (PA1), it can be
configured only as output open-drain or push-pull, not as a general purpose input. Refer to Section Configuring NRST/PA1
pin as general purpose output in STM8L051/L052 Value Line, STM8L151/L152, STM8L162, STM8AL31, STM8AL3L MCU
lines reference manual (RM0031).
2. [ ] Alternate function remapping option (if the same alternate function is shown twice, it indicates an exclusive choice not a
duplication of the function).
3. Available onSTM8AL3LE8xdevices only.
4. A pull-up is applied to PB0 and PB4 during the reset phase. These two pins are input floating after reset release.
5. In the 5 V tolerant I/Os, the protection diode to VDD is not implemented.
6. In the open-drain output column, ‘T’ defines a true open-drain I/O (P-buffer, weak pull-up and protection diode to VDD are
not implemented).
7. Available on STM8AL3LE8x devices only. On STM8AL31E8x devices it is reserved and must be tied to VDD.
8. The PA0 pin is in input pull-up during the reset phase and after reset release.
9. High Sink LED driver capability available on PA0.
Table 5. High-density STM8AL3xE8x pin description (continued)
Pin
number
Pin name
Type
I/O level
Input Output
Main function
(after reset)
Default alternate function
LQFP80
LQFP64
LQFP48
floating
wpu
Ext. interrupt
High sink/source
OD
PP
DocID027180 Rev 5 39/133
STM8AL31E8x STM8AL3LE8x Memory and register map
61
5 Memory and register map
5.1 Memory mapping
The memory map is shown in Figure 9.
Figure 9. Memory map
1. Refer to Table 9 for an overview of hardware register mapping, to Table 8 for details on I/O port hardware
registers, and to Table 10 for information on CPU/SWIM/debug module controller registers.
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40/133 DocID027180 Rev 5
5.2 Register map
Table 6. Flash and RAM boundary addresses
Memory area Size Start address End address
RAM 4 Kbyte 0x00 0000 0x00 0FFF
Flash program memory 64 Kbyte 0x00 8000 0x01 7FFF
Table 7. Factory conversion registers
Address Block Register label Register name Reset
status
0x00 4910 - VREFINT_Factory_CONV(1) Internal reference voltage factory
conversion 0xXX
0x00 4911 - TS_Factory_CONV_V125(2) Temperature sensor output voltage 0xXX
1. The VREFINT_Factory_CONV byte represents the 8 LSB of the result of the VREFINT 12-bit ADC conversion performed in
factory. The 2 MSB have a fixed value: 0x6.
2. The TS_Factory_CONV_V125 byte represents the 8 LSB of the result of the V125 12-bit ADC conversion performed in
factory. The 2 MSB have a fixed value: 0x3.
Table 8. I/O port hardware register map
Address Block Register label Register name Reset
status
0x00 5000
Port A
PA_ODR Port A data output latch register 0x00
0x00 5001 PA_IDR Port A input pin value register 0xXX
0x00 5002 PA_DDR Port A data direction register 0x00
0x00 5003 PA_CR1 Port A control register 1 0x01
0x00 5004 PA_CR2 Port A control register 2 0x00
0x00 5005
Port B
PB_ODR Port B data output latch register 0x00
0x00 5006 PB_IDR Port B input pin value register 0xXX
0x00 5007 PB_DDR Port B data direction register 0x00
0x00 5008 PB_CR1 Port B control register 1 0x00
0x00 5009 PB_CR2 Port B control register 2 0x00
0x00 500A
Port C
PC_ODR Port C data output latch register 0x00
0x00 500B PB_IDR Port C input pin value register 0xXX
0x00 500C PC_DDR Port C data direction register 0x00
0x00 500D PC_CR1 Port C control register 1 0x00
0x00 500E PC_CR2 Port C control register 2 0x00
DocID027180 Rev 5 41/133
STM8AL31E8x STM8AL3LE8x Memory and register map
61
0x00 500F
Port D
PD_ODR Port D data output latch register 0x00
0x00 5010 PD_IDR Port D input pin value register 0xXX
0x00 5011 PD_DDR Port D data direction register 0x00
0x00 5012 PD_CR1 Port D control register 1 0x00
0x00 5013 PD_CR2 Port D control register 2 0x00
0x00 5014
Port E
PE_ODR Port E data output latch register 0x00
0x00 5015 PE_IDR Port E input pin value register 0xXX
0x00 5016 PE_DDR Port E data direction register 0x00
0x00 5017 PE_CR1 Port E control register 1 0x00
0x00 5018 PE_CR2 Port E control register 2 0x00
0x00 5019
Port F
PF_ODR Port F data output latch register 0x00
0x00 501A PF_IDR Port F input pin value register 0xXX
0x00 501B PF_DDR Port F data direction register 0x00
0x00 501C PF_CR1 Port F control register 1 0x00
0x00 501D PF_CR2 Port F control register 2 0x00
0x00 501E
Port G
PG_ODR Port F data output latch register 0x00
0x00 501F PG_IDR Port G input pin value register 0xXX
0x00 5020 PG_DDR Port G data direction register 0x00
0x00 5021 PG_CR1 Port G control register 1 0x00
0x00 5022 PG_CR2 Port G control register 2 0x00
0x00 5023
Port H
PH_ODR Port H data output latch register 0x00
0x00 5024 PH_IDR Port H input pin value register 0xXX
0x00 5025 PH_DDR Port H data direction register 0x00
0x00 5026 PH_CR1 Port H control register 1 0x00
0x00 5027 PH_CR2 Port H control register 2 0x00
0x00 5028
Port I
PI_ODR Port I data output latch register 0x00
0x00 5029 PI_IDR Port I input pin value register 0xXX
0x00 502A PI_DDR Port I data direction register 0x00
0x00 502B PI_CR1 Port I control register 1 0x00
0x00 502C PI_CR2 Port I control register 2 0x00
Table 8. I/O port hardware register map (continued)
Address Block Register label Register name Reset
status
Memory and register map STM8AL31E8x STM8AL3LE8x
42/133 DocID027180 Rev 5
Table 9. General hardware register map
Address Block Register label Register name Reset status
0x00 502E
to
0x00 5049
Reserved area (44 byte)
0x00 5050
Flash
FLASH_CR1 Flash control register 1 0x00
0x00 5051 FLASH_CR2 Flash control register 2 0x00
0x00 5052 FLASH _PUKR Flash program memory unprotection key
register 0x00
0x00 5053 FLASH _DUKR Data EEPROM unprotection key register 0x00
0x00 5054 FLASH _IAPSR Flash in-application programming status
register 0x00
0x00 5055
to
0x00 506F
Reserved area (27 byte)
0x00 5070
DMA1
DMA1_GCSR DMA1 global configuration & status
register 0xFC
0x00 5071 DMA1_GIR1 DMA1 global interrupt register 1 0x00
0x00 5072 to
0x00 5074 Reserved area (3 byte)
0x00 5075
DMA1
DMA1_C0CR DMA1 channel 0 configuration register 0x00
0x00 5076 DMA1_C0SPR DMA1 channel 0 status & priority register 0x00
0x00 5077 DMA1_C0NDTR DMA1 number of data to transfer register
(channel 0) 0x00
0x00 5078 DMA1_C0PARH DMA1 peripheral address high register
(channel 0) 0x52
0x00 5079 DMA1_C0PARL DMA1 peripheral address low register
(channel 0) 0x00
0x00 507A Reserved area (1 byte)
0x00 507B DMA1_C0M0ARH DMA1 memory 0 address high register
(channel 0) 0x00
0x00 507C DMA1_C0M0ARL DMA1 memory 0 address low register
(channel 0) 0x00
0x00 507D to
0x00 507E Reserved area (2 byte)
0x00 507F
DMA1
DMA1_C1CR DMA1 channel 1 configuration register 0x00
0x00 5080 DMA1_C1SPR DMA1 channel 1 status & priority register 0x00
0x00 5081 DMA1_C1NDTR DMA1 number of data to transfer register
(channel 1) 0x00
0x00 5082 DMA1_C1PARH DMA1 peripheral address high register
(channel 1) 0x52
0x00 5083 DMA1_C1PARL DMA1 peripheral address low register
(channel 1) 0x00
DocID027180 Rev 5 43/133
STM8AL31E8x STM8AL3LE8x Memory and register map
61
0x00 5084 Reserved area (1 byte)
0x00 5085
DMA1
DMA1_C1M0ARH DMA1 memory 0 address high register
(channel 1) 0x00
0x00 5086 DMA1_C1M0ARL DMA1 memory 0 address low register
(channel 1) 0x00
0x00 5087
0x00 5088 Reserved area (2 byte)
0x00 5089
DMA1
DMA1_C2CR DMA1 channel 2 configuration register 0x00
0x00 508A DMA1_C2SPR DMA1 channel 2 status & priority register 0x00
0x00 508B DMA1_C2NDTR DMA1 number of data to transfer register
(channel 2) 0x00
0x00 508C DMA1_C2PARH DMA1 peripheral address high register
(channel 2) 0x52
0x00 508D DMA1_C2PARL DMA1 peripheral address low register
(channel 2) 0x00
0x00 508E Reserved area (1 byte)
0x00 508F DMA1_C2M0ARH DMA1 memory 0 address high register
(channel 2) 0x00
0x00 5090 DMA1_C2M0ARL DMA1 memory 0 address low register
(channel 2) 0x00
0x00 5091
0x00 5092 Reserved area (2 byte)
0x00 5093
DMA1
DMA1_C3CR DMA1 channel 3 configuration register 0x00
0x00 5094 DMA1_C3SPR DMA1 channel 3 status & priority register 0x00
0x00 5095 DMA1_C3NDTR DMA1 number of data to transfer register
(channel 3) 0x00
0x00 5096 DMA1_C3PARH_
C3M1ARH
DMA1 peripheral address high register
(channel 3) 0x40
0x00 5097 DMA1_C3PARL_
C3M1ARL
DMA1 peripheral address low register
(channel 3) 0x00
0x00 5098 DMA_C3M0EAR DMA channel 3 memory 0 extended
address register 0x00
0x00 5099 DMA1_C3M0ARH DMA1 memory 0 address high register
(channel 3) 0x00
0x00 509A DMA1_C3M0ARL DMA1 memory 0 address low register
(channel 3) 0x00
0x00 509B to
0x00 509C Reserved area (3 byte)
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status
Memory and register map STM8AL31E8x STM8AL3LE8x
44/133 DocID027180 Rev 5
0x00 509D
SYSCFG
SYSCFG_RMPCR3 Remapping register 3 0x00
0x00 509E SYSCFG_RMPCR1 Remapping register 1 0x00
0x00 509F SYSCFG_RMPCR2 Remapping register 2 0x00
0x00 50A0
ITC - EXTI
EXTI_CR1 External interrupt control register 1 0x00
0x00 50A1 EXTI_CR2 External interrupt control register 2 0x00
0x00 50A2 EXTI_CR3 External interrupt control register 3 0x00
0x00 50A3 EXTI_SR1 External interrupt status register 1 0x00
0x00 50A4 EXTI_SR2 External interrupt status register 2 0x00
0x00 50A5 EXTI_CONF1 External interrupt port select register 1 0x00
0x00 50A6
WFE
WFE_CR1 WFE control register 1 0x00
0x00 50A7 WFE_CR2 WFE control register 2 0x00
0x00 50A8 WFE_CR3 WFE control register 3 0x00
0x00 50A9 WFE_CR4 WFE control register 4 0x00
0x00 50AA
ITC - EXTI
EXTI_CR4 External interrupt control register 4 0x00
0x00 50AB EXTI_CONF2 External interrupt port select register 2 0x00
0x00 50A9
to
0x00 50AF
Reserved area (7 byte)
0x00 50B0
RST
RST_CR Reset control register 0x00
0x00 50B1 RST_SR Reset status register 0x01
0x00 50B2
PWR
PWR_CSR1 Power control and status register 1 0x00
0x00 50B3 PWR_CSR2 Power control and status register 2 0x00
0x00 50B4
to
0x00 50BF
Reserved area (12 byte)
0x00 50C0
CLK
CLK_CKDIVR Clock master divider register 0x03
0x00 50C1 CLK_CRTCR Clock RTC register 0x00(1)
0x00 50C2 CLK_ICKCR Internal clock control register 0x11
0x00 50C3 CLK_PCKENR1 Peripheral clock gating register 1 0x00
0x00 50C4 CLK_PCKENR2 Peripheral clock gating register 2 0x00
0x00 50C5 CLK_CCOR Configurable clock control register 0x00
0x00 50C6 CLK_ECKCR External clock control register 0x00
0x00 50C7 CLK_SCSR System clock status register 0x01
0x00 50C8 CLK_SWR System clock switch register 0x01
0x00 50C9 CLK_SWCR Clock switch control register 0xX0
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status
DocID027180 Rev 5 45/133
STM8AL31E8x STM8AL3LE8x Memory and register map
61
0x00 50CA
CLK
CLK_CSSR Clock security system register 0x00
0x00 50CB CLK_CBEEPR Clock BEEP register 0x00
0x00 50CC CLK_HSICALR HSI calibration register 0xXX
0x00 50CD CLK_HSITRIMR HSI clock calibration trimming register 0x00
0x00 50CE CLK_HSIUNLCKR HSI unlock register 0x00
0x00 50CF CLK_REGCSR Main regulator control status register 0bxx11 100X
0x00 50D0 CLK_PCKENR3 Peripheral clock gating register 3 0x00
0x00 50D1
to
0x00 50D2
Reserved area (2 byte)
0x00 50D3
WWDG
WWDG_CR WWDG control register 0x7F
0x00 50D4 WWDG_WR WWDR window register 0x7F
0x00 50D5
to
00 50DF
Reserved area (11 byte)
0x00 50E0
IWDG
IWDG_KR IWDG key register 0xXX
0x00 50E1 IWDG_PR IWDG prescaler register 0x00
0x00 50E2 IWDG_RLR IWDG reload register 0xFF
0x00 50E3
to
0x00 50EF
Reserved area (13 byte)
0x00 50F0
BEEP
BEEP_CSR1 BEEP control/status register 1 0x00
0x00 50F1
0x00 50F2 Reserved area (2 byte)
0x00 50F3 BEEP_CSR2 BEEP control/status register 2 0x1F
0x00 50F4
to0x00 513F Reserved area (76 byte)
0x00 5140
RTC
RTC_TR1 Time register 1 0x00
0x00 5141 RTC_TR2 Time register 2 0x00
0x00 5142 RTC_TR3 Time register 3 0x00
0x00 5143 Reserved area (1 byte)
0x00 5144
RTC
RTC_DR1 Date register 1 0x01
0x00 5145 RTC_DR2 Date register 2 0x21
0x00 5146 RTC_DR3 Date register 3 0x00
0x00 5147 Reserved area (1 byte)
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status
Memory and register map STM8AL31E8x STM8AL3LE8x
46/133 DocID027180 Rev 5
0x00 5148
RTC
RTC_CR1 Control register 1 0x00(1)
0x00 5149 RTC_CR2 Control register 2 0x00(1)
0x00 514A RTC_CR3 Control register 3 0x00(1)
0x00 514B Reserved area (1 byte)
0x00 514C RTC_ISR1 Initialization and status register 1 0x01
0x00 514D RTC_ISR2 Initialization and Status register 2 0x00
0x00 514E
0x00 514F Reserved area (2 byte)
0x00 5150
RTC
RTC_SPRERH Synchronous prescaler register high 0x00(1)
0x00 5151 RTC_SPRERL Synchronous prescaler register low 0xFF(1)
0x00 5152 RTC_APRER Asynchronous prescaler register 0x7F(1)
0x00 5153 Reserved area (1 byte)
0x00 5154
RTC
RTC_WUTRH Wakeup timer register high 0xFF(1)
0x00 5155 RTC_WUTRL Wakeup timer register low 0xFF(1)
0x00 5156 Reserved area (1 byte)
0x00 5157
RTC
RTC_SSRL Subsecond register low 0x00
0x00 5158 RTC_SSRH Subsecond register high 0x00
0x00 5159 RTC_WPR Write protection register 0x00
0x00 5158 RTC_SSRH Subsecond register high 0x00
0x00 5159 RTC_WPR Write protection register 0x00
0x00 515A RTC_SHIFTRH Shift register high 0x00
0x00 515B RTC_SHIFTRL Shift register low 0x00
0x00 515C RTC_ALRMAR1 Alarm A register 1 0x00(1)
0x00 515D RTC_ALRMAR2 Alarm A register 2 0x00(1)
0x00 515E RTC_ALRMAR3 Alarm A register 3 0x00(1)
0x00 515F RTC_ALRMAR4 Alarm A register 4 0x00(1)
0x00 5160 to
0x00 5163 Reserved area (4 byte)
0x00 5164
RTC
RTC_ALRMASSRH Alarm A subsecond register high 0x00(1)
0x00 5165 RTC_ALRMASSRL Alarm A subsecond register low 0x00(1)
0x00 5166 RTC_ALRMASSMS
KR Alarm A masking register 0x00(1)
0x00 5167 to
0x00 5169 Reserved area (3 byte)
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status
DocID027180 Rev 5 47/133
STM8AL31E8x STM8AL3LE8x Memory and register map
61
0x00 516A
RTC
RTC_CALRH Calibration register high 0x00(1)
0x00 516B RTC_CALRL Calibration register low 0x00(1)
0x00 516C RTC_TCR1 Tamper control register 1 0x00(1)
0x00 516D RTC_TCR2 Tamper control register 2 0x00(1)
0x00 516E to
0x00 518A Reserved area
0x00 5190 CSSLSE CSSLSE_CSR CSS on LSE control and status register 0x00(1)
0x00 519A to
0x00 51FF Reserved area
0x00 5200
SPI1
SPI1_CR1 SPI1 control register 1 0x00
0x00 5201 SPI1_CR2 SPI1 control register 2 0x00
0x00 5202 SPI1_ICR SPI1 interrupt control register 0x00
0x00 5203 SPI1_SR SPI1 status register 0x02
0x00 5204 SPI1_DR SPI1 data register 0x00
0x00 5205 SPI1_CRCPR SPI1 CRC polynomial register 0x07
0x00 5206 SPI1_RXCRCR SPI1 Rx CRC register 0x00
0x00 5207 SPI1_TXCRCR SPI1 Tx CRC register 0x00
0x00 5208
to
0x00 520F
Reserved area (8 byte)
0x00 5210
I2C1
I2C1_CR1 I2C1 control register 1 0x00
0x00 5211 I2C1_CR2 I2C1 control register 2 0x00
0x00 5212 I2C1_FREQR I2C1 frequency register 0x00
0x00 5213 I2C1_OARL I2C1 own address register low 0x00
0x00 5214 I2C1_OARH I2C1 own address register high 0x00
0x00 5215 I2C1_OARH I2C1 own address register for dual mode 0x00
0x00 5216 I2C1_DR I2C1 data register 0x00
0x00 5217 I2C1_SR1 I2C1 status register 1 0x00
0x00 5218 I2C1_SR2 I2C1 status register 2 0x00
0x00 5219 I2C1_SR3 I2C1 status register 3 0x0X
0x00 521A I2C1_ITR I2C1 interrupt control register 0x00
0x00 521B I2C1_CCRL I2C1 clock control register low 0x00
0x00 521C I2C1_CCRH I2C1 clock control register high 0x00
0x00 521D I2C1_TRISER I2C1 TRISE register 0x02
0x00 521E I2C1_PECR I2C1 packet error checking register 0x00
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status
Memory and register map STM8AL31E8x STM8AL3LE8x
48/133 DocID027180 Rev 5
0x00 521F
to
0x00 522F
Reserved area (17 byte)
0x00 5230
USART1
USART1_SR USART1 status register 0xC0
0x00 5231 USART1_DR USART1 data register 0xXX
0x00 5232 USART1_BRR1 USART1 baud rate register 1 0x00
0x00 5233 USART1_BRR2 USART1 baud rate register 2 0x00
0x00 5234 USART1_CR1 USART1 control register 1 0x00
0x00 5235 USART1_CR2 USART1 control register 2 0x00
0x00 5236 USART1_CR3 USART1 control register 3 0x00
0x00 5237 USART1_CR4 USART1 control register 4 0x00
0x00 5238 USART1_CR5 USART1 control register 5 0x00
0x00 5239 USART1_GTR USART1 guard time register 0x00
0x00 523A USART1_PSCR USART1 prescaler register 0x00
0x00 523B
to
0x00 524F
Reserved area (21 byte)
0x00 5250
TIM2
TIM2_CR1 TIM2 control register 1 0x00
0x00 5251 TIM2_CR2 TIM2 control register 2 0x00
0x00 5252 TIM2_SMCR TIM2 Slave mode control register 0x00
0x00 5253 TIM2_ETR TIM2 external trigger register 0x00
0x00 5254 TIM2_DER TIM2 DMA1 request enable register 0x00
0x00 5255 TIM2_IER TIM2 interrupt enable register 0x00
0x00 5256 TIM2_SR1 TIM2 status register 1 0x00
0x00 5257 TIM2_SR2 TIM2 status register 2 0x00
0x00 5258 TIM2_EGR TIM2 event generation register 0x00
0x00 5259 TIM2_CCMR1 TIM2 capture/compare mode register 1 0x00
0x00 525A TIM2_CCMR2 TIM2 capture/compare mode register 2 0x00
0x00 525B TIM2_CCER1 TIM2 capture/compare enable register 1 0x00
0x00 525C TIM2_CNTRH TIM2 counter high 0x00
0x00 525D TIM2_CNTRL TIM2 counter low 0x00
0x00 525E TIM2_PSCR TIM2 prescaler register 0x00
0x00 525F TIM2_ARRH TIM2 auto-reload register high 0xFF
0x00 5260 TIM2_ARRL TIM2 auto-reload register low 0xFF
0x00 5261 TIM2_CCR1H TIM2 capture/compare register 1 high 0x00
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status
DocID027180 Rev 5 49/133
STM8AL31E8x STM8AL3LE8x Memory and register map
61
0x00 5262
TIM2
TIM2_CCR1L TIM2 capture/compare register 1 low 0x00
0x00 5263 TIM2_CCR2H TIM2 capture/compare register 2 high 0x00
0x00 5264 TIM2_CCR2L TIM2 capture/compare register 2 low 0x00
0x00 5265 TIM2_BKR TIM2 break register 0x00
0x00 5266 TIM2_OISR TIM2 output idle state register 0x00
0x00 5267 to
0x00 527F Reserved area (25 byte)
0x00 5280
TIM3
TIM3_CR1 TIM3 control register 1 0x00
0x00 5281 TIM3_CR2 TIM3 control register 2 0x00
0x00 5282 TIM3_SMCR TIM3 Slave mode control register 0x00
0x00 5283 TIM3_ETR TIM3 external trigger register 0x00
0x00 5284 TIM3_DER TIM3 DMA1 request enable register 0x00
0x00 5285 TIM3_IER TIM3 interrupt enable register 0x00
0x00 5286 TIM3_SR1 TIM3 status register 1 0x00
0x00 5287 TIM3_SR2 TIM3 status register 2 0x00
0x00 5288 TIM3_EGR TIM3 event generation register 0x00
0x00 5289 TIM3_CCMR1 TIM3 Capture/Compare mode register 1 0x00
0x00 528A TIM3_CCMR2 TIM3 Capture/Compare mode register 2 0x00
0x00 528B TIM3_CCER1 TIM3 Capture/Compare enable register 1 0x00
0x00 528C TIM3_CNTRH TIM3 counter high 0x00
0x00 528D TIM3_CNTRL TIM3 counter low 0x00
0x00 528E TIM3_PSCR TIM3 prescaler register 0x00
0x00 528F TIM3_ARRH TIM3 Auto-reload register high 0xFF
0x00 5290 TIM3_ARRL TIM3 Auto-reload register low 0xFF
0x00 5291 TIM3_CCR1H TIM3 Capture/Compare register 1 high 0x00
0x00 5292 TIM3_CCR1L TIM3 Capture/Compare register 1 low 0x00
0x00 5293 TIM3_CCR2H TIM3 Capture/Compare register 2 high 0x00
0x00 5294 TIM3_CCR2L TIM3 Capture/Compare register 2 low 0x00
0x00 5295 TIM3_BKR TIM3 break register 0x00
0x00 5296 TIM3_OISR TIM3 output idle state register 0x00
0x00 5297 to
0x00 52AF Reserved area (25 byte)
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status
Memory and register map STM8AL31E8x STM8AL3LE8x
50/133 DocID027180 Rev 5
0x00 52B0
TIM1
TIM1_CR1 TIM1 control register 1 0x00
0x00 52B1 TIM1_CR2 TIM1 control register 2 0x00
0x00 52B2 TIM1_SMCR TIM1 Slave mode control register 0x00
0x00 52B3 TIM1_ETR TIM1 external trigger register 0x00
0x00 52B4 TIM1_DER TIM1 DMA1 request enable register 0x00
0x00 52B5 TIM1_IER TIM1 Interrupt enable register 0x00
0x00 52B6 TIM1_SR1 TIM1 status register 1 0x00
0x00 52B7 TIM1_SR2 TIM1 status register 2 0x00
0x00 52B8 TIM1_EGR TIM1 event generation register 0x00
0x00 52B9 TIM1_CCMR1 TIM1 Capture/Compare mode register 1 0x00
0x00 52BA TIM1_CCMR2 TIM1 Capture/Compare mode register 2 0x00
0x00 52BB TIM1_CCMR3 TIM1 Capture/Compare mode register 3 0x00
0x00 52BC TIM1_CCMR4 TIM1 Capture/Compare mode register 4 0x00
0x00 52BD TIM1_CCER1 TIM1 Capture/Compare enable register 1 0x00
0x00 52BE TIM1_CCER2 TIM1 Capture/Compare enable register 2 0x00
0x00 52BF TIM1_CNTRH TIM1 counter high 0x00
0x00 52C0 TIM1_CNTRL TIM1 counter low 0x00
0x00 52C1 TIM1_PSCRH TIM1 prescaler register high 0x00
0x00 52C2 TIM1_PSCRL TIM1 prescaler register low 0x00
0x00 52C3 TIM1_ARRH TIM1 Auto-reload register high 0xFF
0x00 52C4 TIM1_ARRL TIM1 Auto-reload register low 0xFF
0x00 52C5 TIM1_RCR TIM1 Repetition counter register 0x00
0x00 52C6 TIM1_CCR1H TIM1 Capture/Compare register 1 high 0x00
0x00 52C7 TIM1_CCR1L TIM1 Capture/Compare register 1 low 0x00
0x00 52C8 TIM1_CCR2H TIM1 Capture/Compare register 2 high 0x00
0x00 52C9 TIM1_CCR2L TIM1 Capture/Compare register 2 low 0x00
0x00 52CA TIM1_CCR3H TIM1 Capture/Compare register 3 high 0x00
0x00 52CB TIM1_CCR3L TIM1 Capture/Compare register 3 low 0x00
0x00 52CC TIM1_CCR4H TIM1 Capture/Compare register 4 high 0x00
0x00 52CD TIM1_CCR4L TIM1 Capture/Compare register 4 low 0x00
0x00 52CE TIM1_BKR TIM1 break register 0x00
0x00 52CF TIM1_DTR TIM1 dead-time register 0x00
0x00 52D0 TIM1_OISR TIM1 output idle state register 0x00
0x00 52D1 TIM1_DCR1 DMA1 control register 1 0x00
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status
DocID027180 Rev 5 51/133
STM8AL31E8x STM8AL3LE8x Memory and register map
61
0x00 52D2
TIM1
TIM1_DCR2 TIM1 DMA1 control register 2 0x00
0x00 52D3 TIM1_DMA1R TIM1 DMA1 address for burst mode 0x00
0x00 52D4
to
0x00 52DF
Reserved area (12 byte)
0x00 52E0
TIM4
TIM4_CR1 TIM4 control register 1 0x00
0x00 52E1 TIM4_CR2 TIM4 control register 2 0x00
0x00 52E2 TIM4_SMCR TIM4 Slave mode control register 0x00
0x00 52E3 TIM4_DER TIM4 DMA1 request enable register 0x00
0x00 52E4 TIM4_IER TIM4 Interrupt enable register 0x00
0x00 52E5 TIM4_SR1 TIM4 status register 1 0x00
0x00 52E6 TIM4_EGR TIM4 Event generation register 0x00
0x00 52E7 TIM4_CNTR TIM4 counter 0x00
0x00 52E8 TIM4_PSCR TIM4 prescaler register 0x00
0x00 52E9 TIM4_ARR TIM4 Auto-reload register 0x00
0x00 52EA
to
0x00 52FE
Reserved area (21 byte)
0x00 52FF IRTIM IR_CR Infrared control register 0x00
0x00 5300
TIM5
TIM5_CR1 TIM5 control register 1 0x00
0x00 5301 TIM5_CR2 TIM5 control register 2 0x00
0x00 5302 TIM5_SMCR TIM5 Slave mode control register 0x00
0x00 5303 TIM5_ETR TIM5 external trigger register 0x00
0x00 5304 TIM5_DER TIM5 DMA1 request enable register 0x00
0x00 5305 TIM5_IER TIM5 interrupt enable register 0x00
0x00 5306 TIM5_SR1 TIM5 status register 1 0x00
0x00 5307 TIM5_SR2 TIM5 status register 2 0x00
0x00 5308 TIM5_EGR TIM5 event generation register 0x00
0x00 5309 TIM5_CCMR1 TIM5 Capture/Compare mode register 1 0x00
0x00 530A TIM5_CCMR2 TIM5 Capture/Compare mode register 2 0x00
0x00 530B TIM5_CCER1 TIM5 Capture/Compare enable register 1 0x00
0x00 530C TIM5_CNTRH TIM5 counter high 0x00
0x00 530D TIM5_CNTRL TIM5 counter low 0x00
0x00 530E TIM5_PSCR TIM5 prescaler register 0x00
0x00 530F TIM5_ARRH TIM5 Auto-reload register high 0xFF
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status
Memory and register map STM8AL31E8x STM8AL3LE8x
52/133 DocID027180 Rev 5
0x00 5310
TIM5
TIM5_ARRL TIM5 Auto-reload register low 0xFF
0x00 5311 TIM5_CCR1H TIM5 Capture/Compare register 1 high 0x00
0x00 5312 TIM5_CCR1L TIM5 Capture/Compare register 1 low 0x00
0x00 5313 TIM5_CCR2H TIM5 Capture/Compare register 2 high 0x00
0x00 5314 TIM5_CCR2L TIM5 Capture/Compare register 2 low 0x00
0x00 5315 TIM5_BKR TIM5 break register 0x00
0x00 5316 TIM5_OISR TIM5 output idle state register 0x00
0x00 5317
to
0x00 533F
Reserved area
0x00 5340
ADC1
ADC1_CR1 ADC1 configuration register 1 0x00
0x00 5341 ADC1_CR2 ADC1 configuration register 2 0x00
0x00 5342 ADC1_CR3 ADC1 configuration register 3 0x1F
0x00 5343 ADC1_SR ADC1 status register 0x00
0x00 5344 ADC1_DRH ADC1 data register high 0x00
0x00 5345 ADC1_DRL ADC1 data register low 0x00
0x00 5346 ADC1_HTRH ADC1 high threshold register high 0x0F
0x00 5347 ADC1_HTRL ADC1 high threshold register low 0xFF
0x00 5348 ADC1_LTRH ADC1 low threshold register high 0x00
0x00 5349 ADC1_LTRL ADC1 low threshold register low 0x00
0x00 534A ADC1_SQR1 ADC1 channel sequence 1 register 0x00
0x00 534B ADC1_SQR2 ADC1 channel sequence 2 register 0x00
0x00 534C ADC1_SQR3 ADC1 channel sequence 3 register 0x00
0x00 534D ADC1_SQR4 ADC1 channel sequence 4 register 0x00
0x00 534E ADC1_TRIGR1 ADC1 trigger disable 1 0x00
0x00 534F ADC1_TRIGR2 ADC1 trigger disable 2 0x00
0x00 5350 ADC1_TRIGR3 ADC1 trigger disable 3 0x00
0x00 5351 ADC1_TRIGR4 ADC1 trigger disable 4 0x00
0x00 5352 to
0x00 537F Reserved area (46 byte)
0x00 5380
DAC
DAC_CH1CR1 DAC channel 1 control register 1 0x00
0x00 5381 DAC_CH1CR2 DAC channel 1 control register 2 0x00
0x00 5382 DAC_CH2CR1 DAC channel 2 control register 1 0x00
0x00 5383 DAC_CH2CR2 DAC channel 2 control register 2 0x00
0x00 5384 DAC_SWTRIG DAC software trigger register 0x00
0x00 5385DAC_SR DAC status register 0x00
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status
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STM8AL31E8x STM8AL3LE8x Memory and register map
61
0x00 5386 to
0x00 5387 Reserved area (2 byte)
0x00 5388
DAC
DAC_CH1RDHRH DAC channel 1 right aligned data holding
register high 0x00
0x00 5389 DAC_CH1RDHRL DAC channel 1 right aligned data holding
register low 0x00
0x00 538A to
0x00 538B Reserved area (2 byte)
0x00 538C
DAC
DAC_CH1LDHRH DAC channel 1 left aligned data holding
register high 0x00
0x00 538D DAC_CH1LDHRL DAC channel 1 left aligned data holding
register low 0x00
0x00 538E
to 0x00 538F Reserved area (2 byte)
0x00 5390 DAC DAC_CH1DHR8 DAC channel 1 8-bit data holding register 0x00
0x00 5391 to
0x00 5393 Reserved area (3 byte)
0x00 5394
DAC
DAC_CH2RDHRH DAC channel 2 right aligned data holding
register high 0x00
0x00 5395 DAC_CH2RDHRL DAC channel 2 right aligned data holding
register low 0x00
0x00 5396 to
0x00 5397 Reserved area (2 byte)
0x00 5398
DAC
DAC_CH2LDHRH DAC channel 2 left aligned data holding
register high 0x00
0x00 5399 DAC_CH2LDHRL DAC channel 2 left aligned data holding
register low 0x00
0x00 539A
to 0x00 539B Reserved area (2 byte)
0x00 539C DAC DAC_CH2DHR8 DAC channel 2 8-bit data holding register 0x00
0x00 539D
to 0x00 539F Reserved area (3 byte)
0x00 53A0
DAC
DAC_DCH1RDHRH DAC channel 1 right aligned data holding
register high 0x00
0x00 53A1 DAC_DCH1RDHRL DAC channel 1 right aligned data holding
register low 0x00
0x00 53A2
to 0x00 53AB Reserved area (3 byte)
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status
Memory and register map STM8AL31E8x STM8AL3LE8x
54/133 DocID027180 Rev 5
0x00 53AC
DAC
DAC_DORH DAC data output register high 0x00
0x00 53AD DAC_DORL DAC data output register low 0x00
0x00 53A2 DAC_DCH2RDHRH DAC channel 2 right aligned data holding
register high 0x00
0x00 53A3 DAC_DCH2RDHRL DAC channel 2 right aligned data holding
register low 0x00
0x00 53A4 DAC_DCH1LDHRH DAC channel 1left aligned data holding
register high 0x00
0x00 53A5 DAC_DCH1LDHRL DAC channel 1left aligned data holding
register low 0x00
0x00 53A6 DAC_DCH2LDHRH DAC channel 2 left aligned data holding
register high 0x00
0x00 53A7 DAC_DCH2LDHRL DAC channel 2 left aligned data holding
register low 0x00
0x00 53A8 DAC_DCH1DHR8 DAC channel 1 8-bit mode data holding
register 0x00
0x00 53A9 DAC_DCH2DHR8 DAC channel 2 8-bit mode data holding
register 0x00
0x00 53AA to
0x00 53AB Reserved area (2 byte)
0x00 53AC
DAC
DAC_CH1DORH
Reset value DAC channel 1 data output register high 0x00
0x00 53AD DAC_CH1DORL
Reset value DAC channel 1 data output register low 0x00
0x00 53AE
to 0x00 53AF Reserved area (2 byte)
0x00 53B0
DAC
DAC_CH2DORH
Reset value DAC channel 2 data output register high 0x00
0x00 53B1 DAC_CH2DORL
Reset value DAC channel 2 data output register low 0x00
0x00 53B2
to 0x00 53BF Reserved area
0x00 53C0
SPI2
SPI2_CR1 SPI2 control register 1 0x00
0x00 53C1 SPI2_CR2 SPI2 control register 2 0x00
0x00 53C2 SPI2_ICR SPI2 interrupt control register 0x00
0x00 53C3 SPI2_SR SPI2 status register 0x02
0x00 53C4 SPI2_DR SPI2 data register 0x00
0x00 53C5 SPI2_CRCPR SPI2 CRC polynomial register 0x07
0x00 53C6 SPI2_RXCRCR SPI2 Rx CRC register 0x00
0x00 53C7 SPI2_TXCRCR SPI2 Tx CRC register 0x00
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status
DocID027180 Rev 5 55/133
STM8AL31E8x STM8AL3LE8x Memory and register map
61
0x00 53C8 to
0x00 53CF Reserved area
0x00 53D0
AES
AES_CR AES control register 0x00
0x00 53D1 AES_SR AES status register 0x00
0x00 53D2 AES_DINR AES data input register 0x00
0x00 53D3 AES_DOUTR AES data output register 0x00
0x00 53D4 to
0x00 53DF Reserved area
0x00 53E0
USART2
USART2_SR USART2 status register 0xC0
0x00 53E1 USART2_DR USART2 data register 0xXX
0x00 53E2 USART2_BRR1 USART2 baud rate register 1 0x00
0x00 53E3 USART2_BRR2 USART2 baud rate register 2 0x00
0x00 53E4 USART2_CR1 USART2 control register 1 0x00
0x00 53E5 USART2_CR2 USART2 control register 2 0x00
0x00 53E6 USART2_CR3 USART2 control register 3 0x00
0x00 53E7 USART2_CR4 USART2 control register 4 0x00
0x00 53E8 USART2_CR5 USART2 control register 5 0x00
0x00 53E9 USART2_GTR USART2 guard time register 0x00
0x00 53EA USART2_PSCR USART2 prescaler register 0x00
0x00 53EB to
0x00 53EF Reserved area
0x00 53F0
USART3
USART3_SR USART3 status register 0xC0
0x00 53F1 USART3_DR USART3 data register 0xXX
0x00 53F2 USART3_BRR1 USART3 baud rate register 1 0x00
0x00 53F3 USART3_BRR2 USART3 baud rate register 2 0x00
0x00 53F4 USART3_CR1 USART3 control register 1 0x00
0x00 53F5 USART3_CR2 USART3 control register 2 0x00
0x00 53F6 USART3_CR3 USART3 control register 3 0x00
0x00 53F7 USART3_CR4 USART3 control register 4 0x00
0x00 53F8 USART3_CR5 USART3 control register 5 0x00
0x00 53F9 USART3_GTR USART3 guard time register 0x00
0x00 53FA USART3_PSCR USART3 prescaler register 0x00
0x00 53FB to
0x00 53FF Reserved area
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status
Memory and register map STM8AL31E8x STM8AL3LE8x
56/133 DocID027180 Rev 5
0x00 5400
LCD
LCD_CR1 LCD control register 1 0x00
0x00 5401 LCD_CR2 LCD control register 2 0x00
0x00 5402 LCD_CR3 LCD control register 3 0x00
0x00 5403 LCD_FRQ LCD frequency selection register 0x00
0x00 5404 LCD_PM0 LCD Port mask register 0 0x00
0x00 5405 LCD_PM1 LCD Port mask register 1 0x00
0x00 5406 LCD_PM2 LCD Port mask register 2 0x00
0x00 5407 LCD_PM3 LCD Port mask register 3 0x00
0x00 5408 LCD_PM4 LCD Port mask register 4 0x00
0x00 5409 LCD_PM5 LCD Port mask register 5 0x00
0x00 540A to
0x00 540B Reserved area (2 byte)
0x00 540C
LCD
LCD_RAM0 LCD display memory 0 0x00
0x00 540D LCD_RAM1 LCD display memory 1 0x00
0x00 540E LCD_RAM2 LCD display memory 2 0x00
0x00 540F LCD_RAM3 LCD display memory 3 0x00
0x00 5410 LCD_RAM4 LCD display memory 4 0x00
0x00 5411 LCD_RAM5 LCD display memory 5 0x00
0x00 5412 LCD_RAM6 LCD display memory 6 0x00
0x00 5413 LCD_RAM7 LCD display memory 7 0x00
0x00 5414 LCD_RAM8 LCD display memory 8 0x00
0x00 5415 LCD_RAM9 LCD display memory 9 0x00
0x00 5416 LCD_RAM10 LCD display memory 10 0x00
0x00 5417 LCD_RAM11 LCD display memory 11 0x00
0x00 5418 LCD_RAM12 LCD display memory 12 0x00
0x00 5419 LCD_RAM13 LCD display memory 13 0x00
0x00 541A LCD_RAM14 LCD display memory 14 0x00
0x00 541B LCD_RAM15 LCD display memory 15 0x00
0x00 541C LCD_RAM16 LCD display memory 16 0x00
0x00 541D LCD_RAM17 LCD display memory 17 0x00
0x00 541E LCD_RAM18 LCD display memory 18 0x00
0x00 541F LCD_RAM19 LCD display memory 19 0x00
0x00 5420 LCD_RAM20 LCD display memory 20 0x00
0x00 5421 LCD_RAM21 LCD display memory 21 0x00
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status
DocID027180 Rev 5 57/133
STM8AL31E8x STM8AL3LE8x Memory and register map
61
0x00 5422 to
0x00 542E Reserved area
0x00 542F LCD LCD_CR4 LCD control register 4 0x00
0x00 5430
RI
Reserved area (1 byte) 0x00
0x00 5431 RI_ICR1 Timer input capture routing register 1 0x00
0x00 5432 RI_ICR2 Timer input capture routing register 2 0x00
0x00 5433 RI_IOIR1 I/O input register 1 0xXX
0x00 5434 RI_IOIR2 I/O input register 2 0xXX
0x00 5435 RI_IOIR3 I/O input register 3 0xXX
0x00 5436 RI_IOCMR1 I/O control mode register 1 0x00
0x00 5437 RI_IOCMR2 I/O control mode register 2 0x00
0x00 5438 RI_IOCMR3 I/O control mode register 3 0x00
0x00 5439 RI_IOSR1 I/O switch register 1 0x00
0x00 543A RI_IOSR2 I/O switch register 2 0x00
0x00 543B RI_IOSR3 I/O switch register 3 0x00
0x00 543C RI_IOGCR I/O group control register 0x3F
0x00 543D RI_ASCR1 Analog switch register 1 0x00
0x00 543E RI_ASCR2 Analog switch register 2 0x00
0x00 543F RI_RCR Resistor control register 1 0x00
0x00 5440
COMP1/
COMP2
COMP_CSR1 Comparator control and status register 1 0x00
0x00 5441 COMP_CSR2 Comparator control and status register 2 0x00
0x00 5442 COMP_CSR3 Comparator control and status register 3 0x00
0x00 5443 COMP_CSR4 Comparator control and status register 4 0x00
0x00 5444 COMP_CSR5 Comparator control and status register 5 0x00
1. These registers are not impacted by a system reset. They are reset at power-on.
Table 9. General hardware register map (continued)
Address Block Register label Register name Reset status
Memory and register map STM8AL31E8x STM8AL3LE8x
58/133 DocID027180 Rev 5
Table 10. CPU/SWIM/debug module/interrupt controller registers
Address Block Register label Register name Reset
status
0x00 7F00
CPU(1)
A Accumulator 0x00
0x00 7F01 PCE Program counter extended 0x00
0x00 7F02 PCH Program counter high 0x00
0x00 7F03 PCL Program counter low 0x00
0x00 7F04 XH X index register high 0x00
0x00 7F05 XL X index register low 0x00
0x00 7F06 YH Y index register high 0x00
0x00 7F07 YL Y index register low 0x00
0x00 7F08 SPH Stack pointer high 0x03
0x00 7F09 SPL Stack pointer low 0xFF
0x00 7F0A CCR Condition code register 0x28
0x00 7F0B to
0x00 7F5F Reserved area (85 byte)
0x00 7F60 CPU CFG_GCR Global configuration register 0x00
0x00 7F70
ITC-SPR
ITC_SPR1 Interrupt Software priority register 1 0xFF
0x00 7F71 ITC_SPR2 Interrupt Software priority register 2 0xFF
0x00 7F72 ITC_SPR3 Interrupt Software priority register 3 0xFF
0x00 7F73 ITC_SPR4 Interrupt Software priority register 4 0xFF
0x00 7F74 ITC_SPR5 Interrupt Software priority register 5 0xFF
0x00 7F75 ITC_SPR6 Interrupt Software priority register 6 0xFF
0x00 7F76 ITC_SPR7 Interrupt Software priority register 7 0xFF
0x00 7F77 ITC_SPR8 Interrupt Software priority register 8 0xFF
0x00 7F78
to
0x00 7F79
Reserved area (2 byte)
0x00 7F80 SWIM SWIM_CSR SWIM control status register 0x00
0x00 7F81
to
0x00 7F8F
Reserved area (15 byte)
DocID027180 Rev 5 59/133
STM8AL31E8x STM8AL3LE8x Memory and register map
61
0x00 7F90
DM
DM_BK1RE DM breakpoint 1 register extended byte 0xFF
0x00 7F91 DM_BK1RH DM breakpoint 1 register high byte 0xFF
0x00 7F92 DM_BK1RL DM breakpoint 1 register low byte 0xFF
0x00 7F93 DM_BK2RE DM breakpoint 2 register extended byte 0xFF
0x00 7F94 DM_BK2RH DM breakpoint 2 register high byte 0xFF
0x00 7F95 DM_BK2RL DM breakpoint 2 register low byte 0xFF
0x00 7F96 DM_CR1 DM Debug module control register 1 0x00
0x00 7F97 DM_CR2 DM Debug module control register 2 0x00
0x00 7F98 DM_CSR1 DM Debug module control/status register 1 0x10
0x00 7F99 DM_CSR2 DM Debug module control/status register 2 0x00
0x00 7F9A DM_ENFCTR DM enable function register 0xFF
0x00 7F9B
to
0x00 7F9F
Reserved area (5 byte)
1. Accessible by debug module only
Table 10. CPU/SWIM/debug module/interrupt controller registers (continued)
Address Block Register label Register name Reset
status
Interrupt vector mapping STM8AL31E8x STM8AL3LE8x
60/133 DocID027180 Rev 5
6 Interrupt vector mapping
Note: Slope control of all GPIO pins can be programmed except true open drain pins and by
default is limited to 2 MHz.
Table 11. Interrupt mapping
IRQ
No.
Source
block Description
Wakeup
from Halt
mode
Wakeup
from
Active-halt
mode
Wakeup
from Wait
(WFI
mode)
Wakeup
from Wait
(WFE
mode)(1)
Vector
address
RESET Reset Yes Yes Yes Yes 0x00 8000
TRAP Software interrupt - - - - 0x00 8004
0TLI
(2) External Top level Interrupt - - - - 0x00 8008
1 FLASH EOP/WR_PG_DIS - - Yes Yes(3) 0x00 800C
2 DMA1 0/1 DMA1 channels 0/1 - - Yes Yes(3) 0x00 8010
3 DMA1 2/3 DMA1 channels 2/3 - - Yes Yes(3) 0x00 8014
4RTC/LSE_
CSS
RTC alarm interrupt/LSE
CSS interrupt Yes Yes Yes Yes 0x00 8018
5EXTI
E/F/PVD(4)
PortE/F interrupt/PVD
interrupt Yes Yes Yes Yes(3) 0x00 801C
6 EXTIB/G External interrupt port B/G Yes Yes Yes Yes(3) 0x00 8020
7 EXTID/H External interrupt port D/H Yes Yes Yes Yes(3) 0x00 8024
8 EXTI0 External interrupt 0 Yes Yes Yes Yes(3) 0x00 8028
9 EXTI1 External interrupt 1 Yes Yes Yes Yes(3) 0x00 802C
10 EXTI2 External interrupt 2 Yes Yes Yes Yes(3) 0x00 8030
11 EXTI3 External interrupt 3 Yes Yes Yes Yes(3) 0x00 8034
12 EXTI4 External interrupt 4 Yes Yes Yes Yes(3) 0x00 8038
13 EXTI5 External interrupt 5 Yes Yes Yes Yes(3) 0x00 803C
14 EXTI6 External interrupt 6 Yes Yes Yes Yes(3) 0x00 8040
15 EXTI7 External interrupt 7 Yes Yes Yes Yes(3) 0x00 8044
16 LCD/AES LCD interrupt/AES interrupt - - Yes Yes 0x00 8048
17
CLK/
TIM1/
DAC
System clock switch/CSS
interrupt/TIM1 break/DAC - - Yes Yes 0x00 804C
18
COMP1/
COMP2
ADC1
Comparator 1 and 2
interrupt/ADC1 Yes Yes Yes Yes(3) 0x00 8050
DocID027180 Rev 5 61/133
STM8AL31E8x STM8AL3LE8x Interrupt vector mapping
61
19 TIM2/
USART2
TIM2 update
/overflow/trigger/break/
USART2 transmission
complete/transmit data
register empty
interrupt
--YesYes
(3) 0x00 8054
20 TIM2/
USART2
Capture/Compare/USART
2 interrupt --YesYes
(3) 0x00 8058
21 TIM3/
USART3
TIM3 Update
/Overflow/Trigger/Break/
USART3 transmission
complete/transmit data
register empty
interrupt
--YesYes
(3) 0x00 805C
22 TIM3/
USART3
TIM3 Capture/Compare/
USART3 Receive register
data full/overrun/idle line
detected/parity error/
interrupt
--YesYes
(3) 0x00 8060
23 TIM1 Update /overflow/trigger/
COM ---Yes
(3) 0x00 8064
24 TIM1 Capture/Compare - - - Yes(3) 0x00 8068
25 TIM4 Update/overflow/trigger - - Yes Yes(3) 0x00 806C
26 SPI1 End of Transfer Yes Yes Yes Yes(3) 0x00 8070
27 USART 1/
TIM5
USART1 transmission
complete/transmit data
register empty/
TIM5 update/overflow/
trigger/break
--YesYes
(3) 0x00 8074
28
USART 1/
TIM5
USART1 Receive register
data full/overrun/idle line
detected/parity error/
TIM5 capture/compare
--YesYes
(3) 0x00 8078
29 I2C1/SPI2 I2C1 interrupt(5)/
SPI2 Yes Yes Yes Yes(3) 0x00 807C
1. The Low-power wait mode is entered when executing a WFE instruction in Low-power run mode.
2. The TLI interrupt is the logic OR between TIM2 overflow interrupt, and TIM4 overflow interrupts.
3. In WFE mode, this interrupt is served if it has been previously enabled. After processing the interrupt, the processor goes
back to WFE mode. When this interrupt is configured as a wakeup event, the CPU wakes up and resumes processing.
4. The interrupt from PVD is logically OR-ed with Port E and F interrupts. Register EXTI_CONF allows to select between Port
E and Port F interrupt. See more details about the external interrupt port select register (EXTI_CONF) in the
STM8L051/L052 Value Line, STM8L151/L152, STM8L162, STM8AL31, STM8AL3L MCU lines reference manual
(RM0031).
5. The device is woken up from Halt or Active-halt mode only when the address received matches the interface address.
Table 11. Interrupt mapping (continued)
IRQ
No.
Source
block Description
Wakeup
from Halt
mode
Wakeup
from
Active-halt
mode
Wakeup
from Wait
(WFI
mode)
Wakeup
from Wait
(WFE
mode)(1)
Vector
address
Option byte STM8AL31E8x STM8AL3LE8x
62/133 DocID027180 Rev 5
7 Option byte
Option byte contain configurations for device hardware features as well as the memory
protection of the device. They are stored in a dedicated memory block.
All option byte can be modified in ICP mode (with SWIM) by accessing the EEPROM
address. See Table 12 for details on option byte addresses.
The option byte can also be modified ‘on the fly’ by the application in IAP mode, except for
the ROP, UBC and PCODESIZE values which are only taken into account when they are
modified in ICP mode (with the SWIM).
Refer to the STM8AL31E8x/STM8AL3LE8x Flash programming manual (PM0054) and
STM8 SWIM and Debug Manual (UM0470) for information on SWIM programming
procedures.
Table 12. Option byte addresses
Address Option name
Option
byte
No.
Option bits Factory
default
setting
7654 3 2 1 0
00 4800
Read-out
protection
(ROP)
OPT0 ROP[7:0] 0xAA
00 4802 UBC (User
Boot code size) OPT1 UBC[7:0] 0x00
00 4807 PCODESIZE OPT2 PCODE[7:0] 0x00
00 4808
Independent
watchdog
option
OPT3
[3:0] Reserved WWDG
_HALT
WWDG
_HW
IWDG
_HALT
IWDG
_HW 0x00
00 4809
Number of
stabilization
clock cycles for
HSE and LSE
oscillators
OPT4 Reserved LSECNT[1:0] HSECNT[1:0] 0x00
00 480A Brownout reset
(BOR)
OPT5
[3:0] Reserved BOR_TH BOR_
ON 0x01
00 480B Bootloader
option byte
(OPTBL)
OPTBL
[15:0] OPTBL[15:0]
0x00
00 480C 0x00
DocID027180 Rev 5 63/133
STM8AL31E8x STM8AL3LE8x Option byte
64
Table 13. Option byte description
Option
byte no. Option description
OPT0
ROP[7:0] Memory readout protection (ROP)
0xAA: Disable readout protection (write access via SWIM protocol)
Refer to Readout protection section in STM8L05xx, STM8L15xx, STM8L162x,
STM8AL31xx and STM8AL3Lxx microcontroller family reference manual (RM0031).
OPT1
UBC[7:0] Size of the user boot code area
UBC[7:0] Size of the user boot code area
0x00: No UBC
0x01: Page 0 reserved for the UBC and write protected.
...
0xFF: Page 0 to 254 reserved for the UBC and write-protected.
Refer to User boot code section in the STM8L05xx, STM8L15xx, STM8L162x,
STM8AL31xx and STM8AL3Lxx microcontroller family reference manual (RM0031).
OPT2
PCODESIZE[7:0] Size of the proprietary code area
0x00: No proprietary code area
0x01: Page 0 reserved for the proprietary code and read/write protected.
...
0xFF: Page 0 to 254 reserved for the proprietary code and read/write protected.
Refer to Proprietary code area (PCODE) section in STM8L05xx, STM8L15xx,
STM8L162x, STM8AL31xx and STM8AL3Lxx microcontroller family reference manual
(RM0031) for more details.
OPT3
IWDG_HW: Independent watchdog
0: Independent watchdog activated by software
1: Independent watchdog activated by hardware
IWDG_HALT: Independent watchdog off in Halt/Active-halt
0: Independent watchdog continues running in Halt/Active-halt mode
1: Independent watchdog stopped in Halt/Active-halt mode
WWDG_HW: Window watchdog
0: Window watchdog activated by software
1: Window watchdog activated by hardware
WWDG_HALT: Window window watchdog reset on Halt/Active-halt
0: Window watchdog stopped in Halt mode
1: Window watchdog generates a reset when MCU enters Halt mode
OPT4
HSECNT: Number of HSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
LSECNT: Number of LSE oscillator stabilization clock cycles
0x00 - 1 clock cycle
0x01 - 16 clock cycles
0x10 - 512 clock cycles
0x11 - 4096 clock cycles
Option byte STM8AL31E8x STM8AL3LE8x
64/133 DocID027180 Rev 5
OPT5
BOR_ON:
0: Brownout reset off
1: Brownout reset on
BOR_TH[3:1]: Brownout reset thresholds. Refer to Table 20 for details on the thresholds
according to the value of BOR_TH bits.
OPTBL
OPTBL[15:0]:
This option is checked by the boot ROM code after reset. Depending on the content of
addresses 00 480B, 00 480C and 0x8000 (reset vector) the CPU jumps to the
bootloader or to the reset vector.
Refer to the UM0560 bootloader user manual for more details.
Table 13. Option byte description (continued)
Option
byte no. Option description
DocID027180 Rev 5 65/133
STM8AL31E8x STM8AL3LE8x Unique ID
65
8 Unique ID
STM8 devices feature a 96-bit unique device identifier which provides a reference number
that is unique for any device and in any context. The 96 bits of the identifier are never
altered by the user.
The unique device identifier is read in single byte and may then be concatenated using a
custom algorithm.
The unique device identifier is ideally suited:
•For use as serial numbers
•For use as security keys to increase the code security in the program memory while
using and combining this unique ID with software cryptographic primitives and
protocols before programming the internal memory.
•To activate secure boot processes
Table 14. Unique ID registers (96 bits)
Address Content
description
Unique ID bits
76543 2 1 0
0x4926 X co-ordinate on
the wafer
U_ID[7:0]
0x4927 U_ID[15:8]
0x4928 Y co-ordinate on
the wafer
U_ID[23:16]
0x4929 U_ID[31:24]
0x492A Wafer number U_ID[39:32]
0x492B
Lot number
U_ID[47:40]
0x492C U_ID[55:48]
0x492D U_ID[63:56]
0x492E U_ID[71:64]
0x492F U_ID[79:72]
0x4930 U_ID[87:80]
0x4931 U_ID[95:88]
Electrical parameters STM8AL31E8x STM8AL3LE8x
66/133 DocID027180 Rev 5
9 Electrical parameters
9.1 Parameter conditions
Unless otherwise specified, all voltages are referred to VSS.
9.1.1 Minimum and maximum values
Unless otherwise specified the minimum and maximum values are guaranteed in the worst
conditions of ambient temperature, supply voltage and frequencies by tests in production on
100% of the devices with an ambient temperature at TA= 25 °C and TA = TA max (given by
the selected temperature range).
Data based on characterization results, design simulation and/or technology characteristics
are indicated in the table footnotes and are not tested in production.
9.1.2 Typical values
Unless otherwise specified, typical data are based on TA = 25 °C, VDD = 3 V. They are given
only as design guidelines and are not tested.
Typical ADC and DAC accuracy values are determined by characterization of a batch of
samples from a standard diffusion lot over the full temperature range.
9.1.3 Typical curves
Unless otherwise specified, all typical curves are given only as design guidelines and are
not tested.
9.1.4 Loading capacitor
The loading conditions used for pin parameter measurement are shown in Figure 10.
Figure 10. Pin loading conditions
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STM8AL31E8x STM8AL3LE8x Electrical parameters
119
9.1.5 Pin input voltage
The input voltage measurement on a pin of the device is described in Figure 11.
Figure 11. Pin input voltage
9.2 Absolute maximum ratings
Stresses above the absolute maximum ratings listed in Table 15: Voltage characteristics,
Table 16: Current characteristics and Table 17: Thermal characteristics may cause
permanent damage to the device. These are stress ratings only, and a functional operation
of the device at these conditions is not implied. Exposure to maximum rating conditions for
extended periods of time may affect the device’s reliability.
The device’s mission profile (application conditions) is compliant with the JEDEC JESD47
qualification standard, its extended mission profiles are available on demand.
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Table 15. Voltage characteristics
Symbol Ratings Min Max Unit
VDD- VSS
External supply voltage
(including VDDA)(1)
1. All power (VDD1, VDD2, VDD3, VDD4, VDDA) and ground (VSS1, VSS2, VSS3, VSS4, VSSA) pins must always
be connected to the external power supply.
- 0.3 4.0
V
VIN(2)
2. VIN maximum must always be respected. Refer to Table 16. for maximum allowed injected current values.
Input voltage on true open-drain pins
(PC0 and PC1)
VSS - 0.3
VDD + 4.0
Input voltage on five-volt tolerant (FT)
pins VDD + 4.0
Input voltage on any other pin 4.0
VESD Electrostatic discharge voltage
see Absolute maximum
ratings (electrical sensitivity)
on page 118
Electrical parameters STM8AL31E8x STM8AL3LE8x
68/133 DocID027180 Rev 5
Table 16. Current characteristics
Symbol Ratings Max. Unit
IVDD Total current into VDD power line (source) 80
mA
IVSS Total current out of VSS ground line (sink) 80
IIO
Output current sunk by IR_TIM pin
(with high sink LED driver capability) 80
Output current sunk by any other I/O and control pin 25
Output current sourced by any I/Os and control pin - 25
IINJ(PIN)
Injected current on true open-drain pins (PC0 and PC1)(1) - 5 / +0
Injected current on five-volt tolerant (FT) pins(1)
1. Positive injection is not possible on these I/Os. A negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 15. for maximum allowed input voltage values.
- 5 / +0
Injected current on any other pin (2)
2. A positive injection is induced by VIN>VDD while a negative injection is induced by VIN<VSS. IINJ(PIN) must
never be exceeded. Refer to Table 15. for maximum allowed input voltage values.
- 5 / +5
ΣIINJ(PIN) Total injected current (sum of all I/O and control pins) (3)
3. When several inputs are submitted to a current injection, the maximum ΣIINJ(PIN) is the absolute sum of the
positive and negative injected currents (instantaneous values).
± 25
Table 17. Thermal characteristics
Symbol Ratings Value Unit
TSTG Storage temperature range -65 to +150
° C
TJMaximum junction temperature 150
Table 18. Operating lifetime (OLF)(1)
1. For detailed mission profile analysis, please contact your local ST Sales Office.
Symbol Ratings Value Unit
OLF Conforming to AEC-Q100 -40 to 125 °C Grade 1
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STM8AL31E8x STM8AL3LE8x Electrical parameters
119
9.3 Operating conditions
Subject to general operating conditions for VDD and TA.
9.3.1 General operating conditions
Table 19. General operating conditions
Symbol Parameter Conditions Min. Max. Unit
fSYSCLK(1) System clock
frequency 1.65 V ≤ VDD < 3.6 V 0 16 MHz
VDD
Standard operating
voltage BOR detector enabled 1.65(2) 3.6 V
VDDA Analog operating
voltage
ADC and DAC
not used Must be at the same
potential as VDD
1.65(2) 3.6 V
ADC or DAC
used 1.8 3.6 V
PD(3)
Power dissipation at
TA= 85 °C for suffix A
devices
LQFP80 - - 288
mW
LQFP64 - - 288
LQFP48 - - 288
Power dissipation at
TA= 125 °C for suffix C
devices
LQFP80 - - 131
LQFP64 - - 104
LQFP48 - - 77
TATemperature range
1.65 V ≤ VDD <
3.6 V (A suffix
version)
- -40 85
°C
1.65 V ≤ VDD <
3.6 V (C suffix
version)
- -40 125
TJ
Junction temperature
range
-40 °C ≤ TA < 85 °C
(A suffix version) -40 105
-40 °C≤ TA < 125 °C
(C suffix version) -40 130
1. fSYSCLK = fCPU
2. 1.8 V at power-up, 1.65 V at power-down if BOR is disabled.
3. To calculate PDmax(TA), use the formula PDmax=(TJmax -TA)/Θ
JA with TJmax in this table and Θ
JA in “Thermal characteristics”
table.
Electrical parameters STM8AL31E8x STM8AL3LE8x
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9.3.2 Embedded reset and power control block characteristics
Table 20. Embedded reset and power control block characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
tVDD
VDD rise time rate BOR detector
enabled 0(1) -∞
(1) µs/V
VDD fall time rate BOR detector
enabled 20(1) -∞
(1) µs/V
tTEMP Reset release delay
VDD rising
BOR detector
enabled
-3-ms
VPDR Power-down reset threshold Falling edge 1.3 1.5 1.65(2)
V
VBOR0
Brown-out reset threshold 0
(BOR_TH[2:0]=000)
Falling edge 1.67 1.7 1.74(2)
Rising edge 1.69(2) 1.75 1.80
VBOR1
Brown-out reset threshold 1
(BOR_TH[2:0]=001)
Falling edge 1.87 1.93 1.97(2)
Rising edge 1.96(2) 2.04 2.07
VBOR2
Brown-out reset threshold 2
(BOR_TH[2:0]=010)
Falling edge 2.22 2.3 2.35(2)
Rising edge 2.31(2) 2.41 2.44
VBOR3
Brown-out reset threshold 3
(BOR_TH[2:0]=011)
Falling edge 2.45 2.55 2.60(2)
Rising edge 2.54(2) 2.66 2.7
VBOR4
Brown-out reset threshold 4
(BOR_TH[2:0]=100)
Falling edge 2.68 2.80 2.85(2)
Rising edge 2.78(2) 2.90 2.95
VPVD0 PVD threshold 0
Falling edge 1.80 1.84 1.88(2)
V
Rising edge 1.88(2) 1.94 1.99
VPVD1 PVD threshold 1
Falling edge 1.98 2.04 2.09(2)
Rising edge 2.08(2) 2.14 2.18
VPVD2 PVD threshold 2
Falling edge 2.2 2.24 2.28(2)
Rising edge 2.28(2) 2.34 2.38
VPVD3 PVD threshold 3
Falling edge 2.39 2.44 2.48(2)
Rising edge 2.47(2) 2.54 2.58
VPVD4 PVD threshold 4
Falling edge 2.57 2.64 2.69(2)
Rising edge 2.68(2) 2.74 2.79
VPVD5 PVD threshold 5
Falling edge 2.77 2.83 2.88(2)
Rising edge 2.87(2) 2.94 2.99
VPVD6 PVD threshold 6
Falling edge 2.97 3.05 3.09(2)
Rising edge 3.08(2) 3.15 3.20
DocID027180 Rev 5 71/133
STM8AL31E8x STM8AL3LE8x Electrical parameters
119
Figure 12. Power supply thresholds
Vhyst Hysteresis voltage
BOR0 threshold - 40(1) -
mV
All BOR and PVD
thresholds
excepting BOR0
-100
(1) -
1. Guaranteed by design.
2. Guaranteed by characterization results.
Table 20. Embedded reset and power control block characteristics (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit
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Electrical parameters STM8AL31E8x STM8AL3LE8x
72/133 DocID027180 Rev 5
9.3.3 Supply current characteristics
Total current consumption
The MCU is placed under the following conditions:
•All I/O pins in input mode with a static value at VDD or VSS (no load)
•All peripherals are disabled except if explicitly mentioned.
General conditions for VDD apply, TA = -40 °C to 125 °C.
Table 21. Total current consumption in Run mode
Symbol Parameter Conditions Typ. Max. Unit
IDD(RUN)
Supply
current in
run mode(1)
All peripherals
OFF, code
executed
from RAM,
VDD from
1.65 V to 3.6 V
HSI RC osc.
(16 MHz)(2)
fCPU = 125 kHz 0.40 0.55(3)
mA
fCPU = 1 MHz 0.50 0.65(3)
fCPU = 4 MHz 0.75 1.00(3)
fCPU = 8 MHz 1.10 1.40(3)
fCPU = 16 MHz 1.85 2.35
HSE external clock
(fCPU=fHSE)(4)
fCPU = 125 kHz 0.07 0.20(3)
fCPU = 1 MHz 0.20 0.25(3)
fCPU = 4 MHz 0.55 0.75(3)
fCPU = 8 MHz 1.00 1.25(3)
fCPU = 16 MHz 1.90 2.30(3)
LSI RC osc.
(typ. 38 kHz) fCPU = fLSI 40 50(3)
µA
LSE external clock
(32.768 kHz) fCPU = fLSE 40 60(3)
IDD(RUN)
Supply
current in
Run mode
All peripherals
OFF, code
executed from
Flash,
VDD from
1.65 V to 3.6 V
HSI RC osc.(5)
fCPU = 125 kHz 0.45 0.60(3)
mA
fCPU = 1 MHz 0.60 0.85(3)
fCPU = 4 MHz 1.10 1.45(3)
fCPU = 8 MHz 1.90 2.40(3)
fCPU = 16 MHz 3.80 4.90
HSE external clock
(fCPU=fHSE) (4)
fCPU = 125 kHz 0.30 0.45(3)
fCPU = 1 MHz 0.40 0.55(3)
fCPU = 4 MHz 1.15 1.50(3)
fCPU = 8 MHz 2.15 2.75(3)
fCPU = 16 MHz 4.00 4.75(3)
LSI RC osc. fCPU = fLSI 100 150(3)
µA
LSE external clock
(32.768 kHz)(6) fCPU = fLSE 100 120(3)
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STM8AL31E8x STM8AL3LE8x Electrical parameters
119
Figure 13. Typical IDD(RUN) from RAM vs. VDD (HSI clock source), fCPU =16 MHz(1)
1. Typical current consumption measured with code executed from RAM.
1. CPU executing typical data processing
2. The run from RAM consumption is approximated with the linear formula:
IDD(run_from_RAM) = Freq. * 95 µA/MHz + 250 µA
3. Guaranteed by characterization results.
4. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption
(IDD HSE) must be added. Refer to Table 32.
5. The run from Flash consumption is approximated with the linear formula:
IDD(run_from_Flash) = Freq. * 200 µA/MHz + 330 µA
6. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 33
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Electrical parameters STM8AL31E8x STM8AL3LE8x
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Figure 14. Typical IDD(RUN) from Flash vs. VDD (HSI clock source), fCPU = 16 MHz(1)
1. Typical current consumption measured with code executed from Flash.
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STM8AL31E8x STM8AL3LE8x Electrical parameters
119
In the following table, data are based on characterization results, unless otherwise
specified.
Table 22. Total current consumption in Wait mode
Symbol Parameter Conditions(1) Typ Max Unit
IDD(Wait)
Supply
current in
Wait mode
CPU not
clocked, all
peripherals
OFF, code
executed from
RAM with
Flash in IDDQ
mode,(2) VDD
from 1.65 V to
3.6 V
HSI
fCPU = 125 kHz 0.35 0.45(4)
mA
fCPU = 1 MHz 0.35 0.50(4)
fCPU = 4 MHz 0.40 0.60(4)
fCPU = 8 MHz 0.50 0.60(4)
fCPU = 16 MHz 0.70 0.85
HSE external clock
(fCPU=fHSE)(3)
fCPU = 125 kHz 0.05 0.10(4)
fCPU = 1 MHz 0.10 0.20(4)
fCPU = 4 MHz 0.20 0.40(4)
fCPU = 8 MHz 0.40 0.65(4)
fCPU = 16 MHz 0.76 1.15(4)
LSI fCPU = fLSI 60 80(4)
µA
LSE(5) external
clock (32.768 kHz) fCPU = fLSE 50 70(4)
IDD(Wait)
Supply
current in
Wait mode
CPU not
clocked, all
peripherals
OFF, code
executed from
Flash, VDD
from 1.65 V to
3.6 V
HSI
fCPU = 125 kHz 0.38 0.55(4)
mA
fCPU = 1 MHz 0.40 0.60(4)
fCPU = 4 MHz 0.50 0.65(4)
fCPU = 8 MHz 0.60 0.75(4)
fCPU = 16 MHz 0.80 0.90
HSE(3) external
clock (fCPU= HSE)
fCPU = 125 kHz 0.07 0.15(4)
fCPU = 1 MHz 0.10 0.20(4)
fCPU = 4 MHz 0.25 0.45(4)
fCPU = 8 MHz 0.50 0.65(4)
fCPU = 16 MHz 1.00 1.20(4)
LSI fCPU = fLSI 50 100(4)
µA
LSE(5) external
clock (32.768 kHz) fCPU = fLSE 50 80(4)
1. All peripherals OFF, VDD from 1.65 V to 3.6 V, HSI internal RC osc., fCPU = fSYSCLK
2. Flash is configured in IDDQ mode in Wait mode by setting the EPM or WAITM bit in the Flash_CR1 register.
3. Oscillator bypassed (HSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the HSE consumption
(IDD HSE) must be added. Refer to Table 32.
4. Guaranteed by characterization results.
5. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD HSE) must be added. Refer to Table 33
Electrical parameters STM8AL31E8x STM8AL3LE8x
76/133 DocID027180 Rev 5
Figure 15. Typical IDD(Wait) from RAM vs. VDD (HSI clock source), fCPU = 16 MHz(1)
1. Typical current consumption measured with code executed from RAM.
Figure 16. Typical IDD(Wait) from Flash (HSI clock source), fCPU = 16 MHz(1)
1. Typical current consumption measured with code executed from Flash.
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STM8AL31E8x STM8AL3LE8x Electrical parameters
119
Figure 17. Typical IDD(LPR) vs. VDD (LSI clock source), all peripherals OFF
Table 23. Total current consumption and timing in low-power run mode at VDD = 1.65 V
to 3.6 V
Symbol Parameter Conditions(1) Typ. Max. Unit
IDD(LPR)
Supply current
in low-power
run mode
LSI RC osc.
(at 38 kHz)
all peripherals OFF
TA = -40 °C to 25 °C 5.10 6.50(2)
μA
TA = 85 °C 6.80 11.00(3)
TA = 125 °C 13.40 20.00(3)
LSE (4) external
clock
(32.768 kHz)
TA = -40 °C to 25 °C 5.25 5.60(2)
TA = 85 °C 5.85 6.30(2)
TA = 125 °C 14.00 16.50(2)
1. No floating I/Os
2. Guaranteed by characterization results.
3. Tested at 85°C for temperature range A or 125°C for temperature range C.
4. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 33
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Electrical parameters STM8AL31E8x STM8AL3LE8x
78/133 DocID027180 Rev 5
Figure 18. Typical IDD(LPW) vs. VDD (LSI clock source), all peripherals OFF(1)
1. Typical current consumption measured with code executed from RAM.
Table 24. Total current consumption in low-power wait mode at VDD = 1.65 V to 3.6 V
Symbol Parameter Conditions(1) Typ. Max. Unit
IDD(LPW)
Supply current in
low-power wait
mode
LSI RC osc.
(at 38 kHz)
all peripherals OFF
TA = -40 °C to 25 °C 3.00 3.30(2)
μA
TA = 85 °C 4.40 9.00(3)
TA = 125 °C 11.00 18.00(3)
LSE external
clock(4)
(32.768 kHz)
TA = -40 °C to 25 °C 2.35 2.70(2)
TA = 85 °C 3.10 3.70(2)
TA = 125 °C 12.0 14.0(2)
1. No floating I/Os.
2. Guaranteed by characterization results.
3. Tested at 85°C for temperature range A or 125°C for temperature range C.
4. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 33.
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119
In the following table, data are based on characterization results, unless otherwise
specified.
Table 25. Total current consumption and timing in Active-halt mode
at VDD = 1.65 V to 3.6 V
Symbol Parameter Conditions(1) Typ. Max.(2) Unit
IDD(AH) Supply current in
Active-halt mode
LSI RC
(at 38 kHz)
LCD OFF(3)
TA = -40 °C to 25 °C 0.90 2.10
μA
TA = 85 °C 1.50 3.40
TA = 125 °C 5.10 12.00
LCD ON
(static duty/
external
VLCD) (4)
TA = -40 °C to 25 °C 1.40 3.10
TA = 85 °C 1.90 4.30
TA = 125 °C 5.50 13.00
LCD ON
(1/4 duty/
external
VLCD) (5)
TA = -40 °C to 25 °C 1.90 4.30
TA = 85 °C 2.40 5.40
TA = 125 °C 6.00 15.00
LCD ON
(1/4 duty/
internal
VLCD) (6)
TA = -40 °C to 25 °C 3.90 8.75
TA = 85 °C 4.50 10.20
TA = 125 °C 6.80 16.30
IDD(AH) Supply current in
Active-halt mode
LSE external
clock
(32.768 kHz)
(7)
LCD OFF(8)
TA = -40 °C to 25 °C 0.50 1.20
μA
TA = 85 °C 0.90 2.10
TA = 125 °C 4.80 11.00
LCD ON
(static duty/
external
VLCD) (4)
TA = -40 °C to 25 °C 0.85 1.90
TA = 85 °C 1.30 3.20
TA = 125 °C 5.00 12.00
LCD ON
(1/4 duty/
external
VLCD) (5)
TA = -40 °C to 25 °C 1.50 2.50
TA = 85 °C 1.80 4.20
TA = 125 °C 5.70 14.00
LCD ON
(1/4 duty/
internal
VLCD) (6)
TA = -40 °C to 25 °C 3.40 7.60
TA = 85 °C 3.90 9.20
TA = 125 °C 6.30 15.20
IDD(WUFAH)
Supply current
during wakeup
time from Active-
halt mode
(using HSI)
-- -2.40-mA
Electrical parameters STM8AL31E8x STM8AL3LE8x
80/133 DocID027180 Rev 5
tWU_HSI(AH)(9)(10)
Wakeup time from
Active-halt mode
to Run mode
(using HSI)
- - - 4.70 7.00 μs
tWU_LSI(AH)(9)(10)
Wakeup time from
Active-halt mode
to Run mode
(using LSI)
- - - 150.0 - μs
1. No floating I/O, unless otherwise specified.
2. Guaranteed by characterization results.
3. RTC enabled. Clock source = LSI
4. RTC enabled, LCD enabled with external VLCD = 3 V, static duty, division ratio = 256, all pixels active, no LCD connected.
5. RTC enabled, LCD enabled with external VLCD, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD connected.
6. LCD enabled with internal LCD booster VLCD = 3 V, 1/4 duty, 1/3 bias, division ratio = 64, all pixels active, no LCD
connected.
7. Oscillator bypassed (LSEBYP = 1 in CLK_ECKCR). When configured for external crystal, the LSE consumption
(IDD LSE) must be added. Refer to Table 33
8. RTC enabled. Clock source = LSE
9. Wakeup time until start of interrupt vector fetch.
The first word of interrupt routine is fetched 4 CPU cycles after tWU.
10. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
Table 25. Total current consumption and timing in Active-halt mode
at VDD = 1.65 V to 3.6 V (continued)
Symbol Parameter Conditions(1) Typ. Max.(2) Unit
Table 26. Typical current consumption in Active-halt mode, RTC clocked by LSE
external crystal
Symbol Parameter Condition(1) Typ. Unit
IDD(AH) (2) Supply current in Active-halt
mode
VDD = 1.8 V
LSE 1.15
µA
LSE/32(3) 1.05
VDD = 3 V
LSE 1.30
LSE/32(3) 1.20
VDD = 3.6 V
LSE 1.45
LSE/32(3) 1.35
1. No floating I/O, unless otherwise specified.
2. Based on measurements on bench with 32.768 kHz external crystal oscillator.
3. RTC clock is LSE divided by 32.
Electrical parameters STM8AL31E8x STM8AL3LE8x
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In the following table, data are based on characterization results, unless otherwise
specified.
Figure 20. Typical IDD(Halt) vs. VDD (internal reference voltage OFF)
Table 27. Total current consumption and timing in Halt mode at VDD = 1.65 to 3.6 V
Symbol Parameter Condition(1) Typ. Max. Unit
IDD(Halt)
Supply current in Halt mode
(ultra-low-power ULP bit =1 in
the PWR_CSR2 register)
TA = -40 °C to 25 °C 0.4 0.9(2)
µA
TA = 85 °C 0.9 2.8(3)
TA = 125 °C 4.4 13(3)
IDD(WUHalt)
Supply current during wakeup
time from Halt mode (using
HSI)
-2.4-mA
tWU_HSI(Halt)(4)(5) Wakeup time from Halt to Run
mode (using HSI) -4.7
7(2)
µs
tWU_LSI(Halt) (4)(5) Wakeup time from Halt mode
to Run mode (using LSI) -150-
1. TA = -40 to 125 °C, no floating I/O, unless otherwise specified.
2. Guaranteed by characterization results.
3. Tested at 85 °C for temperature range A or 125°C for temperature range C.
4. ULP=0 or ULP=1 and FWU=1 in the PWR_CSR2 register.
5. Wakeup time until start of interrupt vector fetch. The first word of interrupt routine is fetched 4 CPU cycles after tWU.
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119
Current consumption of on-chip peripherals
Table 28. Peripheral current consumption
Symbol Parameter Typ.
VDD = 3.0 V Unit
IDD(TIM1) TIM1 supply current(1) 10
µA/MHz
IDD(TIM2) TIM2 supply current (1) 7
IDD(TIM3) TIM3 supply current (1) 7
IDD(TIM5) TIM5 supply current (1) 7
IDD(TIM4) TIM4 timer supply current (1) 3
IDD(USART1) USART1 supply current (2) 5
IDD(USART2) USART2 supply current (2) 5
IDD(USART3) USART3 supply current (2) 5
IDD(SPI1) SPI1 supply current (2) 3
IDD(SPI2) SPI2 supply current (2) 3
IDD(I2C1) I2C1 supply current (2) 4
IDD(DMA1) DMA1 supply current(2) 3
IDD(WWDG) WWDG supply current(2) 1
IDD(ALL) Peripherals ON(3) 63
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IDD(TIM1) TIM1 supply current(1) 10
µA/MHz
IDD(TIM2) TIM2 supply current (4) 7
IDD(TIM3) TIM3 supply current (1) 7
IDD(TIM5) TIM5 supply current (1) 7
IDD(TIM4) TIM4 timer supply current (1) 3
IDD(USART1) USART1 supply current (5) 5
IDD(USART2) USART2 supply current (6) 5
IDD(USART3) USART3 supply current (7) 5
IDD(SPI1) SPI1 supply current (4) 3
IDD(SPI2) SPI2 supply current (4) 3
IDD(I2C1) I2C1 supply current (4) 4
IDD(DMA1) DMA1 supply current 3
IDD(AES) AES supply current 4
IDD(WWDG) WWDG supply current 1
IDD(ALL) Peripherals ON(8) 67
IDD(ADC1) ADC1 supply current(9) 1500
µA
IDD(DAC) DAC supply current(10) 370
IDD(COMP1) Comparator 1 supply current(11) 0.160
IDD(COMP2) Comparator 2 supply current(11) Slow mode 2
Fast mode 5
IDD(PVD/BOR)
Power voltage detector and brownout Reset unit supply
current (12) 2.6
IDD(BOR) Brownout Reset unit supply current (12) 2.4
IDD(IDWDG) Independent watchdog supply current
including LSI supply
current 0.45
excluding LSI
supply current 0.05
1. Data based on a differential IDD measurement between all peripherals OFF and a timer counter running at 16 MHz. The
CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production.
2. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and
the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling.
Not tested in production.
3. Peripherals listed above the IDD(ALL) parameter ON: TIM1, TIM2, TIM3, TIM4, TIM5, USART1, USART2, USART3, SPI1,
SPI2, I2C1, DMA1, WWDG.
4. Data based on a differential IDD measurement between all peripherals OFF and a timer counter running at 16 MHz. The
CPU is in Wait mode in both cases. No IC/OC programmed, no I/O pins toggling. Not tested in production.
Table 28. Peripheral current consumption (continued)
Symbol Parameter Typ.
VDD = 3.0 V Unit
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STM8AL31E8x STM8AL3LE8x Electrical parameters
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9.3.4 Clock and timing characteristics
HSE external clock (HSEBYP = 1 in CLK_ECKCR)
Subject to general operating conditions for VDD and TA.
5. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and
the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling.
Not tested in production.
6. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and
the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling.
Not tested in production.
7. Data based on a differential IDD measurement between the on-chip peripheral in reset configuration and not clocked and
the on-chip peripheral when clocked and not kept under reset. The CPU is in Wait mode in both cases. No I/O pins toggling.
Not tested in production.
8. Peripherals listed above the IDD(ALL) parameter ON: TIM1, TIM2, TIM3, TIM4, USART1, SPI1, I2C1, DMA1, WWDG.
9. Data based on a differential IDD measurement between ADC in reset configuration and continuous ADC conversion.
10. Data based on a differential IDD measurement between DAC in reset configuration and continuous DAC conversion of
VDD /2. Floating DAC output.
11. Data based on a differential IDD measurement between COMP1 or COMP2 in reset configuration and COMP1 or COMP2
enabled with static inputs. Supply current of internal reference voltage excluded.
12. Including supply current of internal reference voltage.
Table 29. Current consumption under external reset
Symbol Parameter Conditions Typ. Unit
IDD(RST)
Supply current under
external reset (1)
PB1/PB3/PA5 pins are
externally tied to VDD
VDD = 1.8 V 48
µAVDD = 3 V 80
VDD = 3.6 V 95
1. All pins except PA0, PB0 and PB4 are floating under reset. PA0, PB0 and PB4 are configured with pull-up under reset.
PB1, PB3 and PA5 must be tied externally under reset to avoid the consumption due to their schmitt trigger.
Table 30. HSE external clock characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
fHSE_ext(1) External clock source
frequency
-
1-16MHz
VHSEH OSC_IN input pin high-
level voltage 0.7 x VDD -V
DD
V
VHSEL OSC_IN input pin low-
level voltage VSS - 0.3 x VDD
Cin(HSE)(1) OSC_IN input capacitance - - 2.6 - pF
ILEAK_HSE OSC_IN input leakage
current VSS < VIN < VDD --±500nA
1. Guaranteed by design.
Electrical parameters STM8AL31E8x STM8AL3LE8x
86/133 DocID027180 Rev 5
LSE external clock (LSEBYP=1 in CLK_ECKCR)
The LSE is available on STM8AL31E8x devices only.
Subject to general operating conditions for VDD and TA.
HSE crystal/ceramic resonator oscillator
The HSE clock can be supplied with a 1 to 16 MHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
Table 31. LSE external clock characteristics
Symbol Parameter Min. Typ. Max. Unit
fLSE_ext External clock source frequency - 32.768 - kHz
VLSEH OSC32_IN input pin high-level voltage 0.7xVDD(1) -V
DD(1)
V
VLSEL OSC32_IN input pin low-level voltage VSS(1) 0.3xVDD(1)
Cin(LSE) OSC32_IN input capacitance - 0.6 - pF
ILEAK_LSE OSC32_IN input leakage current - - ±500 nA
1. Guaranteed by characterization results.
Table 32. HSE oscillator characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
fHSE
High speed external oscillator
frequency -1-16MHz
RFFeedback resistor - - 200 - kΩ
C(1)(2) Recommended load capacitance - - 20 - pF
IDD(HSE) HSE oscillator power consumption
C = 20 pF,
fOSC = 16 MHz --
2.5 (startup)
0.7 (stabilized)(3)
mA
C = 10 pF,
fOSC =16 MHz --
2.5 (startup)
0.46 (stabilized)(3)
gmOscillator transconductance - 3.5(3) --mA/V
tSU(HSE)(4) Startup time VDD is stabilized 1 - ms
1. C=
C
L1
=
C
L2
is approximately equivalent to 2 x crystal CLOAD.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with small Rm value.
Refer to crystal manufacturer for more details
3. Guaranteed by design.
4. tSU(HSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 16 MHz oscillation. This
value is measured for a standard crystal resonator and it varies significantly with the crystal manufacturer.
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119
Figure 21. HSE oscillator circuit diagram
HSE oscillator critical gm formula
Rm: Motional resistance (see crystal specification), Lm: Motional inductance (see crystal specification),
Cm: Motional capacitance (see crystal specification), Co: Shunt capacitance (see crystal specification),
CL1=CL2=C: Grounded external capacitance
gm >> gmcrit
LSE crystal/ceramic resonator oscillator
The LSE is available on STM8AL31E8x devices only.
The LSE clock can be supplied with a 32.768 kHz crystal/ceramic resonator oscillator. All
the information given in this paragraph is based on characterization results with specified
typical external components. In the application, the resonator and the load capacitors have
to be placed as close as possible to the oscillator pins in order to minimize output distortion
and startup stabilization time. Refer to the crystal resonator manufacturer for more details
(frequency, package, accuracy...).
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Figure 22. LSE oscillator circuit diagram
Internal clock sources
Subject to general operating conditions for VDD, and TA.
High speed internal RC oscillator (HSI)
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
Table 33. LSE oscillator characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
fLSE
Low speed external oscillator
frequency - - 32.768 - kHz
RFFeedback resistor ΔV = 200 mV - 1.2 - MΩ
C(1)(2) Recommended load capacitance - - 8 - pF
IDD(LSE) LSE oscillator power consumption
VDD = 1.8 V - 450 -
nAVDD = 3 V - 600 -
VDD = 3.6 V - 750 -
gmOscillator transconductance - 3(3) --µA/V
tSU(LSE)(4) Startup time VDD is stabilized - 1 - s
1. C=
C
L1
=
C
L2
is approximately equivalent to 2 x crystal CLOAD.
2. The oscillator selection can be optimized in terms of supply current using a high quality resonator with a small Rm value.
Refer to crystal manufacturer for more details.
3. Guaranteed by design.
4. tSU(LSE) is the startup time measured from the moment it is enabled (by software) to a stabilized 32.768 kHz oscillation.
This value is measured for a standard crystal resonator and it varies significantly with the crystal manufacturer.
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STM8AL31E8x STM8AL3LE8x Electrical parameters
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Figure 23. Typical HSI frequency vs. VDD
Table 34. HSI oscillator characteristics
Symbol Parameter Conditions(1) Min. Typ. Max. Unit
fHSI Frequency VDD = 3.0 V - 16 - MHz
ACCHSI
HSI oscillator user
trimming accuracy
Trimmed by the application for any VDD
and TA conditions -1 - 1
%
HSI oscillator accuracy
(factory calibrated)
VDD ≤ 1.8 V≤ VDD ≤ 3.6 V
-40 °C ≤ TA ≤ 125 °C -5 - 5
TRIM HSI user trimming
step(2)
Trimming code ≠ multiple of 16 - 0.4 0.7(2)
%
Trimming code = multiple of 16 - - ± 1.5(2)
tsu(HSI)
HSI oscillator setup
time (wakeup time) --3.76
(3) µs
IDD(HSI)
HSI oscillator power
consumption - - 100 140(3) µA
1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified.
2. The trimming step differs depending on the trimming code. It is usually negative on the codes which are multiples of 16
(0x00, 0x10, 0x20, 0x30...0xE0). Refer to the AN3101 “STM8L15x internal RC oscillator calibration” application note for
more details.
3. Guaranteed by design.
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Low speed internal RC oscillator (LSI)
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
Figure 24. Typical LSI clock source frequency vs. VDD
9.3.5 Memory characteristics
TA = -40 to 125 °C unless otherwise specified.
Table 35. LSI oscillator characteristics
Symbol Parameter Conditions(1)
1. VDD = 1.65 V to 3.6 V, TA = -40 to 125 °C unless otherwise specified.
Min. Typ. Max. Unit
fLSI Frequency - 26 38 56 kHz
tsu(LSI) LSI oscillator wakeup time - - - 200(2)
2. Guaranteed by design.
µs
D(LSI)
LSI oscillator frequency
drift(3)
3. This is a deviation for an individual part, once the initial frequency has been measured.
0 °C ≤ TA ≤ 85 °C -12 - 11 %
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Table 36. RAM and hardware registers
Symbol Parameter Conditions Min. Typ. Max. Unit
VRM Data retention mode (1)
1. Minimum supply voltage without losing data stored in RAM (in Halt mode or under Reset) or in hardware
registers (only in Halt mode). Guaranteed by characterization results.
Halt mode (or Reset) 1.65 - - V
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119
Flash memory
Data memory
Table 37. Flash program memory/data EEPROM memory
Symbol Parameter Conditions Min. Typ. Max. Unit
VDD
Operating voltage
(all modes, read/write/erase) fSYSCLK = 16 MHz 1.65 - 3.6 V
tprog
Programming time for 1 or 128 byte (block)
erase/write cycles (on programmed byte) --6-ms
Programming time for 1 to 128 byte (block)
write cycles (on erased byte) --3-ms
Iprog Programming/ erasing consumption
TA=+25 °C, VDD = 3.0 V -
0.7
-
mA
TA=+25 °C, VDD = 1.8 V - -
Table 38. Flash program memory
Symbol Parameter Conditions Min. Max. Unit
TWE Temperature for writing and erasing - -40 125 °C
NWE
Flash program memory endurance
(erase/write cycles)(1) TA= 25 °C 1000 - cycles
tRET Data retention time
TA= 25 °C 40 -
years
TA= 55 °C 20 -
1. The physical granularity of the memory is 4 byte, so cycling is performed on 4 byte even when a write/erase operation
addresses a single byte.
Table 39. Data memory
Symbol Parameter Conditions Min. Max. Unit
TWE Temperature for writing and erasing - -40 125 °C
NWE
Data memory endurance
(erase/write cycles)(1)
TA= 25 °C 300 k -
cycles
TA= -40 to 125 °C 100 k(2) -
tRET Data retention time
TA= 25 °C 40(2) (3) -
years
TA= 55 °C 20(2) (3) -
1. The physical granularity of the memory is 4 byte, so cycling is performed on 4 byte even when a write/erase operation
addresses a single byte.
2. More information on the relationship between data retention time and number of write/erase cycles is available in a
separate technical document.
3. Retention time for 256B of data memory after up to 1000 cycles at 125 °C.
Electrical parameters STM8AL31E8x STM8AL3LE8x
92/133 DocID027180 Rev 5
9.3.6 I/O current injection characteristics
As a general rule, current injection to the I/O pins, due to external voltage below VSS or
above VDD (for standard pins) should be avoided during normal product operation.
However, in order to give an indication of the robustness of the microcontroller in cases
when abnormal injection accidentally happens, susceptibility tests are performed on a
sample basis during device characterization.
Functional susceptibility to I/O current injection
While a simple application is executed on the device, the device is stressed by injecting
current into the I/O pins programmed in floating input mode. While current is injected into
the I/O pin, one at a time, the device is checked for functional failures.
The failure is indicated by an out of range parameter: ADC error, out of spec current
injection on adjacent pins or other functional failure (for example reset, oscillator frequency
deviation, LCD levels, etc.).
The test results are given in the following table.
9.3.7 I/O port pin characteristics
General characteristics
Subject to general operating conditions for VDD and TA unless otherwise specified. All
unused pins must be kept at a fixed voltage: using the output mode of the I/O for example or
an external pull-up or pull-down resistor.
Table 40. I/O current injection susceptibility
Symbol Description
Functional susceptibility
Unit
Negative
injection
Positive
injection
IINJ
Injected current on true open-drain pins -5 +0
mAInjected current on all 5 V tolerant (FT) pins -5 +0
Injected current on any other pin -5 +5
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Table 41. I/O static characteristics
Symbol Parameter Conditions(1) Min. Typ. Max. Unit
VIL Input low-level voltage Input voltage on all
pins Vss-0.3 - 0.3 x VDD V
VIH Input high-level voltage
Input voltage on true
open-drain pins (PC0
and PC1)
with VDD < 2 V
0.70 x VDD
-5.2(2)
V
Input voltage on true
open-drain pins (PC0
and PC1)
with VDD ≥ 2 V
-5.5(2)
Input voltage on five-
volt tolerant (FT) pins
with VDD < 2 V
-5.2(2)
Input voltage on five-
volt tolerant (FT) pins
with VDD ≥ 2 V
-5.5(2)
Input voltage on any
other pin -VDD+0.3(2)
Vhys Schmitt trigger voltage hysteresis (3) Standard I/Os - 200 -
mV
True open drain I/Os - 200 -
Ilkg Input leakage current (4)
VSS≤ VIN≤ VDD
Standard I/Os --50
nA
VSS≤ VIN≤ VDD
True open drain I/Os - - 200
VSS≤ VIN≤ VDD
PA0 with high sink LED
driver capability
- - 200
RPU Weak pull-up equivalent resistor(5) VIN=VSS 30(6) 45 60(6) kΩ
CIO I/O pin capacitance - - 5 - pF
1. VDD = 3.0 V, TA = -40 to 125 °C unless otherwise specified.
2. If VIH maximum is not respected, the injection current must be limited externally to IINJ(PIN) maximum.
3. Hysteresis voltage between Schmitt trigger switching levels. Based on characterization results, not tested.
4. The max. value may be exceeded if negative current is injected on adjacent pins.
5. RPU pull-up equivalent resistor based on a resistive transistor (corresponding IPU current characteristics described in
Figure 28).
6. Guaranteed by characterization results.
Electrical parameters STM8AL31E8x STM8AL3LE8x
94/133 DocID027180 Rev 5
Figure 25. Typical VIL and VIH vs. VDD (standard I/Os)
Figure 26. Typical VIL and VIH vs. VDD (true open drain I/Os)
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Figure 27. Typical pull-up resistance RPU vs. VDD with VIN=VSS
Figure 28. Typical pull-up current Ipu vs. VDD with VIN=VSS
Output driving current
Subject to general operating conditions for VDD and TA unless otherwise specified.
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Table 42. Output driving current (high sink ports)
I/O
Type Symbol Parameter Conditions Min. Max. Unit
Standard
VOL (1)
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 16 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.
Output low-level voltage for an I/O pin
IIO = +2 mA,
VDD = 3.0 V -0.45V
IIO = +2 mA,
VDD = 1.8 V -0.45V
IIO = +10 mA,
VDD = 3.0 V -0.7V
VOH (2)
2. The IIO current sourced must always respect the absolute maximum rating specified in Table 16 and the
sum of IIO (I/O ports and control pins) must not exceed IVDD.
Output high-level voltage for an I/O pin
IIO = -2 mA,
VDD = 3.0 V VDD-0.45 -V
IIO = -1 mA,
VDD = 1.8 V VDD-0.45 -V
IIO = -10 mA,
VDD = 3.0 V VDD-0.7 - V
Table 43. Output driving current (true open drain ports)
I/O
Type Symbol Parameter Conditions Min. Max. Unit
Open drain
VOL (1)
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 16 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.
Output low-level voltage for an I/O pin
IIO = +3 mA,
VDD = 3.0 V -0.45
V
IIO = +1 mA,
VDD = 1.8 V -0.45
Table 44. Output driving current (PA0 with high sink LED driver capability)
I/O
Type Symbol Parameter Conditions Min. Max. Unit
IR
VOL (1)
1. The IIO current sunk must always respect the absolute maximum rating specified in Table 16 and the sum
of IIO (I/O ports and control pins) must not exceed IVSS.
Output low-level voltage for an I/O pin IIO = +20 mA,
VDD = 2.0 V -0.45V
DocID027180 Rev 5 97/133
STM8AL31E8x STM8AL3LE8x Electrical parameters
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Figure 29. Typical VOL @ VDD = 3.0 V (high sink
ports)
Figure 30. Typical VOL @ VDD = 1.8 V (high sink
ports)
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Figure 32. Typical VOL @ VDD = 1.8 V (true open
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Figure 34. Typical VDD - VOH @ VDD = 1.8 V (high
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NRST pin
Subject to general operating conditions for VDD and TA unless otherwise specified.
Figure 35. Typical NRST pull-up resistance RPU vs. VDD
Table 45. NRST pin characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
VIL(NRST) NRST input low-level voltage - VSS(1) -0.8(1)
V
VIH(NRST) NRST input high-level voltage (1) -1.4(1) -VDD(1)
VOL(NRST) NRST output low-level voltage (1)
IOL = 2 mA
for 2.7 V ≤ VDD ≤ 3.6 V --
0.4(1)
IOL = 1.5 mA
for VDD < 2.7 V --
VHYST NRST input hysteresis -10%VDD
(2)(3) --mV
RPU(NRST) NRST pull-up equivalent resistor -30(1) 45 60(1) kΩ
VF(NRST) NRST input filtered pulse ---50
(3)
ns
VNF(NRST) NRST input not filtered pulse -300(3) --
1. Guaranteed by characterization results.
2. 200 mV min.
3. Guaranteed by design.
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Figure 36. Typical NRST pull-up current Ipu vs. VDD
The reset network shown in Figure 37 protects the device against parasitic resets. The user
must ensure that the level on the NRST pin goes below the VIL max. level specified in
Table 45. Otherwise the reset is not taken into account internally. For power consumption-
sensitive applications, the capacity of the external reset capacitor has to be reduced to limit
the charge/discharge current. If the NRST signal is used to reset the external circuitry, the
user must pay attention to the charge/discharge time of the external capacitor to meet the
reset timing conditions of the external devices. The minimum recommended capacity is 10
nF.
Figure 37. Recommended NRST pin configuration
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9.3.8 Communication interfaces
SPI1 - Serial peripheral interface
Unless otherwise specified, the parameters given in Table 46 are derived from tests
performed under ambient temperature, fSYSCLK frequency and VDD supply voltage
conditions summarized in Section 9.3.1. Refer to I/O port characteristics for more details on
the input/output alternate function characteristics (NSS, SCK, MOSI, MISO).
Table 46. SPI1 characteristics
Symbol Parameter Conditions(1) Min. Max. Unit
fSCK
1/tc(SCK)
SPI1 clock frequency
Master mode 0 8
MHz
Slave mode 0 8
tr(SCK)
tf(SCK)
SPI1 clock rise and fall
time Capacitive load: C = 30 pF - 30
ns
tsu(NSS)(2) NSS setup time Slave mode 4 x 1/fSYSCLK -
th(NSS)(2) NSS hold time Slave mode 80 -
tw(SCKH)(2)
tw(SCKL)(2) SCK high and low time Master mode,
fMASTER = 8 MHz, fSCK= 4 MHz 105 145
tsu(MI) (2)
tsu(SI)(2) Data input setup time
Master mode 30 -
Slave mode 3 -
th(MI) (2)
th(SI)(2) Data input hold time
Master mode 15 -
Slave mode 0 -
ta(SO)(2)(3) Data output access time Slave mode - 3x 1/fSYSCLK
tdis(SO)(2)(4) Data output disable time Slave mode 30 -
tv(SO) (2) Data output valid time Slave mode (after enable edge) - 60
tv(MO)(2) Data output valid time Master mode (after enable
edge) -20
th(SO)(2)
Data output hold time
Slave mode (after enable edge) 15 -
th(MO)(2) Master mode (after enable
edge) 1-
1. Parameters are given by selecting 10 MHz I/O output frequency.
2. Guaranteed by characterization results or by design.
3. Min. time is for the minimum time to drive the output and max. time is for the maximum time to validate the data.
4. Min. time is for the minimum time to invalidate the output and max. time is for the maximum time to put the data in Hi-Z.
DocID027180 Rev 5 101/133
STM8AL31E8x STM8AL3LE8x Electrical parameters
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Figure 38. SPI1 timing diagram - slave mode and CPHA=0
Figure 39. SPI1 timing diagram - slave mode and CPHA=1(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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Figure 40. SPI1 timing diagram - master mode(1)
1. Measurement points are done at CMOS levels: 0.3VDD and 0.7VDD.
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STM8AL31E8x STM8AL3LE8x Electrical parameters
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I2C - Inter IC control interface
Subject to general operating conditions for VDD, fSYSCLK, and TA unless otherwise specified.
The STM8AL I2C interface (I2C1) meets the requirements of the Standard I2C
communication protocol described in the following table with the restriction mentioned
below:
Refer to I/O port characteristics for more details on the input/output alternate function
characteristics (SDA and SCL).
Note: For speeds around 200 kHz, the achieved speed has a
±
5% tolerance.
For other speed ranges, the achieved speed has a
±
2% tolerance.
The above variations depend on the accuracy of the external components used.
Table 47. I2C characteristics
Symbol Parameter
Standard mode I2C Fast mode I2C(1)
1. fSYSCLK must be at least equal to 8 MHz to achieve max fast I2C speed (400 kHz).
Unit
Min.(2)
2. Data based on standard I2C protocol requirement, not tested in production.
Max. (2) Min. (2) Max. (2)
tw(SCLL) SCL clock low time 4.7 - 1.3 -
μs
tw(SCLH) SCL clock high time 4.0 - 0.6 -
tsu(SDA) SDA setup time 250 - 100 -
ns
th(SDA) SDA data hold time 0 - 0 900
tr(SDA)
tr(SCL)
SDA and SCL rise time - 1000 - 300
tf(SDA)
tf(SCL)
SDA and SCL fall time - 300 - 300
th(STA) START condition hold time 4.0 - 0.6 -
μs
tsu(STA) Repeated START condition setup
time 4.7 - 0.6 -
tsu(STO) STOP condition setup time 4.0 - 0.6 -
tw(STO:STA) STOP to START condition time (bus
free) 4.7 - 1.3 -
CbCapacitive load for each bus line - 400 - 400 pF
Electrical parameters STM8AL31E8x STM8AL3LE8x
104/133 DocID027180 Rev 5
Figure 41. Typical application with I2C bus and timing diagram(1))
1. Measurement points are done at CMOS levels: 0.3 x VDD and 0.7 x VDD
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DocID027180 Rev 5 105/133
STM8AL31E8x STM8AL3LE8x Electrical parameters
119
9.3.9 LCD controller (STM8AL3LE8x only)
In the following table, data are guaranteed by design, not tested in production.
VLCD external capacitor (STM8AL3LE8x only)
The application achieves a stabilized LCD reference voltage when connecting an external
capacitor CEXT to the VLCD pin. CEXT is specified in Table 48.
Table 48. LCD characteristics
Symbol Parameter Min. Typ. Max. Unit
VLCD LCD external voltage - - 3.6
V
VLCD0 LCD internal reference voltage 0 - 2.6 -
VLCD1 LCD internal reference voltage 1 - 2.7 -
VLCD2 LCD internal reference voltage 2 - 2.8 -
VLCD3 LCD internal reference voltage 3 - 3.0 -
VLCD4 LCD internal reference voltage 4 - 3.1 -
VLCD5 LCD internal reference voltage 5 - 3.2 -
VLCD6 LCD internal reference voltage 6 - 3.4 -
VLCD7 LCD internal reference voltage 7 - 3.5 -
CEXT VLCD external capacitance 0.1 1 2 µF
IDD
Supply current(1) at VDD = 1.8 V
1. LCD enabled with 3 V internal booster (LCD_CR1 = 0x08), 1/4 duty, 1/3 bias, division ratio= 64, all pixels
active, no LCD connected.
-3 -
µA
Supply current(1) at VDD = 3 V - 3 -
RHN(2)
2. RHN is the total high value resistive network.
High value resistive network (low drive) - 6.6 - MΩ
RLN(3)
3. RLN is the total low value resistive network.
Low value resistive network (high drive) - 240 - kΩ
V33 Segment/Common higher level voltage - - VLCDx
V
V34 Segment/Common 3/4 level voltage - 3/4VLCDx -
V23 Segment/Common 2/3 level voltage - 2/3VLCDx -
V12 Segment/Common 1/2 level voltage - 1/2VLCDx -
V13 Segment/Common 1/3 level voltage - 1/3VLCDx -
V14 Segment/Common 1/4 level voltage - 1/4VLCDx -
V0Segment/Common lowest level voltage 0 --
Electrical parameters STM8AL31E8x STM8AL3LE8x
106/133 DocID027180 Rev 5
9.3.10 Embedded reference voltage
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
Table 49. Reference voltage characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
IREFINT
Internal reference voltage
consumption - - 1.4 - µA
TS_VREFINT(1)(2) ADC sampling time when reading the
internal reference voltage --510µs
IBUF(1) Internal reference voltage buffer
consumption (used for ADC) - - 13.5 25 µA
VREFINT out Reference voltage output - 1.202
(3) 1.224 1.242
(3) V
ILPBUF(1)
Internal reference voltage low-power
buffer consumption (used for
comparators or output)
- - 730 1200 nA
IREFOUT(1)(4) Buffer output current - - - 1 µA
CREFOUT Reference voltage output load - - - 50 pF
tVREFINT(1) Internal reference voltage startup
time --23ms
tBUFEN(1)(2) Internal reference voltage buffer
startup time once enabled ---10µs
ACCVREFINT(5) Accuracy of VREFINT stored in the
VREFINT_Factory_CONV byte ---± 5mV
STABVREFINT
Stability of VREFINT over temperature -40 °C ≤ TA ≤ 125 °C - 20 50 ppm/°C
Stability of VREFINT over temperature 0 °C ≤ TA ≤ 50 °C - - 20 ppm/°C
STABVREFINT Stability of VREFINT after 1000 hours - - - TBD ppm
1. Guaranteed by design.
2. Defined when ADC output reaches its final value ±1/2LSB
3. Tested in production at VDD = 3 V ±10 mV.
4. To guarantee less than 1% VREFOUT deviation
5. Measured at VDD = 3 V ±10 mV. This value takes into account VDD accuracy and ADC conversion accuracy.
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STM8AL31E8x STM8AL3LE8x Electrical parameters
119
9.3.11 Temperature sensor
In the following table, data are based on characterization results, not tested in production,
unless otherwise specified.
9.3.12 Comparator characteristics
In the following table, data are guaranteed by design, not tested in production.
Table 50. TS characteristics
Symbol Parameter Min. Typ. Max. Unit
V125 (1)
1. Tested in production at VDD = 3 V ±10 mV. The 8 LSB of the V125 ADC conversion result are stored in the
TS_Factory_CONV_V125 byte.
Sensor reference voltage at 125°C
±5 °C, 0.640 0.660 0.680 V
TLVSENSOR linearity with temperature - ±1 ±2 °C
Avg_slope Average slope 1.59(2)
2. Guaranteed by design.
1.62 1.65(2) mV/°C
IDD(TEMP) Consumption - 3.4 6(2) µA
TSTART(3)
3. Defined for ADC output reaching its final value ±1/2LSB.
Temperature sensor startup time - - 10(2) µs
TS_TEMP
ADC sampling time when reading the
temperature sensor -510
(2) µs
Table 51. Comparator 1 characteristics
Symbol Parameter Conditions Min(1) Typ Max(1)
1. Guaranteed by characterization results .
Unit
VDDA Analog supply voltage - 1.65 3.6 V
R400K R400K value - - 400 -
kΩ
R10K R10K value - - 10 -
VIN
Comparator 1 input
voltage range -0.6 V
DDA V
tSTART Comparator startup time - - 7 10
µs
td Propagation delay(2)
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
--310
Voffset Comparator offset - - ±3±10 mV
dVoffset/dt
Comparator offset
variation in worst voltage
stress conditions
VDDA = 3.6 V
VIN+ = 0 V
VIN- = VREFINT
TA = 25 °C
0 1.5 10 mV/1000 h
ICOMP1 Current consumption(3)
3. Comparator consumption only. Internal reference voltage not included.
- - 160 260 nA
Electrical parameters STM8AL31E8x STM8AL3LE8x
108/133 DocID027180 Rev 5
In the following table, data are guaranteed by design, not tested in production, unless
otherwise specified.
Table 52. Comparator 2 characteristics
Symbol Parameter Conditions Min Typ Max(1)
1. Guaranteed by characterization results.
Unit
VDDA Analog supply voltage - 1.65 - 3.6 V
VIN Comparator 2 input voltage range - 0 - VDDA V
tSTART Comparator startup time
Fast mode - 15 20
µs
Slow mode - 20 25
td slow Propagation delay(2) in slow mode
2. The delay is characterized for 100 mV input step with 10 mV overdrive on the inverting input, the non-
inverting input set to the reference.
1.65 V ≤ VDDA ≤ 2.7 V - 1.8 3.5
2.7 V ≤ VDDA ≤ 3.6 V - 2.5 6
td fast Propagation delay(2) in fast mode
1.65 V ≤ VDDA ≤ 2.7 V - 0.8 2
2.7 V ≤ VDDA ≤ 3.6 V - 1.2 4
Voffset Comparator offset error - - ±4±20 mV
dThreshold/dt Threshold voltage temperature
coefficient
VDDA = 3.3V
TA = 0 to 50 °C
V- = VREF+, 3/4
VREF+,
1/2 VREF+, 1/4 VREF+.
-15 30
ppm
/°C
ICOMP2 Current consumption(3)
3. Comparator consumption only. Internal reference voltage (necessary for comparator operation) is not
included.
Fast mode - 3.5 5
µA
Slow mode - 0.5 2
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STM8AL31E8x STM8AL3LE8x Electrical parameters
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9.3.13 12-bit DAC characteristics
In the following table, data are guaranteed by design, not tested in production.
Table 53. DAC characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
VDDA Analog supply voltage - 1.8 - 3.6
V
VREF+ Reference supply voltage - 1.8 - VDDA
IVREF
Current consumption on VREF+
supply
VREF+ = 3.3 V, no
load, middle code
(0x800)
- 130 220
µA
VREF+ = 3.3 V, no
load, worst code
(0x000)
- 220 350
IVDDA
Current consumption on VDDA
supply
VDDA = 3.3 V, no
load, middle code
(0x800)
- 210 320
VDDA = 3.3 V, no
load, worst code
(0x000)
- 320 520
TATemperature range - -40 - 125 °C
RL(1) (2) Resistive load DACOUT buffer ON 5 - kΩ
ROOutput impedance DACOUT buffer OFF - 8 10 kΩ
CL(3) Capacitive load - - - 50 pF
DAC_OUT
(4) DAC_OUT voltage
DACOUT buffer ON 0.2 - VDDA - 0.2 V
DACOUT buffer OFF 0 - VREF+ -1 LSB V
tsettling
Settling time (full scale: for a 12-
bit input code transition between
the lowest and the highest input
codes when DAC_OUT reaches
the final value ±1LSB)
RL ≥5 kΩ, CL≤ 50 pF - 7 12 µs
Update rate
Max frequency for a correct
DAC_OUT (@95%) change
when small variation of the input
code (from code i to i+1LSB).
RL ≥ 5 kΩ, CL ≤ 50 pF - - 1 Msps
tWAKEUP
Wakeup time from OFF state.
Input code between lowest and
highest possible codes.
RL ≥5 kΩ, CL≤ 50 pF - 9 15 µs
PSRR+ Power supply rejection ratio (to
VDDA) (static DC measurement)RL≥ 5 kΩ, CL≤ 50 pF --60 -35 dB
1. Resistive load between DACOUT and GNDA
2. Output on PF0 or PF1
3. Capacitive load at DACOUT pin
4. It gives the output excursion of the DAC
Electrical parameters STM8AL31E8x STM8AL3LE8x
110/133 DocID027180 Rev 5
In the following table, data are based on characterization results, not tested in production.
Table 54. DAC accuracy
Symbol Parameter Conditions Typ. Max.(1) Unit
DNL Differential non linearity(2)
RL ≥5 kΩ, CL≤ 50 pF
DACOUT buffer ON(3) 1.5 3
12-bit
LSB
No load
DACOUT buffer OFF 1.5 3
INL Integral non linearity(4)
RL ≥5 kΩ, CL≤ 50 pF
DACOUT buffer ON(3) 24
No load
DACOUT buffer OFF 24
Offset Offset error(5)
RL ≥5 kΩ, CL≤ 50 pF
DACOUT buffer ON(3) ±10 ±25
No load
DACOUT buffer OFF ±5 ±8
Offset1 Offset error at Code 1 (6) DACOUT buffer OFF ±1.5 ±5
Gain error Gain error(7)
RL ≥5 kΩ, CL≤ 50 pF
DACOUT buffer ON(3) +0.1/-0.2 +0.2/-0.5
%
No load
DACOUT buffer OFF +0/-0.2 +0/-0.4
TUE Total unadjusted error
RL ≥5 kΩ, CL≤ 50 pF
DACOUT buffer ON(3) 12 30 12-bit
LSB
No load -DACOUT buffer OFF 8 12
1. Not tested in production.
2. Difference between two consecutive codes - 1 LSB.
3. In 48-pin package devices the DAC2 output buffer must be kept off and no load must be applied on the DAC_OUT2 output.
4. Difference between measured value at Code i and the value at Code i on a line drawn between Code 0 and last Code 1023.
5. Difference between the value measured at Code (0x800) and the ideal value = VREF+/2.
6. Difference between the value measured at Code (0x001) and the ideal value.
7. Difference between the ideal slope of the transfer function and the measured slope computed from Code 0x000 and 0xFFF
when buffer is ON, and from Code giving 0.2 V and (VDDA -0.2) V when buffer is OFF.
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STM8AL31E8x STM8AL3LE8x Electrical parameters
119
In the following table, data are guaranteed by design, not tested in production.
Table 55. DAC output on PB4-PB5-PB6(1)
1. 32 or 28-pin packages only. The DAC channel is routed either on PB4, PB5 or PB6 using the routing
interface I/O switch registers.
Symbol Parameter Conditions Max Unit
Rint
Internal resistance
between DAC output and
PB4-PB5-PB6 output
2.7 V < VDD < 3.6 V 1.4
kΩ
2.4 V < VDD < 3.6 V 1.6
2.0 V < VDD < 3.6 V 3.2
1.8 V < VDD < 3.6 V 8.2
Electrical parameters STM8AL31E8x STM8AL3LE8x
112/133 DocID027180 Rev 5
9.3.14 12-bit ADC1 characteristics
In the following table, data are guaranteed by design, not tested in production.
Table 56. ADC1 characteristics
Symbol Parameter Conditions Min. Typ. Max. Unit
VDDA Analog supply voltage - 1.8 - 3.6 V
VREF+ Reference supply
voltage
2.4 V ≤ VDDA≤ 3.6 V 2.4 - VDDA V
1.8 V≤ VDDA≤ 2.4 V VDDA V
VREF- Lower reference voltage - VSSA V
IVDDA
Current on the VDDA
input pin - - 1000 1450 µA
IVREF+
Current on the VREF+
input pin
--
400
700
(peak)(1) µA
-- 450
(average)(1) µA
VAIN Conversion voltage
range -0(2) -VREF+
TATemperature range - -40 - 125 °C
RAIN External resistance on
VAIN
on PF0/1/2/3 fast
channels --
50(3) kΩ
on all other channels - -
CADC Internal sample and hold
capacitor
on PF0/1/2/3 fast
channels -
16
-
pF
on all other channels - -
fADC ADC sampling clock
frequency
2.4 V≤ VDDA≤ 3.6 V
without zooming 0.320 - 16 MHz
1.8 V≤ VDDA≤ 2.4 V
with zooming 0.320 - 8 MHz
fCONV 12-bit conversion rate
VAIN on PF0/1/2/3 fast
channels --
1(3)(4) MHz
VAIN on all other
channels --
760(3)(4) kHz
fTRIG External trigger
frequency ---
tconv 1/fADC
tLAT External trigger latency - - - 3.5 1/fSYSCLK
DocID027180 Rev 5 113/133
STM8AL31E8x STM8AL3LE8x Electrical parameters
119
tSSampling time
VAIN PF0/1/2/3 fast
channels
VDDA < 2.4 V
0.43(3)(4) --
µs
VAIN PF0/1/2/3 fast
channels
2.4 V ≤ VDDA≤ 3.6 V
0.22(3)(4) --
VAIN on slow channels
VDDA < 2.4 V 0.86(3)(4) --
VAIN on slow channels
2.4 V ≤ VDDA≤ 3.6 V 0.41(3)(4) --
tconv 12-bit conversion time
- 12000000 / fADC + tS
16 MHz 1(3) --
tWKUP Wakeup time from OFF
state ---3
tIDLE(5) Time before a new
conversion ---∞s
tVREFINT
Internal reference
voltage startup time ---
refer to
Table 49 ms
1. The current consumption through VREF is composed of two parameters:
- one constant (max 300 µA)
- one variable (max 400 µA), only during sampling time + 2 first conversion pulses.
So, peak consumption is 300+400 = 700 µA and average consumption is 300 + [(4 sampling + 2) /16] x 400 = 450 µA at
1Msps
2. VREF- must be tied to ground.
3. Minimum sampling and conversion time is reached for maximum RAIN= 0.5 kΩ. .
4. Value obtained for continuous conversion on fast channel.
5. In the RM0031, tIDLE defines the time between 2 conversions, or between ADC ON and the first conversion. tIDLE is not
relevant for this device.
Table 56. ADC1 characteristics (continued)
Symbol Parameter Conditions Min. Typ. Max. Unit
Electrical parameters STM8AL31E8x STM8AL3LE8x
114/133 DocID027180 Rev 5
In the following three tables, data are guaranteed by characterization result, not tested in
production.
Table 57. ADC1 accuracy with VDDA = 3.3 V to 2.5 V
Symbol Parameter Conditions Typ. Max.(1)
1. Guaranteed by characterization results.
Unit
DNL Differential non linearity
fADC = 16 MHz 1 1.6
LSB
fADC = 8 MHz 1 1.6
fADC = 4 MHz 1 1.5
INL Integral non linearity
fADC = 16 MHz 1.2 2
fADC = 8 MHz 1.2 1.8
fADC = 4 MHz 1.2 1.7
TUE Total unadjusted error
fADC = 16 MHz 2.2 3.0
fADC = 8 MHz 1.8 2.5
fADC = 4 MHz 1.8 2.3
Offset Offset error
fADC = 16 MHz 1.5 2
LSB
fADC = 8 MHz 1 1.5
fADC = 4 MHz 0.7 1.2
Gain Gain error
fADC = 16 MHz
11.5fADC = 8 MHz
fADC = 4 MHz
Table 58. ADC1 accuracy with VDDA = 2.4 V to 3.6 V
Symbol Parameter Typ. Max.(1)
1. Guaranteed by characterization results.
Unit
DNL Differential non linearity 1 2 LSB
INL Integral non linearity 1.7 3 LSB
TUE Total unadjusted error 2 4 LSB
Offset Offset error 1 2 LSB
Gain Gain error 1.5 3 LSB
Table 59. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V
Symbol Parameter Typ. Max.(1) Unit
DNL Differential non linearity 1 2 LSB
INL Integral non linearity 2 3 LSB
TUE Total unadjusted error 3 5 LSB
DocID027180 Rev 5 115/133
STM8AL31E8x STM8AL3LE8x Electrical parameters
119
Figure 42. ADC1 accuracy characteristics
Figure 43. Typical connection diagram using the ADC
1. Refer to Table 56 for the values of RAIN and CADC.
2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the
pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy
this, fADC should be reduced.
General PCB design guidelines
Power supply decoupling should be performed as shown in Figure 44 or Figure 45,
depending on whether VREF+ is connected to VDDA or not. Good quality ceramic 10 nF
capacitors should be used. They should be placed as close as possible to the chip.
Offset Offset error 2 3 LSB
Gain Gain error 2 3 LSB
1. Guaranteed by characterization results.
Table 59. ADC1 accuracy with VDDA = VREF+ = 1.8 V to 2.4 V (continued)
Symbol Parameter Typ. Max.(1) Unit
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Figure 44. Power supply and reference decoupling (VREF+ not connected to VDDA)
Figure 45. Power supply and reference decoupling (VREF+ connected to VDDA)
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STM8AL31E8x STM8AL3LE8x Electrical parameters
119
9.3.15 EMC characteristics
Susceptibility tests are performed on a sample basis during product characterization.
Functional EMS (electromagnetic susceptibility)
Based on a simple running application on the product (toggling 2 LEDs through I/O ports),
the product is stressed by two electromagnetic events until a failure occurs (indicated by the
LEDs).
•ESD: Electrostatic discharge (positive and negative) is applied on all pins of the device
until a functional disturbance occurs. This test conforms to the ANSI/ESDA/JEDEC JS-
001, JESD22-A115 and ANSI/ESD S5.3.1.
•FTB: A burst of fast transient voltage (positive and negative) is applied to VDD and VSS
through a 100 pF capacitor, until a functional disturbance occurs. This test conforms
with the IEC 61000 standard.
A device reset allows normal operations to be resumed. The test results are given in the
table below based on the EMS levels and classes defined in application note AN1709.
Designing hardened software to avoid noise problems
EMC characterization and optimization are performed at component level with a typical
application environment and simplified MCU software. It should be noted that good EMC
performance is highly dependent on the user application and the software in particular.
Therefore it is recommended that the user applies EMC software optimization and
prequalification tests in relation with the EMC level requested for his application.
Prequalification trials:
Most of the common failures (unexpected reset and program counter corruption) are
reproduced by manually forcing a low state on the NRST pin or the Oscillator pins for 1
second.
To complete these trials, ESD stress is applied directly on the device, over the range of
specification values. When unexpected behavior is detected, the software is hardened to
prevent unrecoverable errors occurring (see application note AN1015).
Table 60. EMS data
Symbol Parameter Conditions Level/
Class
VFESD
Voltage limits to be applied on
any I/O pin to induce a functional
disturbance
VDD = 3.3 V, TA = +25 °C,
fCPU= 16 MHz,
conforms to IEC 61000
2B
VEFTB
Fast transient voltage burst limits
to be applied through 100 pF on
VDD and VSS pins to induce a
functional disturbance
VDD = 3.3 V, TA = +25 °C,
fCPU = 16 MHz,
conforms to IEC 61000
Using HSI 4A
Using HSE 2B
Electrical parameters STM8AL31E8x STM8AL3LE8x
118/133 DocID027180 Rev 5
Electromagnetic interference (EMI)
Based on a simple application running on the product (toggling 2 LEDs through the I/O
ports), the product is monitored in terms of emission. This emission test is in line with the
norm IEC61967-2 which specifies the board and the loading of each pin.
Absolute maximum ratings (electrical sensitivity)
Based on two different tests (ESD and LU) using specific measurement methods, the
product is stressed in order to determine its performance in terms of electrical sensitivity.
For more details, refer to the application note AN1181.
Electrostatic discharge (ESD)
Electrostatic discharges (a positive then a negative pulse separated by 1 second) are
applied to the pins of each sample according to each pin combination. The sample size
depends on the number of supply pins in the device (3 parts*(n+1) supply pin). Two models
are simulated: human body model and charge device model. This test conforms to the
ANSI/ESDA/JEDEC JS-001, JESD22-A115 and ANSI/ESD S5.3.1.
Table 61. EMI data (1)
1. Guaranteed by characterization results.
Symbol Parameter Conditions Monitored
frequency band
Max vs.
Unit
16 MHz
SEMI Peak level
VDD = 3.6 V,
TA = +25 °C,
LQFP80
conforming to
IEC61967-2
0.1 MHz to 30 MHz 10
dBμV30 MHz to 130 MHz 4
130 MHz to 1 GHz 1
EMI Level 1.5 -
Table 62. ESD absolute maximum ratings
Symbol Ratings Conditions Class Maximum
value (1)
1. Guaranteed by characterization results.
Unit
VESD(HBM) Electrostatic discharge voltage
(human body model)
TA = 25 °C, conforming
to ANSI/ESDA/
JEDEC JS-001
2 2000
V
VESD(CDM) Electrostatic discharge voltage
(charge device model)
TA = 25 °C, conforming
to ANSI/ESD S5.3.1 C4B 500
VESD(MM) Electrostatic discharge voltage
(machine model)
TA = 25 °C, conforming
to JESD22-A115 M2 200
DocID027180 Rev 5 119/133
STM8AL31E8x STM8AL3LE8x Electrical parameters
119
Static latch-up
•LU: 3 complementary static tests are required on 10 parts to assess the latch-up
performance. A supply overvoltage (applied to each power supply pin) and a current
injection (applied to each input, output and configurable I/O pin) are performed on each
sample. This test conforms to the EIA/JESD 78 IC latch-up standard. For more details,
refer to the application note AN1181.
9.4 Thermal characteristics
The maximum chip junction temperature (TJmax) must never exceed the values given in
Table 19: General operating conditions on page 69.
The maximum chip-junction temperature, TJmax, in degree Celsius, may be calculated using
the following equation:
TJmax = TAmax + (PDmax x Θ
JA)
Where:
•TAmax is the maximum ambient temperature in °C
•Θ
JA is the package junction-to-ambient thermal resistance in °C/W
•PDmax is the sum of PINTmax and PI/Omax (PDmax = PINTmax + PI/Omax)
•PINTmax is the product of IDD and VDD, expressed in Watts. This is the maximum chip
internal power.
•PI/Omax represents the maximum power dissipation on output pins
Where:
PI/Omax = Σ (VOL*IOL) + Σ((VDD-VOH)*I OH),
taking into account the actual VOL/IOL and VOH/IOH of the I/Os at low and high-level in
the application.
Table 63. Electrical sensitivities
Symbol Parameter Conditions Class (1)
1. Class description: the class is an STMicroelectronics internal specification. The class limits are higher than
the JEDEC specifications, that means when a device belongs to class A it exceeds the JEDEC standard. B
class strictly covers all the JEDEC criteria (international standard).
LU Static latch-up class TA = 125 °C A
Table 64. Thermal characteristics(1)
1. Thermal resistances are based on JEDEC JESD51-2 with 4-layer PCB in a natural convection
environment.
Symbol Parameter Value Unit
Θ
JA
Thermal resistance junction-ambient
LQFP48 - 7 x 7 mm 65 °C/W
Θ
JA
Thermal resistance junction-ambient
LQFP 64- 10 x 10 mm 48 °C/W
Θ
JA
Thermal resistance junction-ambient
LQFP 80- 14 x 14 mm 38 °C/W
Package information STM8AL31E8x STM8AL3LE8x
120/133 DocID027180 Rev 5
10 Package information
In order to meet environmental requirements, ST offers these devices in different grades of
ECOPACK® packages, depending on their level of environmental compliance. ECOPACK®
specifications, grade definitions and product status are available at: www.st.com.
ECOPACK® is an ST trademark.
10.1 LQFP80 package information
Figure 46. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package outline
1. Drawing is not to scale.
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STM8AL31E8x STM8AL3LE8x Package information
131
Table 65. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package
mechanical data(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Symbol
millimeters inches
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.220 0.320 0.380 0.0087 0.0126 0.0150
c 0.090 - 0.200 0.0035 - 0.0079
D 15.800 16.000 16.200 0.6220 0.6299 0.6378
D1 13.800 14.000 14.200 0.5433 0.5512 0.5591
D3 - 12.350 - - 0.4862 -
E 15.800 16.000 16.200 0.6220 0.6299 0.6378
E1 13.800 14.000 14.200 0.5433 0.5512 0.5591
E3 - 12.350 - - 0.4862 -
e - 0.650 - - 0.0256 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0°3.5°7° 0°3.5°7°
ccc - - 0.100 - - 0.0039
Package information STM8AL31E8x STM8AL3LE8x
122/133 DocID027180 Rev 5
Figure 47. LQFP80 - 80-pin, 14 x 14 mm low-profile quad flat package
recommended footprint
1. Dimensions are expressed in millimeters.
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
4@'1
DocID027180 Rev 5 123/133
STM8AL31E8x STM8AL3LE8x Package information
131
Figure 48. LQFP80 marking example (package top view)
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted to run a qualification activity prior to any decision to
use these engineering samples.
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124/133 DocID027180 Rev 5
10.2 LQFP64 package information
Figure 49. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package outline
1. Drawing is not to scale.
Table 66. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D - 12.000 - - 0.4724 -
D1 - 10.000 - - 0.3937 -
D3 - 7.500 - - 0.2953 -
E - 12.000 - - 0.4724 -
E1 - 10.000 - - 0.3937 -
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DocID027180 Rev 5 125/133
STM8AL31E8x STM8AL3LE8x Package information
131
Figure 50. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat package
recommended footprint
1. Dimensions are expressed in millimeters.
E3 - 7.500 - - 0.2953 -
e - 0.500 - - 0.0197 -
K 0°3.5°7° 0°3.5°7°
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
ccc - - 0.080 - - 0.0031
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Table 66. LQFP64 - 64-pin, 10 x 10 mm low-profile quad flat
package mechanical data (continued)
Symbol
millimeters inches(1)
Min Typ Max Min Typ Max
AIC
Package information STM8AL31E8x STM8AL3LE8x
126/133 DocID027180 Rev 5
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 51. LQFP64 marking example (package top view)
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted to run a qualification activity prior to any decision to
use these engineering samples.
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DocID027180 Rev 5 127/133
STM8AL31E8x STM8AL3LE8x Package information
131
10.3 LQFP48 package information
Figure 52. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package outline
1. Drawing is not to scale.
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128/133 DocID027180 Rev 5
Table 67. LQFP48 - 48-pin, 7 x 7 mm low-profile quad flat package
mechanical data
Symbol
millimeters inches(1)
1. Values in inches are converted from mm and rounded to 4 decimal digits.
Min Typ Max Min Typ Max
A - - 1.600 - - 0.0630
A1 0.050 - 0.150 0.0020 - 0.0059
A2 1.350 1.400 1.450 0.0531 0.0551 0.0571
b 0.170 0.220 0.270 0.0067 0.0087 0.0106
c 0.090 - 0.200 0.0035 - 0.0079
D 8.800 9.000 9.200 0.3465 0.3543 0.3622
D1 6.800 7.000 7.200 0.2677 0.2756 0.2835
D3 - 5.500 - - 0.2165 -
E 8.800 9.000 9.200 0.3465 0.3543 0.3622
E1 6.800 7.000 7.200 0.2677 0.2756 0.2835
E3 - 5.500 - - 0.2165 -
e - 0.500 - - 0.0197 -
L 0.450 0.600 0.750 0.0177 0.0236 0.0295
L1 - 1.000 - - 0.0394 -
k 0°3.5°7° 0°3.5°7°
ccc - - 0.080 - - 0.0031
Package information STM8AL31E8x STM8AL3LE8x
130/133 DocID027180 Rev 5
Device marking
The following figure gives an example of topside marking orientation versus pin 1 identifier
location.
Other optional marking or inset/upset marks, which identify the parts throughout supply
chain operations, are not indicated below.
Figure 54. LQFP48 marking example (package top view)
1. Parts marked as “ES”,”E” or accompanied by an Engineering Sample notification letter are not yet qualified
and therefore not approved for use in production. ST is not responsible for any consequences resulting
from such use. In no event will ST be liable for the customer using any of these engineering samples in
production. ST’s Quality department must be contacted to run a qualification activity prior to any decision to
use these engineering samples.
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DocID027180 Rev 5 131/133
STM8AL31E8x STM8AL3LE8x Ordering information
131
11 Ordering information
For a list of available options (e.g. memory size, package) and orderable part numbers or for
further information on any aspect of this device, please go to www.st.com or contact the
nearest ST sales office.
Table 68. STM8AL31E8x STM8AL3LE8x ordering information scheme
Example: STM8 AL 31 E 8 8 T C Y
Device family
STM8 microcontroller
Product type
AL = automotive low-power(1)
1. Qualified and characterized according to AECQ100 and Q003 or equivalent, advanced screening
according to AEC Q001 and Q002 or equivalent.
Device subfamily
31: standard devices
3L: devices with LCD
AES encryption hardware accelerator
E = AES encryption hardware accelerator
Program memory size
8 = 64 Kbytes of Flash memory
Pin count
A = 80 pins
9 = 64 pins
8 = 48 pins
Package
T = LQFP
Temperature range
C = -40 to 125 °C
A = -40 to 85 °C
Packing
Y = tray
X = Tape and reel compliant with EIA 481-C
Revision history STM8AL31E8x STM8AL3LE8x
132/133 DocID027180 Rev 5
12 Revision history
Table 69. Document revision history
Date Revision Changes
22-Apr-2015 1 Initial release.
27-Jul-2015 2 Updated the document confidentiality level to “Public”.
No other changes in the content.
19-Aug-2015 3
Changed datasheet status to “production data”.
Added LQFP64 and LQFP80 packages together with
the corresponding part numbers.
18-Oct-2016 4
– Updated Table 5: High-density STM8AL3xE8x pin
description: pin name changed from
PC3/USART1_TX/LCD_SEG23(3)/ADC1_IN5/COMP
_IN3M/COMP2_INM/COMP1_INP to
PC3/USART1_TX/LCD_SEG23(3)/ADC1_IN5/COMP
2_INM/COMP1_INP.
– Added footnote to Table 68: STM8AL31E8x
STM8AL3LE8x ordering information scheme.
– Updated Section : Device marking on page 122,
Section : Device marking on page 126, Section :
Device marking on page 130
– Updated Section 9.2: Absolute maximum ratings
– Updated Figure 12: Power supply thresholds.
5-Dec-2016 5
– Updated Table 5: High-density STM8AL3xE8x pin
description: two pin names changed from
PI0/RTC_TAMP1/[SPI2_NSS]/[TIM3_CH3 to
PI0/RTC_TAMP1/[SPI2_NSS]/[TIM3_CH1
and from
PF2/ADC1_IN26/[SPI2_SCK]/[USART3_SCK] to
PF2/ADC1_IN26/[SPI1_SCK]/[USART3_SCK]
DocID027180 Rev 5 133/133
STM8AL31E8x STM8AL3LE8x
133
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