2010 Microchip Technology Inc. DS22244B-page 1
MCP4801/4811/4821
Features
• MCP4801: 8-Bit Voltage Output DAC
• MCP4811: 10-Bit Voltage Output DAC
• MCP4821: 12-Bit Voltage Output DAC
• Rail-to-Rail Output
• SPI Interface with 20 MHz Cloc k Supp ort
• Simultaneous Latching of the DAC Output
with LDAC Pin
• Fast Settling Time of 4.5 µs
• Selectable Unity or 2x Gain Out put
• 2.048V Internal Voltage Reference
•50ppm/°C V
REF Temperature Coefficient
• 2.7V to 5.5V Single-Supply Operation
• Extended Temperature Range: -40°C to +125°C
Applications
• Set Point or Offset Trimming
• Sensor C alibration
• Precision Selectable Voltage Reference
• Port ab le Instrum en t ati on (Battery-Powered)
• Calibration of Optical Communication Devices
Description
The MCP4801/4811/4821 devices are single channel
8-bit, 10-bit and 12-bit buffered voltage output
Digital-to-Analog Converters (DACs), respectively. The
devices operate from a single 2.7V to 5.5V supply with
an SPI compatible Serial Peri pheral Interface.
The devices have a high precision internal voltage
reference (VREF = 2.048V). The user can configure the
full-scale range of the dev ice to be 2.048V or 4.09 6V by
setting the Gain Selection Option bit (gain of 1 of 2).
The devices can be operated in Active or Shutdown
mode by setting a Configuration register bit or using the
SHDN pin. In Shutdown mode, most of the internal
circuits, including the output amplifier, are turned off for
power savings, while the ampl ifier output (VOUT) stage is
configured to present a known high resistance output
load (500 k typical.
The devices include double-buffered registers,
allowing a synchronous update of the DAC output
using the LDAC pin. These devices also incorporate a
Power-on Reset (POR) circuit to ensure reliable power-
up.
The devices utilize a resistive string architecture, with
its inherent advantages of low DNL error, low ratio
metric temperature coefficient and fast settling time.
These devices are specified over the extended
temperat ure range (+125°C).
The devices provide high accuracy and low noise
performance for consumer and industrial applications
where calibration or compensation of signals (such as
temperature, pressure and humidity) are required.
The MCP4801/4811/4821 devices are available in the
PDIP, SOIC, MSOP and DFN packages.
Related Products(1)
P/N DAC
Resolution No. of
Channel
Voltage
Reference
(VREF)
MCP4801 8 1
Internal
(2.048V)
MCP4811 10 1
MCP4821 12 1
MCP4802 8 2
MCP4812 10 2
MCP4822 12 2
MCP4901 8 1
External
MCP4911 10 1
MCP4921 12 1
MCP4902 8 2
MCP4912 10 2
MCP4922 12 2
Note 1: The products listed here have similar
AC/ DC performances.
8/10/12-Bit Voltage Output Digital-to-Analog Converter
with Internal VREF and SPI Interface
MCP4801/4811/4821
DS22244B-page 2 2010 Microchip Technology Inc.
Package Types
Block Diagram
DFN (2x3)*
1
2
3
4
8
7
6
5
CS
SCK
SDI
V
DD
VSS
VOUT
SHDN
LDAC
MCP4801: 8-bit single DAC
MCP4811: 10-bit single DAC
MCP4821: 12-bit single DAC
MCP48X1
PDIP, SOIC, MSOP
1
2
3
4
8
7
6
5
CS
SCK
SDI
VDD
VSS
VOUT
SHDN
LDAC
9
* Includes Exposed Thermal Pad (EP); see Table 3-1.
Op Amp
VDD
VSS
CS SDI SCK
Interface Logic
Input
Register
DAC
Register
String
DAC
Power-on
Reset
VOUT
LDAC
Output Gain
Logic
(2.048V)
SHDN
VREF
Output
Logic
2010 Microchip Technology Inc. DS22244B-page 3
MCP4801/4811/4821
1.0 ELECTRICAL
CHARACTERISTICS
Absolute Maximum Ratings †
VDD............................................................................................................. 6.5V
All inputs and outputs .....................VSS – 0.3V to VDD + 0.3V
Current at Input Pins ....................................................±2 mA
Current at Supply Pins ...............................................±50 mA
Curren t at Output Pi n s ................. ..................... .........±25 mA
Storage temperature ..................... .. ..... .... .. .. .-65°C to +150°C
Ambient temp. with power applied. ...............- 55°C to +125°C
ESD protection on all pins 4 kV (HBM), 400V (MM)
Maximum Junction Tem peratur e (TJ)..........................+150°C
† Notice: Stresses above those listed under “Maximum
Ratings” may cause permanent damage to the device. This is
a stress rating only and functional operation of the device at
those or any other conditions above those indicated in the
operational listings of this specification is not implied.
Exposure to m aximum rating conditions for extended pe riods
may affect device reliability.
ELECTR ICAL CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V,
Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF, TA = -40 to +85°C. Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Power Requireme nts
Operati ng Voltage VDD 2.7 — 5.5
Operati ng Curren t IDD — 330 40 0 µA All digit a l inpu t s are grou nded,
analog output (VOUT) is
unloaded. Code = 000h
Hardware Shutdown Current ISHDN — 0.3 2 µA POR circuit is turned off
Software Shutdown Current ISHDN_SW — 3.3 6 µA POR circuit remain s turned on
Power-on Reset Threshold VPOR —2.0— V
DC Accuracy
MCP4801
Resolution n 8 — — Bits
INL Error INL -1 ±0.125 1LSb
DNL DNL -0.5 ±0.1 +0.5 LSb Note 1
MCP4811
Resolution n 10 — — Bits
INL Error INL -3.5 ±0.5 3.5 LSb
DNL DNL -0.5 ±0.1 +0.5 LSb Note 1
MCP4821
Resolution n12 — — Bits
INL Error INL -12 ±2 12 LSb
DNL DNL -0.75 ±0.2 +0.75 LSb Note 1
Offset Error VOS -1 ±0.02 1 % of FSR Code = 0x000h
Offset Error Temperature
Coefficient VOS/°C — 0.16 — ppm/°C -45°C to +25°C
— -0.44 — ppm/°C +25°C to +85°C
Gain Error gE-2 -0.10 2 % of FSR Code = 0xFFFh,
not includin g of fs et error
Gain Error Temperature
Coefficient G/°C — -3 — ppm/°C
Note 1: Guaranteed monotonic by des ig n over all code s.
2: This parameter is ensured by design, and not 100% tested.
MCP4801/4811/4821
DS22244B-page 4 2010 Microchip Technology Inc.
Internal Voltage Reference (VREF)
Internal Refere nc e Voltage VREF 2.008 2.048 2.088 V VOUT when G = 1x and
Code = 0xFFFh
Temperature Coefficient
(Note 2) VREF/°C
— 125 32 5 ppm/°C -40°C to 0°C
— 0.25 0.65 LSb/°C -40°C to 0°C
— 45 160 ppm/°C 0°C to +85°C
— 0.09 0.32 LSb/°C 0°C to +85°C
Output Nois e (VREF Noise) ENREF
(0.1-10 Hz) —290—µV
p-p Code = 0xFFFh, G = 1x
Output Nois e De nsi ty eNREF
(1 kHz) —1.2—µV/Hz Code = 0xFFFh, G = 1x
eNREF
(10 kHz) —1.0—µV/Hz Code = 0xFFFh, G = 1x
1/f Corner Frequency fCORNER —400— Hz
Output Amplifier
Output Swing VOUT — 0.01 to
VDD – 0.04 — V Accuracy is better than 1 LSb
for VOUT = 10 mV to
(VDD –40mV)
Phase Margin PM — 66 — Degree (°) CL = 400 pF, RL =
Slew Rate SR — 0.55 — V/µs
Short Circuit Current ISC —1524mA
Settling Time tSETTLING — 4.5 — µs Within ½ LSb of final value
from ¼ to ¾ full-scale rang e
Dynamic Performance (Note 2)
Major Code Transition Glitch — 45 — nV-s 1 LSb change around major
carry (0111...1111 to
1000...0000)
Digital Feedthrough — <10 — nV-s
ELECTRICAL CHARACTERISTICS (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V,
Output Buffer Gain (G) = 2x, RL = 5 k to GND, CL = 100 pF, TA = -40 to +85°C. Typical values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Note 1: Guaranteed monotonic by des ig n over all code s.
2: This parameter is ensured by design, and not 100% tested.
2010 Microchip Technology Inc. DS22244B-page 5
MCP4801/4811/4821
ELECTR IC AL CHARACTERISTIC WITH EXTENDED TEMPE RATURE
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x,
RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Parameters Sym Min Typ Max Units Conditions
Power Requireme nts
Operati ng Voltage VDD 2.7 — 5.5
Operati ng Current IDD — 350 — µA All digital inputs are grou nded,
analog output (VOUT) is
unloaded. Code = 000h
Hardware Shutdown
Current ISHDN — 1.5 — µA POR circuit is turned off
Softw are Shutdown Current ISHDN_SW — 5 — µA POR circuit remains turned on
Power-on Reset threshold VPOR —1.85— V
DC Accuracy
MCP4801
Resolution n 8 — — Bits
INL Error INL — ±0.25 — LSb
DNL DNL —±0.2 —LSb Note 1
MCP4811
Resolution n 10 — — Bits
INL E rro r INL — ±1 — LSb
DNL DNL — ±0.2 — LSb Note 1
MCP4821
Resolution n12 — — Bits
INL Error INL — ±4 —LSb
DNL DNL — ±0.25 — LSb Note 1
Offset Error VOS — ±0.02 — % of FSR Code = 0x000h
Offset Error Temperature
Coefficient VOS/°C — -5 — ppm/°C +25°C to +125°C
Gain Error gE— -0.10 — % of FSR Code = 0xFFFh,
not including offset error
Gain Error Temperature
Coefficient G/°C — -3 — ppm/°C
Internal Voltage Reference (VREF)
Internal Refere nc e Voltage VREF —2.048— VV
OUT when G = 1x and
Code = 0xFFFh
Temperature Coefficient
(Note 2) VREF/°C — 125 — ppm/°C -40°C to 0°C
— 0.25 — LSb/°C -40°C to 0°C
— 45 — ppm/°C 0°C to +85°C
— 0.09 — LSb/°C 0°C to +85°C
Output Nois e (VREF Noise) ENREF
(0.1 – 10 Hz) —290—µV
p-p Code = 0xFFFh, G = 1x
Output Nois e De nsi ty eNREF
(1 kHz) —1.2—µV/
Hz Code = 0xFFFh, G = 1x
eNREF
(10 kHz) —1.0—µV/
Hz Code = 0xFFFh, G = 1x
1/f Corner Frequency fCORNER —400— Hz
Note 1: Guaranteed monotonic by des ig n over all code s.
2: This parameter is ensured by design, and not 100% tested.
MCP4801/4811/4821
DS22244B-page 6 2010 Microchip Technology Inc.
Output Amplifier
Output Swing VOUT — 0. 01 to
VDD – 0.04 — V Accuracy is better than 1 LSb
for VOUT = 10 mV to (VDD –
40 mV)
Phase Margin PM — 66 — Degree (°) CL = 400 pF, RL =
Slew Rate SR — 0.55 — V/µs
Short Circuit Current ISC —17—mA
Settling Time tSETTLING — 4.5 — µs W ithin ½ LSb of final value from
¼ to ¾ full-scale range
Dynamic Performance (Note 2)
Major Code Transition
Glitch — 45 — nV-s 1 LSb change around major
carry (0111...1111 to
1000...0000)
Digital Feedthrough — <10 — nV-s
AC CHARACTERISTICS (SPI TIMING SPECIFICATIONS)
Electrical Specifications: Unless otherwise indicated, VDD= 2.7V – 5.5V, TA= -40 t o +125°C. Typica l values are at +25°C.
Parameters Sym Min Typ Max Units Conditions
Schmitt Trigger High-Level Input
Volta ge (All dig it al input pins) VIH 0.7 V
DD
——V
Schmitt Trigger Low-Level Input
Volta ge (All dig it al input pins) VIL ——0.2V
DD V
Hysteresis of Schmitt Trigger Inputs VHYS —0.05V
DD —
Input Leakage Current ILEAKAGE -1 — 1 A SHDN = LDAC = CS = SDI =
SCK = VDD or VSS
Digital Pin Capacitance
(All inputs/outputs) CIN,
COUT
—10 —pFV
DD = 5.0V, TA = +25°C,
fCLK = 1 MHz (Note 1)
Clock Frequency FCLK —— 20MHzT
A = +25°C (Note 1)
Clock High Time tHI 15 — — ns Note 1
Clock Low Time tLO 15 — — ns Note 1
CS Fall to First Rising CLK Edge tCSSR 40 — — ns Applies onl y when CS falls with
CLK high. (Note 1)
Data Input Setup Time tSU 15 — — ns Note 1
Data Input Hold Time tHD 10 — — ns Note 1
SCK Rise to CS Rise Hold Time tCHS 15 — — ns Note 1
CS High Time tCSH 15 — — ns Note 1
LDAC Pulse Wid th tLD 100 — — ns Note 1
LDAC Setup T i me tLS 40 — — ns Note 1
SCK Idle Time before CS Fall tIDLE 40 — — ns Note 1
Note 1: This parameter is ensured by design and not 100% tested.
ELECTRICAL CHARACTERISTIC WITH E XTENDED TEMPE RATURE (CONTINUED)
Electrical Specifications: Unless otherwise indicated, VDD = 5V, VSS = 0V, VREF = 2.048V, Output Buffer Gain (G) = 2x,
RL = 5 k to GND, CL = 100 pF. Typical values are at +125°C by characterization or simulation.
Parameters Sym Min Typ Max Units Conditions
Note 1: Guaranteed monotonic by des ig n over all code s.
2: This parameter is ensured by design, and not 100% tested.
2010 Microchip Technology Inc. DS22244B-page 7
MCP4801/4811/4821
FIGURE 1-1: SPI Input Timing Data.
TEMPERATURE CHARACTERISTICS
Electrical Specifications: Unless otherwise indicated, VDD = +2.7V to +5.5V, VSS = GND.
Parameters Sym Min Typ Max Units Conditions
Temperature Ranges
Specifie d Temperatu re Range TA-40 — +125 °C
Operati ng Temperature Ra nge TA-40 — +125 °C Note 1
Storage Temperature Range TA-65 — +150 °C
Thermal Package Resistances
Thermal Resistance, 8L-DFN (2x3) JA —68—°C/W
Thermal Resistance, 8L-MSOP JA —211—°C/W
Thermal Resistance, 8L-PDIP JA —90—°C/W
Thermal Resistance, 8L-SOIC JA — 150 — °C/W
Note 1: The MCP4801/4811/4821 devices operate over this extended temperature range, but with reduced
performance. Operation in this range must not cause TJ to exceed the maximum junction temperature
of +150°C.
CS
SCK
SDI
LDAC
tCSSR
tHD
tSU
tLO
tCSH
tCHS
LSb in
MSb in
tIDLE
Mode 1,1
Mode 0,0
tHI
tLD
tLS
MCP4801/4811/4821
DS22244B-page 8 2010 Microchip Technology Inc.
2.0 TYPICAL PE RFORMANCE CURVES
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
FIGURE 2-1: DNL vs. Code (MCP4821).
FIGURE 2-2: DNL vs. Code and
Temperature (MCP4821).
FIGURE 2-3: Absolute DNL vs.
Temperature (MCP4821).
FIGURE 2-4: INL vs. Code and
Temperature (MCP4821).
FIGURE 2-5: Absolute INL vs.
Temperature (MCP4821).
FIGURE 2-6: INL vs. Code (MCP4 821 ).
Note: The g r ap hs and t ables provided fol low i ng thi s n ote are a statis tic al s umm ar y b as ed on a limited num ber of
samples and are provided for informational purposes only. The performance characteristics listed herein
are not tested or guaranteed. In some graphs or tables, the data presented may be outside the specified
operating range (e.g., outside specified power supply range) and therefore outside the warranted range.
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0 1024 2048 3072 4096
Code (Dec imal)
DNL (LSB)
-0.2
-0.1
0
0.1
0.2
0 1024 2048 3072 4096
Code (Dec imal)
DNL (LSB )
125C 85C 25C
0.075
0.0752
0.0754
0.0756
0.0758
0.076
0.0762
0.0764
0.0766
-40-200 20406080100120
Ambient Te mperature (ºC)
Absolute DNL (LSB)
Note: Single device graph for illustration of 64
code effect.
-5
-4
-3
-2
-1
0
1
2
3
4
5
0 1024 2048 3072 4096
Code (Decimal)
INL (LSB)
125C 85 25
Ambient Temperature
0
0.5
1
1.5
2
2.5
-40 -20 0 20 40 60 80 100 120
Ambient Tem perature (ºC)
Abs olute INL (LSB)
-6
-4
-2
0
2
0 1024 2048 3072 4096
Cod e (Decimal )
IN L (L SB)
2010 Microchip Technology Inc. DS22244B-page 9
MCP4801/4811/4821
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
FIGURE 2-7: DNL vs. Code and
Temperature (MCP4811).
FIGURE 2-8: INL vs. Code and
Temperature (MCP4811).
FIGURE 2-9: DNL vs. Code and
Temperature (MCP4801).
FIGURE 2-10: INL vs. Code and
Temperature (MCP4801).
FIGURE 2-11: Full-Scale VOUT vs. Ambient
Temperature and VDD. Gain = 1x.
FIGURE 2-12: Full-Scale VOUT vs. Ambient
Temperature and VDD. Gain = 2x.
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0 128 256 384 512 640 768 896 1024
Code
DNL (LSB)
- 40oC
+25oC to +125oC
-3
-2.5
-2
-1.5
-1
-0.5
0
0.5
1
1.5
0 128 256 384 512 640 768 896 1024
Code
INL (LSB)
25oC
85oC
125oC- 40oC
-0.15
-0.1
-0.05
0
0.05
0.1
0.15
0 32 64 96 128 160 192 224 256
Code
DNL (LSB)
34
Temperature: - 40oC to +125o
C
-0.3
-0.2
-0.1
0
0.1
0.2
0.3
0.4
0.5
0.6
0 326496128160192224256
Code
INL (LSB)
-
40
oC
25oC
85oC
125oC
2.040
2.041
2.042
2.043
2.044
2.045
2.046
2.047
2.048
2.049
2.050
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (°C)
Full Scale VOUT (V)
VDD: 4V
VDD: 3V
VDD : 2.7V
4.076
4.080
4.084
4.088
4.092
4.096
4.100
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (°C)
Full Sc a le VOUT (V)
VDD: 5.5V
VDD: 5V
MCP4801/4811/4821
DS22244B-page 10 2010 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
FIGURE 2-13: Output Noise Voltage
Density (VREF Noise Density) vs. Frequency.
Gain = 1x.
FIGURE 2-14: Output Noise Voltage
(VREF Noise Voltage) vs. Band width. Gain = 2x .
FIGURE 2-15:
I
DD
vs. Temperature an d V
DD
.
FIGURE 2-16: IDD Histogram (VDD = 2.7V).
FIGURE 2-17: IDD Histogra m (VDD = 5.0V).
1.E-07
1.E-06
1.E-05
1.E-04
1E-1 1E+0 1E+1 1E+2 1E+3 1E+4 1E+5
Frequency (Hz)
Output Noise Voltage Density
(µV/Hz)
0.1
1 10 100 1k 10k 100k
100
10
1
0.1
1.E-05
1.E-04
1.E-03
1.E-02
1E+2 1E+3 1E+4 1E+5 1E+6
Bandwi dth ( Hz)
Output Noise Voltage (mV)
100 1k 10k 100k 1M
Eni (in VRMS)
10.0
1.00
0.10
0.01
Eni (in VP-P)
Ma ximum Measurement Time = 10s
180
200
220
240
260
280
300
320
340
-40-200 20406080100120
Am bi en t Te mpe r at ure (°C )
IDD (µA)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
0
2
4
6
8
10
12
14
16
18
20
265
270
275
280
285
290
295
300
305
310
315
320
>320
IDD (µA)
Occurrence
0
2
4
6
8
10
12
14
16
18
285
290
295
300
305
310
315
320
325
330
335
340
345
350
>350
IDD (µA)
Occurrence
2010 Microchip Technology Inc. DS22244B-page 11
MCP4801/4811/4821
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
FIGURE 2-18: Hardware Shutdown Current
vs. Temperature and VDD.
FIGURE 2-19: Software Shutdown Current
vs. Temperature and VDD.
FIGURE 2-20: Offset Error vs. T emperature
and VDD.
FIGURE 2-21: Gain Error vs. Temperature
and VDD.
FIGURE 2-22: VIN High Threshold vs.
Temperature and VDD.
FIGURE 2-23: VIN Low Threshold vs.
Temperature and VDD.
0
0.1
0.2
0.3
0.4
0.5
0.6
0.7
-40-200 20406080100120
Ambient Temperature (ºC)
ISHDN (µA)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
1
1.5
2
2.5
3
3.5
4
-40-200 20406080100120
Ambient Temperature (ºC)
ISHDN_SW (µA)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
-0.03
-0.01
0.01
0.03
0.05
0.07
0.09
0.11
-40 -20 0 20 40 60 80 100 120
Ambi e n t Temper at u r e ( ºC)
Offset E rror (%)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
-0.5
-0.45
-0.4
-0.35
-0.3
-0.25
-0.2
-0.15
-0.1
-0.05
-40 -20 0 20 40 60 80 100 120
Ambi ent Tem per ature ( ºC)
Gain Error (%)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
1
1.5
2
2.5
3
3.5
4
-40-200 20406080100120
Ambient Temperature (ºC)
VIN Hi Threshold (V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
0.8
0.9
1
1.1
1.2
1.3
1.4
1.5
1.6
-40 -20 0 20 40 60 80 100 120
Ambient Temperature (ºC)
VIN Low Threshold (V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
MCP4801/4811/4821
DS22244B-page 12 2010 Microchip Technology Inc.
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
FIGURE 2-24: Input Hysteresis vs.
Temperature and VDD.
FIGURE 2-25: VOUT High Limit
vs.Temperature and VDD.
FIGURE 2-26: VOUT Low Limit vs.
Temperature and VDD.
FIGURE 2-27: IOUT High Short vs.
Temperature and VDD.
FIGURE 2-28: IOUT vs. VOUT. Gain = 2x.
0
0.25
0.5
0.75
1
1.25
1.5
1.75
2
2.25
2.5
-40-200 20406080100120
Ambien t Temperature (ºC )
VIN_SPI Hy steresis (V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
0.015
0.017
0.019
0.021
0.023
0.025
0.027
0.029
0.031
0.033
0.035
-40-200 20406080100120
Ambient Temperature (ºC )
VOUT_HI Li m it ( VDD-Y)(V)
VDD
4.0V
3.0V
2.7V
0.0010
0.0012
0.0014
0.0016
0.0018
0.0020
0.0022
0.0024
0.0026
0.0028
-40-200 20406080100120
Ambient Temperature (ºC)
VOUT_LOW Limit (Y-AVSS)(V)
VDD
5.5V
4.0V
5.0V
3.0V
2.7V
10
11
12
13
14
15
16
-40 -20 0 20 40 60 80 100 120
Ambient Tempera ture (ºC)
IOUT_HI_SHORTED (mA)
V
DD
5.5V
4
.0V
5.0V
3
.0V
2
.7V
0.0
1.0
2.0
3.0
4.0
5.0
6.0
0246810121416
IOUT (mA)
VOUT (V)
VREF = 4.096V
Output Shorted to VSS
Output Shorted to VDD
2010 Microchip Technology Inc. DS22244B-page 13
MCP4801/4811/4821
Note: Unless otherwise indicated, TA = +25°C, VDD = 5V, VSS = 0V, VREF = 2.048V, Gain = 2, RL = 5 k, CL = 100 pF.
FIGURE 2-29: VOUT Rise Time.
FIGURE 2-30: VOUT Fall Time.
FIGURE 2-31: VOUT Rise Time.
FIGURE 2-32: VOUT Rise Time.
FIGURE 2-33: VOUT Rise Time Exit
Shutdown.
FIGURE 2-34: PSRR vs. Frequency.
VOUT
SCK
LDAC
Time (1 µs/div)
VOUT
SCK
LDAC
Time (1 µs/div)
VOUT
SCK
LDAC
Time (1 µs/div)
Time (1 µs/div)
VOUT
LDAC
Time (1 µs/div)
VOUT
SCK
LDAC
Ripple Rejection (dB)
Frequency (Hz)
MCP4801/4811/4821
DS22244B-page 14 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22244B-page 15
MCP4801/4811/4821
3.0 PIN DESCRIPTIONS
The descriptions of the pins are listed in Table 3-1.
3.1 Supply Voltage Pins (VDD, VSS)
VDD is the po siti ve sup ply v oltage input pin. The i nput
supply voltage is relative to VSS and can range from
2.7V to 5.5V. The power supply at the VDD pin should
be as clean as possible for good DAC performance.
Using an appropriate bypass capacitor of about 0.1 µF
(ceramic) to ground is recommended. An additional
10 µF capacitor (tantalum) in parallel is also recom-
mended to further attenuate high-frequency noise
present in application boards.
VSS is the analog ground pin and the current return
path of the device. The user must connect the VSS pin
to a ground plane through a low-impedance
connec tio n. If an analog ground path i s ava il abl e i n th e
application Printed Circuit Board (PCB), it is highly
recommended that the VSS pin be tied to the analog
ground path or isolated within an analog ground plane
of the circuit board.
3.2 Chip Select (CS)
CS is the Chip Select input pin, which requires an
active low to enable serial clock and data functions.
3.3 Serial Clock Input (SCK)
SCK is the SPI compatible serial clock input pin.
3.4 Serial Data Input (SDI)
SDI is the SPI compatible serial data input pin.
3.5 Latch DAC Input (LDAC)
LDAC (latc h DA C syn c hro ni z at i on in pu t ) pi n is us ed to
transfer the input latch register to the DAC register (out-
put latches, VOUT). When this pin is low, VOUT is
updated with input re gister conte nt. This pin can be tied
to low (VSS) if t he V OUT update is de sir ed a t the risi ng
edge of th e C S p in. This pin can be driv en by an ext er-
nal control device such as an MC U I/O pin.
3.6 Analog Output (VOUT)
VOUT is the DAC analog output pin. The DAC output
has an outp ut amplifier . The full-scale range of the DAC
output is from VSS to G*VREF, where G is the gain
selection option (1x or 2x). The DAC analog output
cannot go higher than the supply voltage (VDD).
3.7 Exposed Thermal Pad (EP)
There is an internal electrical connection between the
exposed thermal pad (EP) and the VSS pin. They must
be connected to the same potentia l on the PCB.
TABLE 3-1: PIN FUNCTION TABLE FOR MCP4801/4811/4821
MCP4801/4811/4821
Symbol Description
MSOP, PDIP,
SOIC, DFN DFN
11V
DD Supply Voltage Input (2.7V to 5.5V)
22CS
Chip Select Input
3 3 SCK Serial Clock Input
4 4 SDI Serial Data Input
55
LDAC DAC Output Synchron iz ati on Inp ut. This pin is us ed to trans fer th e inp ut
register (DAC settings) to the ou tput register (VOUT)
66
SHDN Hardware Shutdown Input
77V
SS Ground refe rence point for al l circuitry on the device
88V
OUT DAC Analog Output
— 9 EP Exposed ther mal pad. This pad must be connected to VSS in application
MCP4801/4811/4821
DS22244B-page 16 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22244B-page 17
MCP4801/4811/4821
4.0 GENERAL OVERVIEW
The MCP4801, MCP4811 and MCP4821 are single
channel voltage-output 8-bit, 10-bit and 12-bit DAC
devices, respectively. These devices include rail-to-rail
output amplifier, internal voltage reference, shutdown
and reset-management circuitry. The devices use an
SPI serial communication interface and operate with a
single supply voltage from 2.7V to 5.5V.
The DAC input coding of these devices is straight
binary. Equation 4-1 shows the DAC analog output
voltage calculation.
EQUATION 4-1: ANALOG OUTPUT
VOLTAGE (VOUT)
The ideal output range of each device is:
• MCP4801 (n = 8)
(a) 0.0V to 255/256 * 2.048V when gain setting = 1x.
(b) 0.0V to 255/256 * 4.096V when gain setting = 2x.
•MCP4811 (n = 10)
(a) 0.0V to 1023/1024 * 2.048V when g ain setting = 1x.
(b) 0.0V to 102 3/1024 * 4.096V when gain setting = 2x.
• MCP4821 (n = 12)
(a) 0.0V to 4095/4096 * 2.048V when g ain setting = 1x.
(b) 0.0V to 4095/4096 * 4.096V when g ain setting = 2x.
1 LSb is the ideal voltage difference between two
successive codes. Table 4-1 illustrates the LSb
calculation of each device.
4.0.1 INL ACCURACY
Integral Non-Linearity (INL) error is the maximum
deviation between an actual code transition point and
its corr esp ond ing ideal tra nsit ion point once offse t and
gain errors have been removed. The two endpoints
method (from 0x000 to 0xFFF) is used for the
calculation. Figure 4-1 shows t he det a il s.
A positive INL error represents transition(s) later than
ideal. A negativ e INL error repres ent s transitio n(s) ear-
lier than ideal.
FIGURE 4-1: Example for INL Error.
Note:
See the output swing voltage specification in
Section 1.0 “Ele ctrical Ch aracteristics”
.
VOUT 2.048V Dn
2n
----------------------------------- G=
Where:
2.048V = Internal voltage reference
Dn= DAC input code
G = Gain selection
=2 for <GA
> bit = 0
=1 for <GA> bit = 1
n = DAC Resolution
=8 for MCP4801
=10 for MCP4811
= 12 for MCP4821
TABLE 4-1: LSb OF EACH DEVICE
Device Gain
Selection LSb Size
MCP4801
(n = 8) 1x 2.048V/256 = 8 mV
2x 4.096V/256 = 16 mV
MCP4811
(n = 10) 1x 2.048V/1024 = 2 mV
2x 4.096V/1024 = 4 mV
MCP4821
(n = 12) 1x 2.048V/4096 = 0.5 mV
2x 4.096V/4096 = 1 mV
111
110
101
100
011
010
001
000
Digital
Input
Code
Actual
Transfer
Function
INL < 0
Ideal Transfer
Function
INL < 0
DAC Output
MCP4801/4811/4821
DS22244B-page 18 2010 Microchip Technology Inc.
4.0.2 DNL ACCURACY
A Dif fe renti al Non-Li nearity (DNL) error is the mea su re
of the variations in code widths from the ideal code
width. A DNL error of zero indicates that every code is
exactly 1 LSb wide.
FIGURE 4-2: Example for DNL Error .
4.0.3 OFFSET ERROR
Offset error is the deviation from zero voltage output
when the digital input code is zero.
4.0.4 G AIN ERROR
Gain error is the deviation from the ideal output,
VREF – 1 LSb, excluding the effects of offset error.
4.1 Circuit Descriptions
4.1. 1 OUTPUT AMPLIFIER
The analog DAC output is buffered with a low-power,
precision CMOS amplifier. This amplifier provides low
of fset v ol tage and low no is e. T he output stage e nables
the device to operate with output voltages close to the
power supply rails. Refer to Section 1.0 “Electrical
Characteristics” for the analog output voltage range
and load conditions.
In addition to resistive load-driving capability, the
amplifier will also drive high capacitive loads without
oscill ation. The amp lifier’s strong output allo ws VOUT to
be used as a programmable voltage reference in a
system.
4.1.1.1 Programmable Gain Block
The rail-to-rail output amplifier has two configurable
gain options: a gain of 1x (<GA> = 1) or a gain of 2x
(<GA> = 0). The default setting is a gain of 2x. This
results in an ideal fu ll-s ca le ou tput of 0.000V to 4. 09 6V
due to the internal reference (VREF = 2.048V).
4.1.2 VOLTAGE REFERENCE
The MCP4801/4811/4821 devices utilize internal
2.048V vol tage referenc e. The volt age ref eren ce has a
low temperature coefficient and low noise
characteristics. Refer to Section 1.0 “Electrical Char-
acteristics” for the voltage reference specifications.
111
110
101
100
011
010
001
000
Digital
Input
Code
Actual
Transfer
Function
Ideal Transfer
Function
Narrow Code, <1 LSb
DAC Output
Wide Code, >1 LSb
2010 Microchip Technology Inc. DS22244B-page 19
MCP4801/4811/4821
4.1.3 POWER-ON RESET CIRCUIT
The internal Power-on Reset (POR) circuit moni tors the
power supply voltage (VDD) during the device
operation. The circuit also ensures that the DAC
powers up with high output impedance (<SHDN> = 0,
typically 500 k. The devices will continue to have a
high-impedance output until a valid write command is
received, and the LDAC pin meets the input low
threshold.
If the power supply voltage is less than the POR
threshold (VPOR = 2.0V, typical), the DAC will be held
in the Reset state. It will remain in that state until
VDD >V
POR and a subsequent write command is
received.
Figure 4-3 shows a typical power supply transient
pulse and the duration required to cause a reset to
occur, as well as the relationship between the duration
and trip voltage. A 0.1 µF decoupling capacitor,
mounted as close as possible to the VDD pin, can
provide additional transient immunity.
FIGURE 4-3: Typic al Transi ent Respon se .
4. 1.4 SHUTDOWN MODE
The user can shut down the device using a software
command (<SHDN> = 0) or SHDN pin. During
shutdown mode, most of the internal circuits, including
the output amplifier, are turned off for power savings.
The internal reference is not affected by the shutdown
command. The serial interface also remains active,
allowing a write command to bring the device out of
Shutdown mode. There will be no analog output at the
VOUT pin, which is i nternally s witched to a known re sis-
tive loa d (500 ktypical. Figure 4-4 shows the an alog
output stage during Shutdown mode.
The condition of the Power-on Reset circuit during
Shutdown is as follows:
a) Turned off if shutdown occurred from the SHDN
pin
b) Remains turned on if the shutdown occurred
through software
The device will remain in Shutdown mode until the
<SHDN> bit = 1 is latch ed into the device o r SH DN pi n
is changed to logic high. When the device is changed
from Shut down to Active mode, t he outpu t settl ing tim e
takes < 10 µs, but greater than the standard active
mode settling time (4.5 µs).
FIGURE 4-4: Output Stage for Shutdown
Mode.
Transients above the curve
will cause a reset
Transients below the curve
will NOT cause a reset
5V
Time
Supply Voltages
Transient Duration
VPOR
VDD - VPOR
TA = +25°C
Transient Duration (µs)
10
8
6
4
2
012345
VDD - VPOR (V)
500 k
Power-Down
Control Circuit
Resistive
Load
VOUT
OP
Amp
Resistive String DAC
MCP4801/4811/4821
DS22244B-page 20 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22244B-page 21
MCP4801/4811/4821
5.0 SERIAL INTERFACE
5.1 Overview
The MCP4801/4811/4821 devices are designed to
interface directly with the Serial Peripheral Interface
(SPI) port, available on many microcontrollers, and
support s Mode 0,0 and Mod e 1,1. Comma nds and da ta
are sent to the device via the SDI pin, with data being
clocked-in on the rising edge of SCK. The
communications are unidirectional and, thus, data
cannot be read out of the MCP4801/4811/4821
devices. The CS pin must be held low for the duration
of a write command. The write command consists of
16 bits and is used to configure the DAC’s control and
data latches. Register 5-1 to Register 5-3 detail the
input register that is used to configure and load the
DAC register for each device. Figure 5-1 to Figure 5-3
show the write command for each device.
Refer to Figure 1-1 and the SPI Timing Specifications
Table for deta iled input and output tim ing spec ification s
for both Mode 0,0 and Mode 1,1 operation.
5.2 Write Command
The write command is initiated by driving the CS pin
low, followed by clocking the four Configuration bits and
the 12 data bits into the SDI pin on the rising edge of
SCK. The CS pin i s then ra is ed, causing the data to be
latched into the DAC’s input register.
The MCP4801/4811/4821 devices utilize a double-
buffered latch structure to allow the DAC ou tput to be
synchronized with the LDAC pin, if desired.
By bringing down the LDAC pin to a low state, the
content s tored in the DAC’s input register i s transferre d
into the DAC’s output register (VOUT), and VOUT is
updated.
All writes to the MCP4801/4811/4821 devices are
16-bit w ords. An y clocks af ter the fi rst 16th clock w ill b e
ignored. The Most Significant four bits are
Configuration bits. The remaining 12 bits are data bits.
No data can be transferred into the device with CS
high. The da t a transfe r will on ly occur if 16 c locks hav e
been transferred into the device. If the rising edge of
CS occurs prior, shifting of data into the input register
will be aborted.
MCP4801/4811/4821
DS22244B-page 22 2010 Microchip Technology Inc.
REGISTER 5-1: WRITE COMMAND REGISTER FOR MCP4821 (12-BIT DAC)
REGISTER 5-2: WRITE COMMAND REGISTER FOR MCP4811 (10-BIT DAC)
REGISTER 5-3: WRITE COMMAND REGISTER FOR MCP4801 (8-BIT DAC)
Where:
W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x
0—GA
SHDN D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
bit 15 bit 0
W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x
0—GASHDN D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 x x
bit 15 bit 0
W-x W-x W-x W-0 W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x W-x
0—GA
SHDN D7 D6 D5 D4 D3 D2 D1 D0 xxxx
bit 15 bit 0
bit 15 (1) 0 = Write to DAC register
1 = Ignore this command
bit 14 — Don’t Care
bit 13 GA: Output Gain Selection bit
1 =1x (V
OUT = VREF * D /4096)
0 =2x (V
OUT = 2 * VREF * D/4096), where internal VREF = 2.048V.
bit 12 SHDN: Output Shutdown Co ntrol bit
1 = Active mode operation. VOUT is availabl e.
0 = Shutdown the device. Analog output is not available. VOUT pin is connected to 500 ktypical)
bit 11-0 D11:D0: DAC Input Data bits. Bit x is ignored.
Note 1: This bit must be ‘0’. The device ignores the write command if this MSB bit is not ‘0’.
Legend
R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’
-n = Value at POR 1 = bit is set 0 = bit is cleared x = bit is unknown
2010 Microchip Technology Inc. DS22244B-page 23
MCP4801/4811/4821
FIGURE 5-1: Write Command for MCP4821 (12-bit DAC).
FIGURE 5-2: Write Command for MCP4811 (10-bit DAC).
FIGURE 5-3: Write Command for MCP4801 (8-bit DAC).
SDI
SCK
CS
021
—GA SHDN D11 D10
config bits 12 data bits
LDAC
3 4
D9
567
D8 D7 D6
8 9 10 12
D5 D4 D3 D2 D1 D0
11 13 14 15
VOUT
(Mode 1,1)
(Mode 0,0)
0
SDI
SCK
CS
021
—GA SHDN D9 D8
config bits 12 data bits
LDAC
3 4
D7
5 6 7
D6 D5 D4
8910 12
D3 D2 D1 D0 X X
11 13 14 15
VOUT
(Mode 1,1)
(Mode 0,0)
Note: X = “don’t care” bits.
0
SDI
SCK
CS
021
—GA SHDN
config bits 12 data bits
LDAC
3 4 567
X
D7 D6
8 9 10 12
D5 D4 D3 D2 D1 D0
11 13 14 15
VOUT
(Mode 1,1)
(Mode 0,0)
XX
X
Note: X = “don’t care” bits.
0
MCP4801/4811/4821
DS22244B-page 24 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22244B-page 25
MCP4801/4811/4821
6.0 TYPICAL APPLICATIONS
The MCP4801/481 1/4821 family of devices are general
purpose, single channel voltage output DACs for
various applications where a precision operation with
low-power and internal voltage reference is required.
Applications generally suited for the devices are:
• Set Point or Offset Trimming
• Sensor C alibration
• Precision Selectable Voltage Reference
• Port ab le Instrum en t ati on (Battery-Powered)
• Calibration of Optical Communication Devices
6.1 Digital Interface
The MCP4801/4811/4821 devices utilize a 3-wire
synchronous serial protocol to tran sfer the DAC’s setup
and input codes from the digital devices. The serial
protocol can be interfaced to SPI or Microwire
peripherals which are common on many microcon-
troller units (MCUs), including Microchip’s PIC® MCUs
and dsPIC® DSCs .
In addition to the three serial connections (CS, SCK
and SDI), the LDAC signal synchronizes the DAC
outp ut w i th L D AC pin event. By bringing th e LDAC pin
down “low”, the DAC input codes and settings in the
DAC input register are latched into the output register,
and the DAC analog output is updated. Figure 6-1
shows an ex ample of the pin connections. Note that the
LDAC pin can be tied low (VSS) to reduce the required
connections from 4 to 3 I/O pins. In this case, the DAC
output can be immediately updated when a valid
16 clock transmission has been received and the CS
pin has been raised.
6.2 Power Supply Considerations
The typical application will require a bypass capacitor
to filter out noise in th e power supply t rac es . Th e n ois e
can be induced onto the power supply’s traces from
various events such as digital switching or as a result
of changes on the DAC’s output. The by p ass cap a ci tor
helps minimize the effect of these noise sources.
Figure 6-1 illustrates an appropriate bypass strategy . In
this example, two bypass capacitors are used in paral-
lel: (a ) 0.1 µF (cerami c) and (b)10 µF (t antalu m). These
capacitors should be placed as close to the device
power pin (VDD) as possibl e (wit hin 4 mm).
The power source supplying these devices should be
as clean as possible. If the application circuit has
separate digital and analog power supplies, VDD and
VSS of the device should reside on the analog plane.
6.3 Output Noise Considerat ions
The voltage noise density (in µV/Hz) is illustrated in
Figure 2-13. This noise appears at VOUT, and is
primarily a result of the internal reference voltage.
Its 1/f corner (fCORNER) is approximately 400 Hz.
Figure 2-14 illustrates the voltage noise (in mVRMS or
mVP-P). A small bypass capacitor on VOUT is an
effective method to produce a single-pole Low-Pass
Filter (LPF) that will reduce this noise. For instance, a
bypas s capacitor sized to pr oduce a 1 kHz LP F would
result in an ENREF of a bo ut 10 0 µ V RMS. Thi s w o ul d be
necessary when trying to achieve the low DNL error
perf orm anc e (at G = 1x) th at t he MCP 480 1/48 11/4 821
devices are capable of. The tested range for stability
is .001 µF through 4.7 µF.
FIGURE 6-1: Typical Connection
Diagram.
6.4 Layout Considerations
Inductively-coupled AC transients and digital switching
noises can degrade the output signal integrity, and
potentially reduce the device performance. Careful
board layout will minimize these effects and increase
the Signal-to-Noise Ratio (SNR). Bench testing has
shown that a multi-layer board utilizing a
low-inductance ground plane, isolated inputs and
isolated outputs with proper decoupling, is critical for
the best performance. Particularly harsh environments
may require shielding of critical signals.
Breadboards and wire-wrapped boards are not
recommended if low noise is desired.
VDD
VDD VDD
AVSS
AVSS VSS
VOUT
PIC® Microcontroller
VOUT
SDI
SDI
CS
SDO
SCK
LDAC
CS0
1µF
1µF
MCP48x1
MCP48x1
C1 = 10 µF
C2 = 0.1 µF C1 C2 C2
C1
C1 C2
MCP4801/4811/4821
DS22244B-page 26 2010 Microchip Technology Inc.
6.5 Single-Supply Operation
The MCP4801/4811/4821 devices are rail-to-rail
voltage output DAC devices designed to operate with a
VDD range of 2.7V to 5.5V. Its output amplifier is r obust
enough to drive small-signal loads directly. Therefore, it
does not require any external output buffer for most
applications.
6.5.1 DC SET POINT OR CALIBR ATION
A common application for the devices is a digitally-
controlled set point and/or calibration of variable
parameters, such as sensor offset or slope. For
example, the MCP4821 and MCP4822 provide
4096 output steps. If G = 1x is selected, the internal
2.048V VREF would produce 500 µV of resolution. If
G = 2x is selected, the internal 2.048 VREF would
produce 1 mV of resolution.
6.5.1.1 Decreasing Output Step Size
If the application is calibrating the bias voltage of a
diode or tran sistor , a bia s voltage range of 0.8V may be
desired with about 200 µV resolution per step. Two
common m ethods to achieve a 0.8V ran ge are to e ither
reduce VREF to 0.82V (using the MCP49XX family
device that uses external reference) or use a voltage
divider on the DAC’s output.
Using a VREF is an option if the VREF is av ailab le with
the desired output voltage range. However,
occas ionall y, when using a low- volt ag e VREF, the no is e
floor causes SNR error that is intolerable. Using a
voltage divider method is another option and provides
some advantages when VREF needs to be very low or
when t he des ired ou tput v olt age is not av ailab le. In this
case, a larger value VREF is used while two resistors
scale the output range down to the precise desired
level.
Example 6-1 illustrates this concept. Note that the
bypass capacitor on the output of the voltage divider
plays a critical function in attenuating the output noise
of the DAC and the induced noise from the
environment.
EXAMPLE 6-1: EXAMPLE CIRCUIT OF SET POINT OR THRESHOLD CALIBRATION
VDD
SPI 3-wire
VTRIP
R1
R20.1 µF
Comparator
VOUT 2.048 G Dn
2N
------
=
VCC+
VCC–
VOUT
Vtrip VOUT
R2
R1R2
+
--------------------
=
VDD
RSENSE
DAC
(a) Single Output DAC:
MCP4801
MCP4811
MCP4821
(b) Dual Output DAC:
MCP4802
MCP4812
MCP4822
G = Gain selection (1x or 2x)
Dn= Digital value of DAC (0-255) for MCP4801/MCP4802
= Digital value of DAC (0-1023) for MCP4811/MCP4812
= Digital value of DAC (0-4095) for MCP4821/MCP4822
N = DAC bit resolution
2010 Microchip Technology Inc. DS22244B-page 27
MCP4801/4811/4821
6.5.1.2 Building a “Window” DAC
When calibrating a set point or threshold of a sensor,
typica lly only a sma ll portion of the DAC output ran ge is
utilized. If the LSb size is adequate enough to meet the
application’s accuracy needs, the unused range is
sacrificed without consequences. If greater accuracy is
needed, then the output range will need to be reduced
to increase the resolution around the desired threshold.
If the threshold is not near VREF, 2VREF or VSS, then
creating a “window” around the threshold has several
advantages. One simple method to create this
“windo w” is to use a vo ltage di vider netw ork with a pul l-
up and pull-down resistor. Example 6-2 and
Example 6-4 illustrate this concept.
EXAMPLE 6-2: SINGLE-SUPPLY “WINDOW” DAC
DAC
VDD
SPI 3-wire
VTRIP
R1
R20.1 µF
Comparator
R3
VCC-
VCC+ VCC+
VCC-
VOUT
R23 R2R3
R2R3
+
-------------------=
V23 VCC+R2
VCC-R3
+
R2R3
+
------------------------------------------------------=
Vtrip VOUTR23 V23R1
+
R1R23
+
---------------------------------------------=
R1
R23
V23
VOUT VO
Thevenin
Equivalent
RSENSE
VOUT 2.048 G Dn
2N
------
=
G = Gain selection (1x or 2x)
Dn= Digital value of DAC (0-255) for MCP4801/MCP4802
= Digital value of DAC (0-1023) for MCP4811/M CP48 12
= Digital value of DAC (0-4095) for MCP4821/MCP482 2
N = DAC bit resolution
(a) Single Output DAC:
MCP4801
MCP4811
MCP4821
(b) Dual Output DAC:
MCP4802
MCP4812
MCP4822
MCP4801/4811/4821
DS22244B-page 28 2010 Microchip Technology Inc.
6.6 Bipolar Operation
Bipolar operation is achievable using the
MCP4801/4811/4821 family of devices by utilizing an
external operational amplifier (op amp). This
configuration is desirable due to the wide variety and
availability of op amps. This allows a general purpose
DAC, with its cost and availability advantages, to meet
almost any desired output voltage range, power and
noise performanc e.
Example 6-3 ill ustrate s a simple bipola r volt age so urce
configuration. R1 and R2 allow the gain to be selected,
while R3 and R4 shift the DAC’s output to a selected
of fset. Note that R4 can be tie d to VDD, instea d of VSS,
if a higher offset is desired. Also note that a pull -up to
VDD could be use d in stead of R4, or in additio n to R4, if
a higher offset is desired.
EXAMPLE 6-3: DIGITALLY-CONTR OLLED BIPOLAR VOLTAGE SOURCE
6.6.1 DESIGN EXAMPLE: DESIGN A
BIPOLAR DAC USING EXAMPLE 6-3
WITH 12-BIT MCP4821 OR
MCP4822
An output step magnitude of 1 mV , with an output range
of ±2.05V, is desired for a particular application.
Step 1: Calcula te th e ra nge : +2.05V – (-2.05V) = 4.1V.
Step 2: Calculate the resolution needed:
4.1V/1 mV = 4100
Since 212 = 4096, 12-bit resolution is desired.
Step 3: The amplifier gain (R2/R1), multiplied by full-
scale VOUT (4.096V), must be equ al to the desired
minimum output to achieve bipolar operation.
Since any gain can be realized by choosing
resistor values (R1+R2), the VREF value must be
selected first. If a VREF of 4.096V is used (G=2),
solve f or th e am pl ifi er’s gai n b y setting the DAC to
0, knowing that the output needs to be -2.05V.
The equation can be simplified to:
St ep 4: Next solve for R3 and R4 by setting the D AC to
4096, k nowing that the o utput nee ds to be + 2.05V.
DAC
VDD
VDD
SPI 3-wire
VOUT R3
R4
R2
R1
VIN+
0.1 µF
VCC+
VCC–
VIN+ VOUTR4
R3R4
+
--------------------=
VO
VOVIN+ 1R2
R1
------+
VDD R2
R1
------
–=
VOUT 2.048 G Dn
2N
------
=G = Gain selection (1x or 2x)
Dn= Digital value of DAC (0-255) for MCP4801/MCP4802
= Digital value of DAC (0-1023) for MCP4811/MCP4812
= Digital value of DAC (0-4095) for MCP4821/MCP4822
N = DAC bit resolution
(a) Single Output DAC:
MCP4801
MCP4811
MCP4821
(b) Dual Output DAC:
MCP4802
MCP4812
MCP4822
R2
–
R1
---------2.05–
4.096V
-----------------=
If R1 = 20 k and R2 = 10 k, the gain will be 0.5.
R2
R1
------1
2
---=
R4
R3R4
+
------------------------2.05V 0.5 4.096V
+
1.5 4.096V
------------------------------------------------------- 2
3
---==
If R4 = 20 k, then R3 = 10 k
2010 Microchip Technology Inc. DS22244B-page 29
MCP4801/4811/4821
6.7 Select able Gain and Offset Bipolar
Voltage Output
In some applications, precision digital control of the
output range is desirable. Example 6-4 illustr ates ho w
to use the MCP4801/4811/4821 family of devices to
achieve this in a bipolar or single-supply application.
This circuit is typically used for linearizing a sensor
whose slope and offset varies.
The eq uat ion to desi gn a b ipo lar “w indo w” D AC wo uld
be utilized if R3, R 4 and R5 are populated.
EXAMPLE 6-4: BIPOLAR VOLTAGE SOURCE WITH SELECTABLE GAIN AND OFFSET
VDD
R3
R4
R2
VO
DACA
VDD
R1
(DACA for Gain Adjust)
(DACB for Offset Adjust)
SPI 3
R5
VCC+
Thevenin
Bipolar “Window” DAC using R4 and R5
0.1 µF
VCC–
VCC+
VCC–
VOUTA
VOUTB
VIN+ VOUTBR4VCC-R3
+
R3R4
+
-------------------------------------------------=
VOVIN+ 1R2
R1
------+
VOUTA R2
R1
------
–=
Equivalent V45 VCC+R4VCC-R5
+
R4R5
+
---------------------------------------------=R
45 R4R5
R4R5
+
-------------------=
VIN+ VOUTBR45 V45R3
+
R3R45
+
------------------------------------------------=V
OVIN+ 1R2
R1
------+
VOUTA R2
R1
------
–=
Offset Adjust Gain Adjust
Offset Adjust Gain Adjust
DACB
VOUTA 2.048 GADn
2N
------
=
VOUTB 2.048 GBDn
2N
------
=
VIN+
G = Gain selection (1x or 2x)
N = DAC bit resolution
Dn= Digital value of DAC (0-255) for MCP4801
= Digital value of DAC (0-1023) for MCP4811
= Digital value of DAC (0-4095) for MCP4821
MCP4801/4811/4821
DS22244B-page 30 2010 Microchip Technology Inc.
6.8 Designing a Double- Precision
DAC
Example 6-5 illustrates how to design a single-supply
voltage output capable of up to 24-bit resolution by
using 12-bit DACs. This design is simply a voltage
divider with a buffered output.
As an example, if an application similar to the one
developed in Section 6.6.1 “Design Example:
Design a Bipolar DAC Using Example 6-3 with 12-
bit MCP4821 or MCP4822” required a resolution of
1 µV instead of 1 mV, and a range of 0V to 4.1V, then
12-bit resolution would not be adequate.
Step 1: Calculate the resolution needed:
4.1V/1 µV = 4.1 x 106. Since 222 =4.2x10
6,
22-bit resolution is desired. Since
DNL = ±0.75 LSb, this design can be done with
the 12-bit MCP4821 or MCP4822 DAC devices.
St ep 2: Sinc e D ACB’s VOUTB h as a res ol uti on o f 1 mV,
it s outpu t only ne eds to be “pulled ” 1/10 00 to me et
the 1 µV target. Dividing VOUTA by 1000 would
allow the application to compensate for DACB’s
DNL error.
Step 3: If R2 is 100, then R1 needs to be 100 k.
Step 4: The resulting transfer function is shown in the
equation of Example 6-5.
EXAMPLE 6-5: SIMPLE, DOUBLE-PRECISION DAC WITH MCP4821
VDD
R2
VO
VDD
R1
VOUTA for Fine Adjustment
SPI 3-wire
R1 >> R2
VOVOUTAR2VOUTBR1
+
R1R2
+
------------------------------------------------------=
0.1 µF
VCC+
VCC–
VOUTA 2.048 GADA
212
-------
=
VOUTB 2.048 GBDB
212
-------
=
DACA
Gx= Gain selection (1x or 2x)
Dn= Digital value of DAC (0-4096)
DACBVOUTB for Fine Adjustment
2010 Microchip Technology Inc. DS22244B-page 31
MCP4801/4811/4821
6.9 Building Programmable Current
Source
Example 6-6 shows an example of building a
program mable current so urce usin g a voltage follow er.
The current sensor (sensor resistor) is used to convert
the DAC voltage output into a digitally-selectable
current source.
Adding the resistor network from Example 6-2 would
be advantageous in this application. The smaller
RSENSE is, the less power dissipated across it.
However, this also reduces the resolution that the
current can be controlled with. The voltage divider, or
“window”, DAC configuration would allow the range to
be reduced, thus increasing resolution around the
range of i nter est. Whe n wor king wit h very small sens or
volt ages, plan on e lim in ati ng the amplif ier’s o f fset error
by storing the DAC’s setting under known sensor
conditions.
EXAMPLE 6-6: DIGITALLY-CONTROLLED CURREN T SOURCE
DAC
RSENSE
Ib
Load
IL
VDD
SPI 3-wire
VCC+
VCC–
VOUT
ILVOUT
Rsense
---------------
1+
-------------
=
IbIL
----=
Common-Emitter Current Gainwhere
VDD or VREF
(a) Single Output DAC:
MCP4801
MCP4811
MCP4821
(b) Dual Output DAC:
MCP4802
MCP4812
MCP4822
G = Gain selection (1x or 2x)
Dn= Digital value of DAC (0-255) for MCP4801/M CP48 0 2
= Digital value of DAC (0-1023) for MCP4811/MCP4812
= Digital value of DAC (0-4095) for MCP4821/M CP4 822
N = DAC bit resolution
MCP4801/4811/4821
DS22244B-page 32 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22244B-page 33
MCP4801/4811/4821
7.0 DEVELOPMENT SU PPORT
7.1 Evaluation & Demonstration
Boards
The Mixed Signal PICtail™ Demo Board supports the
MCP4801/4811/4821 family of devices. Refer to
www.microchip.com for further information on this
product’s capabilit ies and availabil i ty.
MCP4801/4811/4821
DS22244B-page 34 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22244B-page 35
MCP4801/4811/4821
8.0 PACKAGING INFORMATION
8.1 Package Marking Information
XXXXXXXX
XXXXXNNN
YYWW
8-Lead PDIP (300 mil) Example:
8-Le ad SOIC (150 mil) Example:
XXXXXXXX
XXXXYYWW
NNN
MCP4821
E/P ^ 256
1010
MCP4811E
SN^^ 1010
256
8-Le ad MSOP Example:
XXXXXX
YWWNNN 4801E
010256
Legend: XX...X Customer-specific information
Y Year code (last digit of calendar year)
YY Year code (last 2 digits of calendar year)
WW Week code (week of January 1 is week ‘01’)
NNN Alphanume ric traceability code
Pb-free JEDEC designator for Matte Ti n (Sn)
*This package is Pb-free. The Pb-free JEDEC designator ( )
can be found on the outer packaging for this package.
Note: In the even t the full M icroc hip p art numb er cann ot be mark ed on one line, it wil l
be carried over to the next line, thus limiting the number of available
characters for customer-specific information.
3
e
3
e
3
e
3
e
8-Lead DFN (2x3) Example:
XXX
YWW
NN 010
25
AHS
MCP4801/4811/4821
DS22244B-page 36 2010 Microchip Technology Inc.
!""#$%&
'
!"#$%!&'(!%&! %(%")%%%"
*&&# "%( %"
+ * ) !%"
& "%,-.
/01 / & %#%! ))%!%%
,21 $& '! !)%!%%'$$&%!
' 2%& %!%*") ' %*$%%"%
%%133)))&&3*
4% 55,,
& 5&% 6 67 8
6!&($ 6 9
% ./0
7:% 9
%"$$ .
0%%* + ,2
75% /0
7;"% , +/0
,# ""5% + < ..
,# "";"% , . < .
0%%;"% ( . +
0%%5% 5 + .
0%%%,# "" = < <
D
N
E
NOTE 1
12
EXPOSED PAD
NOTE 1
21
D2
K
L
E2
N
e
b
A3 A1
A
NOTE 2
BOTTOM VIEW
TOP VIEW
) 0+0
2010 Microchip Technology Inc. DS22244B-page 37
MCP4801/4811/4821
!""#$%&
' 2%& %!%*") ' %*$%%"%
%%133)))&&3*
MCP4801/4811/4821
DS22244B-page 38 2010 Microchip Technology Inc.
()"*+)%)*&
'
!"#$%!&'(!%&! %(%")%%%"
& ","%!"&"$ %! "$ %! %#".&& "
+ & "%,-.
/01 / & %#%! ))%!%%
,21 $& '! !)%!%%'$$&%!
' 2%& %!%*") ' %*$%%"%
%%133)))&&3*
4% 55,,
& 5&% 6 67 8
6!&($ 6 9
% >./0
7:% < <
""** . 9. .
%"$$ < .
7;"% , /0
""*;"% , +/0
75% +/0
2%5% 5 > 9
2%% 5 .,2
2% I? < 9?
5"* 9 < +
5";"% ( <
D
N
E
E1
NOTE 1
12
e
b
A
A1
A2 c
L1 L
φ
) 0/
2010 Microchip Technology Inc. DS22244B-page 39
MCP4801/4811/4821
Note: For the most current package drawings, please see the Microchip Packaging Specification located at
http://www.microchip.com/packaging
MCP4801/4811/4821
DS22244B-page 40 2010 Microchip Technology Inc.
,++"#$%,&
'
!"#$%!&'(!%&! %(%")%%%"
@$%0% %
+ & ","%!"&"$ %! "$ %! %#"A "
& "%,-.
/01/ & %#%! ))%!%%
' 2%& %!%*") ' %*$%%"%
%%133)))&&3*
4% 60:,
& 5&% 6 67 8
6!&($ 6 9
% /0
%% < <
""** . + .
/ %% . < <
!"%!";"% , + +.
""*;"% , . 9
75% +9 +>.
%% 5 . + .
5"* 9 .
45";"% ( >
5)5";"% ( 9
7)@ / < < +
N
E1
NOTE 1
D
123
A
A1
A2
L
b1
b
e
E
eB
c
) 09/
2010 Microchip Technology Inc. DS22244B-page 41
MCP4801/4811/4821
)"*+)((- !""#$%)*,&
'
!"#$%!&'(!%&! %(%")%%%"
@$%0% %
+ & ","%!"&"$ %! "$ %! %#".&& "
& "%,-.
/01 / & %#%! ))%!%%
,21 $& '! !)%!%%'$$&%!
' 2%& %!%*") ' %*$%%"%
%%133)))&&3*
4% 55,,
& 5&% 6 67 8
6!&($ 6 9
% /0
7:% < < .
""** . < <
%"$$@ < .
7;"% , >/0
""*;"% , +/0
75% /0
0&$B%C . < .
2%5% 5 <
2%% 5 ,2
2% I? < 9?
5"* < .
5";"% ( + < .
"$% D.? < .?
"$%/%%& E.? < .?
D
N
e
E
E1
NOTE 1
12 3
b
A
A1
A2
L
L1
c
h
h
φ
β
α
) 0./
MCP4801/4811/4821
DS22244B-page 42 2010 Microchip Technology Inc.
)"*+)((- !""#$%)*,&
' 2%& %!%*") ' %*$%%"%
%%133)))&&3*
2010 Microchip Technology Inc. DS22244B-page 43
MCP4801/4811/4821
APPENDIX A: REVISION HISTORY
Revision A (April 2010)
• Original Release of this Document.
Revision B (April 2010)
• Correc ted the “Related Products” table on
page 1.
MCP4801/4811/4821
DS22244B-page 44 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22244B-page 45
MCP4801/4811/4821
PRODUCT IDENTIFICATION SYSTEM
To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office.
PART NO. X/XX
PackageTemperature
Range
Device
Device MCP4801: 8-Bit Voltage Output DAC
MCP4801T: 8-Bit Voltage Output DAC
(Tape and Reel, DFN, MSOP and SOIC only)
MCP481 1: 10-Bit Voltage Output DAC
MCP481 1T: 10-Bit Voltage Output DAC
(Tape and Reel, DFN, MSOP and SOIC only)
MCP 4 821: 12-B it Voltage Output DAC
MCP4821T: 12-Bit Voltage Output DAC
(Tape and Reel, DFN, MSOP and SOIC only)
Temperatu re Range E = -40C to +125C (Extended)
Package MC = 8-Lead Plastic Dual Flat, No Lead Package -
2x3x0.9 mm Body (DFN)
MS = 8-Lead Plastic Micro Small Outline (MSOP)
P = 8-Lead Plastic Dual In-Line (PDIP)
SN = 8-Lead Plastic Small Outline - Narrow , 150 mil
(SOIC)
Examples:
a) MCP4801-E/MC: Extended temperature,
DFN package
b) MCP4801T-E/MC: Extended temperature,
DFN package,
Tape and Reel
c) MCP4801-E/MS: Extended temperature,
MSOP package.
d) MCP4801T-E/MS: Extended temperature,
MSOP package,
Tape and Reel.
e) MCP4801-E/P: Extended temperature,
PDIP package.
f) MCP4801-E/SN: Extended temperature,
SOIC package.
g) MCP4801T-E/SN: Extended temperature,
SOIC package,
Tape and Reel.
a) MCP4811-E/MC: Extended temperature,
DFN package
b) MCP4811T-E/MC: Extended temperature,
DFN package,
Tape and Reel
c) MCP4811-E/MS: Extended temperature,
MSOP package.
d) MCP4811T-E/MS: Extended temperature,
MSOP package,
Tape and Reel.
e) MCP4811-E/P: Extended temperature,
PDIP package.
f) MCP481 1-E/SN: Extended temperature,
SOIC package.
g) MCP4811T-E/SN: Extended temperature,
SOIC package,
Tape and Reel.
a) MCP4821-E/MC: Extended temperature,
DFN package
b) MCP4821T-E/MC: Extended temperature,
DFN package,
Tape and Reel
c) MCP4821-E/MS: Extended temperature,
MSOP package.
d) MCP4821T-E/MS: Extended temperature,
MSOP package,
Tape and Reel.
e) MCP4821-E/P: Extended temperature,
PDIP package.
f) MCP4821-E/SN: Extended temperature,
SOIC package.
g) MCP4821T-E/SN: Extended temperature,
SOIC package,
Tape and Reel.
MCP4801/4811/4821
DS22244B-page 46 2010 Microchip Technology Inc.
NOTES:
2010 Microchip Technology Inc. DS22244B-page 47
Information contained in this publication regarding device
applications a nd the lik e is p ro vided on ly for yo ur con ve nien ce
and may be supers eded by updates . I t is you r r es ponsibil it y to
ensure that your application meets with your specifications.
MICROCHIP MAKES NO REPRESENTATIONS OR
WARRANTIES OF ANY KIND WHETHER EXPRESS OR
IMPLIED, WRITTEN OR ORAL, STATUTORY OR
OTHERWISE, RELATED TO THE INFORMATION,
INCLUDING BUT NOT LIMITED TO ITS CONDITION,
QUALITY, PERFORMANCE, MERCHANTABILITY OR
FITNESS FOR PURPOSE. Microchip disclaims all liability
arising from this information and its use. Use of Microchip
devices in life support and/or safety applications is entirely at
the buyer’s risk, and the buyer agrees to defend, indemnify and
hold harmless Microchip from any and all damages, claims,
suits, or expenses resulting from such use. No licenses are
conveyed, implicitly or otherwise, under any Microchip
intellectual property rights.
Trademarks
The Microchip name and logo, the Microchip logo, dsPIC,
KEELOQ, KEELOQ logo, MPLAB, PIC, PICmicro, PI CSTART,
PIC32 logo, rfPIC and UNI/O are registered trademarks of
Microchip Technology Incorporat ed in the U.S.A. and other
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MXDEV, MXLAB, SEEVAL and The Embedded Control
Solutions Company are registered trademarks of Microchip
Technology Incorporated in the U.S.A.
Analog-for-the-Digital Age, Application Maestro, CodeGuard,
dsPICDEM, dsPICDEM.net, dsPICworks, dsSPEAK, ECAN,
ECONOMONIT OR, FanSense, HI- TIDE, In-Circu it Se r i a l
Programming, ICSP, Mindi, MiWi, MPAS M, MPLAB Cert ified
logo, MPLIB, MPLINK, mTouch, Octopus, Omniscient Code
Generation, PICC, PICC-18, PICDEM, PICDEM.net, PICkit,
PICtail, REAL ICE, rfLAB, Select Mode, Total Endurance,
TSHARC, UniWinDriver, WiperLock and ZENA are
trademarks of Microchip Technology Inc orporated in the
U.S.A. and other countries.
SQTP is a service mark of Microchip T echnology Incorporated
in the U.S.A.
All other trademarks mentioned herein are property of their
respective companies.
© 2010, Microchip Technology Incorporated, Printed in the
U.S.A., All Rights Reserved.
Printed on recycled paper.
ISBN: 978-1-60932-124-6
Note the following details of the code protection feature on Microchip devices:
• Microchip products meet the specification contained in t heir particular Microchip Data Sheet.
• Microchip believes that its family of products is one of t he most secure famili es of its kind on t he market t oday, when used in the
intended manner and under normal conditions.
• There are dishonest and possibly illegal methods used to breach the code protection feature. All of these methods, to our
knowledge, require using the Microchip products in a manner outside the operating specifications contained in Microchip’s Data
Sheets. Most likely, the person doing so is engaged in theft of intellectual property.
• Microchip is willing to work with the customer who is concerned about the integrity of their code.
• Neither Microchip nor any other semiconductor manufacturer can guarantee the security of their code. Code protection does not
mean that we are guaranteeing the product as “unbreakable.”
Code protection is c onstantly evolving. We a t Microc hip are co m mitted to continuously improving the code prot ect ion featur es of our
products. Attempts to break Microchip’ s code protection feature may be a violation of the Digital Millennium Copyright Act. If such acts
allow unauthorized access to your software or other copyrighted work, you may have a right to sue for relief under that Act.
Microchip received ISO/TS-16949:2002 certification for its worldwide
headquarters, design and wafer fabrication facilities in Chandler and
Tempe, Arizona; Gresham, Oregon and design centers in California
and India. The Company’s quality system processes and procedures
are for its PIC® MCUs and dsPIC® DSCs, KEELOQ® code hopping
devices, Serial EEPROMs, microperiph erals, nonvolatile memory and
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and manufacture of development systems is ISO 9001:2000 certified.
DS22244B-page 48 2010 Microchip Technology Inc.
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India - Pune
Tel: 91-20-2566-1512
Fax: 91-20-2566-1513
Japan - Yokohama
Tel: 81-45-471- 6166
Fax: 81-45-471-6122
Korea - Daegu
Tel: 82-53-744-4301
Fax: 82-53-744-4302
Korea - Seoul
Tel: 82-2-554-7200
Fax: 82-2-558-5932 or
82-2-558-5934
Malaysia - Kuala Lumpur
Tel: 60-3-6201-9857
Fax: 60-3-6201-9859
Malaysia - Penang
Tel: 60-4-227-8870
Fax: 60-4-227-4068
Philippines - Manila
Tel: 63-2-634-9065
Fax: 63-2-634-9069
Singapore
Tel: 65-6334-8870
Fax: 65-6334-8850
Taiwan - Hsin Chu
Tel: 886-3-6578-300
Fax: 886-3-6578-370
Taiwan - Ka ohsiung
Tel: 886-7-536-4818
Fax: 886-7-536-4803
Taiwan - Taipei
Tel: 886-2-2500-6610
Fax: 886-2-2508-0102
Thailand - Bangko k
Tel: 66-2-694-1351
Fax: 66-2-694-1350
EUROPE
Austria - Wels
Tel: 43-7242-2244-39
Fax: 43-7242-2244-393
Denmark - Cop e nha gen
Tel: 45-4450-2828
Fax: 45-4485-2829
France - Paris
Tel: 33-1-69-53 -63-20
Fax: 33-1-69-30-90-79
Germany - Munich
Tel: 49-89-627-144-0
Fax: 49-89-627-14 4-44
Italy - Milan
Tel: 39-0331-742611
Fax: 39-0331-466781
Netherlands - Drunen
Tel: 31-416-690399
Fax: 31-416-690340
Spain - Madrid
Tel: 34-91-708-08-90
Fax: 34-91-708-08 -91
UK - Wokingham
Tel: 44-118-921-5869
Fax: 44-118-921-5820
WORLDWIDE SALES AND SERVICE
01/05/10
