HG
BOOT
ISEN
LG
PGND
FB
VCC
SD
PWGD
FREQ
SS/TRACK
SGND
EAO
PGND
VCC = 3.3V VIN = 3.3V
VOUT = 1.2V@4A
RFB2
CC2 RC1
RCS
CSS
RFADJ
RCC
CCC
D1CBOOT
Q1 CIN1,2
L1
+
CC1 RFB1
CO1,2
LM2743
RC2 CC3
RPULL-UP +
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An IMPORTANT NOTICE at the end of this data sheet addresses availability, warranty, changes, use in safety-critical applications,
intellectual property matters and other important disclaimers. PRODUCTION DATA.
LM2743
SNVS276I –APRIL 2004–REVISED FEBRUARY 2019
LM2743 2.2-V to 16-V Input, voltage mode,
synchronous buck controller with tracking
1
1 Features
1• Power stage input voltage from 1 V to 16 V
• Control stage input voltage from 3 V to 6 V
• Output voltage adjustable down to 0.6 V
• Power-good flag and shutdown
• Output overvoltage and undervoltage detection
• ±2% Feedback voltage accuracy over temperature
• Low-side adjustable current sensing
• Adjustable soft start
• Tracking and sequencing with shutdown and soft-
start pins
• Switching frequency from 50 kHz to 1 MHz
• TSSOP-14 package
• Create a custom design using the LM2743 with
the WEBENCH®Power Designer
2 Applications
• 3.3-V Buck regulation
• Cable modem, DSL and ADSL
• Laser Jet and ink jet printers
• Low-voltage power modules
• DSP, ASIC, core, and I/O
3 Description
The LM2743 is a high-speed synchronous buck
regulator controller with an accurate feedback voltage
accuracy of ±2%. It can provide simple down
conversion to output voltages as low as 0.6 V.
Though the control sections of the IC are rated for 3
V to 6 V, the driver sections are designed to accept
input supply rails as high as 16 V. The use of
adaptive non-overlapping MOSFET gate drivers helps
avoid potential shoot-through problems while
maintaining high efficiency. The IC is designed for the
more cost-effective option of driving only N-channel
MOSFETs in both the high-side and low-side
positions. It senses the low-side switch voltage drop
for providing a simple, adjustable current limit.
The fixed-frequency voltage-mode PWM control
architecture is adjustable from 50 kHz to 1 MHz with
one external resistor. This wide range of switching
frequency gives the power supply designer the
flexibility to make better tradeoffs between
component size, cost and efficiency.
Features include soft start, input undervoltage lockout
(UVLO) and Power Good (based on both
undervoltage and overvoltage detection). In addition,
the shutdown pin of the IC can be used for providing
start-up delay, and the soft-start pin can be used for
implementing precise tracking, for the purpose of
sequencing with respect to an external rail.
Device Information(1)
PART NUMBER PACKAGE BODY SIZE (NOM)
LM2743 TSSOP (14) 5.00 mm × 4.40 mm
(1) For all available packages, see the orderable addendum at
the end of the data sheet.
Typical Application Diagram
2
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Table of Contents
1 Features.................................................................. 1
2 Applications ........................................................... 1
3 Description............................................................. 1
4 Revision History..................................................... 2
5 Pin Configuration and Functions......................... 3
6 Specifications......................................................... 4
6.1 Absolute Maximum Ratings ...................................... 4
6.2 ESD Ratings ............................................................ 4
6.3 Recommended Operating Conditions....................... 4
6.4 Thermal Information.................................................. 4
6.5 Electrical Characteristics........................................... 5
6.6 Typical Characteristics.............................................. 7
7 Detailed Description............................................ 10
7.1 Overview................................................................. 10
7.2 Functional Block Diagram....................................... 10
7.3 Feature Description................................................. 10
7.4 Device Functional Modes........................................ 18
8 Application and Implementation ........................ 19
8.1 Application Information............................................ 19
8.2 Typical Applications ................................................ 19
9 Power Supply Recommendations...................... 33
10 Layout................................................................... 33
10.1 Layout Guidelines ................................................. 33
10.2 Layout Example .................................................... 33
11 Device and Documentation Support................. 34
11.1 Device Support .................................................... 34
11.2 Receiving Notification of Documentation Updates 34
11.3 Community Resources.......................................... 34
11.4 Trademarks........................................................... 34
11.5 Electrostatic Discharge Caution............................ 34
11.6 Glossary................................................................ 34
12 Mechanical, Packaging, and Orderable
Information........................................................... 35
4 Revision History
NOTE: Page numbers for previous revisions may differ from page numbers in the current version.
Changes from Revision H (October 2015) to Revision I Page
• Editorial updates; add links for WEBENCH; no technical changes ....................................................................................... 1
Changes from Revision G (March 2013) to Revision H Page
• Added ESD Ratings table, Feature Description section, Device Functional Modes,Application and Implementation
section, Power Supply Recommendations section, Layout section, Device and Documentation Support section, and
Mechanical, Packaging, and Orderable Information section. ................................................................................................ 1
Changes from Revision F (March 2013) to Revision G Page
• Changed layout of National Data Sheet to TI format ........................................................................................................... 32
LM2743
HG
BOOT
ISEN
LG
PGND
FB
VCC
SD
PWGD
FREQ
SS/TRACK
SGND
EAO
PGND
1
2
3
4
5
6
78
9
10
11
12
13
14
3
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5 Pin Configuration and Functions
PW Package
14-Pin TSSOP
Top View
Pin Functions
PIN DESCRIPTION
NAME NO.
BOOT 1 Bootstrap pin. This is the supply rail for the gate drivers. When the high-side MOSFET turns on, the
voltage on this pin should be at least one gate threshold above the regulator input voltage VIN to
properly turn on the MOSFET. See MOSFET Gate Drivers for more details on how to select
MOSFETs.
LG 2 Low-gate drive pin. This is the gate drive for the low-side N-channel MOSFET. This signal is
interlocked with the high-side gate drive HG (Pin 14), so as to avoid shoot-through.
PGND 3 Power ground. This is also the ground for the low-side MOSFET driver. Both the pins must be
connected together on the PCB and form a ground plane, which is usually also the system ground.
13
SGND 4 Signal ground. It should be connected appropriately to the ground plane with due regard to good layout
practices in switching power regulator circuits.
VCC 5 Supply rail for the control sections of the IC.
PWGD 6 Power Good pin. This is an open drain output, which is typically meant to be connected to VCC or any
other low voltage source through a pull-up resistor. Choose the pull-up resistor so that the current
going into this pin is kept below 1 mA. For most applications a recommended value for the pull-up
resistor is 100 kΩ. The voltage on this pin is thus pulled low under output under-voltage or over-
voltage fault conditions and also under input UVLO.
ISEN 7 Current limit threshold setting pin. This sources a fixed 40 µA current. A resistor of appropriate value
should be connected between this pin and the drain of the low-side MOSFET (switch node).
EAO 8 Output of the error amplifier. The voltage level on this pin is compared with an internally generated
ramp signal to determine the duty cycle. This pin is necessary for compensating the control loop.
SS/TRACK 9 Soft-start and tracking pin. This pin is internally connected to the non-inverting input of the error
amplifier during soft-start, and in fact any time the SS/TRACK pin voltage happens to be below the
internal reference voltage. For the basic soft-start function, a capacitor of minimum value 1 nF is
connected from this pin to ground. To track the rising ramp of another power supply’s output, connect
a resistor divider from the output of that supply to this pin as described in Application and
Implementation.
FB 10 Feedback pin. This is the inverting input of the error amplifier, which is used for sensing the output
voltage and compensating the control loop.
FREQ 11 Frequency adjust pin. The switching frequency is set by connecting a resistor of suitable value
between this pin and ground. The equation for calculating the exact value is provided in Application
and Implementation, but some typical values (rounded up to the nearest standard values) are 324 kΩ
for 100 kHz, 97.6 kΩfor 300 kHz, 56.2 kΩfor 500 kHz, 24.9 kΩfor 1 MHz.
SD 12 IC shutdown pin. Pull this pin to VCC to ensure the IC is enabled. Connect to ground to disable the IC.
Under shutdown, both high-side and low-side drives are off. This pin also features a precision
threshold for power supply sequencing purposes, as well as a low threshold to ensure minimal
quiescent current.
HG 14 High-gate drive pin. This is the gate drive for the high-side N-channel MOSFET. This signal is
interlocked with LG (Pin 2) to avoid shoot-through.
4
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(1) Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings
only, which do not imply functional operation of the device at these or any other conditions beyond those indicated under Recommended
Operating Conditions. Exposure to absolute-maximum-rated conditions for extended periods may affect device reliability.
(2) If Military/Aerospace specified devices are required, please contact the Texas Instruments Sales Office/ Distributors for availability and
specifications.
6 Specifications
6.1 Absolute Maximum Ratings
MIN MAX UNIT
VCC –0.3 7 V
BOOT voltage –0.3 21 V
ISEN –0.3 9.5 V
All other pins –0.3 VCC + 0.3 V
TJJunction temperature 150 °C
Soldering information Lead temperature (soldering, 10 s) 260 °C
Infrared or convection (20 s) 235 °C
Tstg Storage temperature –65 150 °C
(1) The human body model is a 100 pF capacitor discharged through a 1.5-kΩresistor into each pin.
(2) JEDEC document JEP155 states that 500-V HBM allows safe manufacturing with a standard ESD control process.
6.2 ESD Ratings VALUE UNIT
V(ESD) Electrostatic discharge(1) Human-body model (HBM), per ANSI/ESDA/JEDEC JS-001(2) 2000 V
6.3 Recommended Operating Conditions MIN NOM MAX UNIT
VCC Supply voltage range 3 6 V
TJJunction temperature –40 125 °C
(1) For more information about traditional and new thermal metrics, see the Semiconductor and IC Package Thermal Metrics application
report, SPRA953.
6.4 Thermal Information
THERMAL METRIC(1) LM2743
UNITTSSOP (PW)
14 PINS
RθJA Junction-to-ambient thermal resistance 107.9 °C/W
RθJC(top) Junction-to-case (top) thermal resistance 33.7 °C/W
RθJB Junction-to-board thermal resistance 50.7 °C/W
ψJT Junction-to-top characterization parameter 1.8 °C/W
ψJB Junction-to-board characterization parameter 50 °C/W
5
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(1) The power MOSFETs can run on a separate 1-V to 16-V rail (Input voltage, VIN). Practical lower limit of VIN depends on selection of the
external MOSFET.
6.5 Electrical Characteristics
Typical limits are for TJ= 25°C only, represent the most likely parametric norm at TJ= 25°C, and are provided for reference
purposes only; minimum and maximum limits apply over the junction temperature range of –40°C to 125°C. Unless otherwise
specified, VCC = 3.3 V. Data sheet minimum and maximum specification limits are specified by design, test, or statistical
analysis. (See (1))PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VFB FB Pin Voltage VCC = 3 V to 6 V 0.588 0.6 0.612 V
VON UVLO Thresholds Rising
Falling 2.76
2.42 V
IQ_VCC Operating VCC Current
VCC = 3.3 V, VSD = 3.3 V
Fsw = 600 kHz 1 1.5 2.1 mA
VCC = 5V, VSD = 3.3 V
Fsw = 600 kHz 1 1.7 2.1
Shutdown VCC Current VCC = 3.3 V, VSD = 0 V 110 185 µA
tPWGD1 PWGD Pin Response Time VFB Rising 6 µs
tPWGD2 PWGD Pin Response Time VFB Falling 6 µs
ISS-ON SS Pin Source Current VSS = 0 V 7 10 14 µA
ISS-OC SS Pin Sink Current During Over
Current VSS = 2.5 V 90 µA
ISEN-TH ISEN Pin Source Current Trip Point 25 40 55 µA
ERROR AMPLIFIER
GBW Error Amplifier Unity Gain
Bandwidth 9 MHz
G Error Amplifier DC Gain 106 dB
SR Error Amplifier Slew Rate 3.2 V/µs
IEAO EAO Pin Current Sourcing and
Sinking Capability VEAO = 1.5, FB = 0.55 V
VEAO = 1.5, FB = 0.65 V 2.6
9.2 mA
VEA Error Amplifier Output Voltage Minimum 1 V
Maximum 2 V
GATE DRIVE
IQ-BOOT BOOT Pin Quiescent Current VBOOT = 12 V, VSD = 0 18 90 µA
RHG_UP High-Side MOSFET Driver Pull-Up
ON resistance VBOOT = 5 V at 350 mA Sourcing 3 Ω
RHG_DN High-Side MOSFET Driver Pull-
Down ON resistance HG = 5 V at 350 mA Sourcing 2 Ω
RLG_UP Low-Side MOSFET Driver Pull-Up
ON resistance VBOOT = 5 V at 350 mA Sourcing 3 Ω
RLG_DN Low-Side MOSFET Driver Pull-
Down ON resistance LG = 5 V at 350 mA Sourcing 2 Ω
OSCILLATOR
fSW PWM Frequency
RFADJ = 702.1 kΩ50
kHz
RFADJ = 98.74 kΩ300
RFADJ = 45.74 kΩ475 600 725
RFADJ = 24.91 kΩ1000
DMax High-Side Duty Cycle fSW = 300 kHz
fSW = 600 kHz
fSW = 1 MHz
80%
76%
73%
LOGIC INPUTS AND OUTPUTS
VSTBY-IH Standby High Trip Point VFB = 0.575 V, VBOOT = 3.3 V, VSD
Rising 1.1 V
VSTBY-IL Standby Low Trip Point VFB = 0.575 V, VBOOT = 3.3 V, VSD
Falling 0.232 V
VSD-IH SD Pin Logic High Trip Point VSD Rising 1.3 V
6
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Electrical Characteristics (continued)
Typical limits are for TJ= 25°C only, represent the most likely parametric norm at TJ= 25°C, and are provided for reference
purposes only; minimum and maximum limits apply over the junction temperature range of –40°C to 125°C. Unless otherwise
specified, VCC = 3.3 V. Data sheet minimum and maximum specification limits are specified by design, test, or statistical
analysis. (See (1))PARAMETER TEST CONDITIONS MIN TYP MAX UNIT
VSD-IL SD Pin Logic Low Trip Point VSD Falling 0.8 V
VPWGD-TH-LO PWGD Pin Trip Points FB Falling 0.408 0.434 0.457 V
VPWGD-TH-HI PWGD Pin Trip Points FB Rising 0.677 0.710 0.742 V
VPWGD-HYS PWGD Hysteresis FB Falling 60 mV
FB Rising 90
TEMPERATURE (oC)
-40 -25 -10 5 80 95 110125
20 35 50 65
BOOT PIN CURRENT (mA)
5.9
6
6.1
6.2
6.3
6.4
6.5
6.6
6.7
TEMPERATURE (oC)
-40 -25 -10 5 80 95 110125
20 35 50 65
9.3
9.4
9.5
9.6
9.7
9.8
9.9
10
BOOT PIN CURRENT (mA)
EFFICIENCY (%)
20
30
40
50
60
70
80
90
100
VIN = 12V
VIN = 5V
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
OUTPUT CURRENT (A)
0.05 0.25 0.45 0.65 0.85
FREQUENCY (MHz)
1.05
VCC OPERATING CURRENT
PLUS BOOT CURRENT (mA)
0
6
13
19
25
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
OUTPUT CURRENT (A)
20
30
40
50
60
70
80
90
100
EFFICIENCY (%)
VIN = 3.3V
VIN = 12V
VIN = 5V
EFFICIENCY (%)
20
30
40
50
60
70
80
90
100 VIN = 3.3V
VIN = 12V
VIN = 5V
0.0 0.4 0.8 1.2 1.6 2.0 2.4 2.8 3.2 3.6 4.0
OUTPUT CURRENT (A)
7
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6.6 Typical Characteristics
VCC = 3.3 V fSW = 300 kHz
Figure 1. Efficiency VOUT = 1.2 V
VCC = 3.3 V fSW = 300 kHz
Figure 2. Efficiency VOUT = 2.5 V
VCC = 5 V fSW = 300 kHz
Figure 3. Efficiency VOUT = 3.3 V
FDS6898A FET TA= 25°C
Figure 4. VCC Operating Current Plus BOOT Current vs
Frequency
fSW = 300 kHz FDS6898A FET No-Load
Figure 5. BOOT Pin Current vs Temperature for BOOT
Voltage = 3.3 V
fSW = 300 kHz FDS6898A FET No-Load
Figure 6. BOOT Pin Current vs Temperature for BOOT
Voltage = 5 V
2V/div
1V/div
5V/div
100 ns/DIV
LG
SW
HG
2V/div
1V/div
5V/div
100 ns/DIV
HG
SW
LG
0 0.4 0.8 1.2 1.6 2 2.4 2.8 3.2 3.6 4
1.200
1.201
1.202
1.203
1.204
1.205
1.206
1.207
1.208
1.209
1.210
OUTPUT VOLTAGE (V)
OUTPUT CURRENT (A)
TEMPERATURE (oC)
-55 -35 -15 85 105 125
5 25 45 65
FREQUENCY (kHz)
520
540
560
580
600
620
640
TEMPERATURE (oC)
-0.6
-0.5
-0.4
-0.3
-0.2
-0.1
0
0.1
0.2
INTERNAL REFERENCE
VOLTAGE ('%)
-40 -25 -10 5 80 95 110125
20 35 50 65
TEMPERATURE (oC)
-40 -25 -10 5 80 95 110125
20 35 50 65
BOOT PIN CURRENT (mA)
23.9
24
24.1
24.2
24.3
24.4
24.5
24.6
24.7
24.8
24.9
8
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Typical Characteristics (continued)
fSW = 300 kHz FDS6898A FET No-Load
Figure 7. BOOT Pin Current vs Temperature for BOOT
Voltage = 12 V Figure 8. Internal Reference Voltage vs Temperature
Figure 9. Frequency vs Temperature Figure 10. Output Voltage vs Output Current
VCC = 3.3 V VIN = 5 V VOUT = 1.2 V
IOUT = 4 A CSS = 12 nF fSW = 300 kHz
Figure 11. Switch Waveforms (HG Rising)
VCC = 3.3 V VIN = 5 V VOUT = 1.2 V
IOUT = 4 A CSS = 12 nF fSW = 300 kHz
Figure 12. Switch Waveforms (HG Falling)
100 mV/div
100 Ps/DIV
5V/div
VOUT
VIN
100mV/div
100 Ps/DIV
5V/div
VIN
VOUT
20mV/div
100 Ps/DIV
2A/div
VOUT
IOUT
20 mV/div
40 Ps/DIV
2A/div
VOUT
IOUT
50 mV/div
40 Ps/DIV
2A/div
VOUT
IOUT
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Typical Characteristics (continued)
VCC = 3.3 V VIN = 5V VOUT = 1.2V
CSS = 12 nF fSW = 300 kHz
Figure 13. Start-Up (No-Load)
IOUT = 0 A to 4 A VCC = 3.3 V VIN = 5 V
VOUT = 1.2 V CSS = 12nF fSW = 300 kHz
Figure 14. Load Transient Response
IOUT = 4 A to 0 A VCC = 3.3 V VIN = 5 V
VOUT = 1.2 V CSS = 12 nF fSW = 300 kHz
Figure 15. Load Transient Response
VCC = 3.3 V VIN = 5 V VOUT = 1.2 V
CSS = 12 nF fSW = 300 kHz
Figure 16. Load Transient Response
VIN = 3 V to 9 V VCC = 3.3 V VOUT = 1.2 V
Line () , IOUT = 2 A fSW = 300 kHz
Figure 17. Line Transient Response
VIN = 9 V to 3 V VCC = 3.3 V VOUT = 1.2 V
IOUT = 2 A fSW = 300 kHz
Figure 18. Transient Response
CSS = tSS
60
EA
PWM
ILIM
40 PA
10 PA
SYNCHRONOUS
DRIVER LOGIC
OV UV
10 Ps
DELAY
0.71V 0.434V
SHUT DOWN
LOGIC
UVLO
SD VCC SGND
FB EAO
BOOT
HG
LG
ISEN
PWGD
SS/TRACK
PGND
90 PA
SSDONE
Soft-Start
Comparator
+ Logic +
-+
-
VREF = 0.6V
REF
PWM LOGIC
CLOCK &
RAMP
FREQ PGND
1VPP
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7 Detailed Description
7.1 Overview
The LM2743 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It has
output shutdown (SD), input under-voltage lock-out (UVLO) mode and power good (PWGD) flag (based on over-
voltage and under-voltage detection). The over-voltage and under-voltage signals are logically OR'ed to drive the
power good signal and provide a logic signal to the system if the output voltage goes out of regulation. Current
limit is achieved by sensing the voltage VDS across the low-side MOSFET.
7.2 Functional Block Diagram
7.3 Feature Description
7.3.1 Start Up and Soft-Start
When VCC exceeds 2.76V and the shutdown pin (SD) sees a logic high, the soft-start period begins. Then an
internal, fixed 10 µA source begins charging the soft-start capacitor. During soft-start the voltage on the soft-start
capacitor CSS is connected internally to the non-inverting input of the error amplifier. The soft-start period lasts
until the voltage on the soft-start capacitor exceeds the LM2743 reference voltage of 0.6V. At this point the
reference voltage takes over at the non-inverting error amplifier input. The capacitance of CSS determines the
length of the soft-start period, and can be approximated by:
where
0.65 = VOUT1 RT1
RT1 + RT2
Master Power
Supply
VOUT1 = 5V
SS/TRACK
LM2743
RT2
1 k:
RT1
150:
RFB2
10 k:
RFB1
5 k:
FB
VOUT2 = 1.8V
VSS = 0.65V
VFB
RFADJ = -5.93 + 3.06 107
fSW + 0.24 1012
(fSW)2
RFB1
VOUT =RFB1 RFB2
+VFB
(VFB = 0.6V)
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Feature Description (continued)
• CSS is in µF and tSS is in ms (1)
During soft start the Power Good flag is forced low and it is released when the FB pin voltage reaches 70% of
0.6V. At this point the chip enters normal operation mode, and the output overvoltage and undervoltage
monitoring starts.
7.3.2 Normal Operation
While in normal operation mode, the LM2743 regulates the output voltage by controlling the duty cycle of the
high side and low side MOSFETs (see Typical Application Diagram). The equation governing output voltage is:
(2)
The PWM frequency is adjustable between 50 kHz and 1 MHz and is set by an external resistor, RFADJ, between
the FREQ pin and ground. The resistance needed for a desired frequency is approximately:
(3)
Where fSW is in Hz and RFADJ is in kΩ.
7.3.3 Tracking a Voltage Level
The LM2743 can track the output of a master power supply during soft-start by connecting a resistor divider to
the SS/TRACK pin. In this way, the output voltage slew rate of the LM2743 will be controlled by the master
supply for loads that require precise sequencing. When the tracking function is used no soft-start capacitor
should be connected to the SS/TRACK pin. Otherwise, a CSS value of at least 1 nF between the soft-start pin
and ground should be used.
Figure 19. Tracking Circuit
One way to use the tracking feature is to design the tracking resistor divider so that the master supply’s output
voltage (VOUT1) and the LM2743’s output voltage (represented symbolically in Figure 19 as VOUT2, that is, without
explicitly showing the power components) both rise together and reach their target values at the same time. For
this case, the equation governing the values of the tracking divider resistors RT1 and RT2 is:
(4)
5V
1.8V
1.8V
VOUT1
VOUT2
VOUT2 =VOUT1 RT1
RT1 + RT2
5V
1.8V
VOUT1
VOUT2
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Feature Description (continued)
The current through RT1 should be about 3 mA to 4 mA for precise tracking. The final voltage of the SS/TRACK
pin should be set higher than the feedback voltage of 0.6 V (say about 0.65 V as in the above equation). If the
master supply voltage was 5 V and the LM2743 output voltage was 1.8 V, for example, then the value of RT1
needed to give the two supplies identical soft-start times would be 150 Ω. A timing diagram for the equal soft-
start time case is shown in Figure 20.
Figure 20. Tracking with Equal Soft-Start Time
7.3.4 Tracking Voltage Slew Rate
The tracking feature can alternatively be used not to make both rails reach regulation at the same time but rather
to have similar rise rates (in terms of output dV/dt). This method ensures that the output voltage of the LM2743
always reaches regulation before the output voltage of the master supply. Because the output of the master
supply is divided down, in order to track properly the output voltage of the LM2743 must be lower than the
voltage of the master supply. In this case, the tracking resistors can be determined based on the following
equation:
(5)
For the example case of VOUT1 =5VandVOUT2 = 1.8 V, with RT1 set to 150 Ωas before, RT2 is calculated from
the above equation to be 265 Ω. A timing diagram for the case of equal slew rates is shown in Figure 21.
Figure 21. Tracking with Equal Slew Rates
7.3.5 Sequencing
The start up/soft-start of the LM2743 can be delayed for the purpose of sequencing by connecting a resistor
divider from the output of a master power supply to the SD pin, as shown in Figure 22.
t = 5 ms
VOUT1
VOUT2
5V
1.8V
VSD-IH
1.08V
RS1
SRSD = SROUT1 RS1 + RS2
Master Power
Supply
VOUT1
LM2743
RS1 RFB2
RFB1
FB
VOUT2
VFB
SD
RS2
13
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Feature Description (continued)
Figure 22. Sequencing Circuit
A desired delay time tDELAY between the startup of the master supply output voltage and the LM2743 output
voltage can be set based on the SD pin low-to-high threshold VSD-IH and the slew rate of the voltage at the SD
pin, SRSD:
tDELAY = VSD-IH / SRSD (6)
Note again, that in Figure 22, the output voltage of the LM2743 has been represented symbolically as VOUT2,.
without explicitly showing the power components.
VSD-IH is typically 1.08V and SRSD is the slew rate of the SD pin voltage. The values of the sequencing divider
resistors RS1 and RS2 set the SRSD based on the master supply output voltage slew rate, SROUT1, using the
following equation:
(7)
For example, if the master supply output voltage slew rate was 1V/ms and the desired delay time between the
startup of the master supply and LM2743 output voltage was 5ms, then the desired SD pin slew rate would be
(1.08V/5 ms) = 0.216 V/ms. Due to the internal impedance of the SD pin, the maximum recommended value for
RS2 is 1 kΩ. To achieve the desired slew rate, RS1 would then be 274 Ω. A timing diagram for this example is
shown in Figure 23.
Figure 23. Delay for Sequencing
8 PA
17 PA
Bias Enable
Soft-Start Enable
1.25V
10k
SD
+
-
14
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Feature Description (continued)
7.3.6 SD Pin Impedance
When connecting a resistor divider to the SD pin of the LM2743 some care has to be taken. Once the SD voltage
goes above VSD-IH, a 17-µA pull-up current is activated as shown in Figure 24. This current is used to create the
internal hysteresis (≊170 mV); however, high external impedances will affect the SD pin logic thresholds as well.
The external impedance used for the sequencing divider network should preferably be a small fraction of the
impedance of the SD pin for good performance (around 1 kΩ).
Figure 24. SD Pin Logic
7.3.7 MOSFET Gate Drivers
The LM2743 has two gate drivers designed for driving N-channel MOSFETs in a synchronous mode. Note that
unlike most other synchronous controllers, the bootstrap capacitor of the LM2743 provides power not only to the
driver of the upper MOSFET, but the lower MOSFET driver too (both drivers are ground referenced, i.e. no
floating driver). To fully turn the top MOSFET on, the BOOT voltage must be at least one gate threshold greater
than VIN when the high-side drive goes high. This bootstrap voltage is usually supplied from a local charge pump
structure. But looking at the Typical Application schematic, this also means that the difference voltage VCC - VD1,
which is the voltage the bootstrap capacitor charges up to, must be always greater than the maximum tolerance
limit of the threshold voltage of the upper MOSFET. Here VD1 is the forward voltage drop across the bootstrap
diode D1. This therefore may place restrictions on the minimum input voltage and/or type of MOSFET used.
The most basic charge bootstrap pump circuit can be built using one Schottky diode and a small capacitor, as
shown in Figure 25. The capacitor CBOOT serves to maintain enough voltage between the top MOSFET gate and
source to control the device even when the top MOSFET is on and its source has risen up to the input voltage
level. The charge pump circuitry is fed from VCC, which can operate over a range from 3.0V to 6.0V. Using this
basic method the voltage applied to the gates of both high-side and low-side MOSFETs is VCC - VD. This method
works well when VCC is 5 V±10%, because the gate drives will get at least 4.0V of drive voltage during the worst
case of VCC-MIN = 4.5 V and VD-MAX = 0.5 V. Logic level MOSFETs generally specify their on-resistance at VGS =
4.5 V. When VCC = 3.3 V ±10%, the gate drive at worst case could go as low as 2.5 V. Logic level MOSFETs are
not specified to turn on, or may have much higher on-resistance at 2.5 V. Sub-logic level MOSFETs, usually
specified at VGS = 2.5 V, will work, but are more expensive, and tend to have higher on-resistance. The circuit in
Figure 25 works well for input voltages ranging from 1 V up to 16 V and VCC = 5 V ±10%, because the drive
voltage depends only on VCC.
+
LG
HG
BOOT
+
VIN
D1
CBOOT
LM2743
LM78L05
5V
VO
VCC
+
BOOT
HG
LG
VIN
VO
VCC
+
LM2743
D1
CBOOT
15
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Feature Description (continued)
Figure 25. Basic Charge Pump (Bootstrap)
Note that the LM2743 can be paired with a low cost linear regulator like the LM78L05 to run from a single input
rail between 6.0 and 14 V. The 5-V output of the linear regulator powers both the VCC and the bootstrap circuit,
providing efficient drive for logic level MOSFETs. An example of this circuit is shown in Figure 26.
Figure 26. LM78L05 Feeding Basic Charge Pump
Figure 27 shows a second possibility for bootstrapping the MOSFET drives using a doubler. This circuit provides
an equal voltage drive of VCC - 3VD+ VIN to both the high-side and low-side MOSFET drives. This method should
only be used in circuits that use 3.3 V for both VCC and VIN. Even with VIN = VCC = 3.0 V (10% lower tolerance on
3.3 V) and VD= 0.5 V both high-side and low-side gates will have at least 4.5 V of drive. The power dissipation of
the gate drive circuitry is directly proportional to gate drive voltage, hence the thermal limits of the LM2743 IC will
quickly be reached if this circuit is used with VCC or VIN voltages over 5V.
+
BOOT
HG
LG
VIN
VO
VCC
+
LM2743
D1
D2D3
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Feature Description (continued)
Figure 27. Charge Pump with Added Gate Drive
All the gate drive circuits shown in Figure 25 through Figure 27 typically use 100-nF ceramic capacitors in the
bootstrap locations.
7.3.8 Power Good Signal
The open drain output on the Power Good pin needs a pull-up resistor to a low voltage source. The pull-up
resistor should be chosen so that the current going into the Power Good pin is less than 1 mA. A 100-kΩresistor
is recommended for most applications.
The Power Good signal is an OR-gated flag which takes into account both output over-voltage and under-voltage
conditions. If the feedback pin (FB) voltage is 18% above its nominal value (118% x VFB = 0.708V) or falls 28%
below that value (72 %x VFB = 0.42V) the Power Good flag goes low. The Power Good flag can be used to signal
other circuits that the output voltage has fallen out of regulation, however the switching of the LM2743 continues
regardless of the state of the Power Good signal. The Power Good flag will return to logic high whenever the
feedback pin voltage is between 72% and 118% of 0.6V.
7.3.9 UVLO
The 2.76V turn-on threshold on VCC has a built in hysteresis of about 300 mV. If VCC drops below 2.42V, the chip
enters UVLO mode. UVLO consists of turning off the top and bottom MOSFETS and remaining in that condition
until VCC rises above 2.76V. As with shutdown, the soft-start capacitor is discharged through an internal
MOSFET, ensuring that the next start-up will be controlled by the soft-start circuitry.
7.3.10 Current Limit
Current limit is realized by sensing the voltage across the low-side MOSFET while it is on. The RDS(ON) of the
MOSFET is a known value; hence the current through the MOSFET can be determined as:
VDS = IOUT x RDS(ON) (8)
The current through the low-side MOSFET while it is on is also the falling portion of the inductor current. The
current limit threshold is determined by an external resistor, RCS, connected between the switching node and the
ISEN pin. A constant current of 40 µA is forced through RCS, causing a fixed voltage drop. This fixed voltage is
compared against VDS and if the latter is higher, the current limit of the chip has been reached. To obtain a more
accurate value for RCS you must consider the operating values of RDS(ON) and ISEN-TH at their operating
temperatures in your application and the effect of slight parameter differences from part to part. RCS can be found
by using the following equation using the RDS(ON) value of the low side MOSFET at it's expected hot temperature
and the absolute minimum value expected over the full temperature range for the for the ISEN-TH which is 25 µA:
RCS = RDSON-HOT x ILIM / 40 µA (9)
IPK-CL = ILIM + (TSW - 200 ns) VIN - VO
L
ILIM
IL
D
Normal Operation Current Limit
VIN ± 9.5V
RCS 10 mA
t
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Feature Description (continued)
For example, a conservative 15-A current limit in a 10-A design with a minimum RDS(ON) of 10 mΩwould require
a 6-kΩresistor. To prevent the ISEN pin from sinking too much current when the switch node goes above 9.5 V,
the value of the current limit setting resistor RCS should not be too low. The criterion is as follows,
(10)
where the 10 mA is the maximum current ISEN pin is allowed to sink. For example if VIN = 13.2 V, the minimum
value of RCS is 370 Ω. Because current sensing is done across the low-side MOSFET, no minimum high-side on-
time is necessary. The LM2743 enters current limit mode if the inductor current exceeds the current limit
threshold at the point where the high-side MOSFET turns off and the low-side MOSFET turns on. (The point of
peak inductor current, see Figure 28). Note that in normal operation mode the high-side MOSFET always turns
on at the beginning of a clock cycle. In current limit mode, by contrast, the high-side MOSFET on-pulse is
skipped. This causes inductor current to fall. Unlike a normal operation switching cycle, however, in a current
limit mode switching cycle the high-side MOSFET will turn on as soon as inductor current has fallen to the
current limit threshold. The LM2743 will continue to skip high-side MOSFET pulses until the inductor current peak
is below the current limit threshold, at which point the system resumes normal operation.
Figure 28. Current Limit Threshold
Unlike a high-side MOSFET current sensing scheme, which limits the peaks of inductor current, low-side current
sensing is only allowed to limit the current during the converter off-time, when inductor current is falling.
Therefore in a typical current limit plot the valleys are normally well defined, but the peaks are variable, according
to the duty cycle. The PWM error amplifier and comparator control the off-pulse of the high-side MOSFET, even
during current limit mode, meaning that peak inductor current can exceed the current limit threshold. Assuming
that the output inductor does not saturate, the maximum peak inductor current during current limit mode can be
calculated with the following equation:
(11)
Where TSW is the inverse of switching frequency fSW. The 200 ns term represents the minimum off-time of the
duty cycle, which ensures enough time for correct operation of the current sensing circuitry.
(ILIM x RDS(ON)) ± (ISEN x RCS)
RCLF = RCS x VOUT
VIN ± 9.5V
RCS 10 mA
t
PLIM x RDS(ON) = RCS
ISEN
RCLF
VOUT
RCS SW
+
-
40 PA
ILIM ISEN
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Feature Description (continued)
In order to minimize the time period in which peak inductor current exceeds the current limit threshold, the IC
also discharges the soft-start capacitor through a fixed 90-µA sink. The output of the LM2743 internal error
amplifier is limited by the voltage on the soft-start capacitor. Hence, discharging the soft-start capacitor reduces
the maximum duty cycle D of the controller. During severe current limit this reduction in duty cycle will reduce the
output voltage if the current limit conditions last for an extended time. Output inductor current will be reduced in
turn to a flat level equal to the current limit threshold. The third benefit of the soft-start capacitor discharge is a
smooth, controlled ramp of output voltage when the current limit condition is cleared.
7.3.11 Foldback Current Limit
In the case where extra protection is used to help an output short condition, a current foldback resistor (RCLF)
should be considered, see Figure 29. First select the percentage of current limit foldback (PLIM):
PLIM = ILIM x P (12)
where P is a ratio between 0 and 1.
Figure 29. Foldback Current Limit Circuit
Obtain the RCS with the following equation:
(13)
where ISEN = 40 μA. If the switch node goes above 9.5 V the following criterion must be satisfied:
(14)
The equation for calculating the foldback resistance value is:
(15)
7.4 Device Functional Modes
7.4.1 Shutdown
If the shutdown pin is pulled low, (below 0.8 V) the LM2743 enters shutdown mode, and discharges the soft-start
capacitor through a MOSFET switch. The high and low-side MOSFETs are turned off. The LM2743 remains in
this state as long as VSD sees a logic low (see the Electrical Characteristics table). To assure proper IC start-up
the shutdown pin should not be left floating. For normal operation this pin should be connected directly to VCC or
to another voltage between 1.3 V to VCC (see the Electrical Characteristics table).
HG
BOOT
ISEN
LG
PGND
FB
VCC
SD
PWGD
FREQ
SS/TRACK
SGND
EAO
PGND
VCC = 3.3V VIN = 3.3V
VOUT = 1.2V@4A
RFB2
CC2 RC1
RCS
CSS
RFADJ
RCC
CCC
D1CBOOT
Q1 CIN1,2
L1
+
CC1 RFB1
CO1,2
LM2743
RC2 CC3
RPULL-UP +
19
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8 Application and Implementation
NOTE
Information in the following applications sections is not part of the TI component
specification, and TI does not warrant its accuracy or completeness. TI’s customers are
responsible for determining suitability of components for their purposes. Customers should
validate and test their design implementation to confirm system functionality.
8.1 Application Information
The LM2743 is a voltage-mode, high-speed synchronous buck regulator with a PWM control scheme. It is
designed for use in set-top boxes, thin clients, DSL/Cable modems, and other applications that require high-
efficiency buck converters. Use the following design procedure to select component values for the LM2743
device. Use the WEBENCH to generate a complete design (see Custom Design With WEBENCH® Tools.
8.2 Typical Applications
8.2.1 Synchronous Buck Converter Typical Application using LM2743
Figure 30. 3.3 V to 1.2 V at 4 A, fSW = 300 kHz
8.2.1.1 Design Requirements
The following section provides a step-by-step design guide of a voltage-mode synchronous buck converter using
the LM2743. This design converts 3.3 V (VIN) to 1.2 V (VOUT) at a maximum load of 4 A, with an efficiency of
89% and a switching frequency of 300 kHz. The same procedures can be followed to create many other designs
with varying input voltages, output voltages, and load currents.
8.2.1.2 Detailed Design Procedure
8.2.1.2.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM2743 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
PCAP = (IRMS_RIP)2 x ESR
n2
IRMS_RIP = IOUT x D(1 - D)
D =
VOUT + VSWL
VIN - VSWH + VSWL
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Typical Applications (continued)
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
8.2.1.2.2 Duty Cycle Calculation
The complete duty cycle for a buck converter is defined with Equation 16:
(16)
where VSWL and VSWH are the respective forward voltage drops that develop across the low side and high side
MOSFETs. Assuming the inductor ripple current is 20% to 30% of the output current, therefore:
VSWL = IOUT x RDS(ON)LOW (Low-Side MOSFET) (17)
VSWH = IOUT x RDS(ON)HIGH (High-Side MOSFET) (18)
To calculate the maximum duty cycle use the estimated 'hot' RDS(on) value of the MOSFETs, the minimum input
voltage, and maximum load. As shown in Figure 31, the worst case maximum duty cycles of the LM2743 occurs
at 125°C junction temperature vs VCC (IC control section voltage). Ensure that the operating duty cycle is below
the curve in Figure 31, if this condition is not satisfied, the system will be unable to develop the required duty
cycle to derive the necessary system power and so the output voltage will fall out of regulation.
Figure 31. Maximum Duty Cycle vs VCC
TJ= 125°C
8.2.1.2.3 Input Capacitor
The input capacitors in a Buck converter are subjected to high stress due to the input current trapezoidal
waveform. Input capacitors are selected for their ripple current capability and their ability to withstand the heat
generated since that ripple current passes through their ESR. Input rms ripple current is approximately:
(19)
The power dissipated by each input capacitor is:
(20)
ESRMAX = 'VOUT
'IOUT
VIN(MAX) - VO
'IOUT = FSW x LACTUAL x D
L = 3.3V - 1.2V
0.4 x 4A x 300 kHz x1.2V
3.3V
L = VIN - VOUT
'IOUT x fSW x D
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Typical Applications (continued)
where n is the number of capacitors, and ESR is the equivalent series resistance of each capacitor. The equation
above indicates that power loss in each capacitor decreases rapidly as the number of input capacitors increases.
The worst-case ripple for a Buck converter occurs during full load and when the duty cycle (D) is 0.5. For this
3.3V to 1.2V design the duty cycle is 0.364. For a 4A maximum load the ripple current is 1.92A.
8.2.1.2.4 Output Inductor
The output inductor forms the first half of the power stage in a Buck converter. It is responsible for smoothing the
square wave created by the switching action and for controlling the output current ripple (ΔIOUT). The inductance
is chosen by selecting between tradeoffs in efficiency and response time. The smaller the output inductor, the
more quickly the converter can respond to transients in the load current. However, as shown in the efficiency
calculations, a smaller inductor requires a higher switching frequency to maintain the same level of output current
ripple. An increase in frequency can mean increasing loss in the MOSFETs due to the charging and discharging
of the gates. Generally the switching frequency is chosen so that conduction loss outweighs switching loss. The
equation for output inductor selection is:
(21)
(22)
L = 1.6 µH (23)
Here we have plugged in the values for output current ripple, input voltage, output voltage, switching frequency,
and assumed a 40% peak-to-peak output current ripple. This yields an inductance of 1.6 µH. The output inductor
must be rated to handle the peak current (also equal to the peak switch current), which is (IOUT + (0.5 x ΔIOUT)) =
4.8 A, for a 4 A design. The Coilcraft DO3316P-222P is 2.2 µH, is rated to 7.4-A peak, and has a direct current
resistance (DCR) of 12 mΩ.
After selecting an output inductor, inductor current ripple should be re-calculated with the new inductance value,
as this information is needed to select the output capacitor. Re-arranging the equation used to select inductance
yields the following:
(24)
VIN(MAX) is assumed to be 10% above the steady state input voltage, or 3.6V. The actual current ripple will then
be 1.2A. Peak inductor/switch current will be 4.6A.
8.2.1.2.5 Output Capacitor
The output capacitor forms the second half of the power stage of a Buck switching converter. It is used to control
the output voltage ripple (ΔVOUT) and to supply load current during fast load transients.
In this example the output current is 4 A and the expected type of capacitor is an aluminum electrolytic, as with
the input capacitors. Other possibilities include ceramic, tantalum, and solid electrolyte capacitors, however the
ceramic type often do not have the large capacitance needed to supply current for load transients, and tantalums
tend to be more expensive than aluminum electrolytic. Aluminum capacitors tend to have very high capacitance
and fairly low ESR, meaning that the ESR zero, which affects system stability, will be much lower than the
switching frequency. The large capacitance means that at the switching frequency, the ESR is dominant, hence
the type and number of output capacitors is selected on the basis of ESR. One simple formula to find the
maximum ESR based on the desired output voltage ripple, ΔVOUT and the designed output current ripple, ΔIOUT,
is:
(25)
22
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Typical Applications (continued)
In this example, in order to maintain a 2% peak-to-peak output voltage ripple and a 40% peak-to-peak inductor
current ripple, the required maximum ESR is 20 mΩ. The Sanyo 4SP560M electrolytic capacitor will give an
equivalent ESR of 14 mΩ. The capacitance of 560 µF is enough to supply energy even to meet severe load
transient demands.
8.2.1.2.6 MOSFETs
Selection of the power MOSFETs is governed by a tradeoff between cost, size, and efficiency. One method is to
determine the maximum cost that can be endured, and then select the most efficient device that fits that price.
Breaking down the losses in the high-side and low-side MOSFETs and then creating spreadsheets is one way to
determine relative efficiencies between different MOSFETs. Good correlation between the prediction and the
bench result is not specified, however. Single-channel buck regulators that use a controller IC and discrete
MOSFETs tend to be most efficient for output currents of 2A to 10A.
Losses in the high-side MOSFET can be broken down into conduction loss, gate charging loss, and switching
loss. Conduction loss, or I2R loss, is approximately:
PC= D ((IO)2x RDSON-HI x 1.3) (High-Side MOSFET) (26)
PC= (1 - D) x ((IO)2x RDSON-LO x 1.3) (Low-Side MOSFET) (27)
In the above equations, the factor 1.3 accounts for the increase in MOSFET RDSON due to heating. Alternatively,
the 1.3 can be ignored and the RDSON of the MOSFET estimated using the RDSON Vs. Temperature curves in the
MOSFET datasheets.
Gate charging loss results from the current driving the gate capacitance of the power MOSFETs, and is
approximated as:
PGC = n x (VDD) x QGx fSW (28)
where ‘n’ is the number of MOSFETs (if multiple devices have been placed in parallel), VDD is the driving voltage
(see MOSFET Gate Drivers section) and QGS is the gate charge of the MOSFET. If different types of MOSFETs
are used, the nterm can be ignored and their gate charges simply summed to form a cumulative QG. Gate
charge loss differs from conduction and switching losses in that the actual dissipation occurs in the LM2743, and
not in the MOSFET itself.
Switching loss occurs during the brief transition period as the high-side MOSFET turns on and off, during which
both current and voltage are present in the channel of the MOSFET. It can be approximated as:
PSW = 0.5 x VIN x IOx (tr+ tf) x fSW (29)
where tRand tFare the rise and fall times of the MOSFET. Switching loss occurs in the high-side MOSFET only.
For this example, the maximum drain-to-source voltage applied to either MOSFET is 3.6V. The maximum drive
voltage at the gate of the high-side MOSFET is 3.1V, and the maximum drive voltage for the low-side MOSFET
is 3.3V. Due to the low drive voltages in this example, a MOSFET that turns on fully with 3.1V of gate drive is
needed. For designs of 5A and under, dual MOSFETs in SOIC-8 package provide a good trade-off between size,
cost, and efficiency.
8.2.1.2.7 Support Components
CIN2 - A small value (0.1-µF to 1-µF) ceramic capacitor should be placed as close as possible to the drain of the
high-side MOSFET and source of the low-side MOSFET (dual MOSFETs make this easy). This capacitor should
be X5R type dielectric or better.
RCC, CCC- These are standard filter components designed to ensure smooth DC voltage for the chip supply. RCC
should be 1 Ωto 10 Ω. CCC should 1 µF, X5R type or better.
CBOOT- Bootstrap capacitor, typically 100 nF.
RPULL-UP – This is a standard pull-up resistor for the open-drain power good signal (PWGD). The recommended
value is 10 kΩconnected to VCC. If this feature is not necessary, the resistor can be omitted.
= 4.5 kHz
RO + RL
fDP = 1
2SLCO(RO + ESR)
VIN
ADC = VRAMP =3.3
1.0 = 10.4 dB
+
-
+
VRAMP
+
-
VREF
+
-
10 k:
10 k:
CC1
CC2 RC1
RC2
CC3
LRL
CO
RO
VIN
RC
+
-
23
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Typical Applications (continued)
D1- A small Schottky diode should be used for the bootstrap. It allows for a minimum drop for both high and low-
side drivers. The MBR0520 or BAT54 work well in most designs.
RCS - Resistor used to set the current limit. Since the design calls for a peak current magnitude (IOUT+ (0.5 x
ΔIOUT)) of 4.8 A, a safe setting would be 6A. (This is below the saturation current of the output inductor, which is
7 A.) Following the equation from the Current Limit section, a 1.3-kΩresistor should be used.
RFADJ - This resistor is used to set the switching frequency of the chip. The resistor value is calculated from
equation in Normal Operation section. For 300-kHz operation, a 97.6-kΩresistor should be used.
CSS - The soft-start capacitor depends on the user requirements and is calculated based on the equation given in
the section titled Start Up and Soft-Start. Therefore, for a 700-μs delay, a 12-nF capacitor is suitable.
8.2.1.2.8 Control Loop Compensation
The LM2743 uses voltage-mode (‘VM’) PWM control to correct changes in output voltage due to line and load
transients. One of the attractive advantages of voltage mode control is its relative immunity to noise and layout.
However VM requires careful small signal compensation of the control loop for achieving high bandwidth and
good phase margin.
The control loop is comprised of two parts. The first is the power stage, which consists of the duty cycle
modulator, output inductor, output capacitor, and load. The second part is the error amplifier, which for the
LM2743 is a 9-MHz op-amp used in the classic inverting configuration. Figure 32 shows the regulator and control
loop components.
Figure 32. Power Stage and Error Amplifier
One popular method for selecting the compensation components is to create Bode plots of gain and phase for
the power stage and error amplifier. Combined, they make the overall bandwidth and phase margin of the
regulator easy to see. Software tools such as Excel, MathCAD, and Matlab are useful for showing how changes
in compensation or the power stage affect system gain and phase.
The power stage modulator provides a DC gain ADC that is equal to the input voltage divided by the peak-to-peak
value of the PWM ramp. This ramp is 1.0VP-P for the LM2743. The inductor and output capacitor create a
double pole at frequency fDP, and the capacitor ESR and capacitance create a single zero at frequency fESR. For
this example, with VIN = 3.3 V, these quantities are:
(30)
(31)
GEA = AEA x
s
2SfZ1 + 1 s
2SfZ2 + 1
s
2SfP1 + 1 s
2SfP2 + 1
s
100 1k 10k 100k 1M
FREQUENCY (Hz)
-60
-44
-28
-12
4
20
GAIN (dB)
100 1k 10k 100k 1M
FREQUENCY (Hz)
-150
-120
-90
-60
-30
0
PHASE (o)
VIN x RO
GPS = VRAMP
sCORC + 1
a x s2 + b x s + c
x
1
fESR = 2SCOESR = 20.3 kHz
24
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Typical Applications (continued)
(32)
In the equation for fDP, the variable RLis the power stage resistance, and represents the inductor DCR plus the
on resistance of the top power MOSFET. ROis the output voltage divided by output current. The power stage
transfer function GPS is given by the following equation, and Figure 34 shows Bode plots of the phase and gain in
this example.
where
• a = LCO(RO+ RC)
• b = L + CO(RORL+ RORC+ RCRL)
• c = RO+ RL(33)
Figure 33. Gain vs Frequency Figure 34. Power Stage Gain and Phase
The double pole at 4.5 kHz causes the phase to drop to approximately -130° at around 10 kHz. The ESR zero, at
20.3 kHz, provides a +90° boost that prevents the phase from dropping to -180º. If this loop were left
uncompensated, the bandwidth would be approximately 10 kHz and the phase margin 53°. In theory, the loop
would be stable, but would suffer from poor DC regulation (due to the low DC gain) and would be slow to
respond to load transients (due to the low bandwidth.) In practice, the loop could easily become unstable due to
tolerances in the output inductor, capacitor, or changes in output current, or input voltage. Therefore, the loop is
compensated using the error amplifier and a few passive components.
For this example, a Type III, or three-pole-two-zero approach gives optimal bandwidth and phase.
In most voltage mode compensation schemes, including Type III, a single pole is placed at the origin to boost DC
gain as high as possible. Two zeroes fZ1 and fZ2 are placed at the double pole frequency to cancel the double
pole phase lag. Then, a pole, fP1 is placed at the frequency of the ESR zero. A final pole fP2 is placed at one-half
of the switching frequency. The gain of the error amplifier transfer function is selected to give the best bandwidth
possible without violating the Nyquist stability criteria. In practice, a good crossover point is one-fifth of the
switching frequency, or 60 kHz for this example. The generic equation for the error amplifier transfer function is:
(34)
1
CC2 =AEA x 10,000 - CC1 = 882 pF
fZ1
CC1 = AEA x 10,000 x fP2 = 27 pF
100 1k 10k 100k 1M
FREQUENCY (Hz)
-100
-70
-40
-10
20
50
PHASE (o)
100 1k 10k 100k 1M
FREQUENCY (Hz)
0
12
24
36
48
60
GAIN (dB)
GEA x OPG
HEA = 1 + GEA + OPG
2S x 9 MHz
OPG = s
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Typical Applications (continued)
In this equation, the variable AEA is a ratio of the values of the capacitance and resistance of the compensation
components, arranged as shown in Figure 32. AEA is selected to provide the desired bandwidth. A starting value
of 80,000 for AEA should give a conservative bandwidth. Increasing the value will increase the bandwidth, but will
also decrease phase margin. Designs with 45° to 60° are usually best because they represent a good trade-off
between bandwidth and phase margin. In general, phase margin is lowest and gain highest (worst-case) for
maximum input voltage and minimum output current. One method to select AEA is to use an iterative process
beginning with these worst-case conditions.
1. Increase AEA
2. Check overall bandwidth and phase margin
3. Change VIN to minimum and recheck overall bandwidth and phase margin
4. Change IOto maximum and recheck overall bandwidth and phase margin
The process ends when the both bandwidth and the phase margin are sufficiently high. For this example input
voltage can vary from 3.0 to 3.6 V and output current can vary from 0 to 4 A, and after a few iterations a
moderate gain factor of 101 dB is used.
The error amplifier of the LM2743 has a unity-gain bandwidth of 9 MHz. In order to model the effect of this
limitation, the open-loop gain can be calculated as:
(35)
The new error amplifier transfer function that takes into account unity-gain bandwidth is:
(36)
The gain and phase of the error amplifier are shown in Figure 36.
Figure 35. Gain vs Frequency Figure 36. Error Amplifier Gain and Phase
In VM regulators, the top feedback resistor RFB2 forms a part of the compensation. Setting RFB2 to 10 kΩ, ±1%
usually gives values for the other compensation resistors and capacitors that fall within a reasonable range.
(Capacitances > 1 pF, resistances < 1 MΩ) CC1, CC2, CC3, RC1, and RC2 are selected to provide the poles and
zeroes at the desired frequencies, using the following equations:
(37)
(38)
GEA-ACTUAL x OPG
HEA = 1 + GEA-ACTUAL+ OPG
Z1 =
RC2 +1
sCC3
RC1 + RC2 1
sCC3
+
RC1
1
ZF = sCC1 x 10,000 + 1
sCC2
10,000 + 1
sCC1
1
sCC2
+
GEA-ACTUAL = ZF
ZI
1
RC2 = 2SxCC3 x fP1 = 2.55 k:
1
RC1 = 2SxCC2 x fZ1 = 39.8 k:
1
CC3 = 2S x 10,000 x= 2.73 nF
1
fZ2 -1
fP1
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Typical Applications (continued)
(39)
(40)
(41)
In practice, a good trade off between phase margin and bandwidth can be obtained by selecting the closest
±10% capacitor values above what are suggested for CC1 and CC2, the closest ±10% capacitor value below the
suggestion for CC3, and the closest ±1% resistor values below the suggestions for RC1, RC2. Note that if the
suggested value for RC2 is less than 100Ω, it should be replaced by a short circuit. Following this guideline, the
compensation components will be:
CC1 = 27 pF ±10%
CC2 = 820 pF ±10%
CC3 = 2.7 nF ±10%
RC1 = 39.2 kΩ±1%
RC2 = 2.55 kΩ±1%
The transfer function of the compensation block can be derived by considering the compensation components as
impedance blocks ZFand ZIaround an inverting op-amp:
(42)
(43)
(44)
As with the generic equation, GEA-ACTUAL must be modified to take into account the limited bandwidth of the error
amplifier. The result is:
(45)
The total control loop transfer function H is equal to the power stage transfer function multiplied by the error
amplifier transfer function.
H = GPS x HEA (46)
K = POUT
POUT + PTOTAL
x 100%
-180
-156
-132
-108
-84
-60
PHASE (o)
100 1k 10k 100k 1M
FREQUENCY (Hz)
-40
-20
0
20
40
60
GAIN (dB)
100 1k 10k 100k 1M
FREQUENCY (Hz)
27
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Typical Applications (continued)
The bandwidth and phase margin can be read graphically from Bode plots of HEA are shown in Figure 38.
Figure 37. Gain vs Frequency Figure 38. Overall Loop Gain and Phase
The bandwidth of this example circuit is 59 kHz, with a phase margin of 60°.
8.2.1.2.9 Efficiency Calculations
The following is a sample calculation.
A reasonable estimation of the efficiency of a switching buck controller can be obtained by adding together the
Output Power (POUT) loss and the Total Power (PTOTAL) loss:
(47)
The Output Power (POUT) for the Figure 30 design is (1.2 V x 4 A) = 4.8 W. The Total Power (PTOTAL), with an
efficiency calculation to complement the design, is shown below.
The majority of the power losses are due to low and high side of MOSFET’s losses. The losses in any MOSFET
are group of switching (PSW) and conduction losses(PCND).
PFET = PSW + PCND = 61.38 mW + 270.42 mW (48)
PFET = 331.8 mW (49)
The following equations show FET Switching Loss (PSW).
PSW = PSW(ON) + PSW(OFF) (50)
PSW = 0.5 x VIN x IOUT x (tr+ tf) x fSW (51)
PSW = 0.5 x 3.3 V x 4 A x 300 kHz x 31 ns (52)
PSW = 61.38 mW (53)
The FDS6898A has a typical turn-on rise time trand turn-off fall time tfof 15 ns and 16 ns, respectively. The
switching losses for this type of dual N-Channel MOSFETs are 0.061 W.
The following equations show FET Conduction Loss (PCND).
PCND = PCND1 + PCND2 (54)
PCND1 = (IOUT)2x RDS(ON) x k x D (55)
PCND2 = (IOUT)2x RDS(ON) x k x (1-D) (56)
RDS(ON) = 13 mΩand the factor is a constant value (k = 1.3) to account for the increasing RDS(ON) of a FET due to
heating.
PCND1 = (4A)2x 13 mΩx 1.3 x 0.364 (57)
K = 4.8W
4.8W + 0.6W = 89%
K = POUT
POUT + PTOTAL
x 100%
PCAP = (1.924A)2 x 24 m:
12
IRMS_RIP = IOUT x D(1 - D)
PCAP = (IRMS_RIP)2 x ESR
n2
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Typical Applications (continued)
PCND2 = (4A)2x 13 mΩx 1.3 x (1 - 0.364) (58)
PCND = 98.42 mW + 172 mW = 270.42 mW (59)
There are few additional losses that are taken into account:
The following equations show IC Operating Loss (PIC).
PIC = IQ_VCC x VCC, (60)
where IQ-VCC is the typical operating VCC current
PIC= 1.5 mA x 3.3V = 4.95 mW (61)
The following equations show FET Gate Charging Loss (PGATE).
PGATE = n x VCC x QGS x fSW (62)
PGATE = 2 x 3.3 V x 3 nC x 300 kHz (63)
PGATE = 5.94 mW (64)
The value n is the total number of FETs used and QGS is the typical gate-source charge value, which is 3 nC. For
the FDS6898A the gate charging loss is 5.94 mW.
The following equations show Input Capacitor Loss (PCAP).
where (65)
(66)
Here n is the number of paralleled capacitors, ESR is the equivalent series resistance of each, and PCAP is the
dissipation in each. So for example if we use only one input capacitor of 24 mΩ.
(67)
PCAP = 88.8 mW (68)
The following equation shows Output Inductor Loss (PIND).
PIND = I2OUT x DCR (69)
where DCR is the DC resistance. Therefore, for example
PIND = (4A)2x 11 mΩ(70)
PIND = 176 mW (71)
The following equations show Total System Efficiency.
PTOTAL = PFET + PIC + PGATE + PCAP + PIND (72)
(73)
(74)
HG
BOOT
ISEN
LG
PGND
FB
VCC
SD
PWGD
FREQ
SS/TRACK
SGND
EAO
PGND
VCC = VIN= 3.3V
VOUT = 1.8V@2A
RFB2
CC2 RC1
RCS
CSS
RFADJ
RCC
CCC
D1CBOOT
Q1 CIN1,2
L1
+
CC1 RFB1
CO1,2
LM2743
RC2 CC3
RPULL-UP +
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Typical Applications (continued)
8.2.1.3 Application Curves
VCC = 3.3V VOUT = 1.2V
IOUT = 4A CSS = 12nF fSW = 300 kHz
Figure 39. Start-Up (Full-Load)
VCC = 3.3 V VOUT = 1.2 V
IOUT = 4 A CSS = 12 nF fSW = 300 kHz
Figure 40. Shutdown (Full-Load)
8.2.2 Example Circuit 1
Figure 41. 3.3 V to 1.8 V at 2 A, fSW = 300 kHz
8.2.2.1 Design Requirements
This design converts 3.3 V (VIN) to 1.8 V (VOUT) at a maximum load of 2 A, with a switching frequency of 300
kHz.
8.2.2.2 Detailed Design Procedure
Follow the detailed design procedure in Detailed Design Procedure.
HG
BOOT
ISEN
LG
PGND
FB
VCC
SD
PWGD
FREQ
SS/TRACK
SGND
EAO
PGND
VCC = 5V
VIN = 5V
VOUT = 2.5V@2A
RFB2
CC2 RC1
RCS
CSS
RFADJ
RCC
CCC
D1CBOOT
Q1 CIN1,2
L1
+
CC1
RFB1
CO1,2
LM2743
RC2 CC3
RPULL-UP +
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Typical Applications (continued)
8.2.2.3 Bill of Materials
Table 1. Bill of Materials
PART PART NUMBER TYPE PACKAGE DESCRIPTION VENDOR
U1 LM2743 Synchronous
Controller TSSOP-14 TI
Q1 FDS6898A Dual N-MOSFET SOIC-8 20 V, 10 mΩat 4.5 V,
16 nC Fairchild
D1 MBR0520LTI Schottky Diode SOD-123
L1 DO3316P-472 Inductor 4.7 µH, 4.8 Arms, 18
mΩCoilcraft
CIN1 16SP100M Aluminum Electrolytic 10mm x 6mm 100 µF, 16 V, 2.89
Arms Sanyo
CO1 6SP220M Aluminum Electrolytic 10mm x 6mm 220 µF, 6.3 V, 3.1
Arms Sanyo
CCC, CBOOT,
CIN2, CO2VJ1206Y104KXXA Capacitor 1206 0.1 µF, 10% Vishay
CC3 VJ0805Y332KXXA Capacitor 805 3300 pF, 10% Vishay
CSS VJ0805A123KXAA Capacitor 805 12 nF, 10% Vishay
CC2 VJ0805A821KXAA Capacitor 805 820 pF 10% Vishay
CC1 VJ0805A220KXAA Capacitor 805 22 pF, 10% Vishay
RFB2 CRCW08051002F Resistor 805 10.0 kΩ1% Vishay
RFB1 CRCW08054991F Resistor 805 4.99 kΩ1% Vishay
RFADJ CRCW08051103F Resistor 805 110 kΩ1% Vishay
RC2 CRCW08052101F Resistor 805 2.1 kΩ1% Vishay
RCS CRCW08052101F Resistor 805 2.1 kΩ1% Vishay
RCC CRCW080510R0F Resistor 805 10.0 Ω1% Vishay
RC1 CRCW08055492F Resistor 805 54.9 kΩ1% Vishay
RPULL-UP CRCW08051003J Resistor 805 100 kΩ5% Vishay
8.2.3 Example Circuit 2
Figure 42. 5 V to 2.5 V at 2A, fSW = 300kHz
8.2.3.1 Design Requirements
This design converts 5 V (VIN) to 2.5 V (VOUT) at a maximum load of 2 A, with a switching frequency of 300 kHz.
HG
BOOT
ISEN
LG
PGND
FB
VCC
SD
PWGD
FREQ
SS/TRACK
SGND
EAO
PGND
VCC = 5V
VIN = 12V
VOUT = 3.3V@4A
RFB2
CC2 RC1
RCS
CSS
RFADJ
RCC
CCC
D1CBOOT
Q1 CIN1,2
L1
+
CC1
RFB1
CO1,2
LM2743
RC2 CC3
RPULL-UP +
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8.2.3.2 Detailed Design Procedure
Follow the detailed design procedure in Detailed Design Procedure.
8.2.3.3 Bill of Materials
Table 2. Bill of Materials
PART PART NUMBER TYPE PACKAGE DESCRIPTION VENDOR
U1 LM2743 Synchronous
Controller TSSOP-14 TI
Q1 FDS6898A Dual N-MOSFET SOIC-8 20 V, 10 mΩat 4.5 V, 16
nC Fairchild
D1 MBR0520LTI Schottky Diode SOD-123
L1 DO3316P-682 Inductor 6.8 µH, 4.4 Arms, 27 mΩCoilcraft
CIN1 16SP100M Aluminum
Electrolytic 10mm x 6mm 100 µF, 16 V, 2.89 Arms Sanyo
CO1 10SP56M Aluminum
Electrolytic 6.3mm x 6mm 56 µF, 10 V, 1.7 Arms Sanyo
CCC, CBOOT,
CIN2, CO2VJ1206Y104KXXA Capacitor 1206 0.1 µF, 10% Vishay
CC3 VJ0805Y182KXXA Capacitor 805 1800 pF, 10% Vishay
CSS VJ0805A123KXAA Capacitor 805 12 nF, 10% Vishay
CC2 VJ0805A821KXAA Capacitor 805 820 pF 10% Vishay
CC1 VJ0805A330KXAA Capacitor 805 33 pF, 10% Vishay
RFB2 CRCW08051002F Resistor 805 10.0 kΩ1% Vishay
RFB1 CRCW08053161F Resistor 805 3.16 kΩ1% Vishay
RFADJ CRCW08051103F Resistor 805 110 kΩ1% Vishay
RC2 CRCW08051301F Resistor 805 1.3 kΩ1% Vishay
RCS CRCW08052101F Resistor 805 2.1 kΩ1% Vishay
RCC CRCW080510R0F Resistor 805 10.0 Ω1% Vishay
RC1 CRCW08053322F Resistor 805 33.2 kΩ1% Vishay
RPULL-UP CRCW08051003J Resistor 805 100 kΩ5% Vishay
8.2.4 Example Circuit 3
Figure 43. 12 V to 3.3 V at 4 A, fSW = 300 kHz
8.2.4.1 Design Requirements
This design converts 12 V (VIN) to 3.3 V (VOUT) at a maximum load of 4 A, with a switching frequency of 300 kHz.
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8.2.4.2 Detailed Design Procedure
Follow the detailed design procedure in Detailed Design Procedure.
8.2.4.3 Bill of Materials
Table 3. Bill of Materials
PART PART NUMBER TYPE PACKAGE DESCRIPTION VENDOR
U1 LM2743 Synchronous
Controller TSSOP-14 TI
Q1 FDS6898A Dual N-MOSFET SOIC-8 20 V, 10 mΩat 4.5 V, 16
nC Fairchild
D1 MBR0520LTI Schottky Diode SOD-123
L1 DO3316P-332 Inductor 3.3 µH, 5.4 Arms, 15 mΩCoilcraft
CIN1 16SP100M Aluminum Electrolytic 10 mm x 6 mm 100 µF, 16 V, 2.89 Arms Sanyo
CO1 6SP220M Aluminum Electrolytic 10 mm x 6 mm 220 µF, 6.3 V 3.1 Arms Sanyo
CCC, CBOOT,
CIN2, CO2VJ1206Y104KXXA Capacitor 1206 0.1 µF, 10% Vishay
CC3 VJ0805Y222KXXA Capacitor 805 2200 pF, 10% Vishay
CSS VJ0805A123KXAA Capacitor 805 12 nF, 10% Vishay
CC2 VJ0805Y332KXXA Capacitor 805 3300 pF 10% Vishay
CC1 VJ0805A820KXAA Capacitor 805 82 pF, 10% Vishay
RFB2 CRCW08051002F Resistor 805 10.0 kΩ1% Vishay
RFB1 CRCW08052211F Resistor 805 2.21 kΩ1% Vishay
RFADJ CRCW08051103F Resistor 805 110 kΩ1% Vishay
RC2 CRCW08052611F Resistor 805 2.61 kΩ1% Vishay
RCS CRCW08054121F Resistor 805 4.12 kΩ1% Vishay
RCC CRCW080510R0F Resistor 805 10.0 Ω1% Vishay
RC1 CRCW08051272F Resistor 805 12.7 kΩ1% Vishay
RPULL-UP CRCW08051003J Resistor 805 100 kΩ5% Vishay
Controller
VOUTGNDGNDVIN
Inductor
CIN
CIN
COUT
COUT
QHQL
Place controller as
close to the switches
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9 Power Supply Recommendations
The LM2743 is a power management device. The power supply for the device is any DC voltage source within
the specified input range (see Design Requirements).
10 Layout
10.1 Layout Guidelines
In a buck regulator, the primary switching loop consists of the input capacitor and MOSFET switches. Minimixing
the area of this loop reduces the stray inductance, and minimizes noise and possible erratic operation. High
quality input capacitors should be placed as close as possible to the MOSFET switches, with the positive side of
the input capacitor connected directly to the high-side MOSFET drain, and the ground side of the capacitor
connected as close as possible to the low-side MOSFET switch ground connection. Connect all of the low power
ground connections directly to the SGND pin. Connect the VCC capacitor directly to the PGND pin.
10.2 Layout Example
Figure 44. Layout Recommendation
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11 Device and Documentation Support
11.1 Device Support
11.1.1 Development Support
11.1.1.1 Custom Design With WEBENCH® Tools
Click here to create a custom design using the LM2743 device with the WEBENCH® Power Designer.
1. Start by entering the input voltage (VIN), output voltage (VOUT), and output current (IOUT) requirements.
2. Optimize the design for key parameters such as efficiency, footprint, and cost using the optimizer dial.
3. Compare the generated design with other possible solutions from Texas Instruments.
The WEBENCH Power Designer provides a customized schematic along with a list of materials with real-time
pricing and component availability.
In most cases, these actions are available:
• Run electrical simulations to see important waveforms and circuit performance
• Run thermal simulations to understand board thermal performance
• Export customized schematic and layout into popular CAD formats
• Print PDF reports for the design, and share the design with colleagues
Get more information about WEBENCH tools at www.ti.com/WEBENCH.
11.2 Receiving Notification of Documentation Updates
To receive notification of documentation updates, navigate to the device product folder on ti.com. In the upper
right corner, click on Alert me to register and receive a weekly digest of any product information that has
changed. For change details, review the revision history included in any revised document.
11.3 Community Resources
The following links connect to TI community resources. Linked contents are provided "AS IS" by the respective
contributors. They do not constitute TI specifications and do not necessarily reflect TI's views; see TI's Terms of
Use.
TI E2E™ Online Community TI's Engineer-to-Engineer (E2E) Community. Created to foster collaboration
among engineers. At e2e.ti.com, you can ask questions, share knowledge, explore ideas and help
solve problems with fellow engineers.
Design Support TI's Design Support Quickly find helpful E2E forums along with design support tools and
contact information for technical support.
11.4 Trademarks
E2E is a trademark of Texas Instruments.
WEBENCH is a registered trademark of Texas Instruments.
All other trademarks are the property of their respective owners.
11.5 Electrostatic Discharge Caution
These devices have limited built-in ESD protection. The leads should be shorted together or the device placed in conductive foam
during storage or handling to prevent electrostatic damage to the MOS gates.
11.6 Glossary
SLYZ022 —TI Glossary.
This glossary lists and explains terms, acronyms, and definitions.
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12 Mechanical, Packaging, and Orderable Information
The following pages include mechanical, packaging, and orderable information. This information is the most
current data available for the designated devices. This data is subject to change without notice and revision of
this document. For browser-based versions of this data sheet, refer to the left-hand navigation.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 1
PACKAGING INFORMATION
Orderable Device Status
(1)
Package Type Package
Drawing Pins Package
Qty Eco Plan
(2)
Lead finish/
Ball material
(6)
MSL Peak Temp
(3)
Op Temp (°C) Device Marking
(4/5)
Samples
LM2743MTC NRND TSSOP PW 14 94 Non-RoHS
& Green Call TI Call TI -40 to 125 2743
MTC
LM2743MTC/NOPB ACTIVE TSSOP PW 14 94 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2743
MTC
LM2743MTCX/NOPB ACTIVE TSSOP PW 14 2500 RoHS & Green NIPDAU | SN Level-1-260C-UNLIM -40 to 125 2743
MTC
(1) The marketing status values are defined as follows:
ACTIVE: Product device recommended for new designs.
LIFEBUY: TI has announced that the device will be discontinued, and a lifetime-buy period is in effect.
NRND: Not recommended for new designs. Device is in production to support existing customers, but TI does not recommend using this part in a new design.
PREVIEW: Device has been announced but is not in production. Samples may or may not be available.
OBSOLETE: TI has discontinued the production of the device.
(2) RoHS: TI defines "RoHS" to mean semiconductor products that are compliant with the current EU RoHS requirements for all 10 RoHS substances, including the requirement that RoHS substance
do not exceed 0.1% by weight in homogeneous materials. Where designed to be soldered at high temperatures, "RoHS" products are suitable for use in specified lead-free processes. TI may
reference these types of products as "Pb-Free".
RoHS Exempt: TI defines "RoHS Exempt" to mean products that contain lead but are compliant with EU RoHS pursuant to a specific EU RoHS exemption.
Green: TI defines "Green" to mean the content of Chlorine (Cl) and Bromine (Br) based flame retardants meet JS709B low halogen requirements of <=1000ppm threshold. Antimony trioxide based
flame retardants must also meet the <=1000ppm threshold requirement.
(3) MSL, Peak Temp. - The Moisture Sensitivity Level rating according to the JEDEC industry standard classifications, and peak solder temperature.
(4) There may be additional marking, which relates to the logo, the lot trace code information, or the environmental category on the device.
(5) Multiple Device Markings will be inside parentheses. Only one Device Marking contained in parentheses and separated by a "~" will appear on a device. If a line is indented then it is a continuation
of the previous line and the two combined represent the entire Device Marking for that device.
(6) Lead finish/Ball material - Orderable Devices may have multiple material finish options. Finish options are separated by a vertical ruled line. Lead finish/Ball material values may wrap to two
lines if the finish value exceeds the maximum column width.
Important Information and Disclaimer:The information provided on this page represents TI's knowledge and belief as of the date that it is provided. TI bases its knowledge and belief on information
provided by third parties, and makes no representation or warranty as to the accuracy of such information. Efforts are underway to better integrate information from third parties. TI has taken and
continues to take reasonable steps to provide representative and accurate information but may not have conducted destructive testing or chemical analysis on incoming materials and chemicals.
TI and TI suppliers consider certain information to be proprietary, and thus CAS numbers and other limited information may not be available for release.
PACKAGE OPTION ADDENDUM
www.ti.com 11-Jan-2021
Addendum-Page 2
In no event shall TI's liability arising out of such information exceed the total purchase price of the TI part(s) at issue in this document sold by TI to Customer on an annual basis.
TAPE AND REEL INFORMATION
*All dimensions are nominal
Device Package
Type Package
Drawing Pins SPQ Reel
Diameter
(mm)
Reel
Width
W1 (mm)
A0
(mm) B0
(mm) K0
(mm) P1
(mm) W
(mm) Pin1
Quadrant
LM2743MTCX/NOPB TSSOP PW 14 2500 330.0 12.4 6.9 5.6 1.6 8.0 12.0 Q1
LM2743MTCX/NOPB TSSOP PW 14 2500 330.0 12.4 6.95 5.6 1.6 8.0 12.0 Q1
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Dec-2020
Pack Materials-Page 1
*All dimensions are nominal
Device Package Type Package Drawing Pins SPQ Length (mm) Width (mm) Height (mm)
LM2743MTCX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0
LM2743MTCX/NOPB TSSOP PW 14 2500 367.0 367.0 35.0
PACKAGE MATERIALS INFORMATION
www.ti.com 31-Dec-2020
Pack Materials-Page 2
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