Rev. A – 25-Oct-01
1
Dual Common Interface Hardware Controller
The T90-FJR, also known as the CIMaX™ controller, is the hardware extension of
SCM Microsystems’ second generation Common Interface integration package (CI
Pack+™). It enables CI Driver software to directly address two complete independent
Common Interface modules. As such, it contributes to offer an optimized, homoge-
neous and complete solution for digital TV receiver manufacturer that wants to quickly
implement the Common Interface.
This document contains several application notes that give accurate information on
the hardware designer for implementing the CIMaX™ circuit into its digital TV
receiver. It describes how to connect the CIMaX™ to its surrounding environment
(modules, processor…). For each connection type (e.g. modules, host…), several
schematics are provided corresponding to the alternate solutions provided by the
CIMaX™.
Pins marked with a cross (X) should be left unconnected. Those marked with a square
( . ) may be connected but connection is part of another schematic and is not shown
on the current schematic.
Application
Notes
T90FJR
(CIMaX™)
2
T90FJR
Rev. A – 25-Oct-01
System Diagram
RST,CLK
Host processor address and
data busses
INT
TS out
TS in
A[25..15]
Ext CS
WAIT/ACK
RD,WR,CS
I2C
CIMaX™
I2C
Interface
UCSG
Interrupts
Management
Module
A
Module
B
TS interface
Ext
IT Address/
Data
Buffers
HOST
TS Module A
TS Module B
3T90FJR Rev. A – 25-Oct-01
Module Interface Connection of module sockets to CIMaX™ is achieved simply by connecting directly all
the MPEG transport stream signals and common interface control signals of each mod-
ule directly to the corresponding pins of the CIMaX™. The address and data busses are
connected to the host processor busses through standard buffers.
The following Bill Of Materials (BOM) applies:
Quantity Description
1x CIMaX™ (103563)
2x PCMCIA Connector
2x 74HCT373
1x 74HCT245
Figure 1. CiMaX™ connection to DVB modules
GND
GND
Host
processor
address and data
busses
HD4
HD0
HD1
HD2
HD3
HD5
HD6
HD7
HD4
HD0
HD1
HD2
HD3
HD5
HD6
HD7
HD0
HD1
HD2
HD3
HD5
HD6
HD7HD7
HA0
HA1
HA2
HA3
HA4
HA5
HA6
HA7
HA0
HA1
HA2
HA3
HA4
HA5
HA6
HA7
HA10
HA8
HA13
HA15
HA12
HA9
HA14
HA11
HA10HA10
HA8
HA13
HA15
HA12
HA9
HA14
HA11
HA8
HA13
HA15
HA12
HA9
HA14
HA11
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MD0
MD1
MD2
MD3
MD4
MD5
MD6
MD7
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MA0
MA1
MA2
MA3
MA4
MA5
MA6
MA7
MA8
MA9
MA10
MA11
MA12
MA13
MA14
MD5
MD3
MD7
MD2
MD4
MD1
MD6
MD0
MD5
MD3
MD7
MD2
MD4
MD1
MD6
MD0
MD6
MD0
MD1
MD4
MD2
MD7
MD3
MD5
MD6
MD0
MD1
MD4
MD2
MD7
MD3
MD5
MA6
MA0
MA1
MA4
MA2
MA7
MA3
MA5
MA6
MA0
MA1
MA4
MA2
MA7
MA3
MA5
MA8
MA13
MA9
MA11
MA12
MA10
MA14
MA8
MA13
MA9
MA11
MA12
MA10
MA14
U5
74AHCT37
3
D0 3
D1 4
D2 7
D3 8
D4 13
D5 14
D6 17
D7 18
OC 1
G11
Q0
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
U6
74AHCT37
3
D0 3
D1 4
D2 7
D3 8
D4 13
D5 14
D6 17
D7 18
OC 1
G11
Q0
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
U4
74AHCT24
5
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
G19
DIR 1
B1 18
B2 17
B3 16
B4 15
B5 14
B6 13
B7 12
B8 11
R1
10k
R2
10k
R3
10k
R4
10k
JP2
PCMCIA
SOCKET
GND
1GND
34 GND
35 GND
68
VCC 17
VCC 51
MICLK
20
MIVAL
19
MISTRT
46
MDI0
47
MDI1
48
MDI2
49
MDI3
50
MDI4
53
MDI5
54
MDI6
55
MDI7
56
MOVAL
62
MOSTRT
63
MDO0
64
MDO1
65
MDO2
66
MDO3
37
MDO4
38
MDO5
39
MDO6
40
MDO7
41
D0 30
D1 31
D2 32
D3 2
D4 3
D5 4
D6 5
D7 6
A0 29
A1 28
A2 27
A3 26
A4 25
A5 24
A6 23
A7 22
A8 12
A9 11
A10 8
A11 10
A12 21
A13 13
A14 14
CD1 36
CE1
7
CD2 67
CE2
42
IORD
44
IOWR
45 VS1 43
VPP1 18
VPP2 52
RESET 58
WAIT 59
INPACK
60
REG
61
OE
9
WE/PGM
15
IREQ
16
MOCLK
57
IOIS16 33
JP1
PCMCIA
SOCKET
GND
1GND
34 GND
35 GND
68
VCC 17
VCC 51
MICLK
20
MIVAL
19
MISTRT
46
MDI0
47
MDI1
48
MDI2
49
MDI3
50
MDI4
53
MDI5
54
MDI6
55
MDI7
56
MOVAL
62
MOSTRT
63
MDO0
64
MDO1
65
MDO2
66
MDO3
37
MDO4
38
MDO5
39
MDO6
40
MDO7
41
D0 30
D1 31
D2 32
D3 2
D4 3
D5 4
D6 5
D7 6
A0 29
A1 28
A2 27
A3 26
A4 25
A5 24
A6 23
A7 22
A8 12
A9 11
A10 8
A11 10
A12 21
A13 13
A14 14
CD1 36
CE1
7
CD2 67
CE2
42
IORD
44
IOWR
45 VS1 43
VPP1 18
VPP2 52
RESET 58
WAIT 59
INPACK
60
REG
61
OE
9
WE/PGM
15
IREQ
16
MOCLK
57
IOIS16 33
MPEG
input
stream
from
front
end
MPEG
output
stream
to
decoder
I2C
bus
I2C
address
Host
proc.
address
bus
Host
proc.
Control
signals
Ext
periph
control
MPEG
Output
stream
to
module
A
MPEG
input
stream
from
module
A
Module A
control
signals
control
signals
to
both
modules
MPEG
output
stream
to
module
B
MPEG
input
stream
from
module
B
Module B
control
signals
modules
power
control
buffers
control
U3
CIMaX
MICLKA 110
MISTRTA 92
MIVALA 105
MDIA7 116
MDIA6 114
MDIA5 112
MDIA4 107
MDIA3 103
MDIA2 99
MDIA1 96
MDIA0 94
MOCLKA 118
MOSTRTA 127
MOVALA 125
MDOA7 84
MDOA6 80
MDOA5 78
MDOA4 76
MDOA3 74
MDOA2 5
MDOA1 3
MDOA0 1
MICLKB 108
MISTRTB 91
MIVALB 104
MOCLKB 117
MOSTRTB 126
MOVALB 124
MDIB7 115
MDIB6 113
MDIB5 111
MDIB4 106
MDIB3 102
MDIB2 98
MDIB1 95
MDIB0 93
MDOB7 83
MDOB6 79
MDOB5 77
MDOB4 75
MDOB3 73
MDOB2 4
MDOB1 2
MDOB0 128
MICLK
50
MISTRT
49
MIVAL
48
MDI7
47
MDI6
46
MDI5
45
MDI4
44
MDI3
43
MDI2
42
MDI1
41
MDI0
40
MOCLK
63
MOSTRT
62
MOVAL
61
MDO7
60
MDO6
59
MDO5
58
MDO4
57
MDO3
56
MDO2
55
MDO1
54
MDO0
53
RSTA 120
CD1A# 72
CD2A# 7
CE1A# 82
CE2A# 87
RDY/IRQA# 101
WAITA# 122
RSTB 119
CD1B# 71
CD2B# 6
CE1B# 81
CE2B# 85
RDY/IRQB# 100
WAITB# 121
REG# 123
OE# 88
WE# 97
IORD# 89
IOWR# 90
VCCEN 70
VCC_ARRAY
36
VCC_PROC
38
VCC_TSI
51
RST
34
CLK
35
SCL
31
SDA
30
SA1
33
SA0
32
A25
29
A24
28
A23
27
A22
26
A21
25
A20
24
A19
23
A18
22
A17
21
A16
20
A15
19
CS
18
RD/DIR
17
WR/STR
16
WAIT/AC
K
15
INT
14
EXTCS
13
EXTINT
12
DATOE#
69
DATDIR
68
ADLE
66 ADOE#
67
VCC_TSO
64
VCC_DVB1
109
VCC_DVB2
65
GND_ARRAY
37
GND_PROC
9
GND_TSI
39
GND_TSO
52
GND_DVB1
8
GND_DVB2
86
R5
56.
R6 56.
HA[15:0]
HD[7:0]
4
T90FJR
Rev. A – 25-Oct-01
Power Management The CIMaX™ provides the possibility to control the modules power supply with its VCC
output. This output can be configured to drive different types of switches by selecting its
structure (open-drain or push-pull) and its active level. In the example below, an
LTC1477 from Linear Technology is used to switch the modules power supply. In this
case, the output should be programmed to be an active-high push-pull so VCLVL and
VCDRV bits in the power control register should be set during power-up initialization
procedure before setting LOCK bit. Then, the VCC bit in the power control register con-
trols the VCC switch. For more details on the LTC1477, please refer to the 1995 Linear
Databook volume IV from Linear Technology.
Other components can be used to switch the power (integrated circuits or transistors)
such as MAX869L or MAX890L from MAXIM. The VCLVL and VCDRV bits should be
set in accordance with the actual hardware configuration.
It is also possible to directly connect the modules VCC permanently to the host’s VCC
without using the VCC switch facility. In that case, the VCC bit should be set to indicate
to the CIMaX™ that the modules are powered so that the buffers can be enabled (when
VCC is switched off, the buffers are automatically disabled).
5T90FJR Rev. A – 25-Oct-01
The following Bill Of Materials (BOM) applies:
Quantity Description
1x CIMaX™ (103563)
2x PCMCIA Connector
2x 74HCT373
1x 74HCT245
1x LTC1477 (or MAX869L or MAX890L)
Figure 2. Modules Power Connection
GND
GND
GND
VCC
GND
3.3V
GND
GND
GND
GND
GND
GND GND
GND
GND
GND
GND
VCC_PROC
VCC_TSI
VCC_TSO
MODULE B
MODULE A
C7
0.1µf
C11
0.1µf
C5
0.1µf
U5
LTC1477
Vins
3
Vin1
2
Vin2
7
Vin3
6
EN
4
Vout 8
GND 5
Vout 1
U3
74AHCT373
D0 3
D1 4
D2 7
D3 8
D4 13
D5 14
D6 17
D7 18
OC 1
G11
Q0
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
VCC
20
U4
74AHCT373
D0 3
D1 4
D2 7
D3 8
D4 13
D5 14
D6 17
D7 18
OC 1
G11
Q0
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
VCC
20
C6
0.1µf
C8
0.1µf
C3
0.1µf
C9
0.1µf
C4
0.1µf
C2
0.1µf
+C10
1µf
C1
0.1µf
U2
74AHC245
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9G19
DIR 1
B1 18
B2 17
B3 16
B4 15
B5 14
B6 13
B7 12
B8 11
VCC
20
JP2
PCMCIA SOCKET
GND
1GND
34 GND
35 GND
68
VCC 17
VCC 51
MICLK
20
MIVAL
19
MISTRT
46
MDI0
47
MDI1
48
MDI2
49
MDI3
50
MDI4
53
MDI5
54
MDI6
55
MDI7
56
MOVAL
62
MOSTRT
63
MDO0
64
MDO1
65
MDO2
66
MDO3
37
MDO4
38
MDO5
39
MDO6
40
MDO7
41
D0 30
D1 31
D2 32
D3 2
D4 3
D5 4
D6 5
D7 6
A0 29
A1 28
A2 27
A3 26
A4 25
A5 24
A6 23
A7 22
A8 12
A9 11
A10 8
A11 10
A12 21
A13 13
A14 14
CD1 36
CE1
7
CD2 67
CE2
42
IORD
44
IOWR
45 VS1 43
VPP1 18
VPP2 52
RESET 58
WAIT 59
INPACK
60
REG
61
OE
9
WE/PGM
15
IREQ
16
MOCLK
57
IOIS16 33
JP1
PCMCIA SOCKET
GND
1GND
34 GND
35 GND
68
VCC 17
VCC 51
MICLK
20
MIVAL
19
MISTRT
46
MDI0
47
MDI1
48
MDI2
49
MDI3
50
MDI4
53
MDI5
54
MDI6
55
MDI7
56
MOVAL
62
MOSTRT
63
MDO0
64
MDO1
65
MDO2
66
MDO3
37
MDO4
38
MDO5
39
MDO6
40
MDO7
41
D0 30
D1 31
D2 32
D3 2
D4 3
D5 4
D6 5
D7 6
A0 29
A1 28
A2 27
A3 26
A4 25
A5 24
A6 23
A7 22
A8 12
A9 11
A10 8
A11 10
A12 21
A13 13
A14 14
CD1 36
CE1
7
CD2 67
CE2
42
IORD
44
IOWR
45 VS1 43
VPP1 18
VPP2 52
RESET 58
WAIT 59
INPACK
60
REG
61
OE
9
WE/PGM
15
IREQ
16
MOCLK
57
IOIS16 33
MPEG
input
stream
from
front
end
MPEG
output
stream
to
decoder
I2C bus
I2C address
Host proc.
address
bus
Host proc.
control
signals
Ext periph
control
MPEG
output
stream
to
module
A
MPEG
input
stream
from
module
A
module A
control
signals
control
signals
to both
modules
MPEG
output
stream
to
module
B
MPEG
input
stream
from
module
B
module B
control
signals
modules
power
control
buffers
control
U1
CIMaX
MICLKA 110
MISTRTA 92
MIVALA 105
MDIA7 116
MDIA6 114
MDIA5 112
MDIA4 107
MDIA3 103
MDIA2 99
MDIA1 96
MDIA0 94
MOCLKA 118
MOSTRTA 127
MOVALA 125
MDOA7 84
MDOA6 80
MDOA5 78
MDOA4 76
MDOA3 74
MDOA2 5
MDOA1 3
MDOA0 1
MICLKB 108
MISTRTB 91
MIVALB 104
MOCLKB 117
MOSTRTB 126
MOVALB 124
MDIB7 115
MDIB6 113
MDIB5 111
MDIB4 106
MDIB3 102
MDIB2 98
MDIB1 95
MDIB0 93
MDOB7 83
MDOB6 79
MDOB5 77
MDOB4 75
MDOB3 73
MDOB2 4
MDOB1 2
MDOB0 128
MICLK
50
MISTRT
49
MIVAL
48
MDI7
47
MDI6
46
MDI5
45
MDI4
44
MDI3
43
MDI2
42
MDI1
41
MDI0
40
MOCLK
63
MOSTRT
62
MOVAL
61
MDO7
60
MDO6
59
MDO5
58
MDO4
57
MDO3
56
MDO2
55
MDO1
54
MDO0
53
RSTA 120
CD1A# 72
CD2A# 7
CE1A# 82
CE2A# 87
RDY/IRQA# 101
WAITA# 122
RSTB 119
CD1B# 71
CD2B# 6
CE1B# 81
CE2B# 85
RDY/IRQB# 100
WAITB# 121
REG# 123
OE# 88
WE# 97
IORD# 89
IOWR# 90
VCCEN 70
VCC_ARRAY
36
VCC_PROC
38
VCC_TSI
51
RST
34
CLK
35
SCL
31
SDA
30
SA1
33
SA0
32
A25
29
A24
28
A23
27
A22
26
A21
25
A20
24
A19
23
A18
22
A17
21
A16
20
A15
19
CS
18
RD/DIR
17
WR/STR
16
WAIT/ACK
15
INT
14
EXTCS
13
EXTINT
12
DATOE#
69
DATDIR
68
ADLE
66 ADOE#
67
VCC_TSO
64
VCC_DVB1
109
VCC_DVB2
65
GND_ARRAY
37
GND_PROC
9
GND_TSI
39
GND_TSO
52
GND_DVB1
8
GND_DVB2
86
6
T90FJR
Rev. A – 25-Oct-01
Host side connection
Reset, clock At power-up the whole chip is reset by activating the RESET pin (of the chip).
The clock must be stable before reset deactivation.
The clock input should be connected to a 27MHz clock source.
Configuration interface (I2C)
Access to the CIMaX™ internal registers is provided through an I2C serial interface as
defined in [5]. The I2C component address is configurable using SA1 and SA0 pins as
described in page 8, between 80, 82, 84 and 86 hex. Though, SA1 and SA0 pins should
be connected to VCC or GND depending on the desired address for the CIMaX™.
Thanks to this configurable address, it is possible to connect several (up to 4) CIMaX™
on the same board.
SCL and SDA pins should be connected to the host I2C bus.
Host processor addresses The host’s high order addresses A[25:15] should be connected to the CIMaX™ in order
to automatically choose between the modules or to access to memory cards.
Host processor bus control signals
The host processor bus control signals depend on the processor used. Different
configurations are given below.
MPEG signals The MPEG inputs of the CIMaX™ should be connected to the MPEG source of the host
(e.g. satellite or cable front-end) or from another CIMaX™ (see“Chaining. CIMaX™”).
The MPEG signals coming from this source should respect the timing limits defined in
the DVB standard. The MPEG outputs can be connected to any MPEG compliant desti-
nation (e.g. MPEG decoder) or another CIMaX™. The MPEG output signals are guaran-
teed to meet the provided timing specifications that the modules inserted in the daisy
chain also respect those timings.
7T90FJR Rev. A – 25-Oct-01
Schematic Diagram
Figure 3. Connecting CiMaX™ to the host
{Doc}
1.1
Connecting CIMaX to the host
A4
Title
Size
Document Number
Rev
MPEG input transport stream
MPEG output transport stream
Global signals
I2C bus
I2C address (connect either to VCC or GND)
Host processor address bus
MPEG
input
stream
from
front
end
MPEG
output
stream
to
decoder
I2C bus
I2C address
Host proc.
address
bus
Host proc.
control
signals
Ext periph
control
MPEG
output
stream
to
module
A
MPEG
input
stream
from
module
A
module A
control
signals
control
signals
to both
modules
MPEG
output
stream
to
module
B
MPEG
input
stream
from
module
B
module B
control
signals
modules
power
control
buffers
control
U1
CIMaX
MICLKA
110
MISTRTA
92
MIVALA
105
MDIA7
116
MDIA6
114
MDIA5
112
MDIA4
107
MDIA3
103
MDIA2
99
MDIA1
96
MDIA0
94
MOCLKA
118
MOSTRTA
127
MOVALA
125
MDOA7
84
MDOA6
80
MDOA5
78
MDOA4
76
MDOA3
74
MDOA2
5
MDOA1
3
MDOA0
1
MICLKB
108
MISTRTB
91
MIVALB
104
MOCLKB
117
MOSTRTB
126
MOVALB
124
MDIB7
115
MDIB6
113
MDIB5
111
MDIB4
106
MDIB3
102
MDIB2
98
MDIB1
95
MDIB0
93
MDOB7
83
MDOB6
79
MDOB5
77
MDOB4
75
MDOB3
73
MDOB2
4
MDOB1
2
MDOB0
128
MICLK
50
MISTRT
49
MIVAL
48
MDI7
47
MDI6
46
MDI5
45
MDI4
44
MDI3
43
MDI2
42
MDI1
41
MDI0
40
MOCLK
63
MOSTRT
62
MOVAL
61
MDO7
60
MDO6
59
MDO5
58
MDO4
57
MDO3
56
MDO2
55
MDO1
54
MDO0
53
RSTA
120
CD1A#
72
CD2A#
7
CE1A#
82
CE2A#
87
RDY/IRQA#
101
WAITA#
122
RSTB
119
CD1B#
71
CD2B#
6
CE1B#
81
CE2B#
85
RDY/IRQB#
100
WAITB#
121
REG#
123
OE#
88
WE#
97
IORD#
89
IOWR#
90
VCCEN
70
VCC_ARRAY
36
VCC_PROC
38
VCC_TSI
51
RST
34
CLK
35
SCL
31
SDA
30
SA1
33
SA0
32
A25
29
A24
28
A23
27
A22
26
A21
25
A20
24
A19
23
A18
22
A17
21
A16
20
A15
19
CS
18
RD/DIR
17
WR/STR
16
WAIT/ACK
15
INT
14
EXTCS
13
EXTINT
12
DATOE#
69
DATDIR
68
ADLE
66
ADOE#
67
VCC_TSO
64
VCC_DVB1
109
VCC_DVB2
65
GND_ARRAY
37
GND_PROC
9
GND_TSI
39
GND_TSO
52
GND_DVB1
8
GND_DVB2
86
MPEG Clock input
MPEG packet start input
MPEG valid data input
MPEG data input
MPEG clock output
MPEG packet start output
MPEG valid data output
MPEG data output
Host global reset
Host 27MHz clock
SCL
SDA
HA[25:15]
8
T90FJR
Rev. A – 25-Oct-01
Chaining CIMaX™ The CIMaX™ offers control for two CI compliant modules. However, it is possible to use
multiple CIMaX™ to add more DVB-CI slots. The CIMaX™ must be individually identi-
fied by their I2C address in order for the host processor to be able to access the desired
CIMaX™. There are two I2C address pins available on the chip thus providing the ability
to connect up to four CIMaX™.
The MPEG transport stream coming from front-end is input to the first CIMaX™ and the
MPEG transport stream of this CIMaX™ is then input to the next CIMaX™. The MPEG
output stream of the last CIMaX™ of the chain is finally input to the MPEG decoder.
The host processor control signals coming from the processor are input to all the
CIMaX™ in the chain, including the high order addresses. The CIMaX™ address
decoding registers should be set differently in each CIMaX™ to differentiate between all
the available modules. The outputs of the CIMaX™ (INT, WAIT) should be connected
together on a wired-or basis and should be configured to be open-drain (source) driven.
The schematic on the next page gives an example of connecting two CIMaX™ in the
same environment. The I2C address of the first one is fixed to 80hex and the second is
84hex.
9T90FJR Rev. A – 25-Oct-01
Figure 4. Chaining CIMaX™
{Doc} 1.1
Chaining CIMaXes
A2
1 1Friday, November 20, 1998
Title
Size Document Number Rev
Date: Sheet of
GND
GND
VCC
MPEG input transport stream
MPEG output transport stream
Host processor address bus
I2C bus
Host processor bus control
MPEG
input
stream
from
front
end
MPEG
output
stream
to
decoder
I2C bus
I2C address
Host proc.
address
bus
Host proc.
control
signals
Ext periph
control
MPEG
output
stream
to
module
A
MPEG
input
stream
from
module
A
module A
control
signals
control
signals
to both
modules
MPEG
output
stream
to
module
B
MPEG
input
stream
from
module
B
module B
control
signals
modules
power
control
buffers
control
U2
CIMaX
MICLKA 110
MISTRTA 92
MIVALA 105
MDIA7 116
MDIA6 114
MDIA5 112
MDIA4 107
MDIA3 103
MDIA2 99
MDIA1 96
MDIA0 94
MOCLKA 118
MOSTRTA 127
MOVALA 125
MDOA7 84
MDOA6 80
MDOA5 78
MDOA4 76
MDOA3 74
MDOA2 5
MDOA1 3
MDOA0 1
MICLKB 108
MISTRTB 91
MIVALB 104
MOCLKB 117
MOSTRTB 126
MOVALB 124
MDIB7 115
MDIB6 113
MDIB5 111
MDIB4 106
MDIB3 102
MDIB2 98
MDIB1 95
MDIB0 93
MDOB7 83
MDOB6 79
MDOB5 77
MDOB4 75
MDOB3 73
MDOB2 4
MDOB1 2
MDOB0 128
MICLK
50
MISTRT
49
MIVAL
48
MDI7
47
MDI6
46
MDI5
45
MDI4
44
MDI3
43
MDI2
42
MDI1
41
MDI0
40
MOCLK
63
MOSTRT
62
MOVAL
61
MDO7
60
MDO6
59
MDO5
58
MDO4
57
MDO3
56
MDO2
55
MDO1
54
MDO0
53
RSTA 120
CD1A# 72
CD2A# 7
CE1A# 82
CE2A# 87
RDY/IRQA# 101
WAITA# 122
RSTB 119
CD1B# 71
CD2B# 6
CE1B# 81
CE2B# 85
RDY/IRQB# 100
WAITB# 121
REG# 123
OE# 88
WE# 97
IORD# 89
IOWR# 90
VCCEN 70
VCC_ARRAY
36
VCC_PROC
38
VCC_TSI
51
RST
34
CLK
35
SCL
31
SDA
30
SA1
33
SA0
32
A25
29
A24
28
A23
27
A22
26
A21
25
A20
24
A19
23
A18
22
A17
21
A16
20
A15
19
CS
18
RD/DIR
17
WR/STR
16
WAIT/ACK
15
INT
14
EXTCS
13
EXTINT
12
DATOE#
69
DATDIR
68
ADLE
66 ADOE#
67
VCC_TSO
64
VCC_DVB1
109
VCC_DVB2
65
GND_ARRAY
37
GND_PROC
9
GND_TSI
39
GND_TSO
52
GND_DVB1
8
GND_DVB2
86
MPEG
input
stream
from
front
end
MPEG
output
stream
to
decoder
I2C bus
I2C address
Host proc.
address
bus
Host proc.
control
signals
Ext periph
control
MPEG
output
stream
to
module
A
MPEG
input
stream
from
module
A
module A
control
signals
control
signals
to both
modules
MPEG
output
stream
to
module
B
MPEG
input
stream
from
module
B
module B
control
signals
modules
power
control
buffers
control
U1
CIMaX
MICLKA 110
MISTRTA 92
MIVALA 105
MDIA7 116
MDIA6 114
MDIA5 112
MDIA4 107
MDIA3 103
MDIA2 99
MDIA1 96
MDIA0 94
MOCLKA 118
MOSTRTA 127
MOVALA 125
MDOA7 84
MDOA6 80
MDOA5 78
MDOA4 76
MDOA3 74
MDOA2 5
MDOA1 3
MDOA0 1
MICLKB 108
MISTRTB 91
MIVALB 104
MOCLKB 117
MOSTRTB 126
MOVALB 124
MDIB7 115
MDIB6 113
MDIB5 111
MDIB4 106
MDIB3 102
MDIB2 98
MDIB1 95
MDIB0 93
MDOB7 83
MDOB6 79
MDOB5 77
MDOB4 75
MDOB3 73
MDOB2 4
MDOB1 2
MDOB0 128
MICLK
50
MISTRT
49
MIVAL
48
MDI7
47
MDI6
46
MDI5
45
MDI4
44
MDI3
43
MDI2
42
MDI1
41
MDI0
40
MOCLK
63
MOSTRT
62
MOVAL
61
MDO7
60
MDO6
59
MDO5
58
MDO4
57
MDO3
56
MDO2
55
MDO1
54
MDO0
53
RSTA 120
CD1A# 72
CD2A# 7
CE1A# 82
CE2A# 87
RDY/IRQA# 101
WAITA# 122
RSTB 119
CD1B# 71
CD2B# 6
CE1B# 81
CE2B# 85
RDY/IRQB# 100
WAITB# 121
REG# 123
OE# 88
WE# 97
IORD# 89
IOWR# 90
VCCEN 70
VCC_ARRAY
36
VCC_PROC
38
VCC_TSI
51
RST
34
CLK
35
SCL
31
SDA
30
SA1
33
SA0
32
A25
29
A24
28
A23
27
A22
26
A21
25
A20
24
A19
23
A18
22
A17
21
A16
20
A15
19
CS
18
RD/DIR
17
WR/STR
16
WAIT/ACK
15
INT
14
EXTCS
13
EXTINT
12
DATOE#
69
DATDIR
68
ADLE
66 ADOE#
67
VCC_TSO
64
VCC_DVB1
109
VCC_DVB2
65
GND_ARRAY
37
GND_PROC
9
GND_TSI
39
GND_TSO
52
GND_DVB1
8
GND_DVB2
86
MPEG Clock input
MPEG packet start input
MPEG valid data input
MPEG data input
MPEG clock output
MPEG packet start output
MPEG valid data output
MPEG data output
HA[25:15]
SCL
SDA
INT
WAIT
CS
DIR
STR
10
T90FJR
Rev. A – 25-Oct-01
Appendix A: Connecting CIMaX™ to an ST20
This example shows how to connect a CIMaX™ to an ST20 microprocessor. This is just
one possible configuration as there could be some other means of connecting the
CIMaX™ to an ST20.
In the above example, the full Bank3 is allocated to the CIMaX™ so the CIMaX™ is
selected by notMemCAS3 signal. The CS input of the CIMaX™ should be configured to
be active low as notMemCAS is active low so CSLVL bit in the host processor interface
configuration register should be 0.
The bus direction is controlled by notMemRd which is low during a read transfer. The
RD/DIR input is used in direction control mode and the WR/STR input is used as strobe
so RDIR should be 1. The RD/DIR input is low during a read transfer so RDIRLVL
should be 0. The WR/STR input is low during a transfer so WSTRLVL bit should be 0.
The bus wait cycles are inserted when MemWait is high at the beginning of a bus trans-
fer. WAIT/ACK output is used in wait mode so WACK should be 0. MemWait input is
active high so WLVL should be 1. As several peripherals can be and-wired to the Mem-
Wait pin of the ST20, the WAIT/ACK output must be an open-drain driver so the WDRV
bit should be 0.
The CIMaX™ interrupt output is wired to the Interrupt 0 input of the ST20. If CIMaX™ is
the only source to the Interrupt0 input, the INT output driver can be configured to be a
push-pull driver so INTDRV bit in the interrupt control register should be 1.
Interrupt0 input of the ST20 is active-high so INTLVL bit should be 1.
For details on how to configure the ST20 to match this configuration, please refer to the
ST20 documentation.
CS
RD/DIR
WR/STR
WAIT/ACK
INT
notMemCAS3
notMemRd
notMemBE0
MemWait
Interrupt0
ST20
CIMaX™
11 T90FJR Rev. A – 25-Oct-01
Appendix B: Connecting CIMaX™ to other processors
The following provides an example on how to connect CIMaX™ with the VLSI VES2700
and LSI logic L64108 processors. Connection to Motorola MC68340 is the same as
L64108.
The following table gives an example of the corresponding CIMaX™ configuration:
Signal
CIMaX™RD/DIR WR/STR CS WAIT/ACK INT
ST20 notMemRd NotMemBE0 NotMemCAS3 MemWait Interrupt0
VES2700 B_Write GND DESCRAM_CS WAIT INT_EXT0
L64108/MC68340 R/W AS CS DSACK[0] INT0
Register
Microprocessor WAIT/ACK config Processor config Interrupt config
ST20 03h (or 01h) 01h 06h (or 07h)
VES2700 02h (or 00h) 03h 06h (or 07h)
L64108/MC68340 06h (or 04h) 03h 02h (or 03h)
12
T90FJR
Rev. A – 25-Oct-01
Appendix C: Out of Band connection
When used in OpenCable™ compliant Host designs, the CIMaX™ requires additional
glue logic to handle the Point-Of-Deployment (POD) module interface. Hardware differ-
ences between a standard DVB Common Interface implementation and an OpenCa-
ble™ implementation consist in the following:
1. Particular care must be taken for MOCLKA and MOCLKB connections to module
slots. According to [6], MOCLKA/B are connected to pin 14 while they are con-
nected to pin 57 in [2].
2. An OpenCable™ receiver shall control the PCMCIA CE2# pin to enable the
Extended Channel, as defined by SCTE DVS 131.
3. An OpenCable™ receiver shall include a DES-ECB descrambler and be able to
simultaneously store one 64-bit key pair, as defined by the NRSS Part B Copy
Protection Framework (EIA 679 Part B proposed revision -679BrAv5).
4. An OpenCable™ receiver shall include, as defined by SCTE DVS 131, both the
OOB RF transmitter and receiver blocks, and manage the connection between
these blocks and the POD module across the PCMCIA interface, if it wants to
take advantage of the POD Out-of-band PHY and MAC capability.
The CIMaX™ has built-in capability to address Point 2. It doesn't include any crypto-
graphic function and as such a separate descrambler must be inserted between the TS
output of the last CIMaX™ in the daisy chain and the demultiplexer to address Point 2.
This application note doesn't intend to describe how the descrambler shall be connected
to the CIMaX™, however provisions shall be made to ensure that this descrambler
could be driven by the CI Driver™ software stack.
Concerning Point 3 and the OOB Channel, this application note describes how to route
the six I/Os of the OOB RF transmitter and receiver blocks to two PCMCIA connectors.
Additional glue logic is used to multiplex these six OOB signals with Host address sig-
nals A4 to A9, as required by SCTE DVS 131. This implementation adds two static con-
trol signals OOBEN (activation control of OOB mode) and OOBSEL (selection of which
one of the 2 modules is connected to the OOB transceiver) that shall be directly driven
by the Host Processor and the CI Driver software stack
OOBEN OOBSEL Comment
0 0 OOB I/Os are not routed
0 1 OOB I/Os are not routed
1 0 OOB I/Os are routed to slot A
1 1 OOB I/Os are routed to slot B
13 T90FJR Rev. A – 25-Oct-01
The following Bill Of Materials (BOM) applies:
Quantity Description
1x CIMaX™ (103563)
2x PCMCIA Connector
2x 74HCT373
1x 74HCT245
3x 74HCT257
1x 74HCT02
Figure 5. Out of band connection
{Doc} 1.0
out of band connection
A3
5 6Friday, December 17, 1999
Title
Size Document Number Rev
Date: Sheet of
GND
GND GND
GND
VCC
GND
GND
VCC
VCC
Host processor
address and
data busses
Out Of Band
inputs
Out Of Band
outputs
Out Of Band
control
MA0
MA1
MA0
MD4 HD3
MA12
MD2
MA3
MA2
MA4
MD7
MD5
MD6
MA11
MD6
MA10
MD7
MA12
MA5
MA10
MA6
MD1
MA11
MD1
MD4
HD0
HD6
MA1
MD4
MA1
MD2
MA10
MA7
MA9
HD2
HD7
MD5
MA3
MD0
MD3
MA11
MA2
MA3
MA12
HD4
MD7
MD1
MA8
HD5
MD3
MD3
MD0
MA0
MA2
MD5
HD1
MD0
MD2
MD6
MA9
MA8
MA4
MA13
MA13
MA13
MA4
MA8
MA9
MA5
MA6
MA7
HA9
HA8
HA6
HA13
HA15
HA7
HA5
HA3
HA10
HA14
HA1
HA4
HA12
HA2
HA0
HA11
R5
10k
R6
10k
R10
10k
R11
10k
MPEG
input
stream
from
front
end
MPEG
output
stream
to
decoder
I2C bus
I2C address
Host proc.
address
bus
Host proc.
control
signals
Ext periph
control
MPEG
output
stream
to
module
A
MPEG
input
stream
from
module
A
module A
control
signals
control
signals
to both
modules
MPEG
output
stream
to
module
B
MPEG
input
stream
from
module
B
module B
control
signals
modules
power
control
buffers
control
U14
CIMaX
MICLKA 110
MISTRTA 92
MIVALA 105
MDIA7 116
MDIA6 114
MDIA5 112
MDIA4 107
MDIA3 103
MDIA2 99
MDIA1 96
MDIA0 94
MOCLKA 118
MOSTRTA 127
MOVALA 125
MDOA7 84
MDOA6 80
MDOA5 78
MDOA4 76
MDOA3 74
MDOA2 5
MDOA1 3
MDOA0 1
MICLKB 108
MISTRTB 91
MIVALB 104
MOCLKB 117
MOSTRTB 126
MOVALB 124
MDIB7 115
MDIB6 113
MDIB5 111
MDIB4 106
MDIB3 102
MDIB2 98
MDIB1 95
MDIB0 93
MDOB7 83
MDOB6 79
MDOB5 77
MDOB4 75
MDOB3 73
MDOB2 4
MDOB1 2
MDOB0 128
MICLK
50
MISTRT
49
MIVAL
48
MDI7
47
MDI6
46
MDI5
45
MDI4
44
MDI3
43
MDI2
42
MDI1
41
MDI0
40
MOCLK
63
MOSTRT
62
MOVAL
61
MDO7
60
MDO6
59
MDO5
58
MDO4
57
MDO3
56
MDO2
55
MDO1
54
MDO0
53
RSTA 120
CD1A# 72
CD2A# 7
CE1A# 82
CE2A# 87
RDY/IRQA# 101
WAITA# 122
RSTB 119
CD1B# 71
CD2B# 6
CE1B# 81
CE2B# 85
RDY/IRQB# 100
WAITB# 121
REG# 123
OE# 88
WE# 97
IORD# 89
IOWR# 90
VCCEN 70
VCC_ARRAY
36
VCC_PROC
38
VCC_TSI
51
RST
34
CLK
35
SCL
31
SDA
30
SA1
33
SA0
32
A25
29
A24
28
A23
27
A22
26
A21
25
A20
24
A19
23
A18
22
A17
21
A16
20
A15
19
CS
18
RD/DIR
17
WR/STR
16
WAIT/ACK
15
INT
14
EXTCS
13
EXTINT
12
DATOE#
69
DATDIR
68
ADLE
66 ADOE#
67
VCC_TSO
64
VCC_DVB1
109
VCC_DVB2
65
GND_ARRAY
37
GND_PROC
9
GND_TSI
39
GND_TSO
52
GND_DVB1
8
GND_DVB2
86
U17
74AHCT373
D0 3
D1 4
D2 7
D3 8
D4 13
D5 14
D6 17
D7 18
OC 1
G11
Q0
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
U16
74AHCT245
A1
2
A2
3
A3
4
A4
5
A5
6
A6
7
A7
8
A8
9
G19
DIR 1
B1 18
B2 17
B3 16
B4 15
B5 14
B6 13
B7 12
B8 11
U18
74AHCT373
D0 3
D1 4
D2 7
D3 8
D4 13
D5 14
D6 17
D7 18
OC 1
G11
Q0
2
Q1
5
Q2
6
Q3
9
Q4
12
Q5
15
Q6
16
Q7
19
U20
74HCT257
1A 2
1B 3
2A 5
2B 6
3A 11
3B 10
4A 14
4B 13
G15
A/B 1
1Y
4
2Y
7
3Y
9
4Y
12
U13
74HCT257
1A 2
1B 3
2A 5
2B 6
3A 11
3B 10
4A 14
4B 13
G15
A/B 1
1Y
4
2Y
7
3Y
9
4Y
12
U19
74HCT257
1A
2
1B
3
2A
5
2B
6
3A
11
3B
10
4A
14
4B
13
G
15
A/B
1
1Y 4
2Y 7
3Y 9
4Y 12
U21
74HCT244
1A1 2
1A2 4
1A3 6
1A4 8
2A1 11
2A2 13
2A3 15
2A4 17
1G 1
2G 19
1Y1
18
1Y2
16
1Y3
14
1Y4
12
2Y1
9
2Y2
7
2Y3
5
2Y4
3
R7
10k
R8
10k
R9
10k
U15A
74HCT02
2
3
1
U15B
74HCT02
5
6
4
U15C
74HCT02
8
9
10
U15D
74HCT02
11
12
13
R12
10k
R13
10k
R14
10k
R15
10k
R16
10k
R17
10k
R5
56.
R6 56.
JP5
PCMCIA SOCKET
GND
1GND
34 GND
35 GND
68
VCC 17
VCC 51
MICLK
20
MIVAL
19
MISTRT
46
MDI0
47
MDI1
48
MDI2
49
MDI3
50
MDI4
53
MDI5
54
MDI6
55
MDI7
56
MOVAL
62
MOSTRT
63
MDO0
64
MDO1
65
MDO2
66
MDO3
37
MDO4
38
MDO5
39
MDO6
40
MDO7
41
D0 30
D1 31
D2 32
D3 2
D4 3
D5 4
D6 5
D7 6
A0 29
A1 28
A2 27
A3 26
CTX/A4 25
ITX/A5 24
ETX/A6 23
QTX/A7 22
CRX/A8 12
DRX/A9 11
A10 8
A11 10
A12 21
A13 13
CD1 36
CE1
7CD2 67
CE2
42
IORD
44
IOWR
45
VS1 43
VPP1 18
VPP2 52
RESET 58
WAIT 59
INPACK
60
REG
61
OE
9
WE/PGM
15
IREQ
16
MOCLK
14
IOIS16 33
VS2 57
JP5
PCMCIA SOCKET
GND
1GND
34 GND
35 GND
68
VCC 17
VCC 51
MICLK
20
MIVAL
19
MISTRT
46
MDI0
47
MDI1
48
MDI2
49
MDI3
50
MDI4
53
MDI5
54
MDI6
55
MDI7
56
MOVAL
62
MOSTRT
63
MDO0
64
MDO1
65
MDO2
66
MDO3
37
MDO4
38
MDO5
39
MDO6
40
MDO7
41
D0 30
D1 31
D2 32
D3 2
D4 3
D5 4
D6 5
D7 6
A0 29
A1 28
A2 27
A3 26
CTX/A4 25
ITX/A5 24
ETX/A6 23
QTX/A7 22
CRX/A8 12
DRX/A9 11
A10 8
A11 10
A12 21
A13 13
CD1 36
CE1
7CD2 67
CE2
42
IORD
44
IOWR
45
VS1 43
VPP1 18
VPP2 52
RESET 58
WAIT 59
INPACK
60
REG
61
OE
9
WE/PGM
15
IREQ
16
MOCLK
14
IOIS16 33
VS2 57
HD[7:0]
CTX
CRX
DRX
ITX
ETX
QTX
OOBEN
OOBSEL
HA[15:0]
14
T90FJR
Rev. A – 25-Oct-01
Appendix D: External peripheral connection
The following is an example of connecting a TL16C550 UART to the CIMaX™. For more
details about external device connection refer to chapter. Because EXTCS pin is in high
impedance before VCCEN activation, it is recommended to add an external pull-up or
pull-down according to its inactive level configured in Destination Select register (not
drawn below).
Figure 6. Connection of a UART to CiMaX™
GND
VCC
HD0
HD1
HD2
HD3
HD4
HD5
HD6
HD7
HA0
HA1
HA2
U2
TL16C550
A
BAUDOU
T
17
RCLK
10
RI
43
DTR
37
CTS
40
SOUT
13
RTS
36
SIN
11
DSR
41
DCD
42
OUT1
38
OUT2
35
XIN
18
XOUT
19
D0
2
D1
3
D2
4
D3
5
D4
6
D5
7
D6
8
D7
9
RD1
24
WR1
20
INTRPT
33
MR
39
A0
31
A1
30
A2
29
ADS
28
WR2
21
RD2
25
CS2
16
CS1
15
CS0
14
DDIS
26
TXRDY
27
RXRDY
32
MPEG
input
strea
m
from
front
end
MPEG
outpu
t
strea
m
to
decode
r
I2C
bus
I2C
address
Host
proc.
addres
s
bus
Host
proc.
control
signals
Ext
periph
control
MPEG
outpu
t
strea
m
to
modul
e
A
MPEG
input
strea
m
from
modul
e
A
module
A
control
signals
control
signals
to
both
module
s
MPEG
outpu
t
strea
m
to
modul
e
B
MPEG
input
strea
m
from
modul
e
B
module
B
control
signals
module
s
powe
r
control
buffer
s
control
U1
CIMaX
MICLK
A
110
MISTRT
A
92
MIVAL
A
105
MDIA7
116
MDIA6
114
MDIA5
112
MDIA4
107
MDIA3
103
MDIA2
99
MDIA1
96
MDIA0
94
MOCLK
A
118
MOSTRT
A
127
MOVAL
A
125
MDOA7
84
MDOA6
80
MDOA5
78
MDOA4
76
MDOA3
74
MDOA2
5
MDOA1
3
MDOA0
1
MICLK
B
108
MISTRT
B
91
MIVAL
B
104
MOCLK
B
117
MOSTRT
B
126
MOVAL
B
124
MDIB7
115
MDIB6
113
MDIB5
111
MDIB4
106
MDIB3
102
MDIB2
98
MDIB1
95
MDIB0
93
MDOB7
83
MDOB6
79
MDOB5
77
MDOB4
75
MDOB3
73
MDOB2
4
MDOB1
2
MDOB0
128
MICLK
50
MISTRT
49
MIVAL
48
MDI7
47
MDI6
46
MDI5
45
MDI4
44
MDI3
43
MDI2
42
MDI1
41
MDI0
40
MOCLK
63
MOSTRT
62
MOVA
L
61
MDO7
60
MDO6
59
MDO5
58
MDO4
57
MDO3
56
MDO2
55
MDO1
54
MDO0
53
RSTA
120
CD1A#
72
CD2A#
7
CE1A
#
82
CE2A
#
87
RDY/IRQA
#
101
WAITA
#
122
RSTB
119
CD1B#
71
CD2B#
6
CE1B
#
81
CE2B
#
85
RDY/IRQB
#
100
WAITB
#
121
REG#
123
OE#
88
WE# 97
IORD#
89
IOWR
#
90
VCCEN
70
VCC_ARRA
Y
36
VCC_PRO
C
38
VCC_TS
51
RST
34
CLK
35
SCL
31
SDA
30
SA1
33
SA0
32
A25
29
A24
28
A23
27
A22
26
A21
25
A20
24
A19
23
A18
22
A17
21
A16
20
A15
19
CS#
18
RD/DIR
17
WR/ST
R
16
WAIT/AC
K
15
INT
14
EXTCS
13
EXTINT
12
DATOE
69
DATDIR
68
ADLE
66
ADOE
67
VCC_TS
O
64
VCC_DVB
1
109
VCC_DVB
2
65
GND_ARRA
Y
37
GND_PRO
C
9
GND_TS
39
GND_TS
O
52
GND_DVB
1
8
GND_DVB
2
86
HD[7:0
HA[2:0
15 T90FJR Rev. A – 25-Oct-01
Documents 1. PC Card Standard March 1997
2. Common Interface Specification for Conditional Access and other Digital Video
Broadcasting Decoder Applications, February 1997, EN 5022.
3. Guidelines for implementation and use of the common interface for DVB decoder
applications
4. Errata in EN 50221 and the Cenelec report [3] – CIT057 – rev6
5. I2C standard. Philips data handbook ref: IC12
6. Point-of-Deployment (POD) Module Interface proposal. SCTE DVS 131 Rev 10;
October 4, 1999
CIMaX™, CI Pack™ and CI Pack+™ are registered trademark of SCM Microsystems.
All other trademarks are the property of their respective companies.
© Atmel Nantes SA, 2001.
Atmel Corporation makes no warranty for the use of its products, other than those expressly contained in the Company’s standard warranty
which is detailed in Atmel’s Terms and Conditions located on the Company’s web site. The Company assumes no responsibility for any errors
which may appear in this document, reserves the right to change devices or specifications detailed herein at any time without notice, and does
not make any commitment to update the information contained herein. No licenses to patents or other intellectual property of Atmel are granted
by the Company in connection with the sale of Atmel products, expressly or by implication. Atmel’s products are not authorized for use as critical
components in life support devices or systems.
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