PRELIMINARY PRODUCT SPECIFICATIONS (R) Integrated Circuits Group LH28F320BFN-PTTLZJ Flash Memory 32M (2M x 16) (Model No.: LHF32FDH) Spec No.: FM024004 Issue Date: April 1, 2002 sharp LHF32FDH * Handle this document carefully for it contains material protected by international copyright law. Any reproduction, full or in part, of this material is prohibited without the express written permission of the company. * When using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. In no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) The products covered herein are designed and manufactured for the following application areas. When using the products covered herein for the equipment listed in Paragraph (2), even for the following application areas, be sure to observe the precautions given in Paragraph (2). Never use the products for the equipment listed in Paragraph (3). * Office electronics * Instrumentation and measuring equipment * Machine tools * Audiovisual equipment * Home appliance * Communication equipment other than for trunk lines (2) Those contemplating using the products covered herein for the following equipment which demands high reliability, should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. * Control and safety devices for airplanes, trains, automobiles, and other transportation equipment * Mainframe computers * Traffic control systems * Gas leak detectors and automatic cutoff devices * Rescue and security equipment * Other safety devices and safety equipment, etc. (3) Do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. * Aerospace equipment * Communications equipment for trunk lines * Control equipment for the nuclear power industry * Medical equipment related to life support, etc. (4) Please direct all queries and comments regarding the interpretation of the above three Paragraphs to a sales representative of the company. * Please direct all queries regarding the products covered herein to a sales representative of the company. Rev. 2.41 sharp LHF32FDH 1 CONTENTS PAGE PAGE 44-Lead SOP Pinout ................................................... 3 1 Electrical Specifications......................................... 14 Pin Descriptions.......................................................... 4 1.1 Absolute Maximum Ratings ........................... 14 Memory Map .............................................................. 5 1.2 Operating Conditions ...................................... 14 Identifier Codes and OTP Address for Read Operation ............................................. 6 1.2.1 Capacitance .............................................. 15 1.2.2 AC Input/Output Test Conditions ............ 15 OTP Block Address Map for OTP Program............... 7 1.2.3 DC Characteristics ................................... 16 Bus Operation ............................................................. 8 Command Definitions ................................................ 9 Functions of Block Lock and Block Lock-Down...... 11 Block Locking State Transitions upon Command Write................................................. 11 Status Register Definition......................................... 12 Extended Status Register Definition ........................ 13 1.2.4 AC Characteristics - Read-Only Operations......................... 17 1.2.5 AC Characteristics - Write Operations ................................. 20 1.2.6 Reset Operations ...................................... 22 1.2.7 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance.................... 23 2 Related Document Information.............................. 24 Rev. 2.41 sharp LHF32FDH 2 LH28F320BFN-PTTLZJ 32Mbit (2Mbitx16) Page Mode Flash MEMORY 32M density with 16Bit I/O Interface High Performance Reads * 70/25ns 8-Word Page Mode Low Power Operation * 2.7V Read and Write Operations * Automatic Power Savings Mode Reduces ICCR in Static Mode Enhanced Code + Data Storage * 5s Typical Erase/Program Suspends OTP (One Time Program) Block * 4-Word Factory-Programmed Area * 4-Word User-Programmable Area High Performance Program with Page Buffer * 16-Word Page Buffer Enhanced Data Protection Features * Individual Block Lock and Block Lock-Down with Zero-Latency * All blocks are locked at power-up or device reset. * Block Erase, Full Chip Erase, (Page Buffer) Word Program Lockout during Power Transitions Automated Erase/Program Algorithms * 3.0V Low-Power 11s/Word (Typ.) Programming Cross-Compatible Command Support * Basic Command Set * Common Flash Interface (CFI) Extended Cycling Capability * Minimum 100,000 Block Erase Cycles 44-Lead SOP Operating Temperature 0C to +70C ETOXTM* Flash Technology Flexible Blocking Architecture * Eight 4K-word Parameter Blocks * Sixty-three 32K-word Main Blocks * Top Parameter Location Not designed or rated as radiation hardened CMOS Process (P-type silicon substrate) The product, which is Page Mode Flash memory, is a low power, high density, low cost, nonvolatile read/write storage solution for a wide range of applications. The product can operate at VCC=2.7V-3.6V. Its low voltage operation capability greatly extends battery life for portable applications. The product provides high performance asynchronous page mode. It allows code execution directly from Flash, thus eliminating time consuming wait states. The memory array block architecture utilizes Enhanced Data Protection features, and provides separate Parameter and Main Blocks that provide maximum flexibility for safe nonvolatile code and data storage. Fast program capability is provided through the use of high speed Page Buffer Program. Special OTP (One Time Program) block provides an area to store permanent code such as a unique number. * ETOX is a trademark of Intel Corporation. Rev. 2.41 sharp LHF32FDH A19 A18 A17 A7 A6 A5 A4 A3 A2 A1 A0 CE# GND OE# DQ0 DQ8 DQ1 DQ9 DQ2 DQ10 DQ3 DQ11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 44 43 42 41 40 39 38 37 36 35 44-LEAD SOP STANDARD PINOUT 34 13.2mm x 28.2mm 33 32 TOP VIEW 31 30 29 28 27 26 25 24 23 3 RST# WE# A20 NC A8 A9 A10 A11 A12 A13 A14 A15 A16 DQ15 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12 DQ4 VCC Figure 1. 44-Lead SOP Pinout Rev. 2.41 sharp LHF32FDH 4 Table 1. Pin Descriptions Symbol Type Name and Function A0-A20 INPUT DQ0-DQ15 INPUT/ OUTPUT DATA INPUTS/OUTPUTS: Inputs data and commands during CUI (Command User Interface) write cycles, outputs data during memory array, status register, query code and identifier code reads. Data pins float to high-impedance (High Z) when the chip or outputs are deselected. Data is internally latched during an erase or program cycle. CE# INPUT CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers. CE#-high (VIH) deselects the device and reduces power consumption to standby levels. RST# INPUT RESET: When low (VIL), RST# resets internal automation and inhibits write operations which provides data protection. RST#-high (VIH) enables normal operation. After power-up or reset mode, the device is automatically set to read array mode. RST# must be low during power-up/down. OE# INPUT OUTPUT ENABLE: Gates the device's outputs during a read cycle. WE# INPUT WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of CE# or WE# (whichever goes high first). VCC SUPPLY DEVICE POWER SUPPLY (2.7V-3.6V): With VCCVLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VCC voltage (see DC Characteristics) produce spurious results and should not be attempted. GND SUPPLY NC ADDRESS INPUTS: Inputs for addresses. 32M: A0-A20 GROUND: Do not float any ground pins. NO CONNECT: Lead is not internally connected; it may be driven or floated. Rev. 2.41 sharp LHF32FDH BLOCK NUMBER 5 ADDRESS RANGE 70 4K-WORD 1FF000H - 1FFFFFH 69 4K-WORD 1FE000H - 1FEFFFH 68 4K-WORD 1FD000H - 1FDFFFH 67 4K-WORD 1FC000H - 1FCFFFH 66 4K-WORD 1FB000H - 1FBFFFH 65 4K-WORD 1FA000H - 1FAFFFH 64 4K-WORD 1F9000H - 1F9FFFH BLOCK NUMBER 63 4K-WORD 1F8000H - 1F8FFFH 31 32K-WORD 0F8000H - 0FFFFFH 62 32K-WORD 1F0000H - 1F7FFFH 30 32K-WORD 0F0000H - 0F7FFFH 61 32K-WORD 1E8000H - 1EFFFFH 29 32K-WORD 0E8000H - 0EFFFFH 60 32K-WORD 1E0000H - 1E7FFFH 28 32K-WORD 0E0000H - 0E7FFFH 0D8000H - 0DFFFFH ADDRESS RANGE 59 32K-WORD 1D8000H - 1DFFFFH 27 32K-WORD 58 32K-WORD 1D0000H - 1D7FFFH 26 32K-WORD 0D0000H - 0D7FFFH 0C8000H - 0CFFFFH 57 32K-WORD 1C8000H - 1CFFFFH 25 32K-WORD 56 32K-WORD 1C0000H - 1C7FFFH 24 32K-WORD 0C0000H - 0C7FFFH 55 32K-WORD 1B8000H - 1BFFFFH 23 32K-WORD 0B8000H - 0BFFFFH 54 32K-WORD 1B0000H - 1B7FFFH 22 32K-WORD 0B0000H - 0B7FFFH 53 32K-WORD 1A8000H - 1AFFFFH 21 32K-WORD 0A8000H - 0AFFFFH 52 32K-WORD 1A0000H - 1A7FFFH 20 32K-WORD 0A0000H - 0A7FFFH 51 32K-WORD 198000H - 19FFFFH 19 32K-WORD 098000H - 09FFFFH 50 32K-WORD 190000H - 197FFFH 18 32K-WORD 090000H - 097FFFH 49 32K-WORD 188000H - 18FFFFH 17 32K-WORD 088000H - 08FFFFH 48 32K-WORD 180000H - 187FFFH 16 32K-WORD 080000H - 087FFFH 47 32K-WORD 178000H - 17FFFFH 15 32K-WORD 078000H - 07FFFFH 46 32K-WORD 170000H - 177FFFH 14 32K-WORD 070000H - 077FFFH 45 32K-WORD 168000H - 16FFFFH 13 32K-WORD 068000H - 06FFFFH 44 32K-WORD 160000H - 167FFFH 12 32K-WORD 060000H - 067FFFH 43 32K-WORD 158000H - 15FFFFH 11 32K-WORD 058000H - 05FFFFH 42 32K-WORD 150000H - 157FFFH 10 32K-WORD 050000H - 057FFFH 41 32K-WORD 148000H - 14FFFFH 9 32K-WORD 048000H - 04FFFFH 40 32K-WORD 140000H - 147FFFH 8 32K-WORD 040000H - 047FFFH 39 32K-WORD 138000H - 13FFFFH 7 32K-WORD 038000H - 03FFFFH 38 32K-WORD 130000H - 137FFFH 6 32K-WORD 030000H - 037FFFH 37 32K-WORD 128000H - 12FFFFH 5 32K-WORD 028000H - 02FFFFH 36 32K-WORD 120000H - 127FFFH 4 32K-WORD 020000H - 027FFFH 35 32K-WORD 118000H - 11FFFFH 3 32K-WORD 018000H - 01FFFFH 34 32K-WORD 110000H - 117FFFH 2 32K-WORD 010000H - 017FFFH 33 32K-WORD 108000H - 10FFFFH 1 32K-WORD 008000H - 00FFFFH 32 32K-WORD 100000H - 107FFFH 0 32K-WORD 000000H - 007FFFH Figure 2. Memory Map (Top Parameter) Rev. 2.41 sharp LHF32FDH 6 Table 2. Identifier Codes and OTP Address for Read Operation Code Address [A20-A0] Data [DQ15-DQ0] Notes Manufacturer Code Manufacturer Code 000000H 00B0H Device Code Top Parameter Device Code 000001H 00B4H 1 Block Lock Configuration Code Block is Unlocked Block Address +2 DQ0 = 0 2 DQ0 = 1 2 Block Address +2 DQ1 = 0 2 DQ1 = 1 2 OTP Lock 000080H OTP-LK 3 OTP 000081000088H OTP 4 Block is Locked Block is not Locked-Down Block is Locked-Down OTP NOTES: 1. Top parameter device has its parameter blocks at the highest address. 2. DQ15-DQ2 are reserved for future implementation. 3. OTP-LK=OTP Block Lock configuration. 4. OTP=OTP Block data. Rev. 2.41 sharp LHF32FDH 7 [A20-A0] 000088H Customer Programmable Area 000085H 000084H Factory Programmed Area 000081H 000080H Reserved for Future Implementation (DQ15-DQ2) Customer Programmable Area Lock Bit (DQ1) Factory Programmed Area Lock Bit (DQ0) Figure 3. OTP Block Address Map for OTP Program (The area outside 80H~88H cannot be used.) Rev. 2.41 sharp LHF32FDH 8 Table 3. Bus Operation(1, 2) Mode Notes RST# CE# OE# WE# Address DQ0-15 6 VIH VIL VIL VIH X DOUT Output Disable VIH VIL VIH VIH X High Z Standby VIH VIH X X X High Z Read Array Reset 3 VIL X X X X High Z Read Identifier Codes/OTP 6 VIH VIL VIL VIH See Table 2 See Table 2 6,7 VIH VIL VIL VIH See Appendix See Appendix 4,5,6 VIH VIL VIH VIL X DIN Read Query Write NOTES: 1. See DC Characteristics for VIL or VIH voltages. 2. X can be VIL or VIH for control pins and addresses. 3. RST# at GND0.2V ensures the lowest power consumption. 4. Command writes involving block erase, full chip erase, (page buffer) program or OTP program are reliably executed when VCC=2.7V-3.6V. 5. Refer to Table 4 for valid DIN during a write operation. 6. Never hold OE# low and WE# low at the same timing. 7. Refer to Appendix of LH28F320BF series for more information about query code. Rev. 2.41 sharp LHF32FDH 9 Table 4. Command Definitions(10) Bus Cycles Req'd Notes Oper(1) Addr(2) Data(3) 1 2 Write X FFH Read Identifier Codes/OTP 2 2,3,4 Write X Read Query 2 2,3,4 Write X Read Status Register 2 2,3,11 Write Clear Status Register 1 2 Block Erase 2 Full Chip Erase 2 Command Read Array Program First Bus Cycle Second Bus Cycle Oper(1) Addr(2) Data(3) 90H Read IA or OA ID or OD 98H Read QA QD BA or WA 70H Read BA or WA SRD Write X 50H 2,3,5 Write BA 20H Write BA D0H 2,5,8 Write X 30H Write X D0H 2 2,3,5,6 Write WA 40H or 10H Write WA WD Write WA N-1 4 2,3,5,7 Write WA E8H Block Erase and (Page Buffer) Program Suspend 1 2,8 Write BA or WA B0H Block Erase and (Page Buffer) Program Resume 1 2,8 Write BA or WA D0H Set Block Lock Bit 2 2 Write BA 60H Write BA 01H Clear Block Lock Bit 2 2,9 Write BA 60H Write BA D0H Set Block Lock-down Bit 2 2 Write BA 60H Write BA 2FH OTP Program 2 2,3,8 Write OA C0H Write OA OD Page Buffer Program NOTES: 1. Bus operations are defined in Table 3. 2. The address which is written at the first bus cycle should be the same as the address which is written at the second bus cycle. X=Any valid address within the device. IA=Identifier codes address (See Table 2). QA=Query codes address. Refer to Appendix of LH28F320BF series for details. BA=Address within the block being erased, set/cleared block lock bit or set block lock-down bit. WA=Address of memory location for the Program command or the first address for the Page Buffer Program command. OA=Address of OTP block to be read or programmed (See Figure 3). 3. ID=Data read from identifier codes. (See Table 2). QD=Data read from query database. Refer to Appendix of LH28F320BF series for details. SRD=Data read from status register. See Table 7 and Table 8 for a description of the status register bits. WD=Data to be programmed at location WA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). OD=Data to be programmed at location OA. Data is latched on the rising edge of WE# or CE# (whichever goes high first). N-1=N is the number of the words to be loaded into a page buffer. 4. Following the Read Identifier Codes/OTP command, read operations access manufacturer code, device code, block lock configuration code, and the data within OTP block (See Table 2). The Read Query command is available for reading CFI (Common Flash Interface) information. 5. Block erase, full chip erase or (page buffer) program cannot be executed when the selected block is locked. Unlocked block can be erased or programmed when RST# is VIH. 6. Either 40H or 10H are recognized by the CUI (Command User Interface) as the program setup. 7. Following the third bus cycle, inputs the program sequential address and write data of "N" times. Finally, input the any valid address within the target block to be programmed and the confirm command (D0H). Refer to Appendix of LH28F320BF series for details. 8. Full chip erase and OTP program operations can not be suspended. The OTP Program command can not be accepted Rev. 2.41 sharp LHF32FDH 10 while the block erase operation is being suspended. 9. Following the Clear Block Lock Bit command, the selected block is unlocked regardless of lock-down configuration. 10. Commands other than those shown above are reserved by SHARP for future device implementations and should not be used. 11. When the status register data is read, input the address to which the erase or program operation is executed. Rev. 2.41 sharp LHF32FDH 11 Table 5. Functions of Block Lock(4) and Block Lock-Down Current State Erase/Program Allowed (2) DQ1(1) DQ0(1) 0 0 Unlocked Yes 0 1 Locked No [10] 1 0 Unlocked Yes [11] 1 1 Locked No State [00] [01] (3) State Name NOTES: 1. DQ0=1: a block is locked; DQ0=0: a block is unlocked. DQ1=1: a block is locked-down; DQ 1=0: a block is not locked-down. 2. Erase and program are general terms, respectively, to express: block erase, full chip erase and (page buffer) program operations. 3. At power-up or device reset, all blocks default to locked state and are not locked-down, that is, [01] regardless of the states before power-off or reset operation. 4. OTP (One Time Program) block has the lock function which is different from those described above. Table 6. Block Locking State Transitions upon Command Write Current State Result after Lock Command Written (Next State) State DQ1 DQ0 Set Lock(1) Clear Lock(1) Set Lock-down(1) [00] 0 0 [01] No Change(3) [11](2) [01] 0 1 No Change [00] [11] [10] 1 0 [11] No Change [11](2) [11] 1 1 No Change [10] No Change NOTES: 1. "Set Lock" means Set Block Lock Bit command, "Clear Lock" means Clear Block Lock Bit command and "Set Lock-down" means Set Block Lock-Down Bit command. 2. When the Set Block Lock-Down Bit command is written to the unlocked block (DQ0=0), the corresponding block is locked-down and automatically locked at the same time. 3. "No Change" means that the state remains unchanged after the command written. Rev. 2.41 sharp LHF32FDH 12 Table 7. Status Register Definition R R R R R R R R 15 14 13 12 11 10 9 8 WSMS BESS BEFCES PBPOPS R PBPSS DPS R 7 6 5 4 3 2 1 0 SR.15 - SR.8 = RESERVED FOR FUTURE ENHANCEMENTS (R) NOTES: SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy Check SR.7 to determine block erase, full chip erase, (page buffer) program or OTP program completion. SR.6 - SR.1 are invalid while SR.7="0". SR.6 = BLOCK ERASE SUSPEND STATUS (BESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed If both SR.5 and SR.4 are "1"s after a block erase, full chip erase, page buffer program, set/clear block lock bit, set block lock-down bit, attempt, an improper command sequence was entered. SR.5 = BLOCK ERASE AND FULL CHIP ERASE STATUS (BEFCES) 1 = Error in Block Erase or Full Chip Erase 0 = Successful Block Erase or Full Chip Erase SR.4 = (PAGE BUFFER) PROGRAM AND OTP PROGRAM STATUS (PBPOPS) 1 = Error in (Page Buffer) Program or OTP Program 0 = Successful (Page Buffer) Program or OTP Program SR.1 does not provide a continuous indication of block lock bit. The WSM interrogates the block lock bit only after Block Erase, Full Chip Erase, (Page Buffer) Program or OTP Program command sequences. It informs the system, depending on the attempted operation, if the block lock bit is set. Reading the block lock configuration codes after writing the Read Identifier Codes/OTP command indicates block lock bit status. SR.15 - SR.8, SR.3 and SR.0 are reserved for future use and SR.3 = RESERVED FOR FUTURE ENHANCEMENTS (R) should be masked out when polling the status register. SR.2 = (PAGE BUFFER) PROGRAM SUSPEND STATUS (PBPSS) 1 = (Page Buffer) Program Suspended 0 = (Page Buffer) Program in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = Erase or Program Attempted on a Locked Block, Operation Abort 0 = Unlocked SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) Rev. 2.41 sharp LHF32FDH 13 Table 8. Extended Status Register Definition R R R R R R R R 15 14 13 12 11 10 9 8 SMS R R R R R R R 7 6 5 4 3 2 1 0 XSR.15-8 = RESERVED FOR FUTURE ENHANCEMENTS (R) XSR.7 = STATE MACHINE STATUS (SMS) 1 = Page Buffer Program available 0 = Page Buffer Program not available NOTES: After issue a Page Buffer Program command (E8H), XSR.7="1" indicates that the entered command is accepted. If XSR.7 is "0", the command is not accepted and a next Page Buffer Program command (E8H) should be issued again to check if page buffer is available or not. XSR.15-8 and XSR.6-0 are reserved for future use and should be masked out when polling the extended status XSR.6-0 = RESERVED FOR FUTURE ENHANCEMENTS (R) register. Rev. 2.41 sharp LHF32FDH 1 Electrical Specifications 14 *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability. 1.1 Absolute Maximum Ratings* Operating Temperature During Read, Erase and Program ...... 0C to +70C (1) NOTES: 1. Operating temperature is for commercial temperature product defined by this specification. 2. All specified voltages are with respect to GND. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VCC pins. During transitions, this level may undershoot to -2.0V for periods <20ns. Maximum DC voltage on input/output pins and VCC is VCC+0.5V which, during transitions, may overshoot to VCC +2.0V for periods <20ns. 3. Output shorted for no more than one second. No more than one output shorted at a time. Storage Temperature During under Bias............................... -10C to +80C During non Bias................................ -65C to +125C Voltage On Any Pin (except VCC)............................ -0.5V to VCC+0.5V (2) VCC Supply Voltage ........................... -0.2V to +3.9V (2) Output Short Circuit Current ........................... 100mA (3) 1.2 Operating Conditions Parameter Operating Temperature VCC Supply Voltage Symbol Min. Typ. Max. Unit TA 0 +25 +70 C VCC 2.7 3.0 3.6 V Main Block Erase Cycling 100,000 Cycles Parameter Block Erase Cycling 100,000 Cycles Notes 1 NOTES: 1. See DC Characteristics tables for voltage range-specific specification. Rev. 2.41 sharp LHF32FDH 15 1.2.1 Capacitance(1) (TA=+25C, f=1MHz) Symbol Condition Typ. Max. Unit Input Capacitance Parameter CIN VIN=0.0V 4 7 pF RST# Input Capacitance CIN VIN=0.0V 20 28 pF COUT VOUT=0.0V 6 10 pF Output Capacitance Min. NOTE: 1. Sampled, not 100% tested. 1.2.2 AC Input/Output Test Conditions VCC INPUT VCC/2 VCC/2 OUTPUT TEST POINTS 0.0 AC test inputs are driven at VCC(min) for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends at VCC/2. Input rise and fall times (10% to 90%) < 5ns. Worst case speed conditions are when VCC=VCC(min). Figure 4. Transient Input/Output Reference Waveform for VCC=2.7V-3.6V Table 9. Configuration Capacitance Loading Value VCC(min)/2 1N914 DEVICE UNDER TEST CL Includes Jig Capacitances. RL=3.3k Test Configuration CL (pF) VCC=2.7V-3.6V 50 OUT CL Figure 5. Transient Equivalent Testing Load Circuit Rev. 2.41 sharp LHF32FDH 16 1.2.3 DC Characteristics VCC=2.7V-3.6V Symbol Parameter Notes Min. Typ. Max. Unit Test Conditions ILI Input Load Current 1 -1.0 +1.0 A ILO Output Leakage Current 1 -1.0 +1.0 A ICCS VCC Standby Current 1 6 25 A VCC=VCCMax., CE#=RST#= VCC0.2V ICCAS VCC Automatic Power Savings Current 1,4 4 20 A VCC=VCCMax., CE#=GND0.2V ICCD VCC Reset Power-Down Current 1 4 20 A RST#=GND0.2V Average VCC Read Current Normal Mode 1 15 25 mA Average VCC Read 8 Word Read Current Page Mode 1 5 10 mA VCC=VCCMax., CE#=VIL, OE#=VIH, f=5MHz ICCR VCC=VCCMax., VIN/VOUT=VCC or GND ICCW VCC (Page Buffer) Program Current 1,5 20 60 mA ICCE VCC Block Erase, Full Chip Erase Current 1,5 10 30 mA ICCWS ICCES VCC (Page Buffer) Program or Block Erase Suspend Current 1,2 15 210 A VIL Input Low Voltage 5 -0.4 0.4 V VIH Input High Voltage 5 VCC -0.4 VCC + 0.4 V VOL Output Low Voltage 5 0.2 V VCC=VCCMin., IOL=100A VOH Output High Voltage 5 VCC -0.2 V VCC=VCCMin., IOH=-100A VLKO VCC Lockout Voltage 3 1.5 V CE#=VIH NOTES: 1. All currents are in RMS unless otherwise noted. Typical values are the reference values at VCC=3.0V and TA=+25C unless VCC is specified. 2. ICCWS and ICCES are specified with the device de-selected. If read or (page buffer) program while in block erase suspend mode, the device's current draw is the sum of ICCWS or ICCES and ICCR or ICCW, respectively. 3. Block erase, full chip erase, (page buffer) program and OTP program are inhibited when VCCVLKO, and not guaranteed outside the specified voltage. 4. The Automatic Power Savings (APS) feature automatically places the device in power save mode after read cycle completion. Standard address access timings (tAVQV) provide new data when addresses are changed. 5. Sampled, not 100% tested. Rev. 2.41 sharp LHF32FDH 17 1.2.4 AC Characteristics - Read-Only Operations(1) VCC=2.7V-3.6V, TA=0C to +70C Symbol Parameter Notes Min. Max. Unit tAVAV Read Cycle Time tAVQV Address to Output Delay tELQV CE# to Output Delay tAPA Page Address Access Time tGLQV OE# to Output Delay tPHQV RST# High to Output Delay tEHQZ, tGHQZ CE# or OE# to Output in High Z, Whichever Occurs First 2 tELQX CE# to Output in Low Z 2 0 ns tGLQX OE# to Output in Low Z 2 0 ns tOH Output Hold from First Occurring Address, CE# or OE# change 2 0 ns 70 3 3 ns 70 ns 70 ns 25 ns 20 ns 150 ns 20 ns NOTES: 1. See AC input/output reference waveform for timing measurements and maximum allowable input slew rate. 2. Sampled, not 100% tested. 3. OE# may be delayed up to tELQV tGLQV after the falling edge of CE# without impact to tELQV. Rev. 2.41 sharp LHF32FDH VIH A20-0 (A) 18 VALID ADDRESS VIL tAVQV tEHQZ tGHQZ VIH CE# (E) VIL tELQV VIH OE# (G) VIL VIH WE# (W) VIL tGLQV tGLQX tELQX VOH DQ15-0 (D/Q) High Z tOH VALID OUTPUT VOL tPHQV RST# (P) VIH VIL Figure 6. AC Waveform for Single Asynchronous Read Operations from Status Register, Identifier Codes, OTP Block or Query Code Rev. 2.41 sharp LHF32FDH A20-3 (A) VIH 19 VALID ADDRESS VIL tAVQV A2-0 (A) CE# (E) VIH VALID ADDRESS VIL VALID ADDRESS VALID ADDRESS VALID ADDRESS VIH VIL tELQV OE# (G) WE# (W) tEHQZ tGHQZ VIH VIL VIH tGLQV VIL tGLQX tAPA tELQX DQ15-0 (D/Q) VOH High Z VALID OUTPUT VOL VALID OUTPUT tOH VALID OUTPUT VALID OUTPUT tPHQV RST# (P) VIH VIL Figure 7. AC Waveform for Asynchronous Page Mode Read Operations from Main Blocks or Parameter Blocks Rev. 2.41 sharp LHF32FDH 20 1.2.5 AC Characteristics - Write Operations(1), (2) VCC=2.7V-3.6V, TA=0C to +70C Symbol Parameter tAVAV Write Cycle Time tPHWL (tPHEL) RST# High Recovery to WE# (CE#) Going Low tELWL (tWLEL) Notes Min. Max. Unit 70 ns 3 150 ns CE# (WE#) Setup to WE# (CE#) Going Low 4 0 ns tWLWH (tELEH) WE# (CE#) Pulse Width 4 50 ns tDVWH (tDVEH) Data Setup to WE# (CE#) Going High 7 40 ns tAVWH (tAVEH) Address Setup to WE# (CE#) Going High 7 50 ns tWHEH (tEHWH) CE# (WE#) Hold from WE# (CE#) High 0 ns tWHDX (tEHDX) Data Hold from WE# (CE#) High 0 ns tWHAX (tEHAX) Address Hold from WE# (CE#) High 0 ns tWHWL (tEHEL) WE# (CE#) Pulse Width High 20 ns tWHGL (tEHGL) Write Recovery before Read 30 ns tWHR0 (tEHR0) WE# (CE#) High to SR.7 Going "0" 5 3, 6 tAVQV+ 40 ns NOTES: 1. The timing characteristics for reading the status register during block erase, full chip erase, (page buffer) program and OTP program operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 2. A write operation can be initiated and terminated with either CE# or WE#. 3. Sampled, not 100% tested. 4. Write pulse width (tWP) is defined from the falling edge of CE# or WE# (whichever goes low last) to the rising edge of CE# or WE# (whichever goes high first). Hence, tWP=tWLWH=tELEH=tWLEH=tELWH. 5. Write pulse width high (tWPH) is defined from the rising edge of CE# or WE# (whichever goes high first) to the falling edge of CE# or WE# (whichever goes low last). Hence, t WPH=tWHWL=tEHEL=tWHEL=tEHWL. 6. tWHR0 (tEHR0) after the Read Query or Read Identifier Codes/OTP command=tAVQV+100ns. 7. Refer to Table 4 for valid address and data for block erase, full chip erase, (page buffer) program, OTP program or lock bit configuration. Rev. 2.41 sharp LHF32FDH NOTE 1 A20-0 (A) VIH VIL NOTE 2 NOTE 3 VALID ADDRESS VALID ADDRESS tAVAV CE# (E) NOTES 5, 6 VIL tWHEH (tEHWH) tWHGL (tEHGL) NOTES 5, 6 VIH VIL tWHWL (tEHEL) VIH VIL tWLWH (tELEH ) DQ15-0 (D/Q) NOTE 5 VALID ADDRESS tAVWH (tAVEH) VIH tPHWL (tPHEL) WE# (W) NOTE 4 tWHAX (tEHAX) tELWL (tWLEL) OE# (G) 21 tWHQV1,2,3 (tEHQV1,2,3) tWHDX (tEHDX) tDVWH (tDVEH) VIH VIL DATA IN VALID SRD DATA IN tWHR0 (tEHR0) SR.7 (R) "1" "0" RST# (P) VIH VIL NOTES: 1. VCC power-up and standby. 2. Write each first cycle command. 3. Write each second cycle command or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. For read operation, OE# and CE# must be driven active, and WE# de-asserted. Figure 8. AC Waveform for Write Operations Rev. 2.41 sharp LHF32FDH 22 1.2.6 Reset Operations tPHQV RST# VIH (P) VIL V DQ15-0 (D/Q) OH VOL tPLPH High Z VALID OUTPUT (A) Reset during Read Array Mode SR.7="1" tPLRH RST# VIH VIL (P) V DQ15-0 (D/Q) OH VOL ABORT COMPLETE tPHQV tPLPH High Z VALID OUTPUT (B) Reset during Erase or Program Mode VCC(min) VCC tVHQV GND t2VPH RST# (P) tPHQV VIH VIL V DQ15-0 (D/Q) OH VOL High Z VALID OUTPUT (C) RST# rising timing Figure 9. AC Waveform for Reset Operations Reset AC Specifications (VCC=2.7V-3.6V, TA=0C to +70C) Symbol Parameter Notes Min. 100 tPLPH RST# Low to Reset during Read (RST# should be low during power-up.) 1, 2, 3 tPLRH RST# Low to Reset during Erase or Program 1, 3, 4 t2VPH VCC 2.7V to RST# High 1, 3, 5 tVHQV VCC 2.7V to Output Delay 3 Max. Unit ns 22 100 s ns 1 ms NOTES: 1. A reset time, tPHQV, is required from the later of SR.7 going "1" or RST# going high until outputs are valid. Refer to AC Characteristics - Read-Only Operations for tPHQV. 2. tPLPH is <100ns the device may still reset but this is not guaranteed. 3. Sampled, not 100% tested. 4. If RST# asserted while a block erase, full chip erase, (page buffer) program or OTP program operation is not executing, the reset will complete within 100ns. 5. When the device power-up, holding RST# low minimum 100ns is required after VCC has been in predefined range and also has been in stable there. Rev. 2.41 sharp LHF32FDH 23 1.2.7 Block Erase, Full Chip Erase, (Page Buffer) Program and OTP Program Performance(3) VCC=2.7V-3.6V, TA=0C to +70C Symbol Parameter Notes Page Buffer Command is Used or not Used Min. Typ.(1) Max.(2) Unit tWPB 4K-Word Parameter Block Program Time 2 Not Used 0.05 0.3 s 2 Used 0.03 0.12 s tWMB 32K-Word Main Block Program Time 2 Not Used 0.38 2.4 s 2 Used 0.24 1.0 s tWHQV1/ tEHQV1 Word Program Time tWHOV1/ tEHOV1 2 Not Used 11 200 s 2 Used 7 100 s OTP Program Time 2 Not Used 36 400 s tWHQV2/ tEHQV2 4K-Word Parameter Block Erase Time 2 - 0.3 4 s tWHQV3/ tEHQV3 32K-Word Main Block Erase Time 2 - 0.6 5 s Full Chip Erase Time 2 40 350 s tWHRH1/ tEHRH1 (Page Buffer) Program Suspend Latency Time to Read 4 - 5 10 s tWHRH2/ tEHRH2 Block Erase Suspend Latency Time to Read 4 - 5 20 s tERES Latency Time from Block Erase Resume Command to Block Erase Suspend Command 5 - 500 s NOTES: 1. Typical values measured at VCC=3.0V and TA=+25C. Assumes corresponding lock bits are not set. Subject to change based on device characterization. 2. Excludes external system-level overhead. 3. Sampled, but not 100% tested. 4. A latency time is required from writing suspend command (WE# or CE# going high) until SR.7 going "1". 5. If the interval time from a Block Erase Resume command to a subsequent Block Erase Suspend command is shorter than tERES and its sequence is repeated, the block erase operation may not be finished. Rev. 2.41 sharp LHF32FDH 24 2 Related Document Information(1) Document No. FUM00701 Document Name LH28F320BF series Appendix NOTE: 1. International customers should contact their local SHARP or distribution sales offices. Rev. 2.41 sharp i A-1 RECOMMENDED OPERATING CONDITIONS A-1.1 At Device Power-Up AC timing illustrated in Figure A-1 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly. VCC(min) VCC GND tVR t2VPH tPHQV VIH RP# (P) (RST#) VIL tR or tF tR or tF tAVQV VIH Valid Address ADDRESS (A) VIL tF tR tELQV VIH CE# (E) VIL VIH WE# (W) VIL tF tR tGLQV VIH OE# (G) VIL DATA (D/Q) VOH VOL High Z Valid Output Figure A-1. AC Timing at Device Power-Up For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the "ELECTRICAL SPECIFICATIONS" described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page. Rev. 1.10 sharp ii A-1.1.1 Rise and Fall Time Symbol Parameter Notes Min. Max. Unit 1 0.5 30000 s/V tVR VCC Rise Time tR Input Signal Rise Time 1, 2 1 s/V tF Input Signal Fall Time 1, 2 1 s/V NOTES: 1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations. Rev. 1.10 sharp iii A-1.2 Glitch Noises Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals, as shown in Figure A-2 (b). The acceptable glitch noises are illustrated in Figure A-2 (a). Input Signal Input Signal VIH (Min.) VIH (Min.) VIL (Max.) VIL (Max.) Input Signal Input Signal (a) Acceptable Glitch Noises (b) NOT Acceptable Glitch Noises Figure A-2. Waveform for Glitch Noises See the "DC CHARACTERISTICS" described in specifications for VIH (Min.) and VIL (Max.). Rev. 1.10 sharp iv A-2 RELATED DOCUMENT INFORMATION(1) Document No. Document Name AP-001-SD-E Flash Memory Family Software Drivers AP-006-PT-E Data Protection Method of SHARP Flash Memory AP-007-SW-E RP#, VPP Electric Potential Switching Circuit NOTE: 1. International customers should contact their local SHARP or distribution sales office. Rev. 1.10 SPECIFICATIONS ARE SUBJECT TO CHANGE WITHOUT NOTICE. Suggested applications (if any) are for standard use; See Important Restrictions for limitations on special applications. See Limited Warranty for SHARP's product warranty. The Limited Warranty is in lieu, and exclusive of, all other warranties, express or implied. ALL EXPRESS AND IMPLIED WARRANTIES, INCLUDING THE WARRANTIES OF MERCHANTABILITY, FITNESS FOR USE AND FITNESS FOR A PARTICULAR PURPOSE, ARE SPECIFICALLY EXCLUDED. In no event will SHARP be liable, or in any way responsible, for any incidental or consequential economic or property damage. NORTH AMERICA EUROPE JAPAN SHARP Microelectronics of the Americas 5700 NW Pacific Rim Blvd. Camas, WA 98607, U.S.A. Phone: (1) 360-834-2500 Fax: (1) 360-834-8903 Fast Info: (1) 800-833-9437 www.sharpsma.com SHARP Microelectronics Europe Division of Sharp Electronics (Europe) GmbH Sonninstrasse 3 20097 Hamburg, Germany Phone: (49) 40-2376-2286 Fax: (49) 40-2376-2232 www.sharpsme.com SHARP Corporation Electronic Components & Devices 22-22 Nagaike-cho, Abeno-Ku Osaka 545-8522, Japan Phone: (81) 6-6621-1221 Fax: (81) 6117-725300/6117-725301 www.sharp-world.com TAIWAN SINGAPORE KOREA SHARP Electronic Components (Taiwan) Corporation 8F-A, No. 16, Sec. 4, Nanking E. Rd. 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