NAND Flash Memory
MT29F16G08CBACA, MT29F32G08CFACA, MT29F16G08CBACB,
MT29F32G08CFACB
Features
• Open NAND Flash Interface (ONFI) 2.2-compliant1
• Multiple-level cell (MLC) technology
• Organization
– Page size x8: 4320 bytes (4096 + 224 bytes)
– Block size: 256 pages (1024K + 56K bytes)
– Plane size: 2 planes x 1024 blocks per plane
– Device size: 16Gb: 2048 blocks;
32Gb: 4096 blocks
• Synchronous I/O performance
– Up to synchronous timing mode 4
– Clock rate: 12ns (DDR)
– Read/write throughput per pin: 166 MT/s
• Asynchronous I/O performance
– Up to asynchronous timing mode 5
– Read/write throughput per pin: 50 MT/s
–tRC/tWC: 20ns (MIN)
• Array performance
– Read page: 75µs (MAX)
– Program page: 1300µs (TYP)
– Erase block: 3.8ms (TYP)
• Operating Voltage Range
– VCC: 2.7–3.6V
– VCCQ: 2.7–3.6V
• Command set: ONFI NAND Flash Protocol
• Advanced Command Set
– Program cache
– Read cache sequential
– Read cache random
– One-time programmable (OTP) mode
– Multi-plane commands
– Multi-LUN operations
– Read unique ID
– Copyback
• First block (block address 00h) is valid when ship-
ped from factory. For minimum required ECC, see
Error Management (page 97).
• RESET (FFh) required as first command after pow-
er-on
• Operation status byte provides software method for
detecting
– Operation completion
– Pass/fail condition
– Write-protect status
• Copyback operations supported within the plane
from which data is read
• Quality and reliability
– Data retention: JESD47G compliant; see qualifi-
cation report
– Endurance: 3000 PROGRAM/ERASE cycles
• Operating temperature:
– Commercial: 0°C to +70°C
– Industrial (IT): –40ºC to +85ºC
• Package
– 56-ball BGA
– 48-pin TSOP
Note: 1. The ONFI 2.2 specification is available at
www.onfi.org.
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Products and specifications discussed herein are subject to change by Micron without notice.
Part Numbering Information
Micron NAND Flash devices are available in different configurations and densities. Verify valid part numbers by
using Micron’s part catalog search at www.micron.com. To compare features and specifications by device type,
visit www.micron.com/products. Contact the factory for devices not found.
Figure 1: Part Numbering
MT 29F 16G 08 C B A C A WP ES :C
Micron Technology
NAND Flash
29F = NAND Flash memory
Density
16G = 16Gb
32G = 32Gb
Device Width
08 = 8 bits
Level
Bit/Cell
C 2-bit
Classification
Die # of CE# # of R/B# I/O
B 1 1 1 Common
F 2 2 2 Common
Operating Voltage Range
A = VCC: 3.3V (2.7–3.6V), VCCQ: 3.3V (2.7–3.6V)
Design Revision
C = Third revision
Production Status
Blank = Production
ES = Engineering sample
Reserved for Future Use
Blank
Operating Temperature Range
Blank = Commercial (0°C to +70°C)
IT = Industrial (–40°C to +85°C)
Speed Grade (synchronous mode only)
12 = 166 MT/s
Package Code
H5 = 56-ball VFBGA 9.5mm x 12.8mm x 0.9mm1
WP = 48-pin TSOP1 (CPL)
Interface
A = Async only
B = Sync/Async
Generation Feature Set
C = Third set of device features
Note: 1. Pb-free package.
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Contents
General Description ......................................................................................................................................... 9
Asynchronous and Synchronous Signal Descriptions ......................................................................................... 9
Signal Assignments ......................................................................................................................................... 11
Package Dimensions ....................................................................................................................................... 13
Architecture ................................................................................................................................................... 15
Device and Array Organization ........................................................................................................................ 16
Bus Operation – Asynchronous Interface ......................................................................................................... 19
Asynchronous Enable/Standby ................................................................................................................... 19
Asynchronous Bus Idle ............................................................................................................................... 19
Asynchronous Commands .......................................................................................................................... 20
Asynchronous Addresses ............................................................................................................................ 21
Asynchronous Data Input ........................................................................................................................... 22
Asynchronous Data Output ......................................................................................................................... 23
Write Protect .............................................................................................................................................. 24
Ready/Busy# .............................................................................................................................................. 24
Bus Operation – Synchronous Interface ........................................................................................................... 28
Synchronous Enable/Standby ..................................................................................................................... 29
Synchronous Bus Idle/Driving .................................................................................................................... 29
Synchronous Commands ............................................................................................................................ 30
Synchronous Addresses .............................................................................................................................. 31
Synchronous DDR Data Input ..................................................................................................................... 32
Synchronous DDR Data Output .................................................................................................................. 33
Write Protect .............................................................................................................................................. 35
Ready/Busy# .............................................................................................................................................. 35
Device Initialization ....................................................................................................................................... 36
Activating Interfaces ....................................................................................................................................... 38
Activating the Asynchronous Interface ........................................................................................................ 38
Activating the Synchronous Interface .......................................................................................................... 38
Command Definitions .................................................................................................................................... 40
Reset Operations ............................................................................................................................................ 42
RESET (FFh) ............................................................................................................................................... 42
SYNCHRONOUS RESET (FCh) .................................................................................................................... 43
RESET LUN (FAh) ....................................................................................................................................... 44
Identification Operations ................................................................................................................................ 45
READ ID (90h) ............................................................................................................................................ 45
READ ID Parameter Tables .......................................................................................................................... 46
READ PARAMETER PAGE (ECh) .................................................................................................................. 47
Parameter Page Data Structure Tables ..................................................................................................... 48
READ UNIQUE ID (EDh) ............................................................................................................................ 55
Configuration Operations ............................................................................................................................... 56
SET FEATURES (EFh) .................................................................................................................................. 56
GET FEATURES (EEh) ................................................................................................................................. 57
Status Operations ........................................................................................................................................... 61
READ STATUS (70h) ................................................................................................................................... 62
READ STATUS ENHANCED (78h) ................................................................................................................ 63
Column Address Operations ........................................................................................................................... 64
CHANGE READ COLUMN (05h-E0h) .......................................................................................................... 64
CHANGE READ COLUMN ENHANCED (06h-E0h) ....................................................................................... 65
CHANGE WRITE COLUMN (85h) ................................................................................................................ 66
CHANGE ROW ADDRESS (85h) ................................................................................................................... 67
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Read Operations ............................................................................................................................................. 69
READ MODE (00h) ..................................................................................................................................... 71
READ PAGE (00h-30h) ................................................................................................................................ 72
READ PAGE CACHE SEQUENTIAL (31h) ...................................................................................................... 73
READ PAGE CACHE RANDOM (00h-31h) .................................................................................................... 74
READ PAGE CACHE LAST (3Fh) .................................................................................................................. 76
READ PAGE MULTI-PLANE (00h-32h) ......................................................................................................... 77
Program Operations ....................................................................................................................................... 79
PROGRAM PAGE (80h-10h) ......................................................................................................................... 79
PROGRAM PAGE CACHE (80h-15h) ............................................................................................................. 81
PROGRAM PAGE MULTI-PLANE (80h-11h) ................................................................................................. 83
Erase Operations ............................................................................................................................................ 85
ERASE BLOCK (60h-D0h) ............................................................................................................................ 85
ERASE BLOCK MULTI-PLANE (60h-D1h) .................................................................................................... 86
Copyback Operations ..................................................................................................................................... 87
COPYBACK READ (00h-35h) ....................................................................................................................... 88
COPYBACK PROGRAM (85h–10h) ............................................................................................................... 89
COPYBACK READ MULTI-PLANE (00h-32h) ................................................................................................ 89
COPYBACK PROGRAM MULTI-PLANE (85h-11h) ........................................................................................ 90
One-Time Programmable (OTP) Operations .................................................................................................... 91
PROGRAM OTP PAGE (80h-10h) ................................................................................................................. 92
PROTECT OTP AREA (80h-10h) ................................................................................................................... 93
READ OTP PAGE (00h-30h) ......................................................................................................................... 94
Multi-Plane Operations .................................................................................................................................. 95
Multi-Plane Addressing .............................................................................................................................. 95
Interleaved Die (Multi-LUN) Operations .......................................................................................................... 96
Error Management ......................................................................................................................................... 97
Shared Pages .................................................................................................................................................. 98
Output Drive Impedance ............................................................................................................................... 100
AC Overshoot/Undershoot Specifications ....................................................................................................... 102
Synchronous Input Slew Rate ......................................................................................................................... 103
Output Slew Rate ........................................................................................................................................... 104
Electrical Specifications ................................................................................................................................. 105
Electrical Specifications – DC Characteristics and Operating Conditions (Asynchronous) ................................. 106
Electrical Specifications – DC Characteristics and Operating Conditions (Synchronous) ................................... 107
Electrical Specifications – DC Characteristics and Operating Conditions (VCCQ) ............................................... 107
Electrical Specifications – AC Characteristics and Operating Conditions (Asynchronous) ................................. 107
Electrical Specifications – AC Characteristics and Operating Conditions (Synchronous) ................................... 110
Electrical Specifications – Array Characteristics .............................................................................................. 113
Asynchronous Interface Timing Diagrams ...................................................................................................... 114
Synchronous Interface Timing Diagrams ........................................................................................................ 125
Revision History ............................................................................................................................................ 147
Rev. E Production – 9/12 ............................................................................................................................ 147
Rev. D Production – 5/12 ............................................................................................................................ 147
Rev. C Production – 3/11 ............................................................................................................................ 147
Rev. B – 2/11 .............................................................................................................................................. 147
Rev. A – 7/10 .............................................................................................................................................. 147
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List of Figures
Figure 1: Part Numbering ................................................................................................................................ 2
Figure 2: 48-Pin TSOP Type 1 (Top View) ........................................................................................................ 11
Figure 3: 56-Ball BGA (Ball-Down, Top View) .................................................................................................. 12
Figure 4: 48-Pin TSOP – Type 1 CPL (Package Code: WP) ................................................................................. 13
Figure 5: 56-Ball VFBGA – 9.5mm x 12.8mm (Package Code: H5) ..................................................................... 14
Figure 6: NAND Flash Die (LUN) Functional Block Diagram ............................................................................ 15
Figure 7: Device Organization for Single-Die Package (TSOP/BGA) ................................................................. 16
Figure 8: Device Organization for Two-Die Package (TSOP) ............................................................................. 17
Figure 9: Array Organization per Logical Unit (LUN) ....................................................................................... 18
Figure 10: Asynchronous Command Latch Cycle ............................................................................................ 20
Figure 11: Asynchronous Address Latch Cycle ................................................................................................ 21
Figure 12: Asynchronous Data Input Cycles .................................................................................................... 22
Figure 13: Asynchronous Data Output Cycles ................................................................................................. 23
Figure 14: Asynchronous Data Output Cycles (EDO Mode) ............................................................................. 24
Figure 15: READ/BUSY# Open Drain .............................................................................................................. 25
Figure 16: tFall and tRise (VCCQ = 2.7-3.6V) ...................................................................................................... 26
Figure 17: IOL vs Rp (VCCQ = 2.7-3.6V) ............................................................................................................ 26
Figure 18: TC vs Rp ........................................................................................................................................ 27
Figure 19: Synchronous Bus Idle/Driving Behavior ......................................................................................... 30
Figure 20: Synchronous Command Cycle ....................................................................................................... 31
Figure 21: Synchronous Address Cycle ........................................................................................................... 32
Figure 22: Synchronous DDR Data Input Cycles ............................................................................................. 33
Figure 23: Synchronous DDR Data Output Cycles ........................................................................................... 35
Figure 24: R/B# Power-On Behavior ............................................................................................................... 36
Figure 25: Activating the Synchronous Interface ............................................................................................. 39
Figure 26: RESET (FFh) Operation .................................................................................................................. 42
Figure 27: SYNCHRONOUS RESET (FCh) Operation ....................................................................................... 43
Figure 28: RESET LUN (FAh) Operation .......................................................................................................... 44
Figure 29: READ ID (90h) with 00h Address Operation .................................................................................... 45
Figure 30: READ ID (90h) with 20h Address Operation .................................................................................... 45
Figure 31: READ PARAMETER (ECh) Operation .............................................................................................. 47
Figure 32: READ UNIQUE ID (EDh) Operation ............................................................................................... 55
Figure 33: SET FEATURES (EFh) Operation .................................................................................................... 57
Figure 34: GET FEATURES (EEh) Operation .................................................................................................... 57
Figure 35: READ STATUS (70h) Operation ...................................................................................................... 63
Figure 36: READ STATUS ENHANCED (78h) Operation ................................................................................... 63
Figure 37: CHANGE READ COLUMN (05h-E0h) Operation ............................................................................. 64
Figure 38: CHANGE READ COLUMN ENHANCED (06h-E0h) Operation .......................................................... 65
Figure 39: CHANGE WRITE COLUMN (85h) Operation ................................................................................... 66
Figure 40: CHANGE ROW ADDRESS (85h) Operation ...................................................................................... 68
Figure 41: READ PAGE (00h-30h) Operation ................................................................................................... 72
Figure 42: READ PAGE CACHE SEQUENTIAL (31h) Operation ......................................................................... 73
Figure 43: READ PAGE CACHE RANDOM (00h-31h) Operation ....................................................................... 75
Figure 44: READ PAGE CACHE LAST (3Fh) Operation ..................................................................................... 76
Figure 45: READ PAGE MULTI-PLANE (00h-32h) Operation ............................................................................ 78
Figure 46: PROGRAM PAGE (80h-10h) Operation ............................................................................................ 80
Figure 47: PROGRAM PAGE CACHE (80h–15h) Operation (Start) ..................................................................... 82
Figure 48: PROGRAM PAGE CACHE (80h–15h) Operation (End) ...................................................................... 82
Figure 49: PROGRAM PAGE MULTI-PLANE (80h–11h) Operation .................................................................... 84
Figure 50: ERASE BLOCK (60h-D0h) Operation .............................................................................................. 85
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Figure 51: ERASE BLOCK MULTI-PLANE (60h–D1h) Operation ....................................................................... 86
Figure 52: COPYBACK READ (00h-35h) Operation .......................................................................................... 88
Figure 53: COPYBACK READ (00h–35h) with CHANGE READ COLUMN (05h–E0h) Operation .......................... 88
Figure 54: COPYBACK PROGRAM (85h–10h) Operation .................................................................................. 89
Figure 55: COPYBACK PROGRAM (85h-10h) with CHANGE WRITE COLUMN (85h) Operation ......................... 89
Figure 56: COPYBACK PROGRAM MULTI-PLANE (85h-11h) Operation ........................................................... 90
Figure 57: PROGRAM OTP PAGE (80h-10h) Operation .................................................................................... 92
Figure 58: PROGRAM OTP PAGE (80h-10h) with CHANGE WRITE COLUMN (85h) Operation .......................... 93
Figure 59: PROTECT OTP AREA (80h-10h) Operation ...................................................................................... 94
Figure 60: READ OTP PAGE (00h-30h) Operation ............................................................................................ 94
Figure 61: Overshoot .................................................................................................................................... 102
Figure 62: Undershoot .................................................................................................................................. 102
Figure 63: RESET Operation .......................................................................................................................... 114
Figure 64: RESET LUN Operation .................................................................................................................. 114
Figure 65: READ STATUS Cycle ..................................................................................................................... 115
Figure 66: READ STATUS ENHANCED Cycle .................................................................................................. 115
Figure 67: READ PARAMETER PAGE ............................................................................................................. 116
Figure 68: READ PAGE .................................................................................................................................. 116
Figure 69: READ PAGE Operation with CE# “Don’t Care” ............................................................................... 117
Figure 70: CHANGE READ COLUMN ............................................................................................................ 118
Figure 71: READ PAGE CACHE SEQUENTIAL ................................................................................................ 119
Figure 72: READ PAGE CACHE RANDOM ...................................................................................................... 120
Figure 73: READ ID Operation ...................................................................................................................... 121
Figure 74: PROGRAM PAGE Operation .......................................................................................................... 121
Figure 75: PROGRAM PAGE Operation with CE# “Don’t Care” ........................................................................ 122
Figure 76: PROGRAM PAGE Operation with CHANGE WRITE COLUMN ......................................................... 122
Figure 77: PROGRAM PAGE CACHE .............................................................................................................. 123
Figure 78: PROGRAM PAGE CACHE Ending on 15h ........................................................................................ 123
Figure 79: COPYBACK .................................................................................................................................. 124
Figure 80: ERASE BLOCK Operation .............................................................................................................. 124
Figure 81: SET FEATURES Operation ............................................................................................................ 125
Figure 82: READ ID Operation ...................................................................................................................... 126
Figure 83: GET FEATURES Operation ............................................................................................................ 127
Figure 84: RESET (FCh) Operation ................................................................................................................ 128
Figure 85: READ STATUS Cycle ..................................................................................................................... 129
Figure 86: READ STATUS ENHANCED Operation .......................................................................................... 130
Figure 87: READ PARAMETER PAGE Operation ............................................................................................. 131
Figure 88: READ PAGE Operation .................................................................................................................. 132
Figure 89: CHANGE READ COLUMN ............................................................................................................ 133
Figure 90: READ PAGE CACHE SEQUENTIAL (1 of 2) ..................................................................................... 134
Figure 91: READ PAGE CACHE SEQUENTIAL (2 of 2) ..................................................................................... 135
Figure 92: READ PAGE CACHE RANDOM (1 of 2) ........................................................................................... 136
Figure 93: READ PAGE CACHE RANDOM (2 of 2) ........................................................................................... 136
Figure 94: Multi-Plane Read Page (1 of 2) ....................................................................................................... 137
Figure 95: Multi-Plane Read Page (2 of 2) ....................................................................................................... 138
Figure 96: PROGRAM PAGE Operation (1 of 2) ............................................................................................... 139
Figure 97: PROGRAM PAGE Operation (2 of 2) ............................................................................................... 139
Figure 98: CHANGE WRITE COLUMN ........................................................................................................... 140
Figure 99: Multi-Plane Program Page ............................................................................................................ 141
Figure 100: ERASE BLOCK ............................................................................................................................ 142
Figure 101: COPYBACK (1 of 3) ..................................................................................................................... 142
Figure 102: COPYBACK (2 of 3) ..................................................................................................................... 143
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Figure 103: COPYBACK (3 of 3) ..................................................................................................................... 143
Figure 104: READ OTP PAGE ......................................................................................................................... 144
Figure 105: PROGRAM OTP PAGE (1 of 2) ...................................................................................................... 145
Figure 106: PROGRAM OTP PAGE (2 of 2) ...................................................................................................... 145
Figure 107: PROTECT OTP AREA ................................................................................................................... 146
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List of Tables
Table 1: Asynchronous and Synchronous Signal Definitions .............................................................................. 9
Table 2: Array Addressing for Logical Unit (LUN) ............................................................................................ 18
Table 3: Asynchronous Interface Mode Selection ............................................................................................ 19
Table 4: Synchronous Interface Mode Selection .............................................................................................. 28
Table 5: Command Set .................................................................................................................................. 40
Table 6: Read ID Parameters for Address 00h .................................................................................................. 46
Table 7: Read ID Parameters for Address 20h .................................................................................................. 46
Table 8: Parameter Page Data Structure .......................................................................................................... 48
Table 9: Feature Address Definitions .............................................................................................................. 56
Table 10: Feature Address 01h: Timing Mode .................................................................................................. 58
Table 11: Feature Addresses 10h and 80h: Programmable Output Drive Strength .............................................. 59
Table 12: Feature Addresses 81h: Programmable R/B# Pull-Down Strength ...................................................... 59
Table 13: Feature Addresses 90h: Array Operation Mode ................................................................................. 60
Table 14: Status Register Definition ................................................................................................................ 61
Table 15: OTP Area Details ............................................................................................................................. 92
Table 16: Error Management Details .............................................................................................................. 97
Table 17: Shared Pages .................................................................................................................................. 98
Table 18: Output Drive Strength Conditions (VCCQ = 2.7–3.6V) ....................................................................... 100
Table 19: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) ............................................................ 100
Table 20: Pull-Up and Pull-Down Output Impedance Mismatch ..................................................................... 101
Table 21: Asynchronous Overshoot/Undershoot Parameters .......................................................................... 102
Table 22: Synchronous Overshoot/Undershoot Parameters ............................................................................ 102
Table 23: Test Conditions for Input Slew Rate ................................................................................................ 103
Table 24: Input Slew Rate (VCCQ= 2.7–3.6V) ................................................................................................... 103
Table 25: Test Conditions for Output Slew Rate .............................................................................................. 104
Table 26: Output Slew Rate (VCCQ = 2.7–3.6V) ................................................................................................ 104
Table 27: Absolute Maximum Ratings by Device ............................................................................................ 105
Table 28: Recommended Operating Conditions ............................................................................................. 105
Table 29: Valid Blocks per LUN ...................................................................................................................... 105
Table 30: Capacitance: 48-Pin TSOP Package ................................................................................................. 105
Table 31: Capacitance: 56-Ball BGA Package .................................................................................................. 106
Table 32: Test Conditions .............................................................................................................................. 106
Table 33: DC Characteristics and Operating Conditions (Asynchronous Interface) .......................................... 106
Table 34: DC Characteristics and Operating Conditions (Synchronous Interface) ............................................ 107
Table 35: DC Characteristics and Operating Conditions ................................................................................. 107
Table 36: AC Characteristics: Asynchronous Command, Address, and Data ..................................................... 108
Table 37: AC Characteristics: Synchronous Command, Address, and Data ...................................................... 110
Table 38: Array Characteristics ...................................................................................................................... 113
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General Description
Micron NAND Flash devices include an asynchronous data interface for high-perform-
ance I/O operations. These devices use a highly multiplexed 8-bit bus (DQx) to transfer
commands, address, and data. There are five control signals used to implement the
asynchronous data interface: CE#, CLE, ALE, WE#, and RE#. Additional signals control
hardware write protection (WP#) and monitor device status (R/B#).
This Micron NAND Flash device additionally includes a synchronous data interface for
high-performance I/O operations. When the synchronous interface is active, WE# be-
comes CLK and RE# becomes W/R#. Data transfers include a bidirectional data strobe
(DQS).
This hardware interface creates a low pin-count device with a standard pinout that re-
mains the same from one density to another, enabling future upgrades to higher densi-
ties with no board redesign.
A target is the unit of memory accessed by a chip enable signal. A target contains one or
more NAND Flash die. A NAND Flash die is the minimum unit that can independently
execute commands and report status. A NAND Flash die, in the ONFI specification, is
referred to as a logical unit (LUN). For further details, see Device and Array Organiza-
tion.
Asynchronous and Synchronous Signal Descriptions
Table 1: Asynchronous and Synchronous Signal Definitions
Asynchronous
Signal1
Synchronous
Signal1Type Description2
ALE ALE Input Address latch enable: Loads an address from DQx into the address
register.
CE# CE# Input Chip enable: Enables or disables one or more die (LUNs) in a target1.
CLE CLE Input Command latch enable: Loads a command from DQx into the com-
mand register.
DQx DQx I/O Data inputs/outputs: The bidirectional I/Os transfer address, data, and
command information.
– DQS I/O Data strobe: Provides a synchronous reference for data input and out-
put.
RE# W/R# Input Read enable and write/read: RE# transfers serial data from the NAND
Flash to the host system when the asynchronous interface is active.
When the synchronous interface is active, W/R# controls the direction of
DQx and DQS.
WE# CLK Input Write enable and clock: WE# transfers commands, addresses, and seri-
al data from the host system to the NAND Flash when the asynchronous
interface is active. When the synchronous interface is active, CLK latches
command and address cycles.
WP# WP# Input Write protect: Enables or disables array PROGRAM and ERASE opera-
tions.
R/B# R/B# Output Ready/busy: An open-drain, active-low output that requires an exter-
nal pull-up resistor. This signal indicates target array activity.
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Table 1: Asynchronous and Synchronous Signal Definitions (Continued)
Asynchronous
Signal1
Synchronous
Signal1Type Description2
VCC VCC Supply VCC: Core power supply
VCCQ VCCQ Supply VCCQ: I/O power supply
VSS VSS Supply VSS: Core ground connection
VSSQ VSSQ Supply VSSQ: I/O ground connection
NC NC – No connect: NCs are not internally connected. They can be driven or
left unconnected.
DNU DNU – Do not use: DNUs must be left unconnected.
RFU RFU – Reserved for future use: RFUs must be left unconnected.
Notes: 1. See Device and Array Organization for detailed signal connections.
2. See Bus Operation – Asynchronous Interface (page 19) and Bus Operation – Synchro-
nous Interface (page 28) for detailed asynchronous and synchronous interface signal
descriptions.
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Signal Assignments
Figure 2: 48-Pin TSOP Type 1 (Top View)
Sync
x8
NC
NC
NC
NC
NC
R/B2#1
R/B#
W/R#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
CLK
WP#
NC
NC
NC
NC
NC
Async
x8
NC
NC
NC
NC
NC
R/B2#1
R/B#
RE#
CE#
CE2#1
NC
VCC
VSS
NC
NC
CLE
ALE
WE#
WP#
NC
NC
NC
NC
NC
Async
x8
DNU/VSSQ2
DNU
NC
NC
DQ7
DQ6
DQ5
DQ4
NC
DNU/VCCQ2
DNU
VCC
VSS
DNU
DNU/VCCQ2
NC
DQ3
DQ2
DQ1
DQ0
NC
NC
NC
DNU/VSSQ2
Sync
x8
DNU/VSSQ2
DNU
NC
NC
DQ7
DQ6
DQ5
DQ4
NC
DNU/VCCQ2
DNU
VCC
VSS
DQS
DNU/VCCQ2
NC
DQ3
DQ2
DQ1
DQ0
NC
NC
NC
DNU/VSSQ2
1 l
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
Notes: 1. CE2# and R/B2# are available on dual die packages. They are NC for other configura-
tions.
2. These VCCQ and VSSQ pins are for compatibility with ONFI 2.2. If not supplying VCCQ or
VSSQ to these pins, do not use them.
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Figure 3: 56-Ball BGA (Ball-Down, Top View)
A
B
C
D
E
F
G
H
J
K
L
M
N
P
A
B
C
D
E
F
G
H
J
K
L
M
N
P
2
NC
NC
VSS
WE#
ALE
NC
NC
CE0#
VCC
VSS
NC
NC
NC
NC
18
NC
NC
DQ1
DQ3
NC
DQ5
DQ6
NC
NC
NC
NC
NC
NC
NC
1
NC
NC
VCC
CLE
RE#
WP#
NC
R/B#
VCC
VSS
NC
NC
NC
NC
19
NC
NC
DQ0
DQ2
NC
DQ4
DQ7
NC
NC
NC
NC
NC
NC
NC
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Package Dimensions
Figure 4: 48-Pin TSOP – Type 1 CPL (Package Code: WP)
1.20 MAX
0.15 +0.03
-0.02
0.27 MAX
0.17 MIN
See detail A
18.40 ±0.08
20.00 ±0.25
Detail A
0.50 ±0.1
0.80
0.10 +0.10
-0.05
0.10
0.25
Gage
plane
0.25
for reference only
0.50 TYP
for reference
only
12.00 ±0.08
1
24
48
25
Plated lead finish:
100% Sn
Mold compound:
Epoxy novolac
Package width and length
do not include mold
protrusion. Allowable
protrusion is 0.25 per side.
Note: 1. All dimensions are in millimeters.
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Figure 5: 56-Ball VFBGA – 9.5mm x 12.8mm (Package Code: H5)
Seating plane
0.1 A
Ball A1 ID Ball A1 ID
A
0.32 MIN
0.9 ±0.1
11.7 CTR
12.8 ±0.1
0.65 TYP
8.45 CTR
9.5 ±0.1
0.65 TYP
A
B
C
D
E
F
G
H
J
K
L
M
N
P
19 18 2 1
56X Ø0.45
Dimensions apply
to solder balls post-
reflow on∅Ø0.35 SMD
ball pads.
Solder ball material:
SAC305 (96.5% Sn,
3% Ag, 0.5% Cu).
Note: 1. All dimensions are in millimeters.
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Architecture
These devices use NAND Flash electrical and command interfaces. Data, commands,
and addresses are multiplexed onto the same pins and received by I/O control circuits.
The commands received at the I/O control circuits are latched by a command register
and are transferred to control logic circuits for generating internal signals to control de-
vice operations. The addresses are latched by an address register and sent to a row de-
coder to select a row address, or to a column decoder to select a column address.
Data is transferred to or from the NAND Flash memory array, byte by byte, through a
data register and a cache register.
The NAND Flash memory array is programmed and read using page-based operations
and is erased using block-based operations. During normal page operations, the data
and cache registers act as a single register. During cache operations, the data and cache
registers operate independently to increase data throughput.
The status register reports the status of die (LUN) operations.
Figure 6: NAND Flash Die (LUN) Functional Block Diagram
Status register
Command register
Vccq Vssq
CE#
CLE
N/A
ALE
RE#
WP#
DQ[7:0]
Async
WE#
R/B#
CE#
CLE
DQS
ALE
W/R#
WP#
DQ[7:0]
Sync
CLK
R/B#
Vcc Vss
Control
logic
Data Register
Cache Register
Row Decode
Column Decode
NAND Flash
Array
Data register
Cache register
Row Decode
Column decode
NAND Flash
array (2 planes)
Address register
I/O
control
Notes: 1. N/A: This signal is tri-stated when the asynchronous interface is active.
2. Some devices do not include the synchronous interface.
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Device and Array Organization
Figure 7: Device Organization for Single-Die Package (TSOP/BGA)
Async Sync
CE# CE#
CLE CLE
ALE ALE
WE# CLK
RE# W/R#
DQ[7:0] DQ[7:0]
N/A DQS
WP# WP#
LUN 1
Target 1
Package
R/B#
Note: 1. BGA devices do not support the synchronous interface.
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Figure 8: Device Organization for Two-Die Package (TSOP)
CE#
CLE
ALE
CLK
W/R#
DQ[7:0]
DQS
WP#
LUN 1
Target 1
Package
R/B#
CE2#
CLE
ALE
CLK
W/R#
DQ[7:0]
DQS
WP#
CE#
CLE
ALE
WE#
RE#
DQ[7:0]
N/A
WP#
CE2#
CLE
ALE
WE#
RE#
DQ[7:0]
N/A
WP#
LUN 1
Target 2
R/B2#
Async Sync
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Figure 9: Array Organization per Logical Unit (LUN)
Cache Registers
Data Registers
1024 blocks per plane
2048 blocks per LUN 1 Block 1 Block
Plane 0
(0, 2, 4, ..., 2046)
Plane 1
(1, 3, 5, ..., 2047)
2244096 224
4320 bytes4320 bytes
224224
4096
4096
4096
1 Block
1 page = (4K + 224 bytes)
1 block = (4K + 224) bytes x 256 pages
= (1024K + 56K) bytes
1 plane = (1024K + 56K) bytes x 1024 blocks
= 8640Mb
1 LUN = 8640Mb x 2 planes
= 17,280Mb
DQ0
DQ7
Logical Unit (LUN)
Table 2: Array Addressing for Logical Unit (LUN)
Cycle DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0
First CA7 CA6 CA5 CA4 CA3 CA2 CA1 CA02
Second LOW LOW LOW CA123CA11 CA10 CA9 CA8
Third PA7 PA6 PA5 PA4 PA3 PA2 PA1 PA0
Fourth BA15 BA14 BA13 BA12 BA11 BA10 BA9 BA84
Fifth LOW LOW LOW LOW LA05BA18 BA17 BA16
Notes: 1. CAx = column address, PAx = page address, BAx = block address, LAx = LUN address; the
page address, block address, and LUN address are collectively called the row address.
2. When using the synchronous interface, CA0 is forced to 0 internally; one data cycle al-
ways returns one even byte and one odd byte.
3. Column addresses 4320 (10E0h) through 8191 (1FFFh) are invalid, out of bounds, do not
exist in the device, and cannot be addressed.
4. BA[8] is the plane-select bit:
Plane 0: BA[8] = 0
Plane 1: BA[8] = 1
5. LA0 is the LUN-select bit. It is present only when two LUNs are shared on the target; oth-
erwise, it should be held LOW.
LUN 0: LA0 = 0
LUN 1: LA0 = 1
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Bus Operation – Asynchronous Interface
The asynchronous interface is active when the NAND Flash device powers on. The I/O
bus, DQ[7:0], is multiplexed sharing data I/O, addresses, and commands. The DQS sig-
nal, if present, is tri-stated when the asynchronous interface is active.
Asynchronous interface bus modes are summarized below.
Table 3: Asynchronous Interface Mode Selection
Mode CE# CLE ALE WE# RE# DQS DQx WP# Notes
Standby H X X X X X X 0V/VCCQ22
Bus idle L X X H H X X X
Command input L H L H X input H
Address input L L H H X input H
Data input L L L H X input H
Data output L L L H X output X
Write protect X X X X X X X L
Notes: 1. DQS is tri-stated when the asynchronous interface is active.
2. WP# should be biased to CMOS LOW or HIGH for standby.
3. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH
or VIL.
Asynchronous Enable/Standby
A chip enable (CE#) signal is used to enable or disable a target. When CE# is driven
LOW, all of the signals for that target are enabled. With CE# LOW, the target can accept
commands, addresses, and data I/O. There may be more than one target in a NAND
Flash package. Each target is controlled by its own chip enable; the first target (Target 0)
is controlled by CE#; the second target (if present) is controlled by CE2#, etc.
A target is disabled when CE# is driven HIGH, even when the target is busy. When disa-
bled, all of the target's signals are disabled except CE#, WP#, and R/B#. This functionali-
ty is also known as CE# "Don't Care". While the target is disabled, other devices can uti-
lize the disabled NAND signals that are shared with the NAND Flash.
A target enters low-power standby when it is disabled and is not busy. If the target is
busy when it is disabled, the target enters standby after all of the die (LUNs) complete
their operations. Standby helps reduce power consumption.
Asynchronous Bus Idle
A target's bus is idle when CE# is LOW, WE# is HIGH, and RE# is HIGH.
During bus idle, all of the signals are enabled except DQS, which is not used when the
asynchronous interface is active. No commands, addresses, and data are latched into
the target; no data is output.
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Asynchronous Commands
An asynchronous command is written from DQ[7:0] to the command register on the ris-
ing edge of WE# when CE# is LOW, ALE is LOW, CLE is HIGH, and RE# is HIGH.
Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
commands, including READ STATUS (70h) and READ STATUS ENHANCED (78h), are
accepted by die (LUNs) even when they are busy.
Figure 10: Asynchronous Command Latch Cycle
WE#
CE#
ALE
CLE
DQx COMMAND
tWP
tCH
tCS
tALH
tDH
tDS
tALS
tCLH
tCLS
Don’t Care
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Asynchronous Addresses
An asynchronous address is written from DQ[7:0] to the address register on the rising
edge of WE# when CE# is LOW, ALE is HIGH, CLE is LOW, and RE# is HIGH.
Bits that are not part of the address space must be LOW (see Device and Array Organiza-
tion). The number of cycles required for each command varies. Refer to the command
descriptions to determine addressing requirements (see Command Definitions).
Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
addresses are accepted by die (LUNs) even when they are busy; for example, address cy-
cles that follow the READ STATUS ENHANCED (78h) command.
Figure 11: Asynchronous Address Latch Cycle
WE#
CE#
ALE
CLE
DQx Col
add 1
tWP tWH
tCS
tDH
tDS
tALS
tALH
tCLS
Col
add 2 Row
add 1 Row
add 2 Row
add 3
Don’t Care Undefined
tWC
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Asynchronous Data Input
Data is written from DQ[7:0] to the cache register of the selected die (LUN) on the rising
edge of WE# when CE# is LOW, ALE is LOW, CLE is LOW, and RE# is HIGH.
Data input is ignored by die (LUNs) that are not selected or are busy (RDY = 0).
Figure 12: Asynchronous Data Input Cycles
WE#
CE#
ALE
CLE
DQx
tWP tWP tWP
tWH
tALS
tDH
tDS tDH
tDS tDH
tDS
tCLH
tCH
DIN M+1 DIN N
Don’t Care
tWC
DIN M
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Asynchronous Data Output
Data can be output from a die (LUN) if it is in a READY state. Data output is supported
following a READ operation from the NAND Flash array. Data is output from the cache
register of the selected die (LUN) to DQ[7:0] on the falling edge of RE# when CE# is
LOW, ALE is LOW, CLE is LOW, and WE# is HIGH.
If the host controller is using a tRC of 30ns or greater, the host can latch the data on the
rising edge of RE# (see Figure 13 for proper timing). If the host controller is using a tRC
of less than 30ns, the host can latch the data on the next falling edge of RE# (see Fig-
ure 14 (page 24) for extended data output (EDO) timing).
Using the READ STATUS ENHANCED (78h) command prevents data contention follow-
ing an interleaved die (multi-LUN) operation. After issuing the READ STATUS EN-
HANCED (78h) command, to enable data output, issue the READ MODE (00h) com-
mand.
Data output requests are typically ignored by a die (LUN) that is busy (RDY = 0); howev-
er, it is possible to output data from the status register even when a die (LUN) is busy by
first issuing the READ STATUS (70h) or READ STATUS ENHANCED (78h) command.
Figure 13: Asynchronous Data Output Cycles
CE#
RE#
DQx
tREH
tRP
tRR tRC
tCEA
tREA tREA tREA
Don’t Care
tRHZ
tCHZ
tRHZ
tRHOH
RDY
tCOH
DOUT DOUT DOUT
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Figure 14: Asynchronous Data Output Cycles (EDO Mode)
DOUT DOUT DOUT
CE#
RE#
DQx
RDY
tRR
tCEA
tREA
tRP tREH
tRC
tRLOH
tREA
tRHOH
tRHZ
tCOH
tCHZ
Don’t Care
Write Protect
The write protect# (WP#) signal enables or disables PROGRAM and ERASE operations
to a target. When WP# is LOW, PROGRAM and ERASE operations are disabled. When
WP# is HIGH, PROGRAM and ERASE operations are enabled.
It is recommended that the host drive WP# LOW during power-on until Vcc and Vccq
are stable to prevent inadvertent PROGRAM and ERASE operations (see Device Initiali-
zation (page 36) for additional details).
WP# must be transitioned only when the target is not busy and prior to beginning a
command sequence. After a command sequence is complete and the target is ready,
WP# can be transitioned. After WP# is transitioned, the host must wait tWW before issu-
ing a new command.
The WP# signal is always an active input, even when CE# is HIGH. This signal should
not be multiplexed with other signals.
Ready/Busy#
The ready/busy# (R/B#) signal provides a hardware method of indicating whether a tar-
get is ready or busy. A target is busy when one or more of its die (LUNs) are busy
(RDY = 0). A target is ready when all of its die (LUNs) are ready (RDY = 1). Because each
die (LUN) contains a status register, it is possible to determine the independent status
of each die (LUN) by polling its status register instead of using the R/B# signal (see Sta-
tus Operations (page 61) for details regarding die (LUN) status).
This signal requires a pull-up resistor, Rp, for proper operation. R/B# is HIGH when the
target is ready, and transitions LOW when the target is busy. The signal's open-drain
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driver enables multiple R/B# outputs to be OR-tied. Typically, R/B# is connected to an
interrupt pin on the system controller (see Figure 15 (page 25)).
The combination of Rp and capacitive loading of the R/B# circuit determines the rise
time of the R/B# signal. The actual value used for Rp depends on the system timing re-
quirements. Large values of Rp cause R/B# to be delayed significantly. Between the 10-
to 90-percent points on the R/B# waveform, the rise time is approximately two time
constants (TC).
TC = R × C
Where R = Rp (resistance of pull-up resistor), and C = total capacitive load.
The fall time of the R/B# signal is determined mainly by the output impedance of the
R/B# signal and the total load capacitance. Approximate Rp values using a circuit load
of 100pF are provided in Figure 18 (page 27).
The minimum value for Rp is determined by the output drive capability of the R/B# sig-
nal, the output voltage swing, and Vccq.
Rp = Vcc (MAX) - Vol (MAX)
IOL + Σil
Where Σil is the sum of the input currents of all devices tied to the R/B# pin.
Figure 15: READ/BUSY# Open Drain
Rp
VCC
VCCQ
R/B#
Open drain output
IOL
VSS
Device
To controller
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Figure 16: tFall and tRise (VCCQ = 2.7-3.6V)
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
–1 0 2 4 0 2 4 6
tFall tRise
VCCQ 3.3V
TC
V
Notes: 1. tFALL is VOH(DC) to VOL(AC) and tRISE is VOL(DC) to VOH(AC).
2. tRise dependent on external capacitance and resistive loading and output transistor im-
pedance.
3. tRise primarily dependent on external pull-up resistor and external capacitive loading.
4. tFall = 10ns at 3.3V
5. See TC values in Figure 18 (page 27) for approximate Rp value and TC.
Figure 17: IOL vs Rp (VCCQ = 2.7-3.6V)
3.50
3.00
2.50
2.00
1.50
1.00
0.50
0.00
0 2000 4000 6000 8000 10,000 12,000
IOL at Vccq (MAX)
Rp (Ω)
I (mA)
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Figure 18: TC vs Rp
1200
1000
800
600
400
200
0
0 2000 4000 6000 8000 10,000 12,000
Iol at VCCQ (MAX)
RC = TC
C = 100pF
Rp (Ω)
T(ns)
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Bus Operation – Synchronous Interface
These NAND Flash devices have two interfaces—a synchronous interface for fast data
I/O transfer and an asynchronous interface that is backward compatible with existing
NAND Flash devices.
The NAND Flash command protocol for both the asynchronous and synchronous inter-
faces is identical. However, there are some differences betweeen the asynchronous and
synchronous interfaces when issuing command, address, and data I/O cycles using the
NAND Flash signals.
When the synchronous interface is activated on a target (see Activating Interfaces
(page 38)), the target is capable of high-speed DDR data transfers. Existing signals are
redefined for high-speed DDR I/O. The WE# signal becomes CLK. DQS is enabled. The
RE# signal becomes W/R#. CLK provides a clock reference to the NAND Flash device.
DQS is a bidirectional data strobe. During data output, DQS is driven by the NAND
Flash device. During data input, DQS is controlled by the host controller while inputting
data on DQ[7:0].
The direction of DQS and DQ[7:0] is controlled by the W/R# signal. When the W/R# sig-
nal is latched HIGH, the controller is driving the DQ bus and DQS. When the W/R# is
latched LOW, the NAND Flash is driving the DQ bus and DQS.
The synchronous interface bus modes are summarized below.
Table 4: Synchronous Interface Mode Selection
Mode CE# CLE ALE CLK W/R# DQS DQ[7:0] WP# Notes
Standby H X X X X X X 0V/VCCQ 1, 2
Bus idle L L L H X X X
Bus driv-
ing
L L L L output output X
Command
input
L H L H X input H 3
Address
input
L L H H X input H 3
Data in-
put
L H H H input H 4
Data out-
put
L H H L See Note 5 output X 5
Write pro-
tect
X X X X X X X L
Undefined L L H L output output X
Undefined L H L L output output X
Notes: 1. CLK can be stopped when the target is disabled, even when R/B# is LOW.
2. WP# should be biased to CMOS LOW or HIGH for standby.
3. Commands and addresses are latched on the rising edge of CLK.
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4. During data input to the device, DQS is the “clock” that latches the data in the cache
register.
5. During data output from the NAND Flash device, DQS is an output generated from CLK
after tDQSCK delay.
6. Mode selection settings for this table: H = Logic level HIGH; L = Logic level LOW; X = VIH
or VIL.
Synchronous Enable/Standby
In addition to the description found in Asynchronous Enable/Standby (page 19), the
following requirements also apply when the synchronous interface is active.
Before enabling a target, CLK must be running and ALE and CLE must be LOW. When
CE# is driven LOW, all of the signals for the selected target are enabled. The target is not
enabled until tCS completes; the target's bus is then idle.
Prior to disabling a target, the target's bus must be idle. A target is disabled when CE# is
driven HIGH, even when it is busy. All of the target's signals are disabled except CE#,
WP#, and R/B#. After the target is disabled, CLK can be stopped.
A target enters low-power standby when it is disabled and is not busy. If the target is
busy when it is disabled, the target enters standby after all of the die (LUNs) complete
their operations.
Synchronous Bus Idle/Driving
A target's bus is idle or driving when CLK is running, CE# is LOW, ALE is LOW, and CLE
is LOW.
The bus is idle when W/R# transitions HIGH and is latched by CLK. During the bus idle
mode, all signals are enabled; DQS and DQ[7:0] are inputs. No commands, addresses, or
data are latched into the target; no data is output. When entering the bus idle mode, the
host must wait a minimum of tCAD before changing the bus mode. In the bus idle
mode, the only valid bus modes supported are: bus driving, command, address, and
DDR data input.
The bus is driving when W/R# transitions LOW and is latched by CLK. During the bus
driving mode, all signals are enabled; DQS is LOW and DQ[7:0] is driven LOW or HIGH,
but no valid data is output. Following the bus driving mode, the only valid bus modes
supported are bus idle and DDR data output.
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Figure 19: Synchronous Bus Idle/Driving Behavior
CE#
CLE
ALE
CLK
W/R#
DQS
DQ[7:0]
Undefined (driven by NAND)
tCALS
tDQSD tDQSHZ
tCALS
Bus idle Bus idleBus driving
Note: 1. Only the selected die (LUN) drives DQS and DQ[7:0]. During an interleaved die (multi-
LUN) operation, the host must use the READ STATUS ENHANCED (78h) to prevent data
output contention.
Synchronous Commands
A command is written from DQ[7:0] to the command register on the rising edge of CLK
when CE# is LOW, ALE is LOW, CLE is HIGH, and W/R# is HIGH.
After a command is latched—and prior to issuing the next command, address, or
data I/O—the bus must go to bus idle mode on the next rising edge of CLK, except
when the clock period, tCK, is greater than tCAD.
Commands are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
commands, such as READ STATUS (70h) and READ STATUS ENHANCED (78h), are ac-
cepted by die (LUNs), even when they are busy.
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Figure 20: Synchronous Command Cycle
CLK
ALE
CLE
DQS
DQ[7:0]
tCKL
tCALH
tCAH
tCAS
tCALS
tCALH
tCALS
Don’t Care
tCKH
tCALH
tCALS
tCALS
CE#
tCH
tCS
tCAD starts here1
tCAD
W/R#
tCK
tCALH
tCALS
tDQSHZ
Command
Undefined
Note: 1. When CE# remains LOW, tCAD begins at the rising edge of the clock from which the
command cycle is latched for subsequent command, address, data input, or data output
cycle(s).
Synchronous Addresses
A synchronous address is written from DQ[7:0] to the address register on the rising edge
of CLK when CE# is LOW, ALE is HIGH, CLE is LOW, and W/R# is HIGH.
After an address is latched—and prior to issuing the next command, address, or data
I/O—the bus must go to bus idle mode on the next rising edge of CLK, except when the
clock period, tCK, is greater than tCAD.
Bits not part of the address space must be LOW (see Device and Array Organization).
The number of address cycles required for each command varies. Refer to the com-
mand descriptions to determine addressing requirements.
Addresses are typically ignored by die (LUNs) that are busy (RDY = 0); however, some
addresses such as address cycles that follow the READ STATUS ENHANCED (78h) com-
mand, are accepted by die (LUNs), even when they are busy.
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Figure 21: Synchronous Address Cycle
CLK
ALE
CLE
DQS
DQ[7:0]
tCKL
tCALH
tCALS
tCALH
tCALS
Don’t CareUndefined
tCKH
tCALS
tCALH
tCALS
tCALH
tCALS
CE#
tCH
tCS
tCAD
W/R#
tCK
tDQSHZ
tCAH
tCAS
Address
tCAD starts here1
Note: 1. When CE# remains LOW, tCAD begins at the rising edge of the clock from which the
command cycle is latched for subsequent command, address, data input, or data output
cycle(s).
Synchronous DDR Data Input
To enter the DDR data input mode, the following conditions must be met:
• CLK is running
• CE# is LOW
• W/R# is HIGH
•tCAD is met
• DQS is LOW
• ALE and CLE are HIGH on the rising edge of CLK
Upon entering the DDR data input mode after tDQSS, data is written from DQ[7:0] to
the cache register on each and every rising and falling edge of DQS (center-aligned)
when CLK is running and the DQS to CLK skew meets tDSH and tDSS, CE# is LOW,
W/R# is HIGH, and ALE and CLE are HIGH on the rising edge of CLK.
To exit DDR data input mode, the following conditions must be met:
• CLK is running and the DQS to CLK skew meets tDSH and tDSS
• CE# is LOW
• W/R# is HIGH
• ALE and CLE are latched LOW on the rising edge of CLK
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• The final two data bytes of the data input sequence are written to DQ[7:0] to the cache
register on the rising and falling edges of DQS after the last cycle in the data input se-
quence in which ALE and CLE are latched HIGH.
• DQS is held LOW for tWPST (after the final falling edge of DQS)
Following tWPST, the bus enters bus idle mode and tCAD begins on the next rising edge
of CLK. After tCAD starts, the host can disable the target if desired.
Data input is ignored by die (LUNs) that are not selected or are busy.
Figure 22: Synchronous DDR Data Input Cycles
CLK
ALE
CLE
DQ[7:0]
DQS
tCKL tCALH
tDH
tDS
tDQSS
tCALS
tCALH
tCALS
Don’t Care
tCKH
tCALH
tCALS
tCALS
tCALH
tCALS
tCALS
CE#
tCH
tCS
tCAD
W/R#
tCK
tDQSL
tWPRE tDQSL
tDQSH
tDQSH tDQSH tWPST
DN-1
D2
tDSH tDSH
tDSS tDSH tDSS
tDSH tDSS
tDH
tDS
D3DN-2 DN
D0D1
tCAD
starts
here1
Notes: 1. When CE# remains LOW, tCAD begins at the first rising edge of the clock after tWPST
completes.
2. tDSH (MIN) generally occurs during tDQSS (MIN).
3. tDSS (MIN) generally occurs during tDQSS (MAX).
Synchronous DDR Data Output
Data can be output from a die (LUN) if it is ready. Data output is supported following a
READ operation from the NAND Flash array.
To enter the DDR data output mode, the following conditions must be met:
• CLK is running
• CE# is LOW
• The host has released the DQ[7:0] bus and DQS
• W/R# is latched LOW on the rising edge of CLK to enable the selected die (LUN) to
take ownership of the DQ[7:0] bus and DQS within tWRCK
•tCAD is met
• ALE and CLE are HIGH on the rising edge of CLK
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Upon entering the DDR data output mode, DQS will toggle HIGH and LOW with a delay
of tDQSCK from the respective rising and falling edges of CLK. DQ[7:0] will output data
edge-aligned to the rising and falling edges of DQS, with the first transition delayed by
no more than tAC.
DDR data output mode continues as long as CLK is running, CE# is LOW, W/R# is LOW,
and ALE and CLE are HIGH on the rising edge of CLK.
To exit DDR data output mode, the following conditions must be met:
• CLK is running
• CE# is LOW
• W/R# is LOW
• ALE and CLE are latched LOW on the rising edge of CLK
The final two data bytes are output on DQ[7:0] on the final rising and falling edges of
DQS. The final rising and falling edges of DQS occur tDQSCK after the last cycle in the
data output sequence in which ALE and CLE are latched HIGH. After tCKWR, the bus
enters bus idle mode and tCAD begins on the next rising edge of CLK. Once tCAD starts
the host can disable the target if desired.
Data output requests are typically ignored by a die (LUN) that is busy (RDY = 0); howev-
er, it is possible to output data from the status register even when a die (LUN) is busy by
issuing the READ STATUS (70h) or READ STATUS ENHANCED (78h) command.
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Figure 23: Synchronous DDR Data Output Cycles
CLK
ALE
CLE
DQ[7:0]
DQS
tCKL
tCALH
tCALS
tCALH
tCALS
Don’t Care
tCKH
tCALH
tCALS
tCALS
tCALH
tCALS
tCALS
tCALS
tCALS
CE#
tCH
tCS
tCAD
tDQSD
tWRCK tDQSCK
tAC
W/R#
tDQSCK
tDQSCK
tCKWR
tDQSCK
tDQSCK
tDQSCK
tDQSHZ
tDQSQ tQH
tDQSQ
tCK
tHP tHP
tHP tHP tHP
tHP
Data Transitioning
tDVW
tQH
tDVW
tQH
tDVW
tQH
tDVW
tDVW
tCAD starts
here1
Undefined (driven by NAND)
D0D1D2DN-1
DN-2 DN
tDQSQ
tDQSQ
Notes: 1. When CE# remains LOW, tCAD begins at the rising edge of the clock after tCKWR for
subsequent command or data output cycle(s).
2. See Figure 20 (page 31) for details of W/R# behavior.
3. tAC is the DQ output window relative to CLK and is the long-term component of DQ
skew.
4. For W/R# transitioning HIGH, DQ[7:0] and DQS go to tri-state.
5. For W/R# transitioning LOW, DQ[7:0] drives current state and DQS goes LOW.
6. After final data output, DQ[7:0] is driven until W/R# goes HIGH, but is not valid.
Write Protect
See Write Protect (page 24).
Ready/Busy#
See Ready/Busy# (page 24).
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Device Initialization
Some NAND Flash devices do not support VCCQ. For these devices all references to VCCQ
are replaced with VCC.
Micron NAND Flash devices are designed to prevent data corruption during power
transitions. VCC is internally monitored. (The WP# signal supports additional hardware
protection during power transitions.) When ramping V CC and VCCQ, use the following
procedure to initialize the device:
1. Ramp VCC.
2. Ramp VCCQ. VCCQ must not exceed VCC.
3. The host must wait for R/B# to be valid and HIGH before issuing RESET (FFh) to
any target (see Figure 24). The R/B# signal becomes valid when 50µs has elapsed
since the beginning the VCC ramp, and 10µs has elapsed since VCCQ reaches VCCQ
(MIN) and VCC reaches VCC (MIN).
4. If not monitoring R/B#, the host must wait at least 100µs after VCCQ reaches VCCQ
(MIN) and VCC reaches VCC (MIN). If monitoring
R/B#, the host must wait until R/B# is HIGH.
5. The asynchronous interface is active by default for each target. Each LUN draws
less than an average of IST measured over intervals of 1ms until the RESET (FFh)
command is issued.
6. The RESET (FFh) command must be the first command issued to all targets (CE#s)
after the NAND Flash device is powered on. Each target will be busy for tPOR after
a RESET command is issued. The RESET busy time can be monitored by polling
R/B# or issuing the READ STATUS (70h) command to poll the status register.
7. The device is now initialized and ready for normal operation.
At power-down, VCCQ must go LOW, either before, or simultaneously with, VCC going
LOW.
Figure 24: R/B# Power-On Behavior
Reset (FFh)
is issued
50µs (MIN)
100µs (MAX)
Invalid
10µs
(MAX)
> 0µs
Vcc ramp
starts
Vccq
Vcc
R/B#
Vccq = Vccq (MIN)
Vcc = Vcc (MIN)
Note: 1. Disregard VCCQ for devices that use only VCC.
To initialize a discovered target, the following steps shall be taken. The initialization
process should be followed for each connected CE# signal, including performing the
READ PARAMETER PAGE (ECh) command for each target. Each chip enable corre-
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sponds to a unique target with its own independent properties that the host shall ob-
serve and subsequently use.
The host should issue the READ PARAMETET PAGE (ECh) command. This command
returns information that includes the capabilities, features, and operating parameters
of the device. When the information is read from the device, the host shall check the
CRC to ensure that the data was received correctly and without error prior to taking ac-
tion on that data.
If the CRC of the first parameter page read is not valid, the host should read redundant
parameter page copies. The host can determine whether a redundant parameter page is
present or not by checking if the first four bytes contain at least two bytes of the param-
eter page signature. If the parameter page signature is present, then the host should
read the entirety of that redundant parameter page. The host should then check the
CRC of that redundant parameter page. If the CRC is correct, the host may take action
based on the contents of that redundant parameter page. If the CRC is incorrect, then
the host should attempt to read the next redundant parameter page by the same proce-
dure.
The host should continue reading redundant parameter pages until the host is able to
accurately reconstruct the parameter page contents. The host may use bit-wise majority
or other ECC techniques to recover the contents of the parameter page from the param-
eter page copies present. When the host determines that a parameter page signature is
not present, then all parameter pages have been read.
After successfully retrieving the parameter page, the host has all information necessary
to successfully communicate with that target. If the host has not previously mapped de-
fective block information for this target, the host should next map out all defective
blocks in the target. The host may then proceed to utilize the target, including erase and
program operations.
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Activating Interfaces
After performing the steps under Device Initialization (page 36), the asynchronous in-
terface is active for all targets on the device.
Each target's interface is independent of other targets, so the host is responsible for
changing the interface for each target.
If the host and NAND Flash device, through error, are no longer using the same inter-
face, then steps under Activating the Asynchronous Interface are performed to re-
synchronize the interfaces.
Activating the Asynchronous Interface
To activate the asynchronous NAND interface, once the synchronous interface is active,
the following steps are repeated for each target:
1. The host pulls CE# HIGH, disables its input to CLK, and enables its asynchronous
interface.
2. The host pulls CE# LOW and issues the RESET (FFh) command, using an asyn-
chronous command cycle.
3. R/B# goes LOW for tRST.
4. After tITC, and during tRST, the device enters the asynchronous NAND interface.
READ STATUS (70h) and READ STATUS ENHANCED (78h) are the only commands
that can be issued.
5. After tRST, R/B# goes HIGH. Timing mode feature address (01h), subfeature pa-
rameter P1 is set to 00h, indicating that the asynchronous NAND interface is active
and that the device is set to timing mode 0.
For further details, see Reset Operations.
Activating the Synchronous Interface
To activate the synchronous NAND Flash interface, the following steps are repeated for
each target:
1. Issue the SET FEATURES (EFh) command.
2. Write address 01h, which selects the timing mode.
3. Write P1 with 1Xh, where "X" is the timing mode used in the synchronous inter-
face (see Configuration Operations).
4. Write P2–P4 as 00h-00h-00h.
5. R/B# goes LOW for tITC. The host should pull CE# HIGH. During tITC, the host
should not issue any type of command, including status commands, to the NAND
Flash device.
6. After tITC, R/B# goes HIGH and the synchronous interface is enabled. Before pull-
ing CE# LOW, the host should enable the clock.
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Figure 25: Activating the Synchronous Interface
Cycle type
DQ[7:0]
R/B#
CMD ADDR DIN DIN DIN DIN
EFh 01h TM P2 P3 P4
tADL
tWB
tCAD
CE# may
transition HIGH
CE# may
transition LOW
100ns
tITC
A CB
Note: 1. TM = Timing mode.
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Command Definitions
Table 5: Command Set
Command
Command
Cycle #1
Number of
Valid
Address
Cycles
Data
Input
Cycles
Command
Cycle #2
Valid While
Selected LUN
is Busy1
Valid While
Other LUNs
are Busy2Notes
Reset Operations
RESET FFh 0 – – Yes Yes
SYNCHRONOUS RESET FCh 0 – – Yes Yes
RESET LUN FAh 3 – – Yes Yes
Identification Operations
READ ID 90h 1 – – 3
READ PARAMETER PAGE ECh 1 – –
READ UNIQUE ID EDh 1 – –
Configuration Operations
GET FEATURES EEh 1 – – 3
SET FEATURES EFh 1 4 – 4
Status Operations
READ STATUS 70h 0 – – Yes
READ STATUS EN-
HANCED
78h 3 – – Yes Yes
Column Address Operations
CHANGE READ COLUMN 05h 2 – E0h Yes
CHANGE READ COLUMN
ENHANCED
06h 5 – E0h Yes
CHANGE WRITE COL-
UMN
85h 2 Optional – Yes
CHANGE ROW ADDRESS 85h 5 Optional – Yes 5
Read Operations
READ MODE 00h 0 – – Yes
READ PAGE 00h 5 – 30h Yes 6
READ PAGE MULTI-
PLANE
00h 5 – 32h Yes
READ PAGE CACHE
SEQUENTIAL
31h 0 – – Yes 7
READ PAGE CACHE
RANDOM
00h 5 – 31h Yes 6,7
READ PAGE CACHE LAST 3Fh 0 – – Yes 7
Program Operations
PROGRAM PAGE 80h 5 Yes 10h Yes
PROGRAM PAGE
MULTI-PLANE
80h 5 Yes 11h Yes
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Table 5: Command Set (Continued)
Command
Command
Cycle #1
Number of
Valid
Address
Cycles
Data
Input
Cycles
Command
Cycle #2
Valid While
Selected LUN
is Busy1
Valid While
Other LUNs
are Busy2Notes
PROGRAM PAGE CACHE 80h 5 Yes 15h Yes 8
Erase Operations
ERASE BLOCK 60h 3 – D0h Yes
ERASE BLOCK
MULTI-PLANE
60h 3 – D1h Yes
Copyback Operations
COPYBACK READ 00h 5 – 35h Yes 6
COPYBACK PROGRAM 85h 5 Optional 10h Yes
COPYBACK PROGRAM
MULTI-PLANE
85h 5 Optional 11h Yes
Notes: 1. Busy means RDY = 0.
2. These commands can be used for interleaved die (multi-LUN) operations (see Interleaved
Die (Multi-LUN) Operations (page 96)).
3. The READ ID (90h) and GET FEATURES (EEh) output identical data on rising and falling
DQS edges.
4. The SET FEATURES (EFh) command requires data transition prior to the rising edge of
CLK, with identical data for the rising and falling edges.
5. Command cycle #2 of 11h is conditional. See CHANGE ROW ADDRESS (85h) for more de-
tails.
6. This command can be preceded by up to one READ PAGE MULTI-PLANE (00h-32h) com-
mand to accommodate a maximum simultaneous two-plane array operation.
7. Issuing a READ PAGE CACHE-series (31h, 00h-31h, 00h-32h, 3Fh) command when the ar-
ray is busy (RDY = 1, ARDY = 0) is supported if the previous command was a READ PAGE
(00h-30h) or READ PAGE CACHE-series command; otherwise, it is prohibited.
8. Issuing a PROGRAM PAGE CACHE (80h-15h) command when the array is busy (RDY = 1,
ARDY = 0) is supported if the previous command was a PROGRAM PAGE CACHE
(80h-15h) command; otherwise, it is prohibited.
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Reset Operations
RESET (FFh)
The RESET (FFh) command is used to put a target into a known condition and to abort
command sequences in progress. This command is accepted by all die (LUNs), even
when they are busy.
When FFh is written to the command register, the target goes busy for tRST. During
tRST, the selected target (CE#) discontinues all array operations on all die (LUNs). All
pending single- and multi-plane operations are cancelled. If this command is issued
while a PROGRAM or ERASE operation is occurring on one or more die (LUNs), the data
may be partially programmed or erased and is invalid. The command register is cleared
and ready for the next command. The data register and cache register contents are inva-
lid.
RESET must be issued as the first command to each target following power-up (see De-
vice Initialization). Use of the READ STATUS ENHANCED (78h) command is prohibited
during the power-on RESET. To determine when the target is ready, use READ STATUS
(70h).
If the RESET (FFh) command is issued when the synchronous interface is enabled, the
target's interface is changed to the asynchronous interface and the timing mode is set
to 0. The RESET (FFh) command can be issued asynchronously when the synchronous
interface is active, meaning that CLK does not need to be continuously running when
CE# is transitioned LOW and FFh is latched on the rising edge of CLK. After this com-
mand is latched, the host should not issue any commands during tITC. After tITC, and
during or after tRST, the host can poll each LUN's status register.
If the RESET (FFh) command is issued when the asynchronous interface is active, the
target's asynchronous timing mode remains unchanged. During or after tRST, the host
can poll each LUN's status register.
Figure 26: RESET (FFh) Operation
Cycle type
DQ[7:0]
R/B#
tRST
tWB
FFh
Command
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SYNCHRONOUS RESET (FCh)
When the synchronous interface is active, the SYNCHRONOUS RESET (FCh) command
is used to put a target into a known condition and to abort command sequences in pro-
gress. This command is accepted by all die (LUNs), even when they are BUSY.
When FCh is written to the command register, the target goes busy for tRST. During
tRST, the selected target (CE#) discontinues all array operations on all die (LUNs). All
pending single- and multi-plane operations are cancelled. If this command is issued
while a PROGRAM or ERASE operation is occurring on one or more die (LUNs), the data
may be partially programmed or erased and is invalid. The command register is cleared
and ready for the next command. The data register and cache register contents are inva-
lid and the synchronous interface remains active.
During or after tRST, the host can poll each LUN's status register.
SYNCHRONOUS RESET is only accepted while the synchronous interface is active. Its
use is prohibited when the asynchronous interface is active.
Figure 27: SYNCHRONOUS RESET (FCh) Operation
Cycle type
DQ[7:0]
R/B#
tRST
tWB
FCh
Command
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RESET LUN (FAh)
The RESET LUN (FAh) command is used to put a particular LUN on a target into a
known condition and to abort command sequences in progress. This command is ac-
cepted by only the LUN addressed by the RESET LUN (FAh) command, even when that
LUN is busy.
When FAh is written to the command register, the addressed LUN goes busy for tRST.
During tRST, the selected LUN discontinues all array operations. All pending single- and
multi-plane operations are canceled. If this command is issued while a PROGRAM or
ERASE operation is occurring on the addressed LUN, the data may be partially pro-
grammed or erased and is invalid. The command register is cleared and ready for the
next command. The data register and cache register contents are invalid.
If the RESET LUN (FAh) command is issued when the synchronous interface is enabled,
the targets's interface remains in synchronous mode.
If the RESET LUN (FAh) command is issued when the asynchronous interface is ena-
bled, the target's interface remains in asynchronous mode.
During or after tRST, the host can poll each LUN's status register.
The RESET LUN (FAh) command is prohibited when not in the default array operation
mode.
The RESET LUN (FAh) command can only be issued to a target (CE#) after the RESET
(FFh) command has been issued as the first command to a target following power-up.
Figure 28: RESET LUN (FAh) Operation
Cycle type
DQ[7:0]
R/B#
tRST
tWB
FAh
Command
R1
Address Address Address
R2 R3
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Identification Operations
READ ID (90h)
The READ ID (90h) command is used to read identifier codes programmed into the tar-
get. This command is accepted by the target only when all die (LUNs) on the target are
idle.
Writing 90h to the command register puts the target in read ID mode. The target stays in
this mode until another valid command is issued.
When the 90h command is followed by a 00h address cycle, the target returns a 5-byte
identifier code that includes the manufacturer ID, device configuration, and part-spe-
cific information.
When the 90h command is followed by a 20h address cycle, the target returns the 4-byte
ONFI identifier code.
After the 90h and address cycle are written to the target, the host enables data output
mode to read the identifier information. When the asynchronous interface is active, one
data byte is output per RE# toggle. When the synchronous interface is active, one data
byte is output per rising edge of DQS when ALE and CLE are HIGH; the data byte on the
falling edge of DQS is identical to the data byte output on the previous rising edge of
DQS.
Figure 29: READ ID (90h) with 00h Address Operation
Cycle type
DQ[7:0]
tWHR
Command
90h 00h Byte 0 Byte 1 Byte 2 Byte 3
Address DOUT DOUT DOUT DOUT DOUT DOUT DOUT DOUT
Byte 4 Byte 5 Byte 6 Byte 7
Note: 1. See the READ ID Parameter tables for byte definitions.
Figure 30: READ ID (90h) with 20h Address Operation
Cycle type
DQ[7:0]
tWHR
Command
90h 20h 4Fh 4Eh 46h 49h
Address DOUT DOUT DOUT DOUT
Note: 1. See the READ ID Parameter tables for byte definitions.
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READ ID Parameter Tables
Table 6: Read ID Parameters for Address 00h
Device Byte 0 Byte 1 Byte 2 Byte 3 Byte 4 Byte 5 Byte 6 Byte 7
MT29F16G08CBACA 2Ch 48h 04h 4Ah A5h 00h 00h 00h
MT29F32G08CFACA 2Ch 48h 04h 4Ah A5h 00h 00h 00h
MT29F16G08CBACB 2Ch 48h 04h 4Ah A5h 00h 00h 00h
MT29F32G08CFACB 2Ch 48h 04h 4Ah A5h 00h 00h 00h
Note: 1. h = hexadecimal.
Table 7: Read ID Parameters for Address 20h
Device Byte 0 Byte 1 Byte 2 Byte 3 Byte 4
All 4Fh 4Eh 46h 49h XXh
Notes: 1. h = hexadecimal.
2. XXh = Undefined.
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READ PARAMETER PAGE (ECh)
The READ PARAMETER PAGE (ECh) command is used to read the ONFI parameter page
programmed into the target. This command is accepted by the target only when all die
(LUNs) on the target are idle.
Writing ECh to the command register puts the target in read parameter page mode. The
target stays in this mode until another valid command is issued.
When the ECh command is followed by an 00h address cycle, the target goes busy for tR.
If the READ STATUS (70h) command is used to monitor for command completion, the
READ MODE (00h) command must be used to re-enable data output mode. Use of the
READ STATUS ENHANCED (78h) command is prohibited while the target is busy and
during data output.
After tR completes, the host enables data output mode to read the parameter page.
When the asynchronous interface is active, one data byte is output per RE# toggle.
When the synchronous interface is active, one data byte is output for each rising or fall-
ing edge of DQS.
A minimum of three copies of the parameter page are stored in the device. Each param-
eter page is 256 bytes. If desired, the CHANGE READ COLUMN (05h-E0h) command
can be used to change the location of data output. Use of the CHANGE READ COLUMN
ENHANCED (06h-E0h) command is prohibited.
The READ PARAMETER PAGE (ECh) output data can be used by the host to configure its
internal settings to properly use the NAND Flash device. Parameter page data is static
per part, however the value can be changed through the product cycle of NAND Flash.
The host should interpret the data and configure itself accordingly.
Figure 31: READ PARAMETER (ECh) Operation
Cycle type
DQ[7:0]
R/B#
tWB tRtRR
Command Address DOUT
ECh 00h P00P10
DOUT DOUT
… P01
DOUT DOUT
P11…
DOUT
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Parameter Page Data Structure Tables
Table 8: Parameter Page Data Structure
Byte Description Device Values
Revision information and features block
0–3 Parameter page signature
Byte 0: 4Fh, “O”
Byte 1: 4Eh, “N”
Byte 2: 46h, “F”
Byte 3: 49h, “I”
– 4Fh, 4Eh, 46h, 49h
4–5 Revision number
Bit[15:5]: Reserved (0)
Bit 4: 1 = supports ONFI version 2.2
Bit 3: 1 = supports ONFI version 2.1
Bit 2: 1 = supports ONFI version 2.0
Bit 1: 1 = supports ONFI version 1.0
Bit 0: Reserved (0)
– 1Eh, 00h
6-7 Features supported
Bit[15:9]: Reserved (0)
Bit 8: 1 = supports program page register clear enhance-
ment
Bit 7: 1 = supports extended parameter page
Bit 6: 1 = supports interleaved (multi-plane) read opera-
tions
Bit 5: 1 = supports synchronous interface
Bit 4: 1 = supports odd-to-even page copyback
Bit 3: 1 = supports interleaved (multi-plane) program and
erase operations
Bit 2: 1 = supports non-sequential page programming
Bit 1: 1 = supports multiple LUN operations
Bit 0: 1 = supports 16-bit data bus width
MT29F16G08CBACA D8h, 01h
MT29F32G08CFACA
MT29F16G08CBACB F8h, 01h
MT29F32G08CFACB
–
8–9 Optional commands supported
Bit[15:10]: Reserved (0)
Bit 9: 1 = supports RESET LUN command
Bit 8: 1 = supports small data move
Bit 7: 1 = supports CHANGE ROW ADDRESS
Bit 6: 1 = supports CHANGE READ COLUMN ENHANCED
Bit 5: 1 = supports READ UNIQUE ID
Bit 4: 1 = supports COPYBACK
Bit 3: 1 = supports READ STATUS ENHANCED
Bit 2: 1 = supports GET FEATURES and SET FEATURES
Bit 1: 1 = supports read cache commands
Bit 0: 1 = supports PROGRAM PAGE CACHE
FFh, 03h
10–11 Reserved (0) – All 00h
12–13 Extended parameter page length – 03h, 00h
14 Number of parameter pages – 03h
15–31 Reserved (0) – All 00h
Manufacturer information block
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Table 8: Parameter Page Data Structure (Continued)
Byte Description Device Values
32–43 Device manufacturer (12 ASCII characters)
Micron
– 4Dh, 49h, 43h, 52h,
4Fh, 4Eh, 20h, 20h,
20h, 20h, 20h, 20h
44–63 Device model (20 ASCII characters) MT29F16G08CBACAWP 4Dh, 54h, 32h, 39h,
46h, 31h, 36h, 47h,
30h, 38h, 43h, 42h,
41h, 43h, 41h, 57h,
50h, 20h, 20h, 20h
MT29F16G08CBACAH5 4Dh, 54h, 32h, 39h,
46h, 31h, 36h, 47h,
30h, 38h, 43h, 42h,
41h, 43h, 41h, 48h,
35h, 20h, 20h, 20h
MT29F32G08CFACAWP 4Dh, 54h, 32h, 39h,
46h, 33h, 32h, 47h,
30h, 38h, 43h, 46h,
41h, 43h, 41h, 57h,
50h, 20h, 20h, 20h
MT29F16G08CBACBWP 4Dh, 54h, 32h, 39h,
46h, 31h, 36h, 47h,
30h, 38h, 43h, 42h,
41h, 43h, 42h, 57h,
50h, 20h, 20h, 20h
MT29F32G08CFACBWP 4Dh, 54h, 32h, 39h,
46h, 33h, 32h, 47h,
30h, 38h, 43h, 46h,
41h, 43h, 42h, 57h,
50h, 20h, 20h, 20h
64 JEDEC manufacturer ID – 2Ch
65–66 Date code – 00h, 00h
67–79 Reserved (0) – All 00h
Memory organization block
80–83 Number of data bytes per page – 00h, 10h, 00h, 00h
84–85 Number of spare bytes per page – E0h, 00h
86–91 Reserved (0) – All 00h
92–95 Number of pages per block 00h, 01h, 00h, 00h
96–99 Number of blocks per LUN – 00h, 08h, 00h, 00h
100 Number of LUNs per chip enable MT29F16G08CBACA 01h
MT29F32G08CFACA
MT29F16G08CBACB
MT29F32G08CFACB
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Table 8: Parameter Page Data Structure (Continued)
Byte Description Device Values
101 Number of address cycles
Bit[7:4]: Column address cycles
Bit[3:0]: Row address cycles
– 23h
102 Number of bits per cell – 02h
103–104 Bad blocks maximum per LUN – 32h, 00h
105–106 Block endurance – 03h, 03h
107 Guaranteed valid blocks at beginning of target – 01h
108–109 Block endurance for guaranteed valid blocks – 00h, 00h
110 Number of programs per page – 01h
111 Partial programming attributes
Bit[7:5]: Reserved
Bit 4: 1 = partial page layout is partial page data fol-
lowed by partial page spare
Bit[3:1]: Reserved
Bit 0: 1 = partial page programming has constraints
– 00h
112 Number of bits ECC correctability – FFh
113 Number of interleaved address bits
Bit[7:4]: Reserved (0)
Bit[3:0]: Number of interleaved address bits
– 01h
114 Interleaved operation attributes
Bit[7:5]: Reserved (0)
Bit 4: 1 = supports read cache
Bit 3: Address restrictions for cache operations
Bit 2: 1 = supports program cache
Bit 1: 1 = no block address restrictions
Bit 0: Overlapped/concurrent interleaving support
– 1Eh
115–127 Reserved (0) – All 00h
Electrical parameters block
128 I/O pin capacitance per chip enable MT29F16G08CBACAWP 05h
MT29F16G08CBACAH5 05h
MT29F32G08CFACAWP 04h
MT29F16G08CBACBWP 05h
MT29F32G08CFACBWP 04h
129–130 Asynchronous timing mode support
Bit[15:6]: Reserved (0)
Bit 5: 1 = supports timing mode 5
Bit 4: 1 = supports timing mode 4
Bit 3: 1 = supports timing mode 3
Bit 2: 1 = supports timing mode 2
Bit 1: 1 = supports timing mode 1
Bit 0: 1 = supports timing mode 0, shall be 1
– 3Fh, 00h
131–132 Reserved (0) – All 00h
133–134 tPROG Maximum PROGRAM PAGE time (µs) – 28h, 0Ah
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Table 8: Parameter Page Data Structure (Continued)
Byte Description Device Values
135–136 tBERS Maximum BLOCK ERASE time (µs) – 10h, 27h
137–138 tR Maximum PAGE READ time (µs) – 4Bh, 00h
139–140 tCCS Minimum change column setup time (ns) – C8h, 00h
141–142 Source synchronous timing mode support
Bit[15:6]: Reserved (0)
Bit 5: 1 = supports timing mode 5
Bit 4: 1 = supports timing mode 4
Bit 3: 1 = supports timing mode 3
Bit 2: 1 = supports timing mode 2
Bit 1: 1 = supports timing mode 1
Bit 0: 1 = supports timing mode 0
MT29F16G08CBACAWP 00h, 00h
MT29F16G08CBACAH5
MT29F32G08CFACAWP
MT29F16G08CBACBWP 1Fh, 00h
MT29F32G08CFACBWP
143 Source synchronous features
Bit[7:3]: Reserved (0)
Bit 2: 1 = devices support CLK stopped for data input
Bit 1: 1 = typical capacitance values present
Bit 0: 0 = use tCAD MIN value
MT29F16G08CBACAWP 00h
MT29F16G08CBACAH5
MT29F32G08CFACAWP
MT29F16G08CBACBWP 02h
MT29F32G08CFACBWP
144–145 CLK input pin capacitance, typical MT29F16G08CBACAWP 00h, 00h
MT29F16G08CBACAH5
MT29F32G08CFACAWP
MT29F16G08CBACBWP 34h, 00h
MT29F32G08CFACBWP 27h, 00h
146–147 I/O pin capacitance, typical MT29F16G08CBACAWP 00h, 00h
MT29F16G08CBACAH5
MT29F32G08CFACAWP
MT29F16G08CBACBWP 23h, 00h
MT29F32G08CFACBWP 20h, 00h
148–149 Input capacitance, typical MT29F16G08CBACAWP 00h, 00h
MT29F16G08CBACAH5
MT29F32G08CFACAWP
MT29F16G08CBACBWP 34h, 00h
MT29F32G08CFACBWP 27h, 00h
150 Input pin capacitance, maximum MT29F16G08CBACAWP 06h
MT29F16G08CBACAH5 07h
MT29F32G08CFACAWP 05h
MT29F16G08CBACBWP 06h
MT29F32G08CFACBWP 05h
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Table 8: Parameter Page Data Structure (Continued)
Byte Description Device Values
151 Driver strength support
Bit[7:3]: Reserved (0)
Bit 2: 1 = Supports Overdrive 2 drive strength
Bit 1: 1 = Supports Overdrive 1 drive strength
Bit 0: 1 = Supports driver strength settings
– 07h
152–153 tR maximum interleaved (multi-plane) page read time
(µs)
– 4Bh, 00h
154-155 tADL program register clear enhancement values (ns) – 46h, 00h
156–163 Reserved (0) – All 00h
Vendor block
164–165 Vendor-specific revision number – 01h, 00h
166 TWO-PLANE PAGE READ support
Bit[7:1]: Reserved (0)
Bit 0: 1 = Support for TWO-PLANE PAGE READ
– 01h
167 Read cache support
Bit[7:1]: Reserved (0)
Bit 0: 0 = Does not support Micron-specific read cache
function
– 00h
168 READ UNIQUE ID support
Bit[7:1]: Reserved (0)
Bit 0: 0 = Does not support Micron-specific READ UNIQUE
ID
– 00h
169 Programmable DQ output impedance support
Bit[7:1]: Reserved (0)
Bit 0: 0 = No support for programmable DQ output impe-
dance by B8h command
– 00h
170 Number of programmable DQ output impedance set-
tings
Bit[7:3]: Reserved (0)
Bit [2:0] = Number of programmable DQ output impe-
dance settings
– 04h
171 Programmable DQ output impedance feature address
Bit[7:0] = Programmable DQ output impedance feature
address
– 10h
172 Programmable R/B# pull-down strength support
Bit[7:1]: Reserved (0)
Bit 0: 1 = Support programmable R/B# pull-down
strength
– 01h
173 Programmable R/B# pull-down strength feature address
Bit[7:0] = Feature address used with programmable R/B#
pull-down strength
– 81h
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Table 8: Parameter Page Data Structure (Continued)
Byte Description Device Values
174 Number of programmable R/B# pull-down strength set-
tings
Bit[7:3]: Reserved (0)
Bit[2:0] = Number of programmable R/B# pull-down
strength settings
– 04h
175 OTP mode support
Bit[7:2]: Reserved (0)
Bit 1: 1 = Supports Get/Set Features command set
Bit 0: 0 = Does not support A5h/A0h/AFh OTP command
set
– 02h
176 OTP page start
Bit[7:0] = Page where OTP page space begins
– 02h
177 OTP DATA PROTECT address
Bit[7:0] = Page address to use when issuing OTP DATA
PROTECT command
– 01h
178 Number of OTP pages
Bit[15:5]: Reserved (0)
Bit[4:0] = Number of OTP pages
– 1Eh
179 OTP Feature Address – 90h
180–252 Reserved (0) – All 00h
253 Parameter page revision – 05h
254–255 Integrity CRC MT29F16G08CBACAWP 94h, B4h
MT29F16G08CBACAH5 79h, BDh
MT29F32G08CFACAWP B7h, 68h
MT29F16G08CBACBWP 77h, 51h
MT29F32G08CFACBWP 22h, D6h
Redundant parameter pages
256–511 Value of bytes 0–255 – See bytes 0–255
512–767 Value of bytes 0–255 – See bytes 0–255
Extended parameter pages
768–769 Extended parameter page Integrity CRC – EAh, 27h
770-773 Extended parameter page signature
Byte 0: 45h, “E”
Byte 1: 50h, “P”
Byte 2: 50h, “P”
Byte 3: 53h, “S”
– 45h, 50h, 50h, 53h
774-783 Reserved (0) – All 00h
784 Section 0 type – 02h
785 Section 0 length – 01h
786-799 Reserved (0) – All 00h
800 Number of bits ECC correctability – 18h
801 ECC codeword size – 0Ah
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Table 8: Parameter Page Data Structure (Continued)
Byte Description Device Values
802-803 Bad blocks maximum per LUN – 32h, 00h
804-805 Block endurance – 03h, 03h
806-815 Reserved (0) – All 00h
816-863 Value of bytes 768-815 – See bytes 768-815
864-911 Value of bytes 768-815 – See bytes 768-815
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READ UNIQUE ID (EDh)
The READ UNIQUE ID (EDh) command is used to read a unique identifier programmed
into the target. This command is accepted by the target only when all die (LUNs) on the
target are idle.
Writing EDh to the command register puts the target in read unique ID mode. The tar-
get stays in this mode until another valid command is issued.
When the EDh command is followed by a 00h address cycle, the target goes busy for tR.
If the READ STATUS (70h) command is used to monitor for command completion, the
READ MODE (00h) command must be used to re-enable data output mode.
After tR completes, the host enables data output mode to read the unique ID. When the
asynchronous interface is active, one data byte is output per RE# toggle. When the syn-
chronous interface is active, two data bytes are output, one byte for each rising or falling
edge of DQS.
Sixteen copies of the unique ID data are stored in the device. Each copy is 32 bytes. The
first 16 bytes of a 32-byte copy are unique data, and the second 16 bytes are the comple-
ment of the first 16 bytes. The host should XOR the first 16 bytes with the second 16
bytes. If the result is 16 bytes of FFh, then that copy of the unique ID data is correct. In
the event that a non-FFh result is returned, the host can repeat the XOR operation on a
subsequent copy of the unique ID data. If desired, the CHANGE READ COLUMN (05h-
E0h) command can be used to change the data output location. Use of the CHANGE
READ COLUMN ENHANCED (06h-E0h) command is prohibited.
Figure 32: READ UNIQUE ID (EDh) Operation
Cycle type
DQ[7:0]
R/B#
tWB tRtRR
Command Address DOUT
EDh 00h U00U10
DOUT DOUT
… U01
DOUT DOUT
U11…
DOUT
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Configuration Operations
The SET FEATURES (EFh) and GET FEATURES (EEh) commands are used to modify the
target's default power-on behavior. These commands use a one-byte feature address to
determine which subfeature parameters will be read or modified. Each feature address
(in the 00h to FFh range) is defined in Table 9. The SET FEATURES (EFh) command
writes subfeature parameters (P1-P4) to the specified feature address. The GET FEA-
TURES command reads the subfeature parameters (P1-P4) at the specified feature ad-
dress.
Unless otherwise specifed, the values of the feature addresses do not change when RE-
SET (FFh, FCh) is issued by the host.
Table 9: Feature Address Definitions
Feature Address Definition
00h Reserved
01h Timing mode
02h–0Fh Reserved
10h Programmable output drive strength
11h–7Fh Reserved
80h Programmable output drive strength
81h Programmable RB# pull-down strength
82h–8Fh Reserved
90h Array operation mode
91h–FFh Reserved
SET FEATURES (EFh)
The SET FEATURES (EFh) command writes the subfeature parameters (P1-P4) to the
specified feature address to enable or disable target-specific features. This command is
accepted by the target only when all die (LUNs) on the target are idle.
Writing EFh to the command register puts the target in the set features mode. The target
stays in this mode until another command is issued.
The EFh command is followed by a valid feature address as specified in Table 9. The
host waits for tADL before the subfeature parameters are input. When the asynchronous
interface is active, one subfeature parameter is latched per rising edge of WE#. When
the synchronous interface is active, one subfeature parameter is latched per rising edge
of DQS. The data on the falling edge of DQS should be identical to the subfeature pa-
rameter input on the previous rising edge of DQS. The device is not required to wait for
the repeated data byte before beginning internal actions.
After all four subfeature parameters are input, the target goes busy for tFEAT. The READ
STATUS (70h) command can be used to monitor for command completion.
Feature address 01h (timing mode) operation is unique. If SET FEATURES is used to
modify the interface type, the target will be busy for tITC. See Activating Interfaces
(page 38) for details.
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Figure 33: SET FEATURES (EFh) Operation
Cycle type
DQ[7:0]
R/B#
tADL
Command Address
EFh FA
DIN DIN DIN DIN
P1 P2 P3 P4
tWB tFEAT
GET FEATURES (EEh)
The GET FEATURES (EEh) command reads the subfeature parameters (P1-P4) from the
specified feature address. This command is accepted by the target only when all die
(LUNs) on the target are idle.
Writing EEh to the command register puts the target in get features mode. The target
stays in this mode until another valid command is issued.
When the EEh command is followed by a feature address, the target goes busy for tFEAT.
If the READ STATUS (70h) command is used to monitor for command completion, the
READ MODE (00h) command must be used to re-enable data output mode. During and
prior to data output, use of the READ STATUS ENHANCED (78h) command is prohibi-
ted.
After tFEAT completes, the host enables data output mode to read the subfeature pa-
rameters. When the asynchronous interface is active, one data byte is output per RE#
toggle. When the synchronous interface is active, one subfeature parameter is output
per DQS toggle on rising or falling edge of DQS.
Figure 34: GET FEATURES (EEh) Operation
Cycle type
DQ[7:0]
R/B#
tWB tFEAT tRR
Command Address DOUT
EEh FA P1 P2
DOUT DOUT
P3 P4
DOUT
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Table 10: Feature Address 01h: Timing Mode
Subfeature
Parameter Options DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Value Notes
P1
Timing mode Mode 0 (default) 0 0 0 0 x0h 1, 2
Mode 1 0 0 0 1 x1h
Mode 2 0 0 1 0 x2h
Mode 3 0 0 1 1 x3h
Mode 4 0 1 0 0 x4h
Mode 5 0 1 0 1 x5h
Data interface Asynchronous
(default)
0 0 0xh 1
Synchronous DDR 0 1 1xh
Reserved 1 x 2xh
Program clear Program com-
mand clears all
cache registers on
a target (default)
0 0b
Program com-
mand clears only
addressed LUN
cache register on a
target
1 1b
Reserved 0 0b
P2
Reserved 0 0 0 0 0 0 0 0 00h
P3
Reserved 0 0 0 0 0 0 0 0 00h
P4
Reserved 0 0 0 0 0 0 0 0 00h
Notes: 1. Asynchronous timing mode 0 is the default, power-on value.
2. If the synchronous interface is active, a RESET (FFh) command will change the timing
mode and data interface bits of feature address 01h to their default values. If the asyn-
chronous interface is active, a RESET (FFh) command will not change the values of the
timing mode or data interface bits to their default valued.
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Table 11: Feature Addresses 10h and 80h: Programmable Output Drive Strength
Subfeature Pa-
rameter Options DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Value Notes
P1
Output drive
strength
Overdrive 2 0 0 00h 1
Overdrive 1 0 1 01h
Nominal (de-
fault)
1 0 02h
Underdrive 1 1 03h
Reserved 0 0 0 0 0 0 00h
P2
Reserved 0 0 0 0 0 0 0 0 00h
P3
Reserved 0 0 0 0 0 0 0 0 00h
P4
Reserved 0 0 0 0 0 0 0 0 00h
Note: 1. See Output Drive Impedance section for details.
Table 12: Feature Addresses 81h: Programmable R/B# Pull-Down Strength
Subfeature Pa-
rameter Options DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Value Notes
P1
R/B# pull-down
strength
Full (default) 0 0 00h 1
Three-quarter 0 1 01h
One-half 1 0 02h
One-quarter 1 1 03h
Reserved 0 0 0 0 0 0 00h
P2
Reserved 0 0 0 0 0 0 0 0 00h
P3
Reserved 0 0 0 0 0 0 0 0 00h
P4
Reserved 0 0 0 0 0 0 0 0 00h
Note: 1. This feature address is used to change the default R/B# pull-down strength. Its strength
should be selected based on the expected loading of R/B#. Full strength is the default,
power-on value.
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Table 13: Feature Addresses 90h: Array Operation Mode
Subfeature Pa-
rameter Options DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 Value Notes
P1
Array Operation
Mode
Normal (de-
fault)
0 00h
OTP Block 1 01h 1
Reserved 0 0 0 0 0 0 0 00h
P2
Reserved 0 0 0 0 0 0 0 0 00h
P3
Reserved 0 0 0 0 0 0 0 0 00h
P4
Reserved 0 0 0 0 0 0 0 0 00h
Notes: 1. See One-Time Programmable (OTP) Operations for details.
2. A RESET (FFh) command will cause the bits of the array operation mode to change to
their default values.
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Status Operations
Each die (LUN) provides its status independently of other die (LUNs) on the same target
through its 8-bit status register.
After the READ STATUS (70h) or READ STATUS ENHANCED (78h) command is issued,
status register output is enabled. The contents of the status register are returned on
DQ[7:0] for each data output request.
When the asynchronous interface is active and status register output is enabled,
changes in the status register are seen on DQ[7:0] as long as CE# and RE# are LOW; it is
not necessary to toggle RE# to see the status register update.
When the synchronous interface is active and status register output is enabled, changes
in the status register are seen on DQ[7:0] as long as CE# and W/R# are LOW and ALE
and CLE are HIGH. DQS also toggles while ALE and CLE are HIGH.
While monitoring the status register to determine when a data transfer from the Flash
array to the data register (tR) is complete, the host must issue the READ MODE (00h)
command to disable the status register and enable data output (see READ MODE (00h)
(page 71)).
The READ STATUS (70h) command returns the status of the most recently selected die
(LUN). To prevent data contention during or following an interleaved die (multi-LUN)
operation, the host must enable only one die (LUN) for status output by using the READ
STATUS ENHANCED (78h) command (see Interleaved Die (Multi-LUN) Operations
(page 96)).
Table 14: Status Register Definition
SR Bit Definition
Independent
per Plane1Description
7 WP# – Write Protect:
0 = Protected
1 = Not protected
In the normal array mode, this bit indicates the value of the WP# signal. In
OTP mode this bit is set to 0 if a PROGRAM OTP PAGE operation is attemp-
ted and the OTP area is protected.
6 RDY – Ready/Busy I/O:
0 = Busy
1 = Ready
This bit indicates that the selected die (LUN) is not available to accept new
commands, address, or data I/O cycles with the exception of RESET (FFh),
SYNCHRONOUS RESET (FCh), READ STATUS (70h), and READ STATUS EN-
HANCED (78h). This bit applies only to the selected die (LUN).
5 ARDY – Ready/Busy Array:
0 = Busy
1 = Ready
This bit goes LOW (busy) when an array operation is occurring on any
plane of the selected die (LUN). It goes HIGH when all array operations on
the selected die (LUN) finish. This bit applies only to the selected die (LUN).
4 – – Reserved (0)
3 – – Reserved (0)
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Table 14: Status Register Definition (Continued)
SR Bit Definition
Independent
per Plane1Description
2 – – Reserved (0)
1 FAILC Yes Pass/Fail (N–1):
0 = Pass
1 = Fail
This bit is set if the previous operation on the selected die (LUN) failed. This
bit is valid only when RDY (SR bit 6) is 1. It applies to PROGRAM-, and
COPYBACK PROGRAM-series operations (80h-10h, 80h-15h, 85h-10h). This
bit is not valid following an ERASE-series or READ-series operation.
0 FAIL Yes Pass/Fail (N):
0 = Pass
1 = Fail
This bit is set if the most recently finished operation on the selected die
(LUN) failed. This bit is valid only when ARDY (SR bit 5) is 1. It applies to
PROGRAM-, ERASE-, and COPYBACK PROGRAM-series operations (80h-10h,
80h-15h, 60h-D0h, 85h-10h). This bit is not valid following a READ-series
operation.
Note: 1. After a multi-plane operation begins, the FAILC and FAIL bits are ORed together for the
active planes when the READ STATUS (70h) command is issued. After the READ STATUS
ENHANCED (78h) command is issued, the FAILC and FAIL bits reflect the status of the
plane selected.
READ STATUS (70h)
The READ STATUS (70h) command returns the status of the last-selected die (LUN) on
a target. This command is accepted by the last-selected die (LUN) even when it is busy
(RDY = 0).
If there is only one die (LUN) per target, the READ STATUS (70h) command can be used
to return status following any NAND command.
In devices that have more than one die (LUN) per target, during and following inter-
leaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command
must be used to select the die (LUN) that should report status. In this situation, using
the READ STATUS (70h) command will result in bus contention, as two or more die
(LUNs) could respond until the next operation is issued. The READ STATUS (70h) com-
mand can be used following all single die (LUN) operations.
If following a multi-plane operation, regardless of the number of LUNs per target, the
READ STATUS (70h) command indicates an error occurred (FAIL = 1), use the READ
STATUS ENHANCED (78h) command—once for each plane—to determine which plane
operation failed.
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Figure 35: READ STATUS (70h) Operation
Cycle type
DQ[7:0]
tWHR
Command DOUT
70h SR
READ STATUS ENHANCED (78h)
The READ STATUS ENHANCED (78h) command returns the status of the addressed die
(LUN) on a target even when it is busy (RDY = 0). This command is accepted by all die
(LUNs), even when they are BUSY (RDY = 0).
Writing 78h to the command register, followed by three row address cycles containing
the page, block, and LUN addresses, puts the selected die (LUN) into read status mode.
The selected die (LUN) stays in this mode until another valid command is issued. Die
(LUNs) that are not addressed are deselected to avoid bus contention.
The selected LUN's status is returned when the host requests data output. The RDY and
ARDY bits of the status register are shared for all of the planes of the selected die (LUN).
The FAILC and FAIL bits are specific to the plane specified in the row address.
The READ STATUS ENHANCED (78h) command also enables the selected die (LUN) for
data output. To begin data output following a READ-series operation after the selected
die (LUN) is ready (RDY = 1), issue the READ MODE (00h) command, then begin data
output. If the host needs to change the cache register that will output data, use the
CHANGE READ COLUMN ENHANCED (06h-E0h) command after the die (LUN) is
ready (see CHANGE READ COLUMN ENHANCED (06h-E0h)).
Use of the READ STATUS ENHANCED (78h) command is prohibited during the power-
on RESET (FFh) command and when OTP mode is enabled. It is also prohibited follow-
ing some of the other reset, identification, and configuration operations. See individual
operations for specific details.
Figure 36: READ STATUS ENHANCED (78h) Operation
Cycle type
DQx
tWHR
Command Address Address Address
78h R1 R2 R3
Dout
SR
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Column Address Operations
The column address operations affect how data is input to and output from the cache
registers within the selected die (LUNs). These features provide host flexibility for man-
aging data, especially when the host internal buffer is smaller than the number of data
bytes or words in the cache register.
When the asynchronous interface is active, column address operations can address any
byte in the selected cache register.
When the synchronous interface is active, column address operations are aligned to
word boundaries (CA0 is forced to 0), because as data is transferred on DQ[7:0] in two-
byte units.
CHANGE READ COLUMN (05h-E0h)
The CHANGE READ COLUMN (05h-E0h) command changes the column address of the
selected cache register and enables data output from the last selected die (LUN). This
command is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It
is also accepted by the selected die (LUN) during CACHE READ operations
(RDY = 1; ARDY = 0).
Writing 05h to the command register, followed by two column address cycles containing
the column address, followed by the E0h command, puts the selected die (LUN) into
data output mode. After the E0h command cycle is issued, the host must wait at least
tCCS before requesting data output. The selected die (LUN) stays in data output mode
until another valid command is issued.
In devices with more than one die (LUN) per target, during and following interleaved
die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be
issued prior to issuing the CHANGE READ COLUMN (05h-E0h). In this situation, using
the CHANGE READ COLUMN (05h-E0h) command without the READ STATUS EN-
HANCED (78h) command will result in bus contention, as two or more die (LUNs)
could output data.
Figure 37: CHANGE READ COLUMN (05h-E0h) Operation
Cycle type
DQ[7:0]
SR[6]
Command Address Address
05h
Command
E0hC1 C2
tCCS
tRHW
DOUT
Dk
DOUT
Dk + 1
DOUT
Dk + 2
DOUT
Dn
DOUT
Dn + 1
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CHANGE READ COLUMN ENHANCED (06h-E0h)
The CHANGE READ COLUMN ENHANCED (06h-E0h) command enables data output
on the addressed die’s (LUN’s) cache register at the specified column address. This
command is accepted by a die (LUN) when it is ready (RDY = 1; ARDY = 1).
Writing 06h to the command register, followed by two column address cycles and three
row address cycles, followed by E0h, enables data output mode on the address LUN’s
cache register at the specified column address. After the E0h command cycle is issued,
the host must wait at least tCCS before requesting data output. The selected die (LUN)
stays in data output mode until another valid command is issued.
Following a multi-plane read page operation, the CHANGE READ COLUMN EN-
HANCED (06h-E0h) command is used to select the cache register to be enabled for data
output. After data output is complete on the selected plane, the command can be is-
sued again to begin data output on another plane.
In devices with more than one die (LUN) per target, after all of the die (LUNs) on the
target are ready (RDY = 1), the CHANGE READ COLUMN ENHANCED (06h-E0h) com-
mand can be used following an interleaved die (multi-LUN) read operation. Die (LUNs)
that are not addressed are deselected to avoid bus contention.
In devices with more than one die (LUN) per target, during interleaved die (multi-LUN)
operations where more than one or more die (LUNs) are busy (RDY = 1; ARDY = 0 or
RDY = 0; ARDY = 0), the READ STATUS ENHANCED (78h) command must be issued to
the die (LUN) to be selected prior to issuing the CHANGE READ COLUMN ENHANCED
(06h-E0h). In this situation, using the CHANGE READ COLUMN ENHANCED (06h-E0h)
command without the READ STATUS ENHANCED (78h) command will result in bus
contention, as two or more die (LUNs) could output data.
If there is a need to update the column address without selecting a new cache register
or LUN, the CHANGE READ COLUMN (05h-E0h) command can be used instead.
Figure 38: CHANGE READ COLUMN ENHANCED (06h-E0h) Operation
Cycle
type
DQ[7:0]
Command Address Address
06h
Command
E0hC1 C2
Address Address
R1 R2
Address
R3
tCCS
tRHW
Dout
Dk
Dout
Dk + 1
Dout
Dk + 2
Dout
Dn
Dout
Dn + 1
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CHANGE WRITE COLUMN (85h)
The CHANGE WRITE COLUMN (85h) command changes the column address of the se-
lected cache register and enables data input on the last-selected die (LUN). This com-
mand is accepted by the selected die (LUN) when it is ready (RDY = 1; ARDY = 1). It is
also accepted by the selected die (LUN) during cache program operations
(RDY = 1; ARDY = 0).
Writing 85h to the command register, followed by two column address cycles containing
the column address, puts the selected die (LUN) into data input mode. After the second
address cycle is issued, the host must wait at least tCCS before inputting data. The selec-
ted die (LUN) stays in data input mode until another valid command is issued. Though
data input mode is enabled, data input from the host is optional. Data input begins at
the column address specified.
The CHANGE WRITE COLUMN (85h) command is allowed after the required address
cycles are specified, but prior to the final command cycle (10h, 11h, 15h) of the follow-
ing commands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM
PAGE MULTI-PLANE (80h-11h), PROGRAM PAGE CACHE (80h-15h), COPYBACK PRO-
GRAM (85h-10h), and COPYBACK PROGRAM MULTI-PLANE (85h-11h).
In devices that have more than one die (LUN) per target, the CHANGE WRITE COLUMN
(85h) command can be used with other commands that support interleaved die (multi-
LUN) operations.
Figure 39: CHANGE WRITE COLUMN (85h) Operation
Cycle type
DQ[7:0]
RDY
Command Address Address
85h C1 C2
tCCS
DIN
Dk
DIN
Dk + 1
DIN
Dk + 2
DIN
Dn
DIN
Dn + 1
As defined for PAGE
(CACHE) PROGRAM
As defined for PAGE
(CACHE) PROGRAM
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CHANGE ROW ADDRESS (85h)
The CHANGE ROW ADDRESS (85h) command changes the row address (block and
page) where the cache register contents will be programmed in the NAND Flash array. It
also changes the column address of the selected cache register and enables data input
on the specified die (LUN). This command is accepted by the selected die (LUN) when
it is ready (RDY = 1; ARDY = 1). It is also accepted by the selected die (LUN) during cache
programming operations (RDY = 1; ARDY = 0).
Write 85h to the command register. Then write two column address cycles and three
row address cycles. This updates the page and block destination of the selected plane
for the addressed LUN and puts the cache register into data input mode. After the fifth
address cycle is issued the host must wait at least tCCS before inputting data. The selec-
ted LUN stays in data input mode until another valid command is issued. Though data
input mode is enabled, data input from the host is optional. Data input begins at the
column address specified.
The CHANGE ROW ADDRESS (85h) command is allowed after the required address cy-
cles are specified, but prior to the final command cycle (10h, 11h, 15h) of the following
commands while data input is permitted: PROGRAM PAGE (80h-10h), PROGRAM PAGE
MULTI-PLANE (80h-11h), PROGRAM PAGE CACHE (80h-15h), COPYBACK PROGRAM
(85h-10h), and COPYBACK PROGRAM MULTI-PLANE (85h-11h). When used with these
commands, the LUN address and plane select bits are required to be identical to the
LUN address and plane select bits originally specified.
The CHANGE ROW ADDRESS (85h) command enables the host to modify the original
page and block address for the data in the cache register to a new page and block ad-
dress.
In devices that have more than one die (LUN) per target, the CHANGE ROW ADDRESS
(85h) command can be used with other commands that support interleaved die (multi-
LUN) operations.
The CHANGE ROW ADDRESS (85h) command can be used with the CHANGE READ
COLUMN (05h-E0h) or CHANGE READ COLUMN ENHANCED (06h-E0h) commands to
read and modify cache register contents in small sections prior to programming cache
register contents to the NAND Flash array. This capability can reduce the amount of
buffer memory used in the host controller.
To modify the cache register contents in small sections, first issue a PAGE READ
(00h-30h) or COPYBACK READ (00h-35h) operation. When data output is enabled, the
host can output a portion of the cache register contents. To modify the cache register
contents, issue the 85h command, the column and row addresses, and input the new
data. The host can re-enable data output by issuing the 11h command, waiting tDBSY,
and then issuing the CHANGE READ COLUMN (05h-E0h) or CHANGE READ COLUMN
ENHANCED (06h-E0h) command. It is possible toggle between data output and data
input multiple times. After the final CHANGE ROW ADDRESS (85h) operation is com-
plete, issue the 10h command to program the cache register to the NAND Flash array.
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Figure 40: CHANGE ROW ADDRESS (85h) Operation
Cycle type
DQ[7:0]
RDY
Command Address Address Address Address Address
85h C1 C2
tCCS
DIN
Dk
DIN
Dk + 1
DIN
Dk + 2
DIN
Dn
DIN
Dn + 1
As defined for PAGE
(CACHE) PROGRAM
As defined for PAGE
(CACHE) PROGRAM
R1 R2 R3
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Read Operations
Read operations are used to copy data from the NAND Flash array of one or more of the
planes to their respective cache registers and to enable data output from the cache reg-
isters to the host through the DQ bus.
Read Operations
The READ PAGE (00h-30h) command, when issued by itself, reads one page from the
NAND Flash array to its cache register and enables data output for that cache register.
During data output the following commands can be used to read and modify the data in
the cache registers: CHANGE READ COLUMN (05h-E0h) and CHANGE ROW ADDRESS
(85h).
Read Cache Operations
To increase data throughput, the READ PAGE CACHE-series (31h, 00h-31h) commands
can be used to output data from the cache register while concurrently copying a page
from the NAND Flash array to the data register.
To begin a read page cache sequence, begin by reading a page from the NAND Flash ar-
ray to its corresponding cache register using the READ PAGE (00h-30h) command.
R/B# goes LOW during tR and the selected die (LUN) is busy (RDY = 0, ARDY = 0). After
tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these commands:
• READ PAGE CACHE SEQUENTIAL (31h)—copies the next sequential page from the
NAND Flash array to the data register
• READ PAGE CACHE RANDOM (00h-31h)—copies the page specified in this command
from the NAND Flash array (any plane) to its corresponding data register
After the READ PAGE CACHE-series (31h, 00h-31h) command has been issued, R/B#
goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while
the next page begins copying data from the array to the data register. After tRCBSY,
R/B# goes HIGH and the die’s (LUN’s) status register bits indicate the device is busy
with a cache operation (RDY = 1, ARDY = 0). The cache register becomes available and
the page requested in the READ PAGE CACHE operation is transferred to the data regis-
ter. At this point, data can be output from the cache register, beginning at column ad-
dress 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the
column address of the data output by the die (LUN).
After outputting the desired number of bytes from the cache register, either an addi-
tional READ PAGE CACHE-series (31h, 00h-31h) operation can be started or the READ
PAGE CACHE LAST (3Fh) command can be issued.
If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target,
and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data register is copied
into the cache register. After tRCBSY, R/B# goes HIGH and RDY = 1 and
ARDY = 1, indicating that the cache register is available and that the die (LUN) is ready.
Data can then be output from the cache register, beginning at column address 0. The
CHANGE READ COLUMN (05h-E0h) command can be used to change the column ad-
dress of the data being output.
For READ PAGE CACHE-series (31h, 00h-31h, 3Fh), during the die (LUN) busy time,
tRCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations
(70h, 78h) and RESET (FFh, FCh). When RDY = 1 and ARDY = 0, the only valid com-
mands during READ PAGE CACHE-series (31h, 00h-31h) operations are status opera-
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tions (70h, 78h), READ MODE (00h), READ PAGE CACHE-series (31h, 00h-31h),
CHANGE READ COLUMN (05h-E0h), and RESET (FFh, FCh).
Multi-Plane Read Operations
Multi-plane read page operations improve data throughput by copying data from more
than one plane simultaneously to the specified cache registers. This is done by pre-
pending one or more READ PAGE MULTI-PLANE (00h-32h) commands in front of the
READ PAGE (00h-30h) command.
When the die (LUN) is ready, the CHANGE READ COLUMN ENHANCED (06h-E0h)
command determines which plane outputs data. During data output, the following
commands can be used to read and modify the data in the cache registers: CHANGE
READ COLUMN (05h-E0h) and CHANGE ROW ADDRESS (85h). See Multi-Plane Opera-
tions for details.
Multi-Plane Read Cache Operations
Multi-plane read cache operations can be used to output data from more than one
cache register while concurrently copying one or more pages from the NAND Flash ar-
ray to the data register. This is done by prepending READ PAGE MULTI-PLANE
(00h-32h) commands in front of the PAGE READ CACHE RANDOM (00h-31h) com-
mand.
To begin a multi-plane read page cache sequence, begin by issuing a MULTI-PLANE
READ PAGE operation using the READ PAGE MULTI-PLANE (00h-32h) and READ PAGE
(00h-30h) commands. R/B# goes LOW during tR and the selected die (LUN) is busy
(RDY = 0, ARDY = 0). After tR (R/B# is HIGH and RDY = 1, ARDY = 1), issue either of these
commands:
• READ PAGE CACHE SEQUENTIAL (31h)—copies the next sequential page from the
previously addressed planes from the NAND Flash array to the data registers.
• READ PAGE MULTI-PLANE (00h-32h) commands, if desired, followed by the READ
PAGE CACHE RANDOM (00h-31h) command—copies the pages specified from the
NAND Flash array to the corresponding data registers.
After the READ PAGE CACHE-series (31h, 00h-31h) command has been issued, R/B#
goes LOW on the target, and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while
the next pages begin copying data from the array to the data registers. After tRCBSY,
R/B# goes HIGH and the LUN’s status register bits indicate the device is busy with a
cache operation (RDY = 1, ARDY = 0). The cache registers become available and the pa-
ges requested in the READ PAGE CACHE operation are transferred to the data registers.
Issue the CHANGE READ COLUMN ENHANCED (06h-E0h) command to determine
which cache register will output data. After data is output, the CHANGE READ COL-
UMN ENHANCED (06h-E0h) command can be used to output data from other cache
registers. After a cache register has been selected, the CHANGE READ COLUMN (05h-
E0h) command can be used to change the column address of the data output.
After outputting data from the cache registers, either an additional MULTI-PLANE
READ CACHE-series (31h, 00h-31h) operation can be started or the READ PAGE CACHE
LAST (3Fh) command can be issued.
If the READ PAGE CACHE LAST (3Fh) command is issued, R/B# goes LOW on the target,
and RDY = 0 and ARDY = 0 on the die (LUN) for tRCBSY while the data registers are cop-
ied into the cache registers. After tRCBSY, R/B# goes HIGH and RDY = 1 and ARDY = 1,
indicating that the cache registers are available and that the die (LUN) is ready. Issue the
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CHANGE READ COLUMN ENHANCED (06h-E0h) command to determine which cache
register will output data. After data is output, the CHANGE READ COLUMN EN-
HANCED (06h-E0h) command can be used to output data from other cache registers.
After a cache register has been selected, the CHANGE READ COLUMN (05h-E0h) com-
mand can be used to change the column address of the data output.
For READ PAGE CACHE-series (31h, 00h-31h, 3Fh), during the die (LUN) busy time,
tRCBSY, when RDY = 0 and ARDY = 0, the only valid commands are status operations
(70h, 78h) and RESET (FFh, FCh). When RDY = 1 and ARDY = 0, the only valid com-
mands during READ PAGE CACHE-series (31h, 00h-31h) operations are status opera-
tions (70h, 78h), READ MODE (00h), multi-plane read cache-series (31h, 00h-32h,
00h-31h), CHANGE READ COLUMN (05h-E0h, 06h-E0h), and RESET (FFh, FCh).
See Multi-Plane Operations for additional multi-plane addressing requirements.
READ MODE (00h)
The READ MODE (00h) command disables status output and enables data output for
the last-selected die (LUN) and cache register after a READ operation (00h-30h,
00h-35h) has been monitored with a status operation (70h, 78h). This command is ac-
cepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the
die (LUN) during READ PAGE CACHE (31h, 3Fh, 00h-31h) operations
(RDY = 1 and ARDY = 0).
In devices that have more than one die (LUN) per target, during and following inter-
leaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command
must be used to select only one die (LUN) prior to issuing the READ MODE (00h) com-
mand. This prevents bus contention.
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READ PAGE (00h-30h)
The READ PAGE (00h–30h) command copies a page from the NAND Flash array to its
respective cache register and enables data output. This command is accepted by the die
(LUN) when it is ready (RDY = 1, ARDY = 1).
To read a page from the NAND Flash array, write the 00h command to the command
register, the write five address cycles to the address registers, and conclude with the 30h
command. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tR as data is
transferred.
To determine the progress of the data transfer, the host can monitor the target's R/B#
signal or, alternatively, the status operations (70h, 78h) can be used. If the status opera-
tions are used to monitor the LUN's status, when the die (LUN) is ready
(RDY = 1, ARDY = 1), the host disables status output and enables data output by issuing
the READ MODE (00h) command. When the host requests data output, output begins
at the column address specified.
During data output the CHANGE READ COLUMN (05h-E0h) command can be issued.
In devices that have more than one die (LUN) per target, during and following inter-
leaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command
must be used to select only one die (LUN) prior to the issue of the READ MODE (00h)
command. This prevents bus contention.
The READ PAGE (00h-30h) command is used as the final command of a multi-plane
read operation. It is preceded by one or more READ PAGE MULTI-PLANE (00h-32h)
commands. Data is transferred from the NAND Flash array for all of the addressed
planes to their respective cache registers. When the die (LUN) is ready
(RDY = 1, ARDY = 1), data output is enabled for the cache register linked to the plane
addressed in the READ PAGE (00h-30h) command. When the host requests data output,
output begins at the column address last specified in the READ PAGE (00h-30h) com-
mand. The CHANGE READ COLUMN ENHANCED (06h-E0h) command is used to ena-
ble data output in the other cache registers. See Multi-Plane Operations for additional
multi-plane addressing requirements.
Figure 41: READ PAGE (00h-30h) Operation
Cycle type
DQ[7:0]
RDY
Command Address Address Address Address Address Command
tWB tRtRR
00h C1 C2 R1 R2 R3 30h
DOUT
Dn
DOUT
Dn+1
DOUT
Dn+2
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READ PAGE CACHE SEQUENTIAL (31h)
The READ PAGE CACHE SEQUENTIAL (31h) command reads the next sequential page
within a block into the data register while the previous page is output from the cache
register. This command is accepted by the die (LUN) when it is ready
(RDY = 1, ARDY = 1). It is also accepted by the die (LUN) during READ PAGE CACHE
(31h, 00h-31h) operations (RDY = 1 and ARDY = 0).
To issue this command, write 31h to the command register. After this command is is-
sued, R/B# goes LOW and the die (LUN) is busy (RDY = 0, ARDY = 0) for tRCBSY. After
tRCBSY, R/B# goes HIGH and the die (LUN) is busy with a cache operation
(RDY = 1, ARDY = 0), indicating that the cache register is available and that the specified
page is copying from the NAND Flash array to the data register. At this point, data can
be output from the cache register beginning at column address 0. The CHANGE READ
COLUMN (05h-E0h) command can be used to change the column address of the data
being output from the cache register.
The READ PAGE CACHE SEQUENTIAL (31h) command can be used to cross block
boundaries. If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after the
last page of a block is read into the data register, the next page read will be the next logi-
cal block in the plane which the 31h command was issued. Do not issue the READ PAGE
CACHE SEQUENTIAL (31h) to cross die (LUN) boundaries. Instead, issue the READ
PAGE CACHE LAST (3Fh) command.
If the READ PAGE CACHE SEQUENTIAL (31h) command is issued after a MULTI-
PLANE READ PAGE operation (00h-32h, 00h-30h), the next sequential pages are read
into the data registers while the previous pages can be output from the cache registers.
After the die (LUN) is ready (RDY = 1, ARDY = 0), the CHANGE READ COLUMN EN-
HANCED (06h-E0h) command is used to select which cache register outputs data.
Figure 42: READ PAGE CACHE SEQUENTIAL (31h) Operation
Cycle type
DQ[7:0]
RDY
tWB tRCBSY tRR
Command DOUT DOUT DOUT Command DOUT
31h
tWB
Command
30h
tWB tRCBSY tRR
D0 … Dn 31h D0
Command Address x5
00h Page Address M
Page M Page M+1
tR
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READ PAGE CACHE RANDOM (00h-31h)
The READ PAGE CACHE RANDOM (00h-31h) command reads the specified block and
page into the data register while the previous page is output from the cache register.
This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is
also accepted by the die (LUN) during READ PAGE CACHE (31h, 00h-31h) operations
(RDY = 1 and ARDY = 0).
To issue this command, write 00h to the command register, then write five address cy-
cles to the address register, and conclude by writing 31h to the command register. The
column address in the address specified is ignored. The die (LUN) address must match
the same die (LUN) address as the previous READ PAGE (00h-30h) command or, if ap-
plicable, the previous READ PAGE CACHE RANDOM (00h-31h) command. There is no
restriction on the plane address.
After this command is issued, R/B# goes LOW and the die (LUN) is busy
(RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is busy
with a cache operation (RDY = 1, ARDY = 0), indicating that the cache register is availa-
ble and that the specified page is copying from the NAND Flash array to the data regis-
ter. At this point, data can be output from the cache register beginning at column ad-
dress 0. The CHANGE READ COLUMN (05h-E0h) command can be used to change the
column address of the data being output from the cache register.
In devices that have more than one die (LUN) per target, during and following inter-
leaved die (multi-LUN) operations the READ STATUS ENHANCED (78h) command fol-
lowed by the READ MODE (00h) command must be used to select only one die (LUN)
and prevent bus contention.
If a MULTI-PLANE CACHE RANDOM (00h-32h, 00h-31h) command is issued after a
MULTI-PLANE READ PAGE operation (00h-32h, 00h-30h), then the addressed pages are
read into the data registers while the previous pages can be output from the cache regis-
ters. After the die (LUN) is ready (RDY = 1, ARDY = 0), the CHANGE READ COLUMN EN-
HANCED (06h-E0h) command is used to select which cache register outputs data.
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Figure 43: READ PAGE CACHE RANDOM (00h-31h) Operation
Cycle type
DQ[7:0]
RDY
tWB tRCBSY tRR
Command DOUT DOUT DOUT
31h
tWB
Command
30h D0 … Dn
Command Address x5
00h
Command
00hPage Address M
Address x5
Page Address N
Command
00h
Page M
tR
1
Cycle type
DQ[7:0]
RDY
DOUT Command DOUT
tWB tRCBSY tRR
Dn 31h D0
Command
00h
Address x5
Page Address P
Page N
1
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READ PAGE CACHE LAST (3Fh)
The READ PAGE CACHE LAST (3Fh) command ends the read page cache sequence and
copies a page from the data register to the cache register. This command is accepted by
the die (LUN) when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN)
during READ PAGE CACHE (31h, 00h-31h) operations (RDY = 1 and ARDY = 0).
To issue the READ PAGE CACHE LAST (3Fh) command, write 3Fh to the command reg-
ister. After this command is issued, R/B# goes LOW and the die (LUN) is busy
(RDY = 0, ARDY = 0) for tRCBSY. After tRCBSY, R/B# goes HIGH and the die (LUN) is
ready (RDY = 1, ARDY = 1). At this point, data can be output from the cache register, be-
ginning at column address 0. The CHANGE READ COLUMN (05h-E0h) command can
be used to change the column address of the data being output from the cache register.
In devices that have more than one LUN per target, during and following interleaved die
(multi-LUN) operations the READ STATUS ENHANCED (78h) command followed by
the READ MODE (00h) command must be used to select only one die (LUN) and pre-
vent bus contention.
If the READ PAGE CACHE LAST (3Fh) command is issued after a MULTI-PLANE READ
PAGE CACHE operation (31h; 00h-32h, 00h-30h), the die (LUN) goes busy until the pa-
ges are copied from the data registers to the cache registers. After the die (LUN) is ready
(RDY = 1, ARDY = 1), the CHANGE READ COLUMN ENHANCED (06h-E0h) command is
used to select which cache register outputs data.
Figure 44: READ PAGE CACHE LAST (3Fh) Operation
Cycle type
DQ[7:0]
RDY
tWB tRCBSY tRR
Command DOUT DOUT DOUT Command DOUT DOUT DOUT
31h
tWB tRCBSY tRR
D0 D0 … Dn
As defined for
READ PAGE CACHE
(SEQUENTIAL OR RANDOM)
… Dn 3Fh
Page NPage Address N
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READ PAGE MULTI-PLANE (00h-32h)
The READ PAGE MULTI-PLANE (00h-32h) command queues a plane to transfer data
from the NAND flash array to its cache register. This command can be issued one or
more times. Each time a new plane address is specified, that plane is also queued for
data transfer. The READ PAGE (00h-30h) command is issued to select the final plane
and to begin the read operation for all previously queued planes. All queued planes will
transfer data from the NAND Flash array to their cache registers.
To issue the READ PAGE MULTI-PLANE (00h-32h) command, write 00h to the com-
mand register, then write five address cycles to the address register, and conclude by
writing 32h to the command register. The column address in the address specified is ig-
nored.
After this command is issued, R/B# goes LOW and the die (LUN) is busy
(RDY = 0, ARDY = 0) for tDBSY. After tDBSY, R/B# goes HIGH and the die (LUN) is ready
(RDY = 1, ARDY = 1). At this point, the die (LUN) and block are queued for data transfer
from the array to the cache register for the addressed plane. During tDBSY, the only val-
id commands are status operations (70h, 78h) and reset commands (FFh, FCh). Follow-
ing tDBSY, to continue the MULTI-PLANE READ operation, the only valid commands
are status operations (70h, 78h), READ PAGE MULTI-PLANE (00h-32h), READ PAGE
(00h-30h), and READ PAGE CACHE RANDOM (00h-31h).
Additional READ PAGE MULTI-PLANE (00h-32h) commands can be issued to queue ad-
ditional planes for data transfer.
If the READ PAGE (00h-30h) command is used as the final command of a MULTI-
PLANE READ operation, data is transferred from the NAND Flash array for all of the ad-
dressed planes to their respective cache registers. When the die (LUN) is ready
(RDY = 1, ARDY = 1), data output is enabled for the cache register linked to the last even
plane addressed. When the host requests data output, it begins at the column address
specified in the READ PAGE (00h-30h) command. To enable data output in the other
cache registers, use the CHANGE READ COLUMN ENHANCED (06h-E0h) command.
Additionally, the CHANGE READ COLUMN (05h-E0h) command can be used to change
the column address within the currently selected plane.
If the READ PAGE CACHE SEQUENTIAL (31h) is used as the final command of a MUL-
TI-PLANE READ CACHE operation, data is copied from the previously read operation
from each plane to each cache register and then data is transferred from the NAND
Flash array for all previously addressed planes to their respective data registers. When
the die (LUN) is ready (RDY = 1, ARDY = 0), data output is enabled. The CHANGE READ
COLUMN ENHANCED (06h-E0h) command is used to determine which cache register
outputs data first. To enable data output in the other cache registers, use the CHANGE
READ COLUMN ENHANCED (06h-E0h) command. Additionally, the CHANGE READ
COLUMN (05h-E0h) command can be used to change the column address within the
currently selected plane.
If the READ PAGE CACHE RANDOM (00h-31h) command is used as the final command
of a MULTI-PLANE READ CACHE operation, data is copied from the previously read op-
eration from the data register to the cache register and then data is transferred from the
NAND Flash array for all of the addressed planes to their respective data registers. When
the die (LUN) is ready (RDY = 1, ARDY = 0), data output is enabled. The CHANGE READ
COLUMN ENHANCED (06h-E0h) command is used to determine which cache register
outputs data first. To enable data output in the other cache registers, use the CHANGE
READ COLUMN ENHANCED (06h-E0h) command. Additionally, the CHANGE READ
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COLUMN (05h-E0h) command can be used to change the column address within the
currently selected plane.
See Multi-Plane Operations for additional multi-plane addressing requirements.
Figure 45: READ PAGE MULTI-PLANE (00h-32h) Operation
Cycle type
DQ[7:0]
RDY
Command Address Address Address Address Address Command
tWB tDBSY
00h C1 C2
Command Address Address
00h C1 ...
R1 R2 R3 32h
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Program Operations
Program operations are used to move data from the cache or data registers to the NAND
array of one or more planes. During a program operation the contents of the cache
and/or data registers are modified by the internal control logic.
Within a block, pages must be programmed sequentially from the least significant page
address to the most significant page address (i.e. 0, 1, 2, 3, …). Programming pages out
of order within a block is prohibited.
Program Operations
The PROGRAM PAGE (80h-10h) command, when not preceded by the PROGRAM PAGE
MULTI-PLANE (80h-11h) command, programs one page from the cache register to the
NAND Flash array. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host should
check the FAIL bit to verify that the operation has completed successfully.
Program Cache Operations
The PROGRAM PAGE CACHE (80h-15h) command can be used to improve program op-
eration system performance. When this command is issued, the die (LUN) goes busy
(RDY = 0, ARDY = 0) while the cache register contents are copied to the data register,
and the die (LUN) is busy with a program cache operation (RDY = 1, ARDY = 0). While
the contents of the data register are moved to the NAND Flash array, the cache register
is available for an additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE
(80h-10h) command.
For PROGRAM PAGE CACHE-series (80h-15h) operations, during the die (LUN) busy
times, tCBSY and tLPROG, when RDY = 0 and ARDY = 0, the only valid commands are
status operations (70h, 78h) and reset (FFh, FCh). When RDY = 1 and ARDY = 0, the only
valid commands during PROGRAM PAGE CACHE-series (80h-15h) operations are status
operations (70h, 78h), PROGRAM PAGE CACHE (80h-15h), PROGRAM PAGE (80h-10h),
CHANGE WRITE COLUMN (85h), CHANGE ROW ADDRESS (85h), and reset (FFh, FCh).
Multi-Plane Program Operations
The PROGRAM PAGE MULTI-PLANE (80h-11h) command can be used to improve pro-
gram operation system performance by enabling multiple pages to be moved from the
cache registers to different planes of the NAND Flash array. This is done by prepending
one or more PROGRAM PAGE MULTI-PLANE (80h-11h) commands in front of the PRO-
GRAM PAGE (80h-10h) command. See Multi-Plane Operations for details.
Multi-Plane Program Cache Operations
The PROGRAM PAGE MULTI-PLANE (80h-11h) command can be used to improve pro-
gram cache operation system performance by enabling multiple pages to be moved
from the cache registers to the data registers and, while the pages are being transferred
from the data registers to different planes of the NAND Flash array, free the cache regis-
ters to receive data input from the host. This is done by prepending one or more PRO-
GRAM PAGE MULTI-PLANE (80h-11h) commands in front of the PROGRAM PAGE
CACHE (80h-15h) command. See Multi-Plane Operations for details.
PROGRAM PAGE (80h-10h)
The PROGRAM PAGE (80h-10h) command enables the host to input data to a cache reg-
ister, and moves the data from the cache register to the specified block and page ad-
dress in the array of the selected die (LUN). This command is accepted by the die (LUN)
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when it is ready (RDY = 1, ARDY = 1). It is also accepted by the die (LUN) when it is busy
with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
To input a page to the cache register and move it to the NAND array at the block and
page address specified, write 80h to the command register. Unless this command has
been preceded by a PROGRAM PAGE MULTI-PLANE (80h-11h) command, issuing the
80h to the command register clears all of the cache registers' contents on the selected
target. Then write five address cycles containing the column address and row address.
Data input cycles follow. Serial data is input beginning at the column address specified.
At any time during the data input cycle the CHANGE WRITE COLUMN (85h) and
CHANGE ROW ADDRESS (85h) commands may be issued. When data input is com-
plete, write 10h to the command register. The selected LUN will go busy
(RDY = 0, ARDY = 0) for tPROG as data is transferred.
To determine the progress of the data transfer, the host can monitor the target's R/B#
signal or, alternatively, the status operations (70h, 78h) may be used. When the die
(LUN) is ready (RDY = 1, ARDY = 1), the host should check the status of the FAIL bit.
In devices that have more than one die (LUN) per target, during and following inter-
leaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command
must be used to select only one die (LUN) for status output. Use of the READ STATUS
(70h) command could cause more than one die (LUN) to respond, resulting in bus con-
tention.
The PROGRAM PAGE (80h-10h) command is used as the final command of a multi-
plane program operation. It is preceded by one or more PROGRAM PAGE MULTI-
PLANE (80h-11h) commands. Data is transferred from the cache registers for all of the
addressed planes to the NAND array. The host should check the status of the operation
by using the status operations (70h, 78h). See Multi-Plane Operations for multi-plane
addressing requirements.
Figure 46: PROGRAM PAGE (80h-10h) Operation
Cycle type
DQ[7:0]
RDY
tADL
Command Address Address Address Address Address
80h
Command
10h
Command
70hC1 C2 R1 R2 R3
DIN DIN DIN DIN
D0 D1 … Dn
DOUT
Status
tWB tPROG
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PROGRAM PAGE CACHE (80h-15h)
The PROGRAM PAGE CACHE (80h-15h) command enables the host to input data to a
cache register; copies the data from the cache register to the data register; then moves
the data register contents to the specified block and page address in the array of the se-
lected die (LUN). After the data is copied to the data register, the cache register is availa-
ble for additional PROGRAM PAGE CACHE (80h-15h) or PROGRAM PAGE (80h-10h)
commands. The PROGRAM PAGE CACHE (80h-15h) command is accepted by the die
(LUN) when it is ready (RDY =1, ARDY = 1). It is also accepted by the die (LUN) when
busy with a PROGRAM PAGE CACHE (80h-15h) operation (RDY = 1, ARDY = 0).
To input a page to the cache register to move it to the NAND array at the block and page
address specified, write 80h to the command register. Unless this command has been
preceded by a PROGRAM PAGE MULTI-PLANE (80h-11h) command, issuing the 80h to
the command register clears all of the cache registers' contents on the selected target.
Then write five address cycles containing the column address and row address. Data in-
put cycles follow. Serial data is input beginning at the column address specified. At any
time during the data input cycle the CHANGE WRITE COLUMN (85h) and CHANGE
ROW ADDRESS (85h) commands may be issued. When data input is complete, write
15h to the command register. The selected LUN will go busy
(RDY = 0, ARDY = 0) for tCBSY to allow the data register to become available from a pre-
vious program cache operation, to copy data from the cache register to the data register,
and then to begin moving the data register contents to the specified page and block ad-
dress.
To determine the progress of tCBSY, the host can monitor the target's R/B# signal or, al-
ternatively, the status operations (70h, 78h) can be used. When the LUN’s status shows
that it is busy with a PROGRAM CACHE operation (RDY = 1, ARDY = 0), the host should
check the status of the FAILC bit to see if a previous cache operation was successful.
If, after tCBSY, the host wants to wait for the program cache operation to complete,
without issuing the PROGRAM PAGE (80h-10h) command, the host should monitor AR-
DY until it is 1. The host should then check the status of the FAIL and FAILC bits.
In devices with more than one die (LUN) per target, during and following interleaved
die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command must be
used to select only one die (LUN) for status output. Use of the READ STATUS (70h) com-
mand could cause more than one die (LUN) to respond, resulting in bus contention.
The PROGRAM PAGE CACHE (80h-15h) command is used as the final command of a
multi-plane program cache operation. It is preceded by one or more PROGRAM PAGE
MULTI-PLANE (80h-11h) commands. Data for all of the addressed planes is transferred
from the cache registers to the corresponding data registers, then moved to the NAND
Flash array. The host should check the status of the operation by using the status opera-
tions (70h, 78h). See Multi-Plane Operations for multi-plane addressing requirements.
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Figure 47: PROGRAM PAGE CACHE (80h–15h) Operation (Start)
Cycle type
DQ[7:0]
RDY
tADL
Command Address Address Address Address Address
80h C1 C2 R1 R2 R3
Din Din Din Din Command
D0 D1 … Dn 15h
1
tWB tCBSY
Cycle type
DQ[7:0]
RDY
tADL
Command Address Address Address Address Address
80h C1 C2 R1 R2 R3
Din Din Din Din Command
D0 D1 … Dn 15h
1
tWB tCBSY
Figure 48: PROGRAM PAGE CACHE (80h–15h) Operation (End)
Cycle type
DQ[7:0]
RDY
tADL
Command Address Address Address Address Address
80h C1 C2 R1 R2 R3
Din Din Din Din Command
D0 D1 … Dn 15h
1
tWB tCBSY
Cycle type
RDY
tADL
Command Address
As defined for
PAGE CACHE PROGRAM
Address Address Address Address
80h C1 C2 R1 R2 R3
Din Din Din Din Command
D0 D1 … Dn 10h
1
tWB tLPROG
DQ[7:0]
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PROGRAM PAGE MULTI-PLANE (80h-11h)
The PROGRAM PAGE MULTI-PLANE (80h-11h) command enables the host to input da-
ta to the addressed plane's cache register and queue the cache register to ultimately be
moved to the NAND Flash array. This command can be issued one or more times. Each
time a new plane address is specified that plane is also queued for data transfer. To in-
put data for the final plane and to begin the program operation for all previously
queued planes, issue either the PROGRAM PAGE (80h-10h) command or the PROGRAM
PAGE CACHE (80h-15h) command. All of the queued planes will move the data to the
NAND Flash array. This command is accepted by the die (LUN) when it is ready
(RDY = 1).
To input a page to the cache register and queue it to be moved to the NAND Flash array
at the block and page address specified, write 80h to the command register. Unless this
command has been preceded by an 11h command, issuing the 80h to the command
register clears all of the cache registers' contents on the selected target. Write five ad-
dress cycles containing the column address and row address; data input cycles follow.
Serial data is input beginning at the column address specified. At any time during the
data input cycle, the CHANGE WRITE COLUMN (85h) and CHANGE ROW ADDRESS
(85h) commands can be issued. When data input is complete, write 11h to the com-
mand register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tDBSY.
To determine the progress of tDBSY, the host can monitor the target's R/B# signal or,
alternatively, the status operations (70h, 78h) can be used. When the LUN's status
shows that it is ready (RDY = 1), additional PROGRAM PAGE MULTI-PLANE (80h-11h)
commands can be issued to queue additional planes for data transfer. Alternatively, the
PROGRAM PAGE (80h-10h) or PROGRAM PAGE CACHE (80h-15h) commands can be is-
sued.
When the PROGRAM PAGE (80h-10h) command is used as the final command of a mul-
ti-plane program operation, data is transferred from the cache registers to the NAND
Flash array for all of the addressed planes during tPROG. When the die (LUN) is ready
(RDY = 1, ARDY = 1), the host should check the status of the FAIL bit for each of the
planes to verify that programming completed successfully.
When the PROGRAM PAGE CACHE (80h-15h) command is used as the final command
of a MULTI-PLANE PROGRAM CACHE operation, data is transferred from the cache
registers to the data registers after the previous array operations finish. The data is then
moved from the data registers to the NAND Flash array for all of the addressed planes.
This occurs during tCBSY. After tCBSY, the host should check the status of the FAILC bit
for each of the planes from the previous program cache operation, if any, to verify that
programming completed successfully.
For the PROGRAM PAGE MULTI-PLANE (80h-11h), PROGRAM PAGE (80h-10h), and
PROGRAM PAGE CACHE (80h-15h) commands, see Multi-Plane Operations for multi-
plane addressing requirements.
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Figure 49: PROGRAM PAGE MULTI-PLANE (80h–11h) Operation
Cycle type
DQ[7:0]
RDY
tADL
Command Address Address Address Address Address
80h C1
Command Address
80h ...
C2 R1 R2 R3
DIN DIN DIN Command
D0 … Dn 11h
tWB tDBSY
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Erase Operations
Erase operations are used to clear the contents of a block in the NAND Flash array to
prepare its pages for program operations.
Erase Operations
The ERASE BLOCK (60h-D0h) command, when not preceded by the ERASE BLOCK
MULTI-PLANE (60h-D1h) command, erases one block in the NAND Flash array. When
the die (LUN) is ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify
that this operation completed successfully.
MULTI-PLANE ERASE Operations
The ERASE BLOCK MULTI-PLANE (60h-D1h) command can be used to further system
performance of erase operations by allowing more than one block to be erased in the
NAND array. This is done by prepending one or more ERASE BLOCK MULTI-PLANE
(60h-D1h) commands in front of the ERASE BLOCK (60h-D0h) command. See Multi-
Plane Operations for details.
ERASE BLOCK (60h-D0h)
The ERASE BLOCK (60h-D0h) command erases the specified block in the NAND Flash
array. This command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1).
To erase a block, write 60h to the command register. Then write three address cycles
containing the row address; the page address is ignored. Conclude by writing D0h to the
command register. The selected die (LUN) will go busy (RDY = 0, ARDY = 0) for tBERS
while the block is erased.
To determine the progress of an ERASE operation, the host can monitor the target's
R/B# signal, or alternatively, the status operations (70h, 78h) can be used. When the die
(LUN) is ready (RDY = 1, ARDY = 1) the host should check the status of the FAIL bit.
In devices that have more than one die (LUN) per target, during and following inter-
leaved die (multi-LUN) operations, the READ STATUS ENHANCED (78h) command
must be used to select only one die (LUN) for status output. Use of the READ STATUS
(70h) command could cause more than one die (LUN) to respond, resulting in bus con-
tention.
The ERASE BLOCK (60h-D0h) command is used as the final command of a MULTI-
PLANE ERASE operation. It is preceded by one or more ERASE BLOCK MULTI-PLANE
(60h-D1h) commands. All of blocks in the addressed planes are erased. The host should
check the status of the operation by using the status operations (70h, 78h). See Multi-
Plane Operations for multi-plane addressing requirements.
Figure 50: ERASE BLOCK (60h-D0h) Operation
Cycle type
DQ[7:0]
SR[6]
Command Address Address Address Command
tWB tBERS
60h R1 R2 R3 D0h
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ERASE BLOCK MULTI-PLANE (60h-D1h)
The ERASE BLOCK MULTI-PLANE (60h-D1h) command queues a block in the specified
plane to be erased in the NAND Flash array. This command can be issued one or more
times. Each time a new plane address is specified, that plane is also queued for a block
to be erased. To specify the final block to be erased and to begin the ERASE operation
for all previously queued planes, issue the ERASE BLOCK (60h-D0h) command. This
command is accepted by the die (LUN) when it is ready (RDY = 1, ARDY = 1).
To queue a block to be erased, write 60h to the command register, then write three ad-
dress cycles containing the row address; the page address is ignored. Conclude by writ-
ing D1h to the command register. The selected die (LUN) will go busy (RDY = 0, ARDY =
0) for tDBSY.
To determine the progress of tDBSY, the host can monitor the target's R/B# signal, or
alternatively, the status operations (70h, 78h) can be used. When the LUN's status
shows that it is ready (RDY = 1, ARDY = 1), additional ERASE BLOCK MULTI-PLANE
(60h-D1h) commands can be issued to queue additional planes for erase. Alternatively,
the ERASE BLOCK (60h-D0h) command can be issued to erase all of the queued blocks.
For multi-plane addressing requirements for the ERASE BLOCK MULTI-PLANE (60h-
D1h) and ERASE BLOCK (60h-D0h) commands, see Multi-Plane Operations.
Figure 51: ERASE BLOCK MULTI-PLANE (60h–D1h) Operation
Cycle type
DQ[7:0]
RDY
Command Address Address Address
60h
Command
D1hR1
Command Address
60h ...
R2 R3
tWB tDBSY
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Copyback Operations
COPYBACK operations make it possible to transfer data within a plane from one page to
another using the cache register. This is particularly useful for block management and
wear leveling.
The COPYBACK operation is a two-step process consisting of a COPYBACK READ
(00h-35h) and a COPYBACK PROGRAM (85h-10h) command. To move data from one
page to another on the same plane, first issue the COPYBACK READ (00h-35h) com-
mand. When the die (LUN) is ready (RDY = 1, ARDY = 1), the host can transfer the data
to a new page by issuing the COPYBACK PROGRAM (85h-10h) command. When the die
(LUN) is again ready (RDY = 1, ARDY = 1), the host should check the FAIL bit to verify
that this operation completed successfully.
To prevent bit errors from accumulating over multiple COPYBACK operations, it is rec-
ommended that the host read the data out of the cache register after the COPYBACK
READ (00h-35h) completes prior to issuing the COPYBACK PROGRAM (85h-10h) com-
mand. The CHANGE READ COLUMN (05h-E0h) command can be used to change the
column address. The host should check the data for ECC errors and correct them. When
the COPYBACK PROGRAM (85h-10h) command is issued, any corrected data can be in-
put. The CHANGE ROW ADDRESS (85h) command can be used to change the column
address.
It is not possible to use the COPYBACK operation to move data from one plane to an-
other or from one die (LUN) to another. Instead, use a READ PAGE (00h-30h) or COPY-
BACK READ (00h-35h) command to read the data out of the NAND, and then use a
PROGRAM PAGE (80h-10h) command with data input to program the data to a new
plane or die (LUN).
Between the COPYBACK READ (00h-35h) and COPYBACK PROGRAM (85h-10h) com-
mands, the following commands are supported: status operations (70h, 78h), and col-
umn address operations (05h-E0h, 06h-E0h, 85h). Reset operations (FFh, FCh) can be
issued after COPYBACK READ (00h-35h), but the contents of the cache registers on the
target are not valid.
In devices which have more than one die (LUN) per target, once the COPYBACK READ
(00h-35h) is issued, interleaved die (multi-LUN) operations are prohibited until after
the COPYBACK PROGRAM (85h-10h) command is issued.
Multi-Plane Copyback Operations
Multi-plane copyback read operations improve read data throughput by copying data
simultaneously from more than one plane to the specified cache registers. This is done
by prepending one or more READ PAGE MULTI-PLANE (00h-32h) commands in front of
the COPYBACK READ (00h-35h) command.
The COPYBACK PROGRAM MULTI-PLANE (85h-11h) command can be used to further
system performance of COPYBACK PROGRAM operations by enabling movement of
multiple pages from the cache registers to different planes of the NAND Flash array.
This is done by prepending one or more COPYBACK PROGRAM (85h-11h) commands
in front of the COPYBACK PROGRAM (85h-10h) command. See Multi-Plane Operations
for details.
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COPYBACK READ (00h-35h)
The COPYBACK READ (00h-35h) command is functionally identical to the READ PAGE
(00h-30h) command, except that 35h is written to the command register instead of 30h.
See READ PAGE (00h-30h) (page 72) for further details.
Though it is not required, it is recommended that the host read the data out of the de-
vice to verify the data prior to issuing the COPYBACK PROGRAM (85h-10h) command
to prevent the propagation of data errors.
Figure 52: COPYBACK READ (00h-35h) Operation
Cycle type
DQ[7:0]
RDY
Command Address Address Address Address Address Command
tWB tRtRR
00h C1 C2 R1 R2 R3 35h
DOUT
Dn
DOUT
Dn+1
DOUT
Dn+2
Figure 53: COPYBACK READ (00h–35h) with CHANGE READ COLUMN (05h–E0h) Operation
Cycle type
DQ[7:0]
RDY
Command Address Address Address Address Address Command
tWB tRtRR
00h C1 C2 R1 R2 R3 35h
1
Cycle type
DQ[7:0]
RDY
Command Address Address Command
tCCS
05h C1 C2 E0h
D0
Dk
… Dj + n
Dk + 1 Dk + 2
1
DOUT
DOUT DOUT DOUT
DOUT DOUT
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COPYBACK PROGRAM (85h–10h)
The COPYBACK PROGRAM (85h-10h) command is functionally identical to the PRO-
GRAM PAGE (80h-10h) command, except that when 85h is written to the command reg-
ister, cache register contents are not cleared. See PROGRAM PAGE (80h-10h) for further
details.
Figure 54: COPYBACK PROGRAM (85h–10h) Operation
Cycle type
DQ[7:0]
RDY
Command Address Address Address Address Address Command
tWB tPROG
85h C1 C2 R1 R2 R3 10h
Figure 55: COPYBACK PROGRAM (85h-10h) with CHANGE WRITE COLUMN (85h) Operation
Cycle type
DQ[7:0]
RDY
Command Address Address Address Address Address
tWB tPROG
85h C1 C2 R1 R2 R3
1
Cycle type
DQ[7:0]
RDY
Command Address Address
tCCS
tCCS
85h
Command
10hC1 C2
DIN
Di
Dj
DIN
DIN
Di + 1
DIN
Dj + 1
DIN
Dj + 2
1
COPYBACK READ MULTI-PLANE (00h-32h)
The COPYBACK READ MULTI-PLANE (00h-32h) command is functionally identical to
the READ PAGE MULTI-PLANE (00h-32h) command, except that the 35h command is
written as the final command. The complete command sequence for the COPYBACK
READ PAGE MULTI-PLANE is 00h-32h-00h-35h. See READ PAGE MULTI-PLANE
(00h-32h) (page 77) for further details.
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COPYBACK PROGRAM MULTI-PLANE (85h-11h)
The COPYBACK PROGRAM MULTI-PLANE (85h-11h) command is functionally identi-
cal to the PROGRAM PAGE MULTI-PLANE (80h-11h) command, except that when 85h
is written to the command register, cache register contents are not cleared. See PRO-
GRAM PAGE MULTI-PLANE (80h-11h) for further details.
Figure 56: COPYBACK PROGRAM MULTI-PLANE (85h-11h) Operation
Cycle type
DQ[7:0]
RDY
tCCS
Command Address Address Address Address Address
85h C1
Command Address
85h ...
C2 R1 R2 R3
DIN DIN DIN Command
D0 … Dn 11h
tWB tDBSY
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One-Time Programmable (OTP) Operations
This Micron NAND Flash device offers a protected, one-time programmable NAND
Flash memory area. Each target has a an OTP area with a range of OTP pages (see Ta-
ble 15 (page 92)); the entire range is guaranteed to be good. Customers can use the
OTP area in any way they desire; typical uses include programming serial numbers or
other data for permanent storage.
The OTP area leaves the factory in an erased state (all bits are 1). Programming an OTP
page changes bits that are 1 to 0, but cannot change bits that are 0 to 1. The OTP area
cannot be erased, even if it is not protected. Protecting the OTP area prevents further
programming of the pages in the OTP area.
Enabling the OTP Operation Mode
The OTP area is accessible while the OTP operation mode is enabled. To enable OTP op-
eration mode, issue the SET FEATURES (EFh) command to feature address 90h and
write 01h to P1, followed by three cycles of 00h to P2 through P4.
When the target is in OTP operation mode, all subsequent PAGE READ (00h-30h) and
PROGRAM PAGE (80h-10h) commands are applied to the OTP area.
ERASE commands are not valid while the target is in OTP operation mode.
Programming OTP Pages
Each page in the OTP area is programming using the PROGRAM OTP PAGE (80h-10h)
command. Each page can be programmed more than once, in sections, up to the maxi-
mum number allowed (see NOP in Table 15 (page 92)). The pages in the OTP area
must be programmed in ascending order.
If the host issues a PAGE PROGRAM (80h-10h) command to an address beyond the
maximum page-address range, the target will be busy for tOBSY and the WP# status reg-
ister bit will be 0, meaning that the page is write-protected.
Protecting the OTP Area
To protect the OTP area, issue the OTP PROTECT (80h-10h) command to the OTP Pro-
tect Page. When the OTP area is protected it cannot be programmed further. It is not
possible to unprotect the OTP area after it has been protected.
Reading OTP Pages
To read pages in the OTP area, whether the OTP area is protected or not, issue the PAGE
READ (00h-30h) command.
If the host issues the PAGE READ (00h-30h) command to an address beyond the maxi-
mum page-address range, the data output will not be valid. To determine whether the
target is busy during an OTP operation, either monitor R/B# or use the READ STATUS
(70h) command. Use of the READ STATUS ENHANCED (78h) command is prohibited
while the OTP operation is in progress.
Returning to Normal Array Operation Mode
To exit OTP operation mode and return to normal array operation mode, issue the SET
FEATURES (EFh) command to feature address 90h and write 00h to P1 through P4.
If the RESET (FFh) command is issued while in OTP operation mode, the target will exit
OTP operation mode and enter normal operating mode. If the synchronous interface is
active, the target will exit OTP operation and enable the asynchronous interface.
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If the SYNCHRONOUS RESET (FCh) command is issued while in the OTP operation
mode, the target will exit OTP operation mode and the synchronous interface remains
active.
Table 15: OTP Area Details
Description Value
Number of OTP pages 30
OTP protect page address 01h
OTP start page address 02h
Number of partial page programs (NOP) to each OTP page 4
PROGRAM OTP PAGE (80h-10h)
The PROGRAM OTP PAGE (80h-10h) command is used to write data to the pages within
the OTP area. To program data in the OTP area, the target must be in OTP operation
mode.
To use the PROGRAM OTP PAGE (80h-10h) command, issue the 80h command. Issue
five address cycles including the column address, the page address within the OTP page
range, and a block address of 0. Next, write the data to the cache register using data in-
put cycles. After data input is complete, issue the 10h command.
R/B# goes LOW for the duration of the array programming time, tPROG. The READ STA-
TUS (70h) command is the only valid command for reading status in OTP operation
mode. The RDY bit of the status register will reflect the state of R/B#. Use of the READ
STATUS ENHANCED (78h) command is prohibited.
When the target is ready, read the FAIL bit of the status register to determine whether
the operation passed or failed (see Status Operations).
The PROGRAM OTP PAGE (80h-10h) command also accepts the CHANGE WRITE COL-
UMN (85h) command during data input.
If a PROGRAM PAGE command is issued to the OTP area after the area has been protec-
ted, then R/B# goes LOW for tOBSY. After tOBSY, the status register is set to 60h.
Figure 57: PROGRAM OTP PAGE (80h-10h) Operation
Cycle type
DQ[7:0]
R/B#
tADL tWHR
Command Address Address Address Address Address
80h
Command
70h
Command
10hC1 C2 OTP Page 00h 00h
DoutDin Din Din
StatusD1 … Dn
tWB tPROG
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Figure 58: PROGRAM OTP PAGE (80h-10h) with CHANGE WRITE COLUMN (85h) Operation
Cycle type
DQ[7:0]
R/B#
tADL
Command Address Address Address Address Address
80h C1 C2 OTP Page 00h 00h
Din Din Din
Dn … Dm
1
Cycle type
DQ[7:0]
R/B#
tWHR
Command
70h
Command
10h
Command Address Address
85h C1 C2
Dout
Status
tCCS
Din Din Din
Dp … Dr
tWB tPROG
1
Command
85h
PROTECT OTP AREA (80h-10h)
The PROTECT OTP AREA (80h-10h) command is used to prevent further programming
of the pages in the OTP area. The protect the OTP area, the target must be in OTP opera-
tion mode.
To protect all data in the OTP area, issue the 80h command. Issue five address cycles
including the column address, OTP protect page address and block address; the column
and block addresses are fixed to 0. Next, write 00h data for the first byte location and
issue the 10h command.
R/B# goes LOW for the duration of the array programming time, tPROG. The READ STA-
TUS (70h) command is the only valid command for reading status in OTP operation
mode. The RDY bit of the status register will reflect the state of R/B#. Use of the READ
STATUS ENHANCED (78h) command is prohibited.
When the target is ready, read the FAIL bit of the status register to determine if the oper-
ation passed or failed (see Status Operations).
If the PROTECT OTP AREA (80h-10h) command is issued after the OTP area has already
been protected, R/B# goes LOW for tOBSY. After tOBSY, the status register is set to 60h.
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Figure 59: PROTECT OTP AREA (80h-10h) Operation
Cycle type
DQ[7:0]
R/B#
tADL tWHR
Command Address Address Address Address Address
80h
Command
70h
Command
10h00h 00h 01h 00h 00h
DoutDin
Status00h
tWB tPROG
Note: 1. OTP data is protected following a status confirmation.
READ OTP PAGE (00h-30h)
The READ OTP PAGE (00h-30h) command is used to read data from the pages in the
OTP area. To read data in the OTP area, the target must be in OTP operation mode.
To use the READ OTP PAGE (00h-30h) command, issue the 00h command. Issue five ad-
dress cycles including the column address, the page address within the OTP page range,
and a block address of 0. Next, issue the 30h command. The selected die (LUN) will go
busy (RDY = 0, ARDY = 0) for tR as data is transferred.
To determine the progress of the data transfer, the host can monitor the target's R/B#
signal, or alternatively the READ STATUS (70h) command can be used. If the status op-
erations are used to monitor the die’s (LUN's) status, when the die (LUN) is ready (RDY
= 1, ARDY = 1) the host disables status output and enables data output by issuing the
READ MODE (00h) command. When the host requests data output, it begins at the col-
umn address specified.
Additional pages within the OTP area can be read by repeating the READ OTP PAGE
(00h-30h) command.
The READ OTP PAGE (00h-30h) command is compatible with the CHANGE READ COL-
UMN (05h-E0h) command. Use of the READ STATUS ENHANCED (78h) and CHANGE
READ COLUMN ENHANCED (06h-E0h) commands are prohibited.
Figure 60: READ OTP PAGE (00h-30h) Operation
Cycle type
DQ[7:0]
R/B#
Command Address Address Address Address Address Command
tWB tRtRR
00h C1 C2 OTP Page 00h 00h 30h
Dout
Dn
Dout
Dn+1
Dout
Dn+2
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Multi-Plane Operations
Each NAND Flash logical unit (LUN) is divided into multiple physical planes. Each
plane contains a cache register and a data register independent of the other planes. The
planes are addressed via the low-order block address bits. Specific details are provided
in Device and Array Organization.
Multi-plane operations make better use of the NAND Flash arrays on these physical
planes by performing concurrent READ, PROGRAM, or ERASE operations on multiple
planes, significantly improving system performance. Multi-plane operations must be of
the same type across the planes; for example, it is not possible to perform a PROGRAM
operation on one plane with an ERASE operation on another.
When issuing MULTI-PLANE PROGRAM or ERASE operations, use the READ STATUS
(70h) command and check whether the previous operation(s) failed. If the READ STA-
TUS (70h) command indicates that an error occurred (FAIL = 1 and/or FAILC = 1), use
the READ STATUS ENHANCED (78h) command—time for each plane—to determine
which plane operation failed.
Multi-Plane Addressing
Multi-plane commands require an address per operational plane. For a given multi-
plane operation, these addresses are subject to the following requirements:
• The LUN address bit(s) must be identical for all of the issued addresses.
• The plane select bit, BA[8], must be different for each issued address.
• The page address bits, PA[7:0], must be identical for each issued address.
The READ STATUS (70h) command should be used following MULTI-PLANE PROGRAM
PAGE and ERASE BLOCK operations on a single die (LUN).
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Interleaved Die (Multi-LUN) Operations
In devices that have more than one die (LUN) per target, it is possible to improve per-
formance by interleaving operations between the die (LUNs). An interleaved die (multi-
LUN) operation is one that individual die (LUNs) involved may be in any combination
of busy or ready status during operations.
Interleaved die (multi-LUN) operations are prohibited following RESET (FFh, FCh),
identification (90h, ECh, EDh), and configuration (EEh, EFh) operations until ARDY =1
for all of the die (LUNs) on the target.
During an interleaved die (multi-LUN) operation, there are two methods to determine
operation completion. The R/B# signal indicates when all of the die (LUNs) have finish-
ed their operations. R/B# remains LOW while any die (LUN) is busy. When R/B# goes
HIGH, all of the die (LUNs) are idle and the operations are complete. Alternatively, the
READ STATUS ENHANCED (78h) command can report the status of each die (LUN) in-
dividually.
If a die (LUN) is performing a cache operation, like PROGRAM PAGE CACHE (80h-15h),
then the die (LUN) is able to accept the data for another cache operation when status
register bit 6 is 1. All operations, including cache operations, are complete on a die
when status register bit 5 is 1.
Use the READ STATUS ENHANCED (78h) command to monitor status for the addressed
die (LUN). When multi-plane commands are used with interleaved die (multi-LUN) op-
erations, the multi-plane commands must also meet the requirements, see Multi-Plane
Operations for details. After the READ STATUS ENHANCED (78h) command has been
issued, the READ STATUS (70h) command may be issued for the previously addressed
die (LUN).
See Command Definitions for the list of commands that can be issued while other die
(LUNs) are busy.
During an interleaved die (multi-LUN) operation that involves a PROGRAM-series
(80h-10h, 80h-15h, 80h-11h) operation and a READ operation, the PROGRAM-series
operation must be issued before the READ-series operation. The data from the READ-
series operation must be output to the host before the next PROGRAM-series operation
is issued. This is because the 80h command clears the cache register contents of all
cache registers on all planes.
When issuing combinations of commands to multiple die (LUNs) (e.g. Reads to one die
(LUN) and Programs to another die (LUN)) or Reads to one die (LUN) and Reads to an-
other die (LUN)), after the READ STATUS ENHANCED (78h) command is issued to the
selected die (LUN) a CHANGE READ COLUMN (05h-E0h) or CHANGE READ COLUMN
ENHANCED (06h-E0h) command shall be issued prior to any data output from the se-
lected die (LUN).
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Error Management
Each NAND Flash die (LUN) is specified to have a minimum number of valid blocks
(NVB) of the total available blocks. This means the die (LUNs) could have blocks that
are invalid when shipped from the factory. An invalid block is one that contains at least
one page that has more bad bits than can be corrected by the minimum required ECC.
Additional blocks can develop with use. However, the total number of available blocks
per die (LUN) will not fall below NVB during the endurance life of the product.
Although NAND Flash memory devices could contain bad blocks, they can be used
quite reliably in systems that provide bad-block management and error-correction al-
gorithms. This type of software environment ensures data integrity.
Internal circuitry isolates each block from other blocks, so the presence of a bad block
does not affect the operation of the rest of the NAND Flash array.
NAND Flash devices are shipped from the factory erased. The factory identifies invalid
blocks before shipping by attempting to program the bad-block mark into every loca-
tion in the first page of each invalid block. It may not be possible to program every loca-
tion with the bad-block mark. However, the first spare area location in each bad block is
guaranteed to contain the bad-block mark. This method is compliant with ONFI Facto-
ry Defect Mapping requirements. See the following table for the first spare area location
and the bad-block mark.
System software should check the first spare area location on the first page of each
block prior to performing any PROGRAM or ERASE operations on the NAND Flash de-
vice. A bad block table can then be created, enabling system software to map around
these areas. Factory testing is performed under worst-case conditions. Because invalid
blocks could be marginal, it may not be possible to recover this information if the block
is erased.
Over time, some memory locations may fail to program or erase properly. In order to
ensure that data is stored properly over the life of the NAND Flash device, the following
precautions are required:
• Always check status after a PROGRAM or ERASE operation
• Under typical conditions, use the minimum required ECC (see table below)
• Use bad-block management and wear-leveling algorithms
The first block (physical block address 00h) for each CE# is guaranteed to be valid with
ECC when shipped from the factory.
Table 16: Error Management Details
Description Requirement
Minimum number of valid blocks (NVB) per LUN 1998
Total available blocks per LUN 2048
First spare area location Byte 4096
Bad-block mark 00h
Minimum required ECC 24-bit ECC per 1080 bytes of data
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Shared Pages
In MLC NAND Flash devices, each memory cell contains two bits of data. These bits are
distributed across two NAND pages. Pages within a NAND block that share the same
NAND memory cells are referred to as shared pages. If any program operation is inter-
rupted (for example, power loss or reset), data in previously programmed shared pages
can also be corrupted.
Table 17: Shared Pages
Shared Pages Shared Pages
0 4 126 132
1 5 127 133
2 8 130 136
3 9 131 137
6 12 134 140
7 13 135 141
10 16 138 144
11 17 139 145
14 20 142 148
15 21 143 149
18 24 146 152
19 25 147 153
22 28 150 156
23 29 151 157
26 32 154 160
27 33 155 161
30 36 158 164
31 37 159 165
34 40 162 168
35 41 163 169
38 44 166 172
39 45 167 173
42 48 170 176
43 49 171 177
46 52 174 180
47 53 175 181
50 56 178 184
51 57 179 185
54 60 182 188
55 61 183 189
58 64 186 192
59 65 187 193
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Table 17: Shared Pages (Continued)
Shared Pages Shared Pages
62 68 190 196
63 69 191 197
66 72 194 200
67 73 195 201
70 76 198 204
71 77 199 205
74 80 202 208
75 81 203 209
78 84 206 212
79 85 207 213
82 88 210 216
83 89 211 217
86 92 214 220
87 93 215 221
90 96 218 224
91 97 219 225
94 100 222 228
95 101 223 229
98 104 226 232
99 105 227 233
102 108 230 236
103 109 231 237
106 112 234 240
107 113 235 241
110 116 238 244
111 117 239 245
114 120 242 248
115 121 243 249
118 124 246 252
119 125 247 253
122 128 250 254
123 129 251 255
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Output Drive Impedance
Because NAND Flash is designed for use in systems that are typically point-to-point
connections, an option to control the drive strength of the output buffers is provided.
Drive strength should be selected based on the expected loading of the memory bus.
There are four supported settings for the output drivers: overdrive 2, overdrive 1, nomi-
nal, and underdrive.
The nominal output drive strength setting is the power-on default value. The host can
select a different drive strength setting using the SET FEATURES (EFh) command.
The output impedance range from minimum to maximum covers process, voltage, and
temperature variations. Devices are not guaranteed to be at the nominal line.
Table 18: Output Drive Strength Conditions (VCCQ = 2.7–3.6V)
Range Process Voltage Temperature
Minimum Fast-Fast 3.6V TA (MIN)
Nominal Typical-Typical 3.3V +25°C
Maximum Slow-Slow 2.7V TA (MAX)
Table 19: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V)
Output
Strength Rpd/Rpu VOUT to VSSQ Minimum Nominal Maximum Unit
Overdrive 2 Rpd VCCQ X 0.2 7.0 16.2 28.7 ohms
VCCQ X 0.5 9.0 18.0 36.0 ohms
VCCQ X 0.8 11.8 21.0 50.0 ohms
Rpu VCCQ X 0.2 11.8 21.0 50.0 ohms
VCCQ X 0.5 9.0 18.0 36.0 ohms
VCCQ X 0.8 7.0 14.0 28.7 ohms
Overdrive 1 Rpd VCCQ X 0.2 9.3 22.3 40.0 ohms
VCCQ X 0.5 12.6 25.0 50.0 ohms
VCCQ X 0.8 16.3 29.0 68.0 ohms
Rpu VCCQ X 0.2 16.3 29.0 68.0 ohms
VCCQ X 0.5 12.6 25.0 50.0 ohms
VCCQ X 0.8 9.3 19.0 40.0 ohms
Nominal Rpd VCCQ X 0.2 12.8 32.0 58.0 ohms
VCCQ X 0.5 18.0 35.0 70.0 ohms
VCCQ X 0.8 23.0 40.0 95.0 ohms
Rpu VCCQ X 0.2 23.0 40.0 95.0 ohms
VCCQ X 0.5 18.0 35.0 70.0 ohms
VCCQ X 0.8 12.8 32.0 58.0 ohms
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Table 19: Output Drive Strength Impedance Values (VCCQ = 2.7–3.6V) (Contin-
ued)
Output
Strength Rpd/Rpu VOUT to VSSQ Minimum Nominal Maximum Unit
Underdrive Rpd VCCQ X 0.2 18.4 45.0 80.0 ohms
VCCQ X 0.5 25.0 50.0 100.0 ohms
VCCQ X 0.8 32.0 57.0 136.0 ohms
Rpu VCCQ X 0.2 32.0 57.0 136.0 ohms
VCCQ X 0.5 25.0 50.0 100.0 ohms
VCCQ X 0.8 18.4 45.0 80.0 ohms
Table 20: Pull-Up and Pull-Down Output Impedance Mismatch
Drive Strength Minimum Maximum Unit Notes
Overdrive 2 0 6.3 ohms 1, 2
Overdrive 1 0 8.8 ohms 1, 2
Nominal 0 12.3 ohms 1, 2
Underdrive 0 17.5 ohms 1, 2
Notes: 1. Mismatch is the absolute value between pull-up and pull-down impedances. Both are
measured at the same temperature and voltage.
2. Test conditions: VCCQ = VCCQ (MIN), VOUT = VCCQ × 0.5, TA = TOPER.
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AC Overshoot/Undershoot Specifications
The supported AC overshoot and undershoot area depends on the timing mode selec-
ted by the host.
Table 21: Asynchronous Overshoot/Undershoot Parameters
Parameter
Timing Mode
Unit0 1 2 3 4 5
Maximum peak amplitude provided for
overshoot area
111111V
Maximum peak amplitude provided for un-
dershoot area
111111V
Maximum overshoot area above VCCQ 3 3 3 3 3 3 V-ns
Maximum undershoot area below VSSQ 3 3 3 3 3 3 V-ns
Table 22: Synchronous Overshoot/Undershoot Parameters
Parameter
Timing Mode
Unit0 1 2 3 4 5
Maximum peak amplitude provided for
overshoot area
111111V
Maximum peak amplitude provided for un-
dershoot area
111111V
Maximum overshoot area above VCCQ 3 3 3 2.25 1.8 1.5 V-ns
Maximum undershoot area below VSSQ 3 3 3 2.25 1.8 1.5 V-ns
Figure 61: Overshoot
Maximum amplitude
Overshoot area
Time (ns)
Volts (V)
VCCQ
Figure 62: Undershoot
Undershoot area
Maximum amplitude
Time (ns)
Volts (V)
VSSQ
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Synchronous Input Slew Rate
Though all AC timing parameters are tested with a nominal input slew rate of 1 V/ns, it
is possible to run the device at a slower slew rate. The input slew rates shown below are
sampled, and not 100% tested. When using slew rates slower than the minimum values,
timing must be derated by the host.
Table 23: Test Conditions for Input Slew Rate
Parameter Value
Rising edge VIL(DC) To VIH(AC)
Falling edge VIH(DC) To VIL(AC)
Temperature range TA
Table 24: Input Slew Rate (VCCQ= 2.7–3.6V)
Command/
Address
and DQ
V/ns
CLK/DQS Slew Rate Derating VIH(AC)/VIL(AC)= 990mV, VIH(DC)/VIL(DC)= 660mV
Unit
1 0.9 0.8 0.7 0.6 0.5 0.4 0.3
set hold set hold set hold set hold set hold set hold set hold set hold
1 0 0 0 0 - - - - - - - - - - - - ps
0.9 0 0 0 0 0 0 - - - - - - - - - - ps
0.8 - - 0 0 0 0 0 0 - - - - - - - - ps
0.7 - - - - 0 0 0 0 0 0 - - - - - - ps
0.6 - - - - - - 0 0 0 0 0 0 - - - - ps
0.5 - - - - - - - - 0 0 0 0 330 330 - - ps
0.4 - - - - - - - - - - 330 330 660 660 1210 1210 ps
0.3 - - - - - - - - - - - - 1210 1210 1760 1760 ps
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Output Slew Rate
The output slew rate is tested using the following setup with only one die per DQ chan-
nel.
Table 25: Test Conditions for Output Slew Rate
Parameter Value
VOL(DC) 0.3 × VCCQ
VOH(DC) 0.7 × VCCQ
VOL(AC) 0.2 × VCCQ
VOH(AC) 0.8 × VCCQ
Rising edge (tRISE) VOL(DC) to VOH(AC)
Falling edge (tFALL) VOH(DC) to VOL(AC)
Output capacitive load (CLOAD) 5pF
Temperature range TA
Table 26: Output Slew Rate (VCCQ = 2.7–3.6V)
Output Drive Strength Min Max Unit
Overdrive 2 1.5 10.0 V/ns
Overdrive 1 1.5 9.0 V/ns
Nominal 1.2 7.0 V/ns
Underdrive 1.0 5.5 V/ns
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Electrical Specifications
Stresses greater than those listed can cause permanent damage to the device. This is a
stress rating only, and functional operation of the device at these or any other condi-
tions above those indicated in the operational sections of this specification is not guar-
anteed. Exposure to absolute maximum rating conditions for extended periods can af-
fect reliability.
Table 27: Absolute Maximum Ratings by Device
Parameter Symbol Min1Max1Unit
Voltage input VIN -0.6 4.6 V
VCC supply voltage VCC -0.6 4.6 V
VCCQ supply voltage VCCQ -0.6 4.6 V
Storage temperature TSTG -65 150 °C
Note: 1. Voltage on any pin relative to VSS.
Table 28: Recommended Operating Conditions
Parameter Symbol Min Typ Max Unit
Operating temperature Commercial TA0 – 70 °C
Industrial –40 – 85
VCC supply voltage VCC 2.7 3.3 3.6 V
VCCQ supply voltage VCCQ 2.7 3.3 3.6 V
VSS ground voltage VSS 0 0 0 V
VSSQ ground voltage VSSQ 0 0 0 V
Table 29: Valid Blocks per LUN
Parameter Symbol Min Max Unit Notes
Valid block number NVB 1998 2048 Blocks 1
Note: 1. Invalid blocks are block that contain one or more bad bits beyond ECC. The device may
contain bad blocks upon shipment. Additional bad blocks may develop over time; how-
ever, the total number of available blocks will not drop below NVB during the endur-
ance life of the device. Do not erase or program blocks marked invalid from the factory.
Table 30: Capacitance: 48-Pin TSOP Package
Description Symbol Device Max Unit Notes
Input capacitance – ALE, CE#, CLE, RE#
WE#, WP#
CIN Single die package 6 pF 1
Dual die package 10
Input/output capacitance – DQ[7:0], DQS CIO Single die package 5 pF 1
Dual die package 8
Note: 1. These parameters are verified in device characterization and are not 100% tested. Test
conditions: TC = 25°C; f = 1 MHz; Vin = 0V.
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Electrical Specifications
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Table 31: Capacitance: 56-Ball BGA Package
Description Symbol Device Max Unit Notes
Input capacitance – ALE, CE#, CLE, RE#,
WE#, WP#
CIN Single die package 7 pF 1
Input/output capacitance – DQ[7:0] CIO Single die package 6 pF 1
Note: 1. These parameters are verified in device characterization and are not 100% tested. Test
conditions: TC = 25°C; f = 1 MHz; Vin = 0V.
Table 32: Test Conditions
Parameter Value Notes
Rising input transition VIL(DC) to VIH(AC) 1
Falling input transition VIH(DC) to VIL(AC) 1
Input rise and fall slew rates 1 V/ns –
Input and output timing levels VCCQ/2 –
Output load: Nominal output drive strength CL = 5pF 2, 3
Notes: 1. The receiver will effectively switch as a result of the signal crossing the AC input level; it
will remain in that status as long as the signal does not ring back above (below) the DC
input LOW (HIGH) level.
2. Transmission line delay is assumed to be very small.
3. This test setup applies to all package configurations.
Electrical Specifications – DC Characteristics and Operating Conditions
(Asynchronous)
Table 33: DC Characteristics and Operating Conditions (Asynchronous Interface)
Parameter Conditions Symbol Min1Typ1Max1Unit
Array read current (active) – ICC1_A – 20 50 mA
Array program current (ac-
tive)
– ICC2_A – 20 50 mA
Erase current (active) – ICC3_A – 20 50 mA
I/O burst read current tRC = tRC (MIN); IOUT= 0mA ICC4R_A – 8 10 mA
I/O burst write current tWC = tWC (MIN) ICC4w_A – 8 10 mA
Bus idle current – ICC5_A – 3 5 mA
Current during first RESET
command after power-on
– ICC6 – – 10 mA
Standby current - VCC CE# = VCCQ - 0.2V;
WP# = 0V/VCCQ
ISB – 10 50 µA
Standby current - VCCQ CE# = VCCQ - 0.2V;
WP# = 0V/VCCQ
ISBQ – 3 10 µA
Staggered power-up current tRISE = 1ms; CLINE = 0.1uF IST – – 10 mA
Note: 1. All values are per die (LUN) unless otherwise specified.
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Electrical Specifications – DC Characteristics and Operating Conditions
(Synchronous)
Table 34: DC Characteristics and Operating Conditions (Synchronous Interface)
Parameter Conditions Symbol Min1Typ1Max1Unit
Array read current (active) CE# = VIL; tCK = tCK (MIN) ICC1_S – 25 50 mA
Array program current (ac-
tive)
tCK = tCK (MIN) ICC2_S – 25 50 mA
Erase current (active) tCK = tCK (MIN) ICC3_S – 25 50 mA
I/O burst read current tCK = tCK (MIN) ICC4R_S – 20 27 mA
I/O burst write current tCK = tCK (MIN) ICC4W_S – 20 27 mA
Bus idle current tCK = tCK (MIN) ICC5_S – 5 10 mA
Standby current - VCC CE# = VCCQ - 0.2V;
WP# = 0V/VCCQ
ISB – 10 50 µA
Standby Current - VCCQ CE# = VCCQ - 0.2V;
WP# = 0V/VCCQ
ISBQ – 3 10 µA
Note: 1. All values are per die (LUN) unless otherwise specified.
Electrical Specifications – DC Characteristics and Operating Conditions
(VCCQ)
Table 35: DC Characteristics and Operating Conditions
Parameter Condition Symbol Min Typ Max Unit Notes
AC input high voltage CE#, DQ[7:0], DQS, ALE, CLE, CLK
(WE#), W/R# (RE#), WP#
VIH(AC) 0.8 × VCCQ – VCCQ + 0.3 V
AC input low voltage VIL(AC) –0.3 – 0.2 × VCCQ V
DC input high voltage DQ[7:0], DQS, ALE, CLE, CLK
(WE#), W/R# (RE#)
VIH(DC) 0.7 × VCCQ – VCCQ + 0.3 V
DC input low voltage VIL(DC) –0.3 – 0.3 × VCCQ V
Input leakage current Any input VIN = 0V to VCCQ
(all other pins under test = 0V)
ILI – – ±10 µA
Output leakage cur-
rent
DQ are disabled; VOUT = 0V to
VCCQ
ILO – – ±10 µA 1
Output low current
(R/B#)
VOL = 0.4V IOL (R/B#) 8 10 – mA 2
Notes: 1. All leakage currents are per die (LUN). Two die (LUNs) have a maximum leakage current
of ±20µA and four die (LUNs) have a maximum leakage current of ±40µA in the asyn-
chronous interface.
2. DC characteristics may need to be relaxed if R/B# pull-down strength is not set to full
strength. See Table 14 (page 61) for additional details.
Electrical Specifications – AC Characteristics and Operating Conditions
(Asynchronous)
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Table 36: AC Characteristics: Asynchronous Command, Address, and Data
Parameter Symbol
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5
Unit NotesMin Max Min Max Min Max Min Max Min Max Min Max
Clock period 100 50 35 30 25 20 ns
Frequency ≈10 ≈20 ≈28 ≈33 ≈40 ≈50 MHz
ALE to data start tADL 200 – 100 – 100 – 100 – 70 – 70 – ns 1
ALE hold time tALH 20 – 10 – 10 – 5 – 5 – 5 – ns
ALE setup time tALS 50 – 25 – 15 – 10 – 10 – 10 – ns
ALE to RE# delay tAR 25 – 10 – 10 – 10 – 10 – 10 – ns
CE# access time tCEA – 100 – 45 – 30 – 25 – 25 – 25 ns
CE# hold time tCH 20 – 10 – 10 – 5 – 5 – 5 – ns
CE# HIGH to output
High-Z
tCHZ – 100 – 50 – 50 – 50 – 30 – 30 ns 2
CLE hold time tCLH 20 – 10 – 10 – 5 – 5 – 5 – ns
CLE to RE# delay tCLR 20 – 10 – 10 – 10 – 10 – 10 – ns
CLE setup time tCLS 50 – 25 – 15 – 10 – 10 – 10 – ns
CE# HIGH to output
hold
tCOH 0 – 15 – 15 – 15 – 15 – 15 – ns
CE# setup time tCS 70 – 35 – 25 – 25 – 20 – 15 – ns
Data hold time tDH 20 – 10 – 5 – 5 – 5 – 5 – ns
Data setup time tDS 40 – 20 – 15 – 10 – 10 – 7 – ns
Output High-Z to
RE# LOW
tIR 10 – 0 – 0 – 0 – 0 – 0 – ns
RE# cycle time tRC 100 – 50 – 35 – 30 – 25 – 20 – ns
RE# access time tREA – 40 – 30 – 25 – 20 – 20 – 16 ns 3
RE# HIGH hold time tREH 30 – 15 – 15 – 10 – 10 – 7 – ns 3
RE# HIGH to output
hold
tRHOH 0 – 15 – 15 – 15 – 15 – 15 – ns 3
RE# HIGH to WE#
LOW
tRHW 200 – 100 – 100 – 100 – 100 – 100 – ns
RE# HIGH to output
High-Z
tRHZ – 200 – 100 – 100 – 100 – 100 – 100 ns 2, 3
RE# LOW to output
hold
tRLOH 0 – 0 – 0 – 0 – 5 – 5 – ns 3
RE# pulse width tRP 50 – 25 – 17 – 15 – 12 – 10 – ns
Ready to RE# LOW tRR 40 – 20 – 20 – 20 – 20 – 20 – ns
WE# HIGH to
R/B# LOW
tWB – 200 – 100 – 100 – 100 – 100 – 100 ns 4
WE# cycle time tWC 100 – 45 – 35 – 30 – 25 – 20 – ns
WE# HIGH hold time tWH 30 – 15 – 15 – 10 – 10 – 7 – ns
WE# HIGH to RE#
LOW
tWHR 120 – 80 – 80 – 60 – 60 – 60 – ns
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Table 36: AC Characteristics: Asynchronous Command, Address, and Data (Continued)
Parameter Symbol
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5
Unit NotesMin Max Min Max Min Max Min Max Min Max Min Max
WE# pulse width tWP 50 – 25 – 17 – 15 – 12 – 10 – ns
WP# transition to
WE# LOW
tWW 100 – 100 – 100 – 100 – 100 – 100 – ns
Notes: 1. Timing for tADL begins in the address cycle, on the final rising edge of WE# and ends
with the first rising edge of WE# for data input.
2. Data transition is measured ±200mV from steady-steady voltage with load. This parame-
ter is sampled and not 100 percent tested.
3. AC characteristics may need to be relaxed if output drive strength is not set to at least
nominal.
4. Do not issue a new command during tWB, even if R/B# or RDY is ready.
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Electrical Specifications – AC Characteristics and Operating Conditions
(Synchronous)
Table 37: AC Characteristics: Synchronous Command, Address, and Data
Parameter Symbol
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5
Unit NotesMin Max Min Max Min Max Min Max Min Max Min Max
Clock period 50 30 20 15 12 10 ns
Frequency ≈20 ≈33 ≈50 ≈67 ≈83 ≈100 MHz
Access window
of DQ[7:0] from
CLK
tAC 3 20 3 20 3 20 3 20 3 20 3 20 ns
ALE to data
loading time
tADL 100 – 100 – 70 – 70 – 70 – 70 – ns
Command, ad-
dress data delay
tCAD 25 – 25 – 25 – 25 – 25 – 25 – ns 1
ALE, CLE, W/R#
hold
tCALH 10 – 5 – 4 – 3 – 2.5 – 2 – ns
ALE, CLE, W/R#
setup
tCALS 10 – 5 – 4 – 3 – 2.5 – 2 – ns
DQ hold – com-
mand, address
tCAH 10 – 5 – 4 – 3 – 2.5 – 2 – ns
DQ setup –
command, ad-
dress
tCAS 10 – 5 – 4 – 3 – 2.5 – 2 – ns
CE# hold tCH 10 – 5 – 4 – 3 – 2.5 – 2 – ns
Average CLK cy-
cle time
tCK
(avg)
50 100 30 50 20 30 15 20 12 15 10 12 ns 3
Absolute CLK
cycle time, from
rising edge to
rising edge
tCK (abs) tCK (abs) MIN = tCK (avg) + tJIT (per) MIN
tCK (abs) MAX = tCK (avg) + tJIT (per) MAX
ns
CLK cycle HIGH tCKH
(abs)
0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 tCK 4
CLK cycle LOW tCKL
(abs)
0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 0.43 0.57 tCK 4
Data output
end to W/R#
HIGH
tCKWR tCKWR(MIN) = RoundUp[(tDQSCK(MAX) + tCK)/tCK] tCK
CE# setup tCS 35 – 25 – 15 – 15 – 15 – 15 – ns
Data In hold tDH 5 – 2.5 – 1.7 – 1.3 – 1.1 – 0.8 – ns
Access window
of DQS from
CLK
tDQSCK – 20 – 20 – 20 – 20 – 20 – 20 ns
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Table 37: AC Characteristics: Synchronous Command, Address, and Data (Continued)
Parameter Symbol
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5
Unit NotesMin Max Min Max Min Max Min Max Min Max Min Max
DQS, DQ[7:0]
Driven by
NAND
tDQSD – 18 – 18 – 18 – 18 – 18 – 18 ns
DQS, DQ[7:0] to
tri-state
tDQSHZ – 20 – 20 – 20 – 20 – 20 – 20 ns 5
DQS input high
pulse width
tDQSH 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
DQS input low
pulse width
tDQSL 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 0.4 0.6 tCK
DQS-DQ skew tDQSQ – 5 – 2.5 – 1.7 – 1.3 – 1.0 – 0.85 ns
Data input tDQSS 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 0.75 1.25 tCK
Data In setup tDS 5 – 3 – 2 – 1.5 – 1.1 – 0.8 – ns
DQS falling
edge from CLK
rising – hold
tDSH 0.2 – 0.2 – 0.2 – 0.2 – 0.2 – 0.2 – tCK
DQS falling to
CLK rising – set-
up
tDSS 0.2 – 0.2 – 0.2 – 0.2 – 0.2 – 0.2 – tCK
Data valid win-
dow
tDVW tDVW = tQH - tDQSQ ns
Half clock peri-
od
tHP tHP = Min(tCKH, tCKL) ns
The deviation
of a given tCK
(abs) from a tCK
(avg)
tJIT (per) –0.7 0.7 –0.7 0.7 –0.7 0.7 –0.6 0.6 –0.6 0.6 –0.5 0.5 ns
DQ-DQS hold,
DQS to first DQ
to go nonvalid,
per access
tQH tQH = tHP - tQHS ns
Data hold skew
factor
tQHS – 6 – 3 – 2 – 1.5 – 1.2 – 1 ns
Data output to
command, ad-
dress, or data
input
tRHW 100 – 100 – 100 – 100 – 100 – 100 ns
Ready to data
output
tRR 20 – 20 – 20 – 20 – 20 – 20 – ns
CLK HIGH to
R/B# LOW
tWB – 100 – 100 – 100 – 100 – 100 – 100 ns
Command cycle
to data output
tWHR 80 – 80 – 80 – 80 – 80 – 80 – ns
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Table 37: AC Characteristics: Synchronous Command, Address, and Data (Continued)
Parameter Symbol
Mode 0 Mode 1 Mode 2 Mode 3 Mode 4 Mode 5
Unit NotesMin Max Min Max Min Max Min Max Min Max Min Max
DQS write pre-
amble
tWPRE 1.5 – 1.5 – 1.5 – 1.5 – 1.5 – 1.5 – tCK
DQS write post-
amble
tWPST 1.5 – 1.5 – 1.5 – 1.5 – 1.5 – 1.5 – tCK
W/R# LOW to
data output cy-
cle
tWRCK 20 – 20 – 20 – 20 – 20 – 20 – ns
WP# transition
to command cy-
cle
tWW 100 – 100 – 100 – 100 – 100 – 100 – ns
Notes: 1. Delay is from start of command to next command, address, or data cycle; start of ad-
dress to next command, address, or data cycle; and end of data to start of next com-
mand, address, or data cycle.
2. This value is specified in the parameter page.
3. tCK(avg) is the average clock period over any consecutive 200-cycle window.
4. tCKH(abs) and tCKL(abs) include static offset and duty cycle jitter.
5. tDQSHZ begins when W/R# is latched HIGH by CLK. This parameter is not referenced to a
specific voltage level; it specifies when the device outputs are no longer driving.
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Electrical Specifications – Array Characteristics
Table 38: Array Characteristics
Parameter Symbol Typ Max Unit Notes
Number of partial page programs NOP – 1 Cycles 1
ERASE BLOCK operation time tBERS 3.8 10 ms
Cache busy tCBSY 35 2600 µs
Change column setup time to data in/out or next command tCCS – 200 ns
Dummy busy time tDBSY 0.5 1 µs
Cache read busy time tRCBSY 3 75 µs
Busy time for SET FEATURES and GET FEATURES operations tFEAT – 1 µs
Busy time for interface change tITC – 1 µs 2
LAST PAGE PROGRAM operation time tLPROG – – µs 3
Busy time for OTP DATA PROGRAM operation if OTP is protected tOBSY – 40 µs
Power-on reset time tPOR – 1 ms
PROGRAM PAGE operation time tPROG 1300 2600 µs
READ PAGE operation time tR – 75 µs
Device reset time (Read/Program/Erase) tRST – 5/10/500 µs 4
Notes: 1. The pages in the OTP Block have an NOP of 4.
2. tITC (MAX) is the busy time when the interface changes from asynchronous to synchro-
nous using the SET FEATURES (EFh) command or synchronous to asynchronous using the
RESET (FFh) command. During the tITC time, any command, including READ STATUS
(70h) and READ STATUS ENHANCED (78h), is prohibited.
3. tLPROG = tPROG (last page) + tPROG (last page - 1) - command load time (last page) -
address load time (last page) - data load time (last page).
4. If RESET command is issued when the target is READY, the target goes busy for a maxi-
mum of 5µs.
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Asynchronous Interface Timing Diagrams
Figure 63: RESET Operation
CLE
CE#
WE#
R/B#
DQ[7:0]
tRST
tWB
FFh
RESET
command
Figure 64: RESET LUN Operation
tWB
Don’t Care
FAh Row add 1 Row add 2 Row add 3
tDS tDH
tWP tWP
tWC
tCH
tALS tALH
tWH
tCLS tCLH
tALH
tCS
tRST
DQ[7:0]
R/B#
ALE
WE#
CLE
CE#
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Figure 65: READ STATUS Cycle
RE#
CE#
WE#
CLE
DQ[7:0]
tRHZ
tWP
tWHR
tCLR
tCH
tCLS
tCS
tCLH
tDH
tRP
tCHZ
tDS tREA
tRHOH
tIR
70h Status
output
Don’t Care
tCEA
tCOH
Figure 66: READ STATUS ENHANCED Cycle
tWHR
tAR
Don’t Care
78h Row add 1 Row add 2 Row add 3 Status output
tDS tDH
tWP tWP
tWC
tCH
tALS tALH
tWH
tCLS tCLH
tALH
tCS
tCEA
tCHZ
tREA tRHOH
tRHZ
tCOH
DQ[7:0]
RE#
ALE
WE#
CLE
CE#
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Figure 67: READ PARAMETER PAGE
WE#
ALE
CLE
RE#
R/B#
ECh 00h
tR
P00P10P2550P01
tWB
tRR
DQ[7:0]
tRP
tRC
Figure 68: READ PAGE
DOUT
N
DOUT
N + 1
DOUT
M
WE#
CE#
ALE
CLE
RE#
RDY
DQx
tWC
Busy
00h 30h
tR
tWB
tAR
tRR tRP
tCLR
tRC tRHZ
Don’t Care
Col
add 1
Col
add 2
Row
add 1
Row
add 2
Row
add 3
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Figure 69: READ PAGE Operation with CE# “Don’t Care”
RE#
CE#
tREA tCHZ
tCOH
tCEA
RE#
CE#
ALE
CLE
DQx
I/Ox Out
RDY
WE#
Data output
tR
Don’t Care
Address (5 cycles)00h 30h
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Figure 70: CHANGE READ COLUMN
WE#
CE#
ALE
CLE
RE#
RDY
DQx
tRHW
tRC
DOUT
M
DOUT
M + 1
Col
add 1 Col
add 2
05h E0h
tREA
tCLR
DOUT
N – 1
DOUT
N
tCCS
Column address M
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Figure 71: READ PAGE CACHE SEQUENTIAL
tWC
WE#
CE#
ALE
CLE
RE#
RDY
DQx
Column address 0
Page address
M
Page address
M
Column address
00h
tCEA
tDS
tCLH
tCLS
tCS
tCH
tDH
tRR
tWB tR
tRC
tREA
30h 31h
Col
add 2 Row
add 1 Row
add 2 Row
add 3
00h
tRCBSY
Col
add 1
tRHW
tCLH
tCH
tDS
tWB
tCLS
tCS
31h
1
WE#
CE#
ALE
CLE
RE#
RDY
DQx
Column address 0
Page address
M
tRC
tREA
DOUT
0
tRHW
DOUT
1
Don’t Care
Column address 0
tCLH
tCH
tREA
tCEA
tRHW
tDS tRR
tRCBSY
tWB
Column address 0
3Fh
tCLS
tCS
tRC
DOUT DOUT
0
DOUT
1DOUT DOUT
0
DOUT
1DOUT
DOUT
0
DOUT
1DOUT
31h
tRCBSY Page address
M + 1 Page address
M + 2
1
tDH
tDH
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Figure 72: READ PAGE CACHE RANDOM
tWC
WE#
CE#
ALE
CLE
RE#
RDY
DQx
Page address
M
Column address
00h
tDS
tCLH
tCLS
tCS
tCH
tDH tWB tR
30h 00h
Col
add 2
Row
add 1
Row
add 2
Row
add 3
00h Col
add 1
Page address
N
Column address
00h
Col
add 2
Row
add 1
Row
add 2
Col
add 1
1
WE#
CE#
ALE
CLE
RE#
RDY
DQx
Don’t Care
Column address 0
tCH
tREA
tCEA tRHW
tDS
tDH
tRR
tRCBSY
tWB
Column address 0
DOUT
0DOUT 3Fh
tCS
tRC
31h
tRCBSY
DOUT
1
DOUT
0DOUT
DOUT
1
Page address
M
Page address
N
Page address
N
Column address
00h
Col
add 2
Row
add 1
Row
add 2
Row
add 3
Col
add 1
1
tCLH
tCLS
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L72A_16Gb_32Gb_Async_Sync_NAND.pdf – Rev. E 9/12 EN 120 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Figure 73: READ ID Operation
WE#
CE#
ALE
CLE
RE#
DQx
Address, 1 cycle
90h 00h or 20h Byte 2Byte 0 Byte 1 Byte 3 Byte 4
tAR
tREA
tWHR
Figure 74: PROGRAM PAGE Operation
WE#
CE#
ALE
CLE
RE#
RDY
DQx
tWC tADL
1 up to m byte
serial Input
80h Col
add 1 Col
add 2 Row
add 1 Row
add 2 Row
add 3 DIN
N
DIN
M70h Status
10h
tPROG tWHR
tWB
Don’t Care
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Asynchronous Interface Timing Diagrams
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Figure 75: PROGRAM PAGE Operation with CE# “Don’t Care”
Address (5 cycles) Data input 10h
WE#
CE#
tWP
tCH
tCS
Don’t Care
Data input80h
CLE
CE#
WE#
ALE
DQx
Figure 76: PROGRAM PAGE Operation with CHANGE WRITE COLUMN
WE#
CE#
ALE
CLE
RE#
RDY
DQx
tWC
Serial input
80h Col
add 1 Col
add 2 Row
add 1 Row
add 2 Row
add 3
DIN
M
DIN
N
tADL tCCS
CHANGE WRITE
COLUMN command
Column address READ STATUS
command
Serial input
85h
tPROG
tWB tWHR
Don’t Care
Col
add 1 Col
add 2
DIN
P
DIN
Q70h Status
10h
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Figure 77: PROGRAM PAGE CACHE
WE#
CE#
ALE
CLE
RE#
RDY
DQx 15h
tCBSY
tWB tWB tWHR
tLPROG
Col
add 1
80h 10h 70h Status
Col
add 2 Row
add 2
Row
add 1
Col
add 1 Col
add 2 Row
add 2
Row
add 1 Row
add 3 DIN
M
DIN
N
DIN
M
DIN
N
Last page - 1 Last page
Serial input
tWC
Don’t Care
80h
tADL
Row
add 3
Figure 78: PROGRAM PAGE CACHE Ending on 15h
WE#
CE#
ALE
CLE
RE#
DQx 15h Col
add 1
80h 15h 70h Status 70h Status70h Status Col
add 2 Row
add 2
Row
add 1 Row
add 3
Col
add 1 Col
add 2 Row
add 2
Row
add 1 Row
add 3
DIN
M
DIN
N
DIN
M
DIN
N
Last pageLast page – 1
Serial input
tWC
Don’t Care
80h
Poll status until:
I/O6 = 1, Ready
To verify successful completion of the last 2 pages:
I/O5 = 1, Ready
I/O0 = 0, Last page PROGRAM successful
I/O1 = 0, Last page – 1 PROGRAM successful
tADL
tWHR tWHR
tADL
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Asynchronous Interface Timing Diagrams
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Figure 79: COPYBACK
WE#
CE#
ALE
CLE
RE#
RDY
DQx
tWB tPROG
tWB
Busy Busy
READ STATUS
command
tWC
Don’t Care
tADL
tWHR
Col
add 2 Row
add 1 Row
add 2 70h10h Status
Data
N
Row
add 3
Col
add 1
00h Col
add 2 Row
add 1 Row
add 2 Row
add 3 35h
(or 30h) Col
add 1
85h Data
1
tR
Data Input
Optional
Figure 80: ERASE BLOCK Operation
WE#
CE#
ALE
CLE
RE#
RDY
DQ[7:0]
READ STATUS
command
Busy
Row address
60h Row
add 1 Row
add 2 Row
add 3 70h Status
D0h
tWC
tBERS
tWB tWHR
Don’t Care
I/O0 = 0, Pass
I/O0 = 1, Fail
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Asynchronous Interface Timing Diagrams
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Synchronous Interface Timing Diagrams
Figure 81: SET FEATURES Operation
CLK
CE#
ALE
CLE
W/R#
R/B#
DQx
tCAD
EFh Feat
Addr
Feat
Addr
tFEAT
tWB
Don’t Care
tCAD
tCS
tCAD
P10P11P20P21P30P31P40P41
DQS
tCALS
tCALS
tDQSS
Notes: 1. When CE# remains LOW, tCAD begins at the rising edge of the clock from which the last
data byte is input for the subsequent command or data input cycle(s).
2. tDSH (MIN) generally occurs during tDQSS (MIN).
3. tDSS (MIN) generally occurs during tDQSS (MAX).
4. The cycle that tCAD is measured from may be an idle cycle (as shown), another com-
mand cycle, an address cycle, or a data cycle. The idle cycle is shown in this diagram for
simplicity.
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Synchronous Interface Timing Diagrams
PDF: 09005aef841356b0
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© 2010 Micron Technology, Inc. All rights reserved.
Figure 82: READ ID Operation
CLK
CE#
ALE
CLE
W/R#
DQ[7:0] 90h 00h
or 20h
tDQSD
Don’t Care
tCAD
tCS
tCAD
tDQSHZ
DQS
tRHW
tCALS
tDQSCK tCALS
Driven
tCALH
tCKWR
tCALH
tWHR
Byte 0 Byte 0 Byte 1 Byte 2 Byte 3 Byte 3 Byte 4 Byte 4Byte 2Byte 1
tCALS
tCALS
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Synchronous Interface Timing Diagrams
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© 2010 Micron Technology, Inc. All rights reserved.
Figure 83: GET FEATURES Operation
CLK
CE#
ALE
CLE
W/R#
RDY
DQ[7:0] EEh
tFEAT
tDQSD
tWB
Don’t Care
tCAD
tCS
tCAD
tDQSHZ
DQS
tRHW
tCALS
tDQSCK
Driven
tCALH
tCKWR
tCALH
tWRCK
Feat
Addr P1 P2 P3 P4
tCALS
tCALS
tCALS
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Synchronous Interface Timing Diagrams
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© 2010 Micron Technology, Inc. All rights reserved.
Figure 84: RESET (FCh) Operation
CLK
ALE
CLE
DQS
DQ[7:0]
R/B#
tCALH
tCAH
tCAS
tCALS
tCALH
Don’t Care
tCALH
tCALS
tRST
CE#
tCH
tCS
tCAD
tWB
W/R#
FCh
SYNCHRONOUS
RESET command
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© 2010 Micron Technology, Inc. All rights reserved.
Figure 85: READ STATUS Cycle
CLK
CE#
ALE
CLE
W/R#
RDY
DQ[7:0]
READ STATUS
command
70h
tWHR
Don’t Care
DQS
tDQSD
tRHW
tCKWR
tDQSHZ
Driven
Status Status
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© 2010 Micron Technology, Inc. All rights reserved.
Figure 86: READ STATUS ENHANCED Operation
CLK
CE#
ALE
CLE
W/R#
DQ[7:0] 78h
tWHR
Don’t Care
tCAD
tCS
tCAD tCAD
tCAD
DQS
tDQSD
tRHW
tCKWR
tDQSHZ
Driven
Row
add 1 Row
add 2 Row
add 3 Status Status
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Synchronous Interface Timing Diagrams
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© 2010 Micron Technology, Inc. All rights reserved.
Figure 87: READ PARAMETER PAGE Operation
CLK
CE#
ALE
CLE
W/R#
RDY
DQ[7:0] ECh
tR
tDQSD
tWB
Driven Don’t Care
tCAD
tCS
tCAD
tDQSHZ
DQS
tRHW
tDQSCK
tCALS
tCALH
tCKWR
tCALH
tWRCK
00h P1 P2 Pn-3 Pn-2 Pn-1 PnP0
tCALS
tCALS
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© 2010 Micron Technology, Inc. All rights reserved.
Figure 88: READ PAGE Operation
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
tCAD
00h Col
add 1 Col
add 2
tR
tWB
Don’t Care
tCAD
tCS
tCAD tCAD
tCAD
tCAD tCAD
DQS
30h
Row
add 1 Row
add 2 Row
add 3
tCALS
Driven
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
tCAD
1 up to m Byte
serial input
tR
tDQSD
tWB
tCAD
tDQSHZ
DQS
30h
tRHW
tCALS
tCALS
tDQSCK
Row
add 3
tCALS
tCALS
tCALH
tCKWR
tCALH
tWRCK
Dout
0
Dout
N-3
Dout
N-2
Dout
N-1
Dout
N
1
1
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Synchronous Interface Timing Diagrams
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Figure 89: CHANGE READ COLUMN
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
Don’t Care
tCAD
tCAD
tCAD
DQS
05h Col
add 1 Col
add 2 E0h
tDQSD
Dout
C+1 Dout
D-2
Dout
CDout
D-1 Dout
D
tDQSHZ
tRHW
tDQSCK
tCALS
tCCS
tRHW
Driven
tCALS
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Synchronous Interface Timing Diagrams
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Figure 90: READ PAGE CACHE SEQUENTIAL (1 of 2)
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
tR
tDQSD
tWB
Don’t Care
tDQSHZ
DQS
30h
tRHW
tDQSCK
31h
tRCBSY
tWB tWB
31h
tRCBSY
Data Output
tDQSD
Driven
Initial Read
Access
Sequential
Read Access A
Sequential
Read Access B
Initial
Read Data
1
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Synchronous Interface Timing Diagrams
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© 2010 Micron Technology, Inc. All rights reserved.
Figure 91: READ PAGE CACHE SEQUENTIAL (2 of 2)
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
Don’t Care
DQS
tRCBSY tWB tRCBSY
tDQSD
tDQSHZ
tRHW
tDQSCK
Data Output 3Fh
tDQSD
tDQSHZ
tRHW
tDQSCK
Data Output
Driven
Sequential
Read Data A
Sequential
Read Data B
1
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Synchronous Interface Timing Diagrams
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© 2010 Micron Technology, Inc. All rights reserved.
Figure 92: READ PAGE CACHE RANDOM (1 of 2)
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
tR
tDQSD
tWB
tDQSHZ
DQS
30h
tRHW
tDQSCK
tRCBSY
tWB
tCAD x 4
00h
tWB
tCAD
31h
tRCBSY
5 Address
Cycles
Data Output
Don’t Care Driven
tRHW tCAD x 4
00h
tCAD
31h
5 Address
Cycles
Initial Read
Access
Random
Read Access A
Random
Read Access B
Initial
Read Data
1
Figure 93: READ PAGE CACHE RANDOM (2 of 2)
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
Don’t Care
DQS
tCAD x 4
tWB
31h
tRCBSY tWB tRCBSY
tDQSD
tDQSHZ
tRHW
tDQSCK
Data Output 3Fh
tDQSD
tDQSHZ
tRHW
tDQSCK
Data Output
Driven
Random
Read Access B
Random
Read Data A
Random
Read Data B
1
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Synchronous Interface Timing Diagrams
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Figure 94: Multi-Plane Read Page (1 of 2)
CLK
W/R#
CE#
ALE
CLE
RDY
DQx
DQS
tWB
tDBSY
32h
tCAD x 5
tCAD
Address A
5 Cycles
00h
tWB tR
tDQSD
tCAD x 5
06h
tCAD
Address B
5 Cycles
tCALS
E0h
00h
tCAD
Address B
5 Cycles
tCAD x 5
30h
tDQSCK
tRHW
Data A
Output
tDQSHZ
If data from a plane other than A is desired, a 06h-E0h command sequence
is required after tR and prior to taking W/R# LOW.
12
tCALS
Don’t Care Driven
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© 2010 Micron Technology, Inc. All rights reserved.
Figure 95: Multi-Plane Read Page (2 of 2)
W/R#
W/R#
2 3
CLK
CE#
ALE
CLE
RDY
DQx
DQS
E0h
tDQSD
tDQSHZ
tDQSCK
Data B
Output 06h
tCAD
Address A
5 Cycles
tRHW tCAD x 5
E0h
tDQSD tDQSCK
3
CLK
CE#
ALE
CLE
RDY
DQx
DQS
tDQSHZ
tDQSCK
Data A
Output 06h
tCAD
Address B
5 Cycles
tRHW tCAD x 5
E0h
tDQSD
tDQSHZ
tDQSCK
Data B
Output
tRHW
Don’t CareUndefined (driven by NAND)
tCCS
tCCS
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Figure 96: PROGRAM PAGE Operation (1 of 2)
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
tADL
80h Col
add 1 Col
add 2 Row
add 1 Row
add 2 Row
add 3 Din
N+1 Din
M-2
tCAD
tCS
tCAD tCAD
tCAD
tCAD tCAD
Din
NDin
M-1 Din
M
DQS
tCALS
tCALS
tDQSS
Don’t Care Driven
1
Figure 97: PROGRAM PAGE Operation (2 of 2)
Don’t Care Driven
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
READ STATUS
command
Din
N+1 Din
M-2 70h10h
tPROG tWHR
tWB
Din
NDin
M-1 Din
M
tCAD
DQS
tCALS
tDQSS
tDQSD
tRHW
tCAD
tCKWR
tDQSHZ
Status Status
1
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Synchronous Interface Timing Diagrams
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Figure 98: CHANGE WRITE COLUMN
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
tCCS
85h Col
add 1 Col
add 2 Din
C+1
tCAD
tCAD tCAD
Din
C
DQS
tDQSS
Din
N+1 Din
M-2 Din
M-1 Din
M
tCALS
Don’t Care Driven
tCALS
1
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
tCCS
85h Col
add 1 Col
add 2 Din
C+1 Din
D-2
tCAD
tCAD tCAD
Din
CDin
D-1 Din
D
DQS
tDQSS tCAD
tCALS tCALS
1
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Figure 99: Multi-Plane Program Page
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
DQS
80h
tCAD
tCAD
tCAD x 4 + tADL
Address A
5 Cycles
tDQSS
11h
tCAD
Data A
tCALS
tCALS
tDBSY
tWB
80h
tCAD
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
DQS
tCAD x 4 + tADL tDQSS
1
1
Address B
5 Cycles
70h
10h
tPROG tWHR
tWB
tCAD
tDQSD
tCAD
tRHW
tDQSHZ
Status Status
Data B
Address B
5 Cycles
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Synchronous Interface Timing Diagrams
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Figure 100: ERASE BLOCK
CLK
CE#
ALE
CLE
W/R#
RDY
DQ[7:0]
tCAD
60h
tBERS
tWB
Don’t Care
tCAD
tCS
tCAD tCAD tCAD
DQS
D0h
Row
add 1 Row
add 2 Row
add 3
READ STATUS
command
70h
tWHR
Status Status
tDQSD tDQSHZ
tRHW
tCAD
Driven
Figure 101: COPYBACK (1 of 3)
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
DQS
tCAD x 5
00h
tWB
tCAD
35h
or 30h
tR
5 Address
Cycles
tDQSD
tDQSHZ
tDQSCK
Data
Output 05h
tCAD tCADx2
E0h
2 Address
Cycles
tRHW
1
Don’t Care Driven
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Synchronous Interface Timing Diagrams
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Figure 102: COPYBACK (2 of 3)
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
DQS
h
tDQSD
Data
Output
tDQSCK
tRHW
tDQSHZ
tCAD x 5
85h
tCAD
5 Address
Cycles 85h
tCAD tCAD + tADL
2 Address
Cycles Data
tCALS
tCALS
tDQSS
1 2
Don’t Care Driven
Figure 103: COPYBACK (3 of 3)
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
DQS
70h10h
tPROG tWHR
tWB
Don’t Care
tCAD
Status Status
tDQSD
tDQSHZ
tCAD
tRHW
Driven
2
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Synchronous Interface Timing Diagrams
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Figure 104: READ OTP PAGE
CLK
CE#
ALE
CLE
W/R#
R/B#
DQx
tCAD
00h Col
add 1 Col
add 2
tR
tDQSD
tWB
Don’t Care
tCAD
tCS
tCAD tCAD
tCAD
tCAD tCAD
Dout
0Dout
N
tDQSHZ
DQS
30h
tRHW
tCALS
tCALS
tDQSCK
tCALS
tCALS
Dout
N-1
Driven
Dout
N-2
Dout
N-3
tCALH
tCKWR
tCALH
00h 00h
OTP
page1
tWRCK
Micron Confidential and Proprietary
16Gb, 32Gb Asynchronous/Synchronous NAND
Synchronous Interface Timing Diagrams
PDF: 09005aef841356b0
L72A_16Gb_32Gb_Async_Sync_NAND.pdf – Rev. E 9/12 EN 144 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Figure 105: PROGRAM OTP PAGE (1 of 2)
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
tADL
80h Col
add 1 Col
add 2 Din
N+1 Din
M-2
Don’t Care
tCAD
tCS
tCAD tCAD
tCAD
tCAD tCAD
Din
NDin
M-1 Din
M
DQS
tCALS
tCALS
tDQSS
00h 00h
OTP
page1
Driven 1
Figure 106: PROGRAM OTP PAGE (2 of 2)
Don’t Care Driven Transitioning
CLK
CE#
ALE
CLE
W/R#
RDY
DQx
READ STATUS
command
Din
M-2 70h10h
tPROG tWHR
tWB
Din
M-1 Din
M
tCAD
DQS
tCALS
tDQSD
tRHW
tCAD
tCKWR
OTP data written
(following "pass"
status confirmation)
tDQSHZ
1
Status Status
Micron Confidential and Proprietary
16Gb, 32Gb Asynchronous/Synchronous NAND
Synchronous Interface Timing Diagrams
PDF: 09005aef841356b0
L72A_16Gb_32Gb_Async_Sync_NAND.pdf – Rev. E 9/12 EN 145 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Figure 107: PROTECT OTP AREA
CLK
CE#
ALE
CLE
W/R#
RDY
DQ[7:0] 80h Col
00h Col
00h 00h
tDQSS
tCAD tCAD tCAD
tCAD
tCAD tCAD tADL
DQS
00h01h 00h
Don’t Care Driven Transitioning
CLK
CE#
ALE
CLE
W/R#
RDY
DQ[7:0]
READ STATUS
command
70h10h
tPROG tWHR
tWB
tCAD
DQS
tDQSD
tDQSHZ
tRHW
tCAD
Status Status
1
1
tCALS
tCALS
Micron Confidential and Proprietary
16Gb, 32Gb Asynchronous/Synchronous NAND
Synchronous Interface Timing Diagrams
PDF: 09005aef841356b0
L72A_16Gb_32Gb_Async_Sync_NAND.pdf – Rev. E 9/12 EN 146 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
Revision History
Rev. E Production – 9/12
• Removed polyimide wafer process option from part numbering
Rev. D Production – 5/12
• Added polyimide wafer process option to part numbering
• Updated the Output Drive Strength Conditions table so that range labels (min & max)
match the ONFI definition
• Changed the Output Drive Strength Conditions table to show minimum temperature
as TA (MIN) and maximum temperature as TA (MAX)
Rev. C Production – 3/11
• Noted synchronous TSOP support to synchronous timing mode 4
• Corrected clock rate to match timing mode on features page
• Corrected READ ID table values
• Updated parameter page capacitance values, rev, and CRC
• Updated Drive Strength Impedance table
• Updated DC Characteristics (Sync) table, Icc4R/W_5, from 10/20 to 20/27 (typ/max)
• Added device reset time to Array Characteristics table
Rev. B – 2/11
• Updated features page to show synchronous timing mode 4 (reflects parameter page)
• Added synchronous devices (updated title and features page, part numbering figure,
READ ID table, and parameter page table)
• Changed tPROG MAX from 2500µs to 2600µs
• Changed tBERS from 3ms to 3.8ms
• Changed ICC4, I/O burst current, from 5mA to 8mA
• Updated CIN and CIO capacitance values
Rev. A – 7/10
• Initial release.
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www.micron.com/productsupport Customer Comment Line: 800-932-4992
Micron and the Micron logo are trademarks of Micron Technology, Inc.
All other trademarks are the property of their respective owners.
This data sheet contains minimum and maximum limits specified over the power supply and temperature range set forth herein.
Although considered final, these specifications are subject to change, as further product development and data characterization some-
times occur.
Micron Confidential and Proprietary
16Gb, 32Gb Asynchronous/Synchronous NAND
Revision History
PDF: 09005aef841356b0
L72A_16Gb_32Gb_Async_Sync_NAND.pdf – Rev. E 9/12 EN 147 Micron Technology, Inc. reserves the right to change products or specifications without notice.
© 2010 Micron Technology, Inc. All rights reserved.
