© Semiconductor Components Industries, LLC, 2012
August, 2018 − Rev. 5 1Publication Order Number:
ADP3120A/D
ADP3120A
Dual Bootstrapped, 12 V
MOSFET Driver with Output
Disable
The ADP3120A is a single Phase 12 V MOSFET gate drivers
optimized to drive the gates of both high−side and low−side power
MOSFETs in a synchronous buck converter. The high−side and
low−side driver is capable of driving a 3000 pF load with a 45 ns
propagation delay and a 25 ns transition time.
With a wide operating voltage range, high or low side MOSFET
gate drive voltage can be optimized for the best efficiency. Internal
adaptive nonoverlap circuitry further reduces switching losses by
preventing simultaneous conduction of both MOSFETs.
The floating top driver design can accommodate VBST voltages as
high as 3 5 V, with transient voltages as high as 40 V. Both gate outputs
can be driven low by applying a low logic level to the Output Disable
(OD) pin. An Undervoltage Lockout function ensures that both driver
outputs are low when the supply voltage is low, and a Thermal
Shutdown function provides the IC with overtemperature protection.
Features
•All−In−One Synchronous Buck Driver
•Bootstrapped High−Side Drive
•One PWM Signal Generates Both Drives
•Anticross Conduction Protection Circuitry
•OD for Disabling the Driver Outputs Meets CPU VR Requirement
when Used with Patented FlexModet Controller
•These are Pb−Free Devices
Applications
•Multiphase Desktop CPU Supplies
•Single−Supply Synchronous Buck Converters
A = Assembly Location
L = Wafer Lot
Y = Year
W = Work Week
G= Pb−Free Package
MARKING
DIAGRAMS
PIN CONNECTIONS
SO−8
D SUFFIX
CASE 751
1
8
DRVLVCC
18
PGNDOD SWNIN DRVHBST
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†For information on tape and reel specifications,
including part orientation and tape sizes, please
refer to our Tape and Reel Packaging Specification
Brochure, BRD8011/D.
3120A
ALYW
G
1
8
DFN8
MN SUFFIX
CASE 506BJ
DRVLVCC
PGNDOD SWNIN DRVHBST
(Top View)
18
1
L3C
ALYWG
G
1
8
Device Package Shipping†
ORDERING INFORMATION
SO−8
(Pb−Free) 98 Units / RailADP3120AJRZ
SO−8
(Pb−Free) 2500 / Tape &
Reel
ADP3120AJRZ−RL
DFN8
(Pb−Free) 3000 / Tape &
Reel
ADP3120AJCPZ−RL
ADP3120A
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2
Figure 1. Block Diagram
8
1
4
7
5
6
2
3
VCC
DRVH
BST
SWN
DRVL
PGND
OD
IN
TSD
UVLO
VCC
MONITOR
FALLING
EDGE
DELAY
MONITOR
FALLING
EDGE
DELAY
NON−OVERLAP
TIMERS
MIN DRVL
OFF TIMER
START STOP
PIN DESCRIPTION
SO−8 DFN8 Symbol Description
1 1 BST Upper MOSFET Floating Bootstrap Supply. A capacitor connected between BST and SW pins holds
this bootstrap voltage for the high−side MOSFET as it is switched. The recommended capacitor value
is between 100 nF and 1.0 mF. An external diode is required with the ADP3120A.
2 2 IN Logic−Level Input. This pin has primary control of the drive outputs.
3 3 OD Output Disable. When low, normal operation is disabled forcing DRVH and DRVL low.
4 4 VCC Input Supply. A 1.0 mF ceramic capacitor should be connected from this pin to PGND.
5 5 DRVL Output drive for the lower MOSFET.
6 6 PGND Power Ground. Should be closely connected to the source of the lower MOSFET.
7 7 SWN Switch Node. Connect to the source of the upper MOSFET.
8 8 DRVH Output drive for the upper MOSFET.
ADP3120A
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MAXIMUM RATINGS
Rating Value Unit
Operating Ambient Temperature, TA−20 to 85 °C
Operating Junction Temperature, TJ (Note 1) −20 to 150 °C
Package Thermal Resistance: SO−8
Junction−to−Case, RqJC
Junction−to−Ambient, RqJA (2−Layer Board)
Package Thermal Resistance: DFN8 (Note 2)
Junction−to−Case, RqJC (From die to exposed pad)
Junction−to−Ambient, RqJA
45
123
7.5
55
°C/W
°C/W
°C/W
°C/W
Storage Temperature Range, TS−65 to 150 °C
Lead Temperature Soldering (10 sec): Reflow (SMD styles only) Pb−Free (Note 3) 260 peak °C
JEDEC Moisture Sensitivity Level SO−8 (260 peak profile) 1 −
Stresses exceeding those listed in the Maximum Ratings table may damage the device. If any of these limits are exceeded, device functionality
should not be assumed, damage may occur and reliability may be af fected.
1. Internally limited by thermal shutdown, 150°C min.
2. 2 layer board, 1 in2 Cu, 1 oz thickness.
3. 60−180 seconds minimum above 237°C.
NOTE: This device is ESD sensitive. Use standard ESD precautions when handling.
MAXIMUM RATINGS
Pin Symbol Pin Name VMAX VMIN
VCC Main Supply Voltage Input 15 V −0.3 V
PGND Ground 0 V 0 V
BST Bootstrap Supply Voltage Input 35 V wrt/PGND
40 V < 50 ns wrt/PGND
15 V wrt/SW
−0.3 V wrt/SW
SW Switching Node
(Bootstrap Supply Return) 35 V
40 V < 50 ns −5.0 V
−10 V < 200 ns
DRVH High−Side Driver Output BST + 0.3 V −0.3 V wrt/SW
−2.0 V < 200 ns wrt/SW
DRVL Low−Side Driver Output VCC + 0.3 V −0.3 V DC
−5.0 V < 200 ns
IN DRVH and DRVL Control Input 6.5 V −0.3 V
OD Output Disable 6.5 V −0.3 V
NOTE: All voltages are with respect to PGND except where noted.
ADP3120A
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ELECTRICAL CHARACTERISTICS (Note 4) (VCC = 12 V, TA = −20°C to +85°C, TJ = 0°C to +125°C unless otherwise noted.)
Characteristic Symbol Condition Min Typ Max Unit
Supply
Supply Voltage Range VCC − 4.6 − 13.2 V
Supply Current ISYS BST = 12 V, IN = 0 V − 0.7 2.0 mA
OD Input
Input Voltage High VOD_HI − 2.0 − − V
Input Voltage Low VOD_LO − − − 0.8 V
Hysteresis − − 400 − mV
Input Current No internal pullup or pulldown resistors −1.0 − +1.0 mA
PWM Input
Input Voltage High VPWM_HI − 2.0 − − V
Input Voltage Low VPWM_LO − − − 0.8 V
Hysteresis − − − 400 − mV
Input Current −No internal pullup or pulldown resistors −1.0 − +1.0 mA
High−Side Driver
Output Resistance, Sourcing Current −BST − SW = 12 V; TA = −20°C to 85°C
BST − SW = 12 V; TA = 25°C− 2.2
−3.9
3.3 W
Output Resistance, Sinking Current −BST − SW = 12 V; TA = −20°C to 85°C
BST − SW = 12 V; TA = 25°C− 1.0
−2.6
1.8 W
Output Resistance, Unbiased −BST − SW = 0 V − 15 − kW
Transition Times trDRVH
tfDRVH BST − SW = 12 V, CLOAD = 3.0 nF
(See Figure 3) − 20
11 40
30 ns
Propagation Delay Times (Note 5) tpdhDRVH
tpdlDRVH
tpdlOD
tpdhOD
BST − SW = 12 V, CLOAD = 3.0 nF
(See Figure 3)
BST − SW = 12 V, CLOAD = 3.0 nF
(See Figure 3)
(See Figure 2)
(See Figure 2)
32 45
25
20
25
70
35
35
55
ns
SW Pulldown Resitance −SW to PGND − 15 − kW
Low−Side Driver
Output Resistance, Sourcing Current − TA = −20°C to 85°C
TA = 25°C− 1.8
−3.9
3.3 W
Output Resistance, Sinking Current − TA = −20°C to 85°C
TA = 25°C− 1.0
−2.6
1.8 W
Output Resistance, Unbiased − VCC = PGND − 15 − kW
Transition Times trDRVL
tfDRVL CLOAD = 3.0 nF, (See Figure 3) − 16
11 35
30 ns
Propagation Delay Times (Note 5) tpdhDRVL
tpdlDRVL
tpdlOD
tpdhOD
CLOAD = 3.0 nF, (See Figure 3)
(Note 6, tpdhDRVL only)
(See Figure 2)
(See Figure 2)
− 12
15
20
20
35
45
35
35
ns
Timeout Delay −DRVH − SW = 0 − 85 − ns
Undervoltage Lockout
UVLO Startup − − 3.9 4.3 4.5 V
UVLO Shutdown − − 3.7 4.1 4.3 V
Hysteresis − − 0.1 0.2 0.4 V
4. All limits at temperature extremes are guaranteed via correlation using standard Statistical Quality Control (SQC).
5. For propagation delays, “tpdh” refers to the specified signal going high; “tpdl” refers to it going low.
6. Guaranteed by design; not tested in production.
ADP3120A
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5
APPLICATIONS INFORMATION
Theory of Operation
The ADP3120A are single phase MOSFET drivers
designed for driving two N−channel MOSFETs in a
synchronous buck converter topology. The ADP3120A will
operate from 5 .0 V o r 1 2 V, but h ave b een o ptimized for h igh
current multi−phase buck regulators that convert 12 V rail
directly to the core voltage required by complex logic chips.
A single PWM input signal is all that is required to properly
drive the h igh−side and t he low−side MOSFETs. Each driver
is capable of driving a 3 n F load at frequencies u p to 1 MHz.
Low−Side Driver
The low−side driver is designed to drive a
ground−referenced low RDS(on) N−Channel MOSFET. The
voltage rail for the low−side driver is internally connected t o
the VCC supply and PGND.
High−Side Driver
The high−side driver is designed to drive a floating low
RDS(on) N−channel MOSFET. The gate voltage for the high
side driver is developed by a bootstrap circuit referenced to
Switch Node (SW) pin.
The bootstrap circuit is comprised of an external diode,
and an external bootstrap capacitor. When the ADP3120A
are starting up, the SW pin is at ground, so the bootstrap
capacitor will char ge up t o VCC through the bootstrap diode
See Figure 4. When the PWM input goes high, the high−side
driver will begin to turn on the high−side MOSFET using the
stored charge of the bootstrap capacitor. As the high−side
MOSFET turns on, the SW pin will rise. When the high−side
MOSFET is fully on, the switch node will be at 12 V, and the
BST pin will be at 12 V plus the charge of the bootstrap
capacitor (approaching 24 V).
The bootstrap capacitor is recharged when the switch
node goes low during the next cycle.
Safety Timer and Overlap Protection Circuit
It is very important that MOSFETs in a synchronous buck
regulator do not both conduct at the same time. Excessive
shoot−through or cross conduction can damage the
MOSFETs, and even a small amount of cross conduction
will cause a decrease in the power conversion efficiency.
The ADP3120A prevent cross conduction by monitoring
the status of the external mosfets and applying the
appropriate amount of “dead−time” or the time between the
turn off of one MOSFET and the turn on of the other
MOSFET.
When the PWM input pin goes high, DRVL will go low
after a propagation delay (tpdlDRVL). The time it takes for
the low−side MOSFET to turn off (tfDRVL) is dependent on
the total charge on the low−side MOSFET gate. The
ADP3120A monitor the gate voltage of both MOSFETs and
the switchnode voltage to determine the conduction status of
the MOSFETs. Once the low−side MOSFET is turned off an
internal timer will delay (tpdhDRVH) the turn on of the
high−side MOSFET
Likewise, when the PWM input pin goes low, DRVH will
go low after the propagation delay (tpdDRVH). The time to
turn off the high−side MOSFET (tfDRVH) is dependent on
the total gate charge of the high−side MOSFET. A timer will
be triggered once the high−side mosfet has stopped
conducting, to delay (tpdhDRVL) the turn on of the
low−side MOSFET
Power Supply Decoupling
The ADP3120A can source and sink relatively large
currents to the gate pins of the external MOSFETs. In order
to maintain a constant and stable supply voltage (VCC) a low
ESR capacitor should be placed near the power and ground
pins. A 1 mF to 4.7 mF multi layer ceramic capacitor (MLCC)
is usually sufficient.
Input Pins
The PWM input and the Output Disable pins of the
ADP3120A have internal protection for Electro Static
Discharge (ESD), but in normal operation they present a
relatively high input impedance. If the PWM controller does
not have internal pulldown resistors, they should be added
externally to ensure that the driver outputs do not go high
before the controller has reached its under voltage lockout
threshold. The NCP5381 controller does include a passive
internal pulldown resistor on the drive−on output pin.
Bootstrap Circuit
The bootstrap circuit uses a charge storage capacitor
(CBST) and the internal (or an external) diode. Selection of
these components can be done after the high−side MOSFET
has been chosen. The bootstrap capacitor must have a
voltage rating that is able to withstand twice the maximum
supply voltage. A minimum 50 V rating is recommended.
The capacitance is determined using the following equation:
CBST +QGATE
DVBST
where QGATE is the total gate charge of the high−side
MOSFET, and DVBST is the voltage droop allowed on the
high−side MOSFET drive. For example, a NTD60N03 has
a total gate charge of about 30 nC. For an allowed droop of
300 mV, the required bootstrap capacitance is 100 nF. A
good quality ceramic capacitor should be used.
The bootstrap diode must be rated to withstand the
maximum supply voltage plus any peak ringing voltages
that may be present on SW. The average forward current can
be estimated by:
IF(AVG) +QGATE fMAX
where fMAX is the maximum switching frequency of the
controller. The peak surge current rating should be checked
in−circuit, since this is dependent on the source impedance
of the 12 V supply and the ESR of CBST.
ADP3120A
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6
Figure 2. Output Disable Timing Diagram
10%
90%
DRVH
or
DRVL
OD
tpdlOD tpdhOD
VOD_HI
VOD_LO
Figure 3. Nonoverlap Timing Diagram
90%
10%
10%
90%
90%
10%
10%
90%
2V
2V
DRVL
tpdlDRVL tfDRVL
tpdhDRVH trDRVH tpdlDRVH tfDRVH trDRVL
tpdhDRVL
DRVH−SW
SW
IN
VPWM_HI
VPWM_LO
ADP3120A
4
3
25
6
7
8
1
Vcc
OD
IN DRVL
PGND
SW
DRVH
BST
Vout
12 V
Output Enable
12 V
PWM in
Figure 4. ADP3120A Example Circuit
ADP3120A
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7
PACKAGE DIMENSIONS
ÇÇÇ
ÇÇÇ
ÇÇÇ
ÇÇÇ
DFN8 3x3, 0.5P
CASE 506BJ
ISSUE O
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERMASK DEFINED
PIN 1
REFERENCE
A
B
C0.10
2X
2X
TOP VIEW
D
E
C0.10
NOTES:
1. DIMENSIONS AND TOLERANCING PER ASME
Y14.5M, 1994.
2. CONTROLLING DIMENSION: MILLIMETERS.
3. DIMENSION b APPLIES TO PLATED TERMINAL
AND IS MEASURED BETWEEN 0.15 AND 0.30
MM FROM TERMINAL.
4. COPLANARITY APPLIES TO THE EXPOSED
PAD AS WELL AS THE TERMINALS.
E2
BOTTOM VIEW
b
0.10
8X
L14
0.05
CAB
C
D2
e
K
85
8X
8X
(A3) C
C0.05
8X
C0.05
SIDE VIEW A1
A
SEATING
PLANE
DIM MIN MAX
MILLIMETERS
A0.80 1.00
A1 0.00 0.05
A3 0.20 REF
b0.18 0.30
D3.00 BSC
D2 1.64 1.84
E3.00 BSC
E2 1.35 1.55
e0.50 BSC
K0.20 −−−
L0.30 0.50
NOTE 3
L
DETAIL A
OPTIONAL
CONSTRUCTION
L1
DETAIL A
ÉÉ
ÉÉ
ÉÉ
DETAIL B
EDGE OF PACKAGE
MOLD CMPD
EXPOSED Cu
L
OPTIONAL
CONSTRUCTION
OPTIONAL
CONSTRUCTION
L1 0.00 0.03
NOTE 4
DETAIL B
3.30
8X
DIMENSION: MILLIMETERS
0.63
1.55
1.85
0.50
PITCH
8X
0.35
MOUNTING FOOTPRINT
DET AIL A
ADP3120A
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8
PACKAGE DIMENSIONS
SOIC−8
D SUFFIX
CASE 751−07
ISSUE AK
1.52
0.060
7.0
0.275
0.6
0.024 1.270
0.050
4.0
0.155
ǒmm
inchesǓ
SCALE 6:1
*For additional information on our Pb−Free strategy and soldering
details, please download the ON Semiconductor Soldering and
Mounting Techniques Reference Manual, SOLDERRM/D.
SOLDERING FOOTPRINT*
SEATING
PLANE
1
4
58
N
J
X 45_
K
NOTES:
1. DIMENSIONING AND TOLERANCING PER
ANSI Y14.5M, 1982.
2. CONTROLLING DIMENSION: MILLIMETER.
3. DIMENSION A AND B DO NOT INCLUDE
MOLD PROTRUSION.
4. MAXIMUM MOLD PROTRUSION 0.15 (0.006)
PER SIDE.
5. DIMENSION D DOES NOT INCLUDE DAMBAR
PROTRUSION. ALLOWABLE DAMBAR
PROTRUSION SHALL BE 0.127 (0.005) TOTAL
IN EXCESS OF THE D DIMENSION AT
MAXIMUM MATERIAL CONDITION.
6. 751−01 THRU 751−06 ARE OBSOLETE. NEW
STANDARD IS 751−07.
A
BS
D
H
C
0.10 (0.004)
DIM
AMIN MAX MIN MAX
INCHES
4.80 5.00 0.189 0.197
MILLIMETERS
B3.80 4.00 0.150 0.157
C1.35 1.75 0.053 0.069
D0.33 0.51 0.013 0.020
G1.27 BSC 0.050 BSC
H0.10 0.25 0.004 0.010
J0.19 0.25 0.007 0.010
K0.40 1.27 0.016 0.050
M0 8 0 8
N0.25 0.50 0.010 0.020
S5.80 6.20 0.228 0.244
−X−
−Y−
G
M
Y
M
0.25 (0.010)
−Z−
Y
M
0.25 (0.010) ZSXS
M
____
ADP3120A/D
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