General Description
The MAX14986 dual-channel redriver is designed to
redrive one full lane of SAS or SATA signals up to 6.0GT/s
(gigatransfers per second) and operates from a single
+3.3V supply.
The MAX14986 features independent input equalization
and output preemphasis. It enhances signal integrity at
the receiver by equalizing the signal at the input and
establishing preemphasis at the output of the device. SAS
and SATA OOB (out-of-band) signaling is supported using
high-speed amplitude detection on the inputs and squelch
on the corresponding outputs. Inputs and outputs are all
internally 50Ω terminated and must be AC-coupled to the
SAS/SATA controller IC and SAS/SATA device.
The MAX14986 is available in a small 28-pin, 3.5mm x
5.5mm TQFN package with flow-through traces for ease
of layout. This device is specified over the -40°C to +85°C
extended operating temperature range.
Applications
● Industrial/Embedded PCs
● Computer on Modules
● Carrier Boards
● Test Equipment
● Rack Server Industrial PCs
● Medical Equipment
Benets and Features
● High-Performance Solution Designed to Overcome
Lossy Channels
• 3dB of Independent (per Channel) Selectable Input
EQ and Output Preemphasis
• Compensates Up to 30in of Channel Losses with
Deterministic Jitter: 23psP-P (max); Random Jitter:
1.5psRMS (max)
• 8dB (typ) of Return Loss Up to 3.0GHz
● Designed to Reliably Operate in Harsh Environments
• Industrial Temperature Rated: -40°C to +85°C
• ±2.5kV Human Body Model (HBM) ESD Protection
on All Pins
• Housed in a Flow-Through (3.5mm x 5.5mm,
28-Pin) TQFN Package for Resistance to
Vibration/Shocks
● Ease of Design and Layout
• Single 3.3V Operation
• Internal Input/Output 50Ω Termination Resistors
on All Pins
• Flow-Through Pinout
Pin Conguration
Ordering Information appears at end of data sheet.
For related parts and recommended products to use with this part, refer
to www.maximintegrated.com/MAX14986.related.
19-6639; Rev 0; 3/13
TOP VIEW
MAX14986
TQFN
11
*EP
12
13
14
EQ0
PE0
EQ1
PE1
28 +
27
26
25
GND
GND
GND
GND
12345678910
24 23 22 21 20 19
*CONNECT EXPOSED PAD (EP) TO GND.
18 17 16 15
EN
VCC
GND
OUT1M
OUT1P
GND
IN0M
IN0P
GND
VCC
VCC
GND
IN1M
IN1P
MODE
GND
OUT0M
OUT0P
GND
VCC
MAX14986 Dual 6GT/s SAS/SATA Redriver
with Equalization and Extended
Temperature Operation
(Voltages referenced to GND.)
VCC .......................................................................-0.3V to +4.0V
All Other Pins ............................................. -0.3V to (VCC+ 0.3V
Continuous Current (PE_, EQ_, MODE) ..........................±15mA
Peak Current (for 10kHz, 1% duty cycle)
(IN__, OUT__) ............................................................... ±100A
Continuous Power Dissipation (TA= +70°C)
TQFN (derate 28.6mW/°C above +70°C)..................2286mW
Operating Temperature Range ........................... -40°C to +85°C
Storage Temperature Range ............................ -55°C to +150°C
Junction Temperature ........................................................ +15°C
Lead Temperature (soldering, 10s) .................................+300°C
Soldering Temperature (reflow) ....................................... +260°C
Junction-to-Ambient Thermal Resistance (θJC) .............2.7°C/W
Junction-to-Ambient Thermal Resistance (θJA) ..............35°C/W
(Note 1)
(VCC = +3.0V to +3.6V, CCOUPLE = 12nF, RL = 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V,
TA = +25°C.) (Note 2)
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Operating Power-Supply Range VCC 3.0 3.6 V
Operating Supply Current ICC EQ_ = PE_ = GND 140 175 mA
EQ_ = PE_ = VCC 175 220
Standby Supply Current ISTBY EN = GND 16 20 mA
Input Termination RRX-SE Single-ended to VCC 42.5 57.5 Ω
Output Termination RTX-SE Single-ended to VCC 42.5 57.5 Ω
AC PERFORMANCE
Differential Input Return Loss
(Note 3) SDD11
0.1GHz ≤ f ≤ 0.3GHz -10
dB0.3GHz ≤ f ≤ 3.0GHz -7.9
3.0GHz ≤ f ≤ 6.0GHz 0
Common-Mode Input Return Loss
(Note 3) SCC11
0.1GHz ≤ f ≤ 0.3GHz -6
dB0.3GHz ≤ f ≤ 3.0GHz -5
3.0GHz ≤ f ≤ 6.0GHz 0
Differential Output Return Loss
(Note 3) SDD22
0.1GHz ≤ f ≤ 0.3GHz -10
dB0.3GHz ≤ f ≤ 3.0GHz -7.9
3.0GHz ≤ f ≤ 6.0GHz 0
Common-Mode Output Return
Loss (Note 3) SCC22
0.1GHz ≤ f ≤ 0.3GHz -6
dB0.3GHz ≤ f ≤ 3.0GHz -4
3.0GHz ≤ f ≤ 6.0GHz 0
Differential Input Voltage VIN-DIFF SAS 1.5, 3.0, or 6.0GT/s MODE = GND 275 1600 mVP-P
SATA 1.5, 3.0, or 6.0GT/s MODE = VCC 225 1600
Input Equalization EQ EQ_ = VCC (Note 4) 3 dB
Differential Output Voltage VOUT-DIFF f = 750MHz, PE_ = GND 750 1200 mVP-P
Note 1: Package thermal resistances were obtained using the method described in JEDEC specification JESD51-7, using a four-layer
board. For detailed information on package thermal considerations, refer to www.maximintegrated.com/thermal-tutorial.
Absolute Maximum Ratings
Stresses beyond those listed under “Absolute Maximum Ratings” may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these
or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect
device reliability.
Electrical Characteristics
Package Thermal Characteristics
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2
MAX14986 Dual 6GT/s SAS/SATA Redriver
with Equalization and Extended
Temperature Operation
(VCC = +3.0V to +3.6V, CCOUPLE = 12nF, RL = 50Ω, TA = -40°C to +85°C, unless otherwise noted. Typical values are at VCC = +3.3V,
TA = +25°C.) (Note 2)
Note 2: All devices are 100% production tested at TA= +85°C. All temperature limits are guaranteed by design.
Note 3: Guaranteed by design.
Note 4: EQ (input equalization) as employed in this device refers to the equivalent of adding preemphasis before the input. For
example, input EQ of 3dB would show the same waveform as output PE of 3dB (see Figure 1).
Figure 1. Output Preemphasis
VLOW_PP VHIGH_PP
PE(dB) = 20log
[( )]
VHIGH_PP
VLOW_PP
PARAMETER SYMBOL CONDITIONS MIN TYP MAX UNITS
Output Preemphasis PE PE_ = VCC, Figure 1 3 dB
Propagation Delay tPD PE_ = EQ_ = GND 300 ps
Output Transition Time TTX-RF PE_ = GND, 20% to 80% 30 ps
Differential Output Skew Same Pair TSK 10 ps
Deterministic Jitter TDJ K28.5 pattern, 6.0GT/s, PE_ = EQ_ = GND
(Note 3) 23 psP-P
Random Jitter TRJ D10.2 pattern, 6.0GT/s, PE_ = EQ_ = GND 1.5 psRMS
OOB Squelch Threshold VSQ-DIFF MODE = GND, f = 0.75GHz 120 220 mVP-P
MODE = VCC, f = 0.75GHz 75 200
OOB Squelch Entry Time TOOB,SQ f = 0.75GHz (Note 3) 5 ns
OOB Squelch Exit Time TOOB,EX f = 0.75GHz (Note 3) 9 ns
OOB Differential Offset Delta ∆VOOB,DIFF Difference between OOB and active-mode
output offset -50 +50 mV
OOB Common-Mode Offset Delta ∆VOOB,CM Difference between OOB and active-mode
output common-mode voltage -30 +30 mV
OOB Output Disable VOOB,OUT OOB disabled output level 30 mVP-P
CONTROL LOGIC INPUTS
Input Logic-High VIH 1.4 V
Input Logic-Low VIL 0.6 V
Input Logic Hysteresis VHYST 75 mV
Input Leakage Current IIN VCC = +3.3V, VIN = +0.5V or +1.5V -50 +50 µA
Electrical Characteristics (continued)
Timing Diagram
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MAX14986 Dual 6GT/s SAS/SATA Redriver
with Equalization and Extended
Temperature Operation
(VCC = +3.3V, TA = +25°C, all eye diagrams measured using K28.5 pattern.)
VIN = 275mVP-P, 1.5Gbps, PE = 0, EQ = 0
200ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
4002000-200-400
-400
-200
0
200
400
MAX14986 toc01
VIN = 275mVP-P, 3Gbps, PE = 0, EQ = 0
100ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
2001000-100-200
-400
-200
0
200
400
MAX14986 toc02
VIN = 275mVP-P, 6Gbps, PE = 0, EQ = 0
50ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
100500-50-100
-400
-200
0
200
400
MAX14986 toc03
600
-600
VIN = 275mVP-P, 1.5Gbps, PE = 1, EQ = 0
200ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
400200-400 -200 0
-600
-400
-200
0
200
400
600
800
-800
MAX14986 toc04
VIN = 275mVP-P, 3Gbps, PE = 1, EQ = 0
100ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
200100-200 -100 0
-600
-400
-200
0
200
400
600
800
-800
MAX14986 toc05
VIN = 275mVP-P, 6Gbps, PE = 1, EQ = 0
50ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
10050-100 -50 0
-600
-400
-200
0
200
400
600
800
-800
MAX14986 toc06
VIN = 1600mVP-P, 1.5Gbps, PE = 0, EQ = 0
200ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
4002000-200-400
-400
-200
0
200
400
MAX14986 toc07
600
-600
Typical Operating Characteristics
Maxim Integrated
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MAX14986 Dual 6GT/s SAS/SATA Redriver
with Equalization and Extended
Temperature Operation
(VCC = +3.3V, TA = +25°C, all eye diagrams measured using K28.5 pattern.)
VIN = 1600mVP-P, 3Gbps, PE = 0, EQ = 0
100ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
2001000-100-200
-400
-200
0
200
400
MAX14986 toc08
600
-600
VIN = 1600mVP-P, 6Gbps, PE = 0, EQ = 0
50ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
100500-50-100
-400
-200
0
200
400
MAX14986 toc09
600
-600
VIN = 1600mVP-P, 1.5Gbps, PE = 1, EQ = 0
200ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
400200-400 -200 0
-600
-400
-200
0
200
400
600
800
-800
MAX14986 toc10
VIN = 1600mVP-P, 3Gbps, PE = 1, EQ = 0
100ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
200100-200 -100 0
-600
-400
-200
0
200
400
600
800
-800
MAX14986 toc11
VIN = 1600mVP-P, 6Gbps, PE = 1, EQ = 0
50ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
10050-100 -50 0
-600
-400
-200
0
200
400
600
800
-800
MAX14986 toc12
VIN = 500mVP-P WITH 20in FR4 STRIPLINE,
3GT/s, PE = 0, EQ = 0
100ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
200100-200 -100 0
-600
-400
-200
0
200
400
600
MAX14986 toc13
-300 300
VIN = 500mVP-P WITH 20in FR4 STRIPLINE,
6GT/s, PE = 0, EQ = 0
50ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
10050-100 -50 0
-600
-400
-200
0
200
400
600
MAX14986 toc14
-150 150
Typical Operating Characteristics (continued)
Maxim Integrated
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MAX14986 Dual 6GT/s SAS/SATA Redriver
with Equalization and Extended
Temperature Operation
(VCC = +3.3V, TA = +25°C, all eye diagrams measured using K28.5 pattern.)
VIN = 500mVP-P WITH 20in FR4 STRIPLINE,
3GT/s, PE = 0, EQ = 1
100ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
200100-200 -100 0
-600
-400
-200
0
200
400
600
MAX14986 toc15
-300 300
VIN = 500mVP-P WITH 20in FR4 STRIPLINE,
6GT/s, PE = 0, EQ = 1
50ps/div
EYE DIAGRAM VOLTAGE (200mV/div)
10050-100 -50 0
-600
-400
-200
0
200
400
600
MAX14986 toc16
-150 150
VIN = 275mVP-P, 3GT/s, PE = 0, EQ = 0,
OUTPUT AFTER 20in FR4 STRIPLINE
100ps/div
EYE DIAGRAM VOLTAGE (100mV/div)
2001000-100-200
-500
-400
-300
-200
-100
0
100
200
300
400
500
-300 300
MAX4952A toc17
VIN = 275mVP-P, 6GT/s, PE = 0, EQ = 0,
OUTPUT AFTER 20in FR4 STRIPLINE
50ps/div
EYE DIAGRAM VOLTAGE (100mV/div)
100500-50-100
-500
-400
-300
-200
-100
0
100
200
300
400
500
-150 150
MAX4952A toc18
VIN = 275mVP-P, 3GT/s, PE = 1, EQ = 0,
OUTPUT AFTER 20in FR4 STRIPLINE
100ps/div
EYE DIAGRAM VOLTAGE (100mV/div)
2001000-100-200
-500
-400
-300
-200
-100
0
100
200
300
400
500
-300 300
MAX14986 toc19
VIN = 275mVP-P, 6GT/s, PE = 1, EQ = 0,
OUTPUT AFTER 20in FR4 STRIPLINE
50ps/div
EYE DIAGRAM VOLTAGE (100mV/div)
100500-50-100
-500
-400
-300
-200
-100
0
100
200
300
400
500
-150 150
MAX14986 toc20
Typical Operating Characteristics (continued)
Maxim Integrated
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MAX14986 Dual 6GT/s SAS/SATA Redriver
with Equalization and Extended
Temperature Operation
PIN NAME FUNCTION
1, 9, 16, 24 VCC Positive Supply Voltage Input. Bypass VCC to GND with 2.2µF and 0.01µF capacitors in parallel as
close as possible to the device, recommended on each VCC pin.
2, 5, 8,
17, 20, 23,
25–28
GND Ground
3IN0P Noninverting Input 0
4 IN0M Inverting Input 0
6OUT1P Noninverting Output 1
7OUT1M Inverting Output 1
10 EN Active-High Enable Input. Drive EN low to put device in standby mode. Drive EN high for normal
operation. EN is internally pulled down.
11 EQ0 Channel 0 Input Equalizer Logic Input. EQ0 is internally pulled down.
12 PE0 Channel 0 Output Preemphasis Logic Input. PE0 is internally pulled down.
13 EQ1 Channel 1 Input Equalizer Logic Input. EQ1 is internally pulled down.
14 PE1 Channel 1 Output Preemphasis Logic Input. PE1 is internally pulled down.
15 MODE OOB Threshold Logic Input. MODE is internally pulled down.
18 IN1M Inverting Input 1
19 IN1P Noninverting Input 1
21 OUT0M Inverting Output 0
22 OUT0P Noninverting Output 0
—EP Exposed Pad. Internally connected to GND. EP must be electrically connected to a ground plane for
proper thermal and electrical operation. Do not use EP as the sole ground connection.
Pin Description
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MAX14986 Dual 6GT/s SAS/SATA Redriver
with Equalization and Extended
Temperature Operation
MAX14986
50Ω
VCC
50Ω50Ω
VCC
50Ω
IN0P
IN0M
OUT0P
OUT0M
50Ω
VCC
50Ω50Ω
VCC
50Ω
OUT1M
OUT1P
IN1M
IN1P
CONTROL LOGICEN MODE
EQ0 PE0 EQ1 PE1
GND
VCC
MAINBOARDMIDPLANE
CONNECTORS
8in BOARD
TRACES
20in BOARD
TRACES
18in SAS
CABLE
SAS
CONTROLLER
SAS/SATA
HDD
MAX14986
Functional Diagram
Typical Application Circuit
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8
MAX14986 Dual 6GT/s SAS/SATA Redriver
with Equalization and Extended
Temperature Operation
Detailed Description
The MAX14986 consists of two identical redrivers with
input equalization and output preemphasis useful for SAS
or SATA signals up to 6.0GT/s.
Input/Output Terminations
Inputs and outputs are internally 50Ω terminated to VCC
(see the Functional Diagram) and must be AC-coupled
using 12nF (max) capacitors to the SAS/SATA controller
IC and SAS/SATA device for proper operation.
Enable Input (EN)
The MAX14986 features an active-high enable input (EN).
EN has an internal pulldown resistor of 70kΩ (typ). When
EN is driven low or left unconnected, the MAX14986
enters low-power standby mode and the redrivers are
disabled. Drive EN high for normal operation.
Out-of-Band Threshold Selector (MODE)
The MAX14986 provides full OOB signal support through
high-speed amplitude detection circuitry. OOB differential
input signals less than the internal OOB threshold (VSQ-
DIFF) are detected as off and not passed to the output.
This prevents the system from responding to unwanted
noise. OOB differential input signals higher than VSQ-
DIFF are detected as on and passed to the output, allow-
ing OOB signals to transmit through the MAX14986. The
logic level of the MODE input sets VSQ-DIFF for either
SAS or SATA OOB signals (see Table 1). MODE has an
internal pulldown resistor of 70kΩ (typ).
Input Equalization (EQ0, EQ1)
The MAX14986 features control logic inputs (EQ0, EQ1)
to enable input equalization on either channel, providing
3dB of boost (see Note 4 in the Electrical Characteristics
table). Drive EQ0 or EQ1 high to enable input equaliza-
tion on channel 0 or channel 1. Drive EQ0 or EQ1 low to
disable input equalization on channel 0 or channel 1 (see
Table 2). EQ0 and EQ1 have internal pulldown resistors
of 70kΩ (typ).
Output Preemphasis (PE0, PE1)
The MAX14986 features control logic inputs (PE0, PE1)
to enable output preemphasis on either channel, provid-
ing 3dB of boost. The MAX14986 uses true preemphasis,
so the transition signal is increased after a changing bit,
thus increasing the total energy content of the signal
when employed. Drive PE0 or PE1 high to enable output
preemphasis on channel 0 or channel 1. Drive PE0 or
PE1 low to disable output preemphasis on channel 0 or
channel 1 (see Table 3). PE0 and PE1 have internal pull-
down resistors of 70kΩ (typ).
Table 1. Out-of-Band Logic Threshold
(MODE)
Table 2. Input Equalization (EQ0, EQ1)
Table 3. Output Preemphasis (PE0, PE1)
PE1 PE0 CHANNEL 1
(dB)
CHANNEL 0
(dB)
0 0 0 0
0 1 0 3 (typ)
1 0 3 (typ) 0
1 1 3 (typ) 3 (typ)
EQ1 EQ0 CHANNEL 1
(dB)
CHANNEL 0
(dB)
0 0 0 0
0 1 0 3 (typ)
1 0 3 (typ) 0
1 1 3 (typ) 3 (typ)
MODE OOB MODE
0 SAS
1SATA
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9
MAX14986 Dual 6GT/s SAS/SATA Redriver
with Equalization and Extended
Temperature Operation
Applications Information
Exposed Pad Package
The exposed pad, 28-pin TQFN package incorporates
features that provide a very low thermal resistance path
for heat removal from the IC. The exposed pad on the
MAX14986 must be soldered to GND for proper thermal
and electrical performance. For more information on
exposed pad packages, refer to Maxim Application Note
HFAN-08.1: Thermal Considerations of QFN and Other
Exposed-Paddle Packages.
Layout
Use controlled-impedance transmission lines to interface
with high-speed inputs and outputs of the MAX14986.
Place power-supply 2.2µF and 0.01µF bypass capacitors
as close as possible to VCC, recommended on each VCC
pin.
Power-Supply Sequencing
Caution: Do not exceed the absolute maximum rat-
ings because stresses beyond the listed ratings can
cause permanent damage to the device.
Proper power-supply sequencing is recommended for all
devices. Always apply VCC before applying signals, espe-
cially if the signal is not current limited.
+Denotes a lead(Pb)-free/RoHS-compliant package.
*EP = Exposed pad.
PART TEMP RANGE PIN-PACKAGE
MAX14986ETI+ -40°C to +85°C 28 TQFN-EP*
PACKAGE
TYPE
PACKAGE
CODE
OUTLINE
NO.
LAND
PATTERN NO.
28 TQFN T283555+1 21-0184 90-0123
Package Information
For the latest package outline information and land patterns
(footprints), go to www.maximintegrated.com/packages. Note
that a “+”, “#”, or “-” in the package code indicates RoHS status
only. Package drawings may show a different suffix character, but
the drawing pertains to the package regardless of RoHS status.
Chip Information
PROCESS: BiCMOS
Ordering Information
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10
MAX14986 Dual 6GT/s SAS/SATA Redriver
with Equalization and Extended
Temperature Operation
REVISION
NUMBER
REVISION
DATE DESCRIPTION PAGES
CHANGED
0 3/13 Initial release —
Revision History
Maxim Integrated cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim Integrated product. No circuit patent licenses
are implied. Maxim Integrated reserves the right to change the circuitry and specications without notice at any time. The parametric values (min and max limits)
shown in the Electrical Characteristics table are guaranteed. Other parametric values quoted in this data sheet are provided for guidance.
Maxim Integrated and the Maxim Integrated logo are trademarks of Maxim Integrated Products, Inc. © 2013 Maxim Integrated Products, Inc.
│
11
MAX14986 Dual 6GT/s SAS/SATA Redriver
with Equalization and Extended
Temperature Operation
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim Integrated’s website at www.maximintegrated.com.
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