CO LEXAS INSTRUMENTS Microprocessor and Memory Proaucts SN54/74S481 SN54/74LS481 4-BIT SLICE SCHOTTKY PROCESSOR ELEMENTS ARCHITECTURAL FEATURES The SN54S/74S481, with its hardwired algorithms, achieves the industrys highest degree of micro/macroprogrammability. Designed with full parallel dual input/output ports, its 4-bit memory-to-memory architecture provides a new dimension in interrupt processing or program context switching flexibilities. Its functional capability, characterized by the 24,780 unique operations, coupled with its modular expandability makes the $481 particularly attractive for implementing advanced high performance computers and controllers. Its static bipolar logic performs each microinstruction within a single 100 ns clock cycle. Primary among the S481 architectural features are : Microprogrammabie, bit-slice design is expandable in 4-bit multiples Double-length accumulator with full shifting capability and sign-bit handling Dual memory address generators on-chip OPERATIONAL FEATURES In addition to the full parallel data bus structure, the S481 architecture also features asynchronous access to data routing and counter updating controls which, when combined with the most versatile instruction set available maximizes flexibility, efficiency, and performance. Simultaneous compound operations in the form of an ALU function with shift, plus destination selection with address/iteration updating, plus address and present data to memory can be accomplished in a single microcycle. Some other operational features are : @ Simultaneous one-clock compound operations with status can reduce microcycles and improve throughput @ Pre-programmed multiply, divide, and CRC algorithms e Performs 16-bit by 16-bit double- precision divide in less than 3 microseconds Double length accumulator with full bidirectional single/double precision arithmetic/logical/circulate shift capabilities include sign protection @ Full-micro-operational control is provided for programming: address updating, data and address source selection, and direct transfer of data to working register or working memory @ Relative position control defines bit-slice rank and sign handling in N-bit applications Full parallel dual input/output ports for use in advanced memory-to-memory architecture Full-function ALU with carry look-ahead, magnitude, and overflow decision capabilities BI/O3 Al2 A10 OP1 or3 ce OP5 OP9 CIN Y/AG COUT PIN ASSIGNMENTS of | nf 12] 13] ia. | 15[_| ef | is. BlY/O2 Al3 OPO OP6 OP8 OP4 POS X/LG BY/O SEL BI/OO ccl AO SEL AOP2 AOPO SN 545481 SN 748481 Gi DOPO DOP2 D1 XWRRT = 47 [ }46 | (145 [ }44 [43 [ ]42 41 40 [_|39 | ]38 |___|37 ND ]36 [_|36 | ]34 L_]33 BE | 431 |_|30 [_]29 | j28 [27 | }26 | |25 BI/O1 CK INC PC AOP3 AOPI CCO/OV INC MC DOP! DOP3 bo XWRLFT WRLFT