74LVC74AD,112 - NXP Semiconductors / Philips Semiconductors

1. General description

The 74LVC74A is a dual edge triggered D-type ﬂip-ﬂop with individual data (D) inputs,

clock (CP) inputs, set (SD) and (RD) inputs, and complementary Q and Q outputs.

The set and reset are asynchronous active LOW inputs and operate independently of the

clock input. Information on the data input is transferred to the Q output on the

LOW-to-HIGH transition of the clock pulse. The D inputs must be stable one set-up time

prior to the LOW-to-HIGH clock transition, for predictable operation.

Schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and

fall times.

2. Features

n5 V tolerant inputs for interlacing with 5 V logic

nWide supply voltage range from 1.2 V to 3.6 V

nCMOS low power consumption

nDirect interface with TTL levels

nComplies with JEDEC standard JESD8-B/JESD36

nESD protection:

uHBM JESD22-A114D exceeds 2000 V

uCDM JESD22-C101C exceeds 1000 V

nSpeciﬁed from −40 °C to +85 °C and −40 °C to 125 °C

3. Ordering information

74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

Rev. 06 — 4 June 2007 Product data sheet

Table 1. Ordering information

Type number Package

Temperature range Name Description Version

74LVC74AD −40 °C to +125 °C SO14 plastic small outline package; 14 leads;

body width 3.9 mm SOT108-1

74LVC74ADB −40 °C to +125 °C SSOP14 plastic shrink small outline package; 14 leads;

body width 5.3 mm SOT337-1

74LVC74APW −40 °C to +125 °C TSSOP14 plastic thin shrink small outline package; 14 leads;

body width 4.4 mm SOT402-1

74LVC74ABQ −40 °C to +125 °C DHVQFN14 plastic dual in-line compatible thermal enhanced very thin

quad ﬂat package; no leads; 14 terminals;

body 2.5 ×3×0.85 mm

SOT762-1

Product data sheet Rev. 06 — 4 June 2007 2 of 16

NXP Semiconductors 74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

4. Functional diagram

Fig 1. Logic symbol Fig 2. IEC logic symbol Fig 3. Functional diagram

mna418

410

Q1Q

11 6

1SD

2CP

1CP

1D D

2SD

113

1RD 2RD

mna419

2C1

12 C1

10 S

13 R

Q1Q

1SD

1CP

1D D

11RD

mna420

Q2Q

2SD

2CP

2D D

13 2RD

Fig 4. Logic diagram for one ﬂip-ﬂop

mna421

Product data sheet Rev. 06 — 4 June 2007 3 of 16

NXP Semiconductors 74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

5. Pinning information

5.1 Pinning

5.2 Pin description

(1) The die substrate is attached to this pad using

conductive die attach material. It can not be used as

a supply pin or input.

Fig 5. Pin conﬁguration for SO14 and (T)SSOP14 Fig 6. Pin conﬁguration for DHVQFN14

1RD VCC

1D 2RD

1CP 2D

1SD 2CP

1Q 2SD

1Q 2Q

GND 2Q

001aad106

7 8

001aad107

Transparent top view

1Q 2Q

1Q 2SD

1SD 2CP

1CP 2D

2RD1D

GND(1)

GND

1RD

VCC

6 9

5 10

4 11

3 12

2 13

terminal 1

index area

Table 2. Pin description

Symbol Pin Description

1RD 1 asynchronous reset-direct input (active LOW)

1D 2 data input

1CP 3 clock input (LOW-to-HIGH, edge-triggered)

1SD 4 asynchronous set-direct input (active LOW)

1Q 5 true output

1Q 6 complement output

GND 7 ground (0 V)

2Q 8 complement output

2Q 9 true output

2SD 10 asynchronous set-direct input (active LOW)

2CP 11 clock input (LOW-to-HIGH, edge-triggered)

2D 12 data input

2RD 13 asynchronous reset-direct input (active LOW)

VCC 14 supply voltage

Product data sheet Rev. 06 — 4 June 2007 4 of 16

NXP Semiconductors 74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

6. Functional description

[1] H = HIGH voltage level

L = LOW voltage level

X = don’t care

[1] H = HIGH voltage level

L = LOW voltage level

↑= LOW-to-HIGH transition

Qn+1 = state after the next LOW-to-HIGH CP transition

X = don’t care

7. Limiting values

[1] The minimum input voltage ratings may be exceeded if the input current ratings are observed.

[2] The output voltage ratings may be exceeded if the output current ratings are observed.

[3] For SO14 packages: above 70 °C the value of Ptot derates linearly with 8 mW/K.

For (T)SSOP14 packages: above 60 °C the value of Ptot derates linearly with 5.5 mW/K.

For DHVQFN14 packages: above 60 °C the value of Ptot derates linearly with 4.5 mW/K.

Table 3. Function table[1]

Input Output

nSD nRD nCP nD nQ nQ

LHXXHL

HLXXLH

LLXXHH

Table 4. Function table[1]

Input Output

nSD nRD nCP nD nQn+1 nQn+1

HH↑LLH

HH↑HHL

Table 5. Limiting values

In accordance with the Absolute Maximum Rating System (IEC 60134). Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions Min Max Unit

VCC supply voltage −0.5 +6.5 V

IIK input clamping current VI < 0 V −50 - mA

VIinput voltage [1] −0.5 +6.5 V

IOK output clamping current VO > VCC or VO < 0 V - ±50 mA

VOoutput voltage [2] −0.5 VCC + 0.5 V

IOoutput current VO = 0 V to VCC -±50 mA

ICC supply current - 100 mA

IGND ground current −100 - mA

Tstg storage temperature −65 +150 °C

Ptot total power dissipation Tamb = −40 °C to +125 °C[3] - 500 mW

Product data sheet Rev. 06 — 4 June 2007 5 of 16

NXP Semiconductors 74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

8. Recommended operating conditions

9. Static characteristics

[1] All typical values are measured at VCC = 3.3 V (unless stated otherwise) and Tamb =25°C.

Table 6. Recommended operating conditions

Symbol Parameter Conditions Min Typ Max Unit

VCC supply voltage for maximum speed performance 2.7 - 3.6 V

for low-voltage applications 1.2 - 3.6 V

VIinput voltage 0 - 5.5 V

Vooutput voltage 0 - VCC V

Tamb ambient temperature −40 - +125 °C

∆t/∆V input transition rise and

fall rate VCC = 1.2 V to 2.7 V 0 - 20 ns/V

VCC = 2.7 V to 3.6 V 0 - 10 ns/V

Table 7. Static characteristics

At recommended operating conditions. Voltages are referenced to GND (ground = 0 V).

Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max

VIH HIGH-level

input voltage VCC = 1.2 V VCC -- V

CC -V

VCC = 2.7 V to 3.6 V 2.0 - - 2.0 - V

VIL LOW-level

input voltage VCC = 1.2 V - - 0 - 0 V

VCC = 2.7 V to 3.6 V - - 0.8 - 0.8 V

VOH HIGH-level

output

voltage

VI=V

IH or VIL

IO=−100 µA;

VCC = 2.7 V to 3.6 V VCC −0.2 - VCC −0.3 - V

IO=−12 mA; VCC = 2.7 V 2.2 - - 2.05 - V

IO=−18 mA; VCC = 3.0 V 2.4 - - 2.25 - V

IO=−24 mA; VCC = 3.0 V 2.2 - - 2.0 - V

VOL LOW-level

output

voltage

VI=V

IH or VIL

IO= 100 µA;

VCC = 2.7 V to 3.6 V - - 0.2 - 0.3 V

IO= 12 mA; VCC = 2.7 V - - 0.4 - 0.6 V

IO= 24 mA; VCC = 3.0 V - - 0.55 - 0.8 V

IIinputleakage

current VCC = 3.6 V; VI= 5.5 Vor GND - ±0.1 ±5-±20 µA

ICC supply

current VCC = 3.6 V; VI=V

CC or GND;

IO=0A - 0.1 10 - 40 µA

∆ICC additional

supply

current

per input pin;

VCC = 2.7 V to 3.6 V;

VI=V

CC −0.6 V; IO=0A

- 5 500 - 5000 µA

CIinput

capacitance VCC = 0 V to 3.6 V;

VI= GND to VCC

- 4.0 - - - pF

Product data sheet Rev. 06 — 4 June 2007 6 of 16

NXP Semiconductors 74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

10. Dynamic characteristics

[1] Typical values are measured at Tamb =25°C. For VCC = 3.0 V to 3.6 V range, typical values are measured at 3.3 V.

[2] tpd is the same as tPLH and tPHL.

[3] Skew between any two outputs of the same package switching in the same direction. This parameter is guaranteed by design.

Table 8. Dynamic characteristics

Voltages are referenced to GND (ground = 0 V). For test circuit see Figure 9.

Symbol Parameter Conditions −40 °C to +85 °C−40 °C to +125 °C Unit

Min Typ[1] Max Min Max

tpd propagation

delay nCP to nQ, nQ; see Figure 7 [2]

VCC = 1.2 V - 15 - - - ns

VCC = 2.7 V 1.0 2.7 6.0 1.0 7.5 ns

VCC = 3.0 V to 3.6 V 1.0 2.5 5.2 1.0 6.5 ns

nSD to nQ, nQ; see Figure 8

VCC = 1.2 V - 15 - - - ns

VCC = 2.7 V 1.0 3.2 6.4 1.0 8.0 ns

VCC = 3.0 V to 3.6 V 1.0 2.5 5.4 1.0 7.0 ns

nRD to nQ, nQ; see Figure 8

VCC = 1.2 V - 15 - - - ns

VCC = 2.7 V 1.0 3.2 6.4 1.0 8.0 ns

VCC = 3.0 V to 3.6 V 1.0 2.5 5.4 1.0 7.0 ns

tWpulse width clock HIGH or LOW; see Figure 7

VCC = 2.7 V 3.3 - - 4.5 - ns

VCC = 3.0 V to 3.6 V 3.3 1.3 - 4.5 - ns

set or reset LOW; see Figure 8

VCC = 2.7 V 3.3 - - 4.5 - ns

VCC = 3.0 V to 3.6 V 3.3 1.7 - 4.5 - ns

trec recovery time set or reset; see Figure 8

VCC = 2.7 V 1.5 - - 1.0 - ns

VCC = 3.0 V to 3.6 V +1.0 −3.0 - 1.0 - ns

tsu set-up time nD to nCP; see Figure 7

VCC = 2.7 V 2.2 - - 2.2 - ns

VCC = 3.0 V to 3.6 V 2.0 0.8 - 2.0 - ns

thhold time nD to nCP; see Figure 7

VCC = 2.7 V 1.0 - - 1.0 - ns

VCC = 3.0 V to 3.6 V +1.0 −0.2 - 1.0 - ns

fmax maximum

frequency nCP; see Figure 7

VCC = 2.7 V 83 - - 66 - MHz

VCC = 3.0 V to 3.6 V 150 250 120 - MHz

tsk(o) output skew time VCC = 3.0 V to 3.6 V [3] - - 1.0 - 1.5 ns

CPD power

dissipation

capacitance

per ﬂip-ﬂop; VI= GND to VCC [4]

VCC = 3.3 V - 15 - - - pF

Product data sheet Rev. 06 — 4 June 2007 7 of 16

NXP Semiconductors 74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

[4] CPD is used to determine the dynamic power dissipation (PDin µW).

PD=C

PD ×VCC2×fi×N+Σ(CL×VCC2×fo) where:

fi= input frequency in MHz; fo= output frequency in MHz

CL= output load capacitance in pF

VCC = supply voltage in Volts

N = number of inputs switching

Σ(CL×VCC2×fo) = sum of the outputs

11. AC waveforms

The shaded areas indicate when the input is permitted to change for predictable output performance.

VM= 1.5 Vat VCC ≥2.7 V;

VM= 0.5 ×VCC at VCC < 2.7 V;

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 7. The clock input (nCP) to output (nQ, nQ) propagation delays, the clock pulse width, the nD to nCP set-up,

the nCP to nD hold times, and the maximum frequency

mna422

tsu

tPHL

tPLH

tsu

1/fmax

GND

nCP input

nD input

VOH

VOL

nQ output

VOH

VOL

nQ output

Product data sheet Rev. 06 — 4 June 2007 8 of 16

NXP Semiconductors 74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

VM= 1.5 Vat VCC ≥2.7 V;

VM= 0.5 ×VCC at VCC < 2.7 V;

VOL and VOH are typical output voltage levels that occur with the output load.

Fig 8. The set (nSD) and reset (nRD) input to output (nQ, nQ) propagation delays, the set and reset pulse widths,

and the nRD to nCP recovery time

mna423

trec

tPHL

tPLH

GND

nSD input

GND

nRD input

nCP input

VOH

VOL

nQ output

VOH

VOL

nQ output

Product data sheet Rev. 06 — 4 June 2007 9 of 16

NXP Semiconductors 74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

Test data is given in Table 9.

Deﬁnitions for test circuit:

RL = Load resistance.

CL = Load capacitance including jig and probe capacitance.

RT = Termination resistance should be equal to output impedance Zo of the pulse generator.

Fig 9. Load circuitry for switching times

VMVM

10 %

90 %

0 V

negative

pulse

positive

pulse

0 V

VMVM

90 %

10 %

001aaf615

VCC

VIVO

DUT

RTRL

PULSE

GENERATOR

Table 9. Test data

Supply voltage Input Load

VItr, tfCLRL

1.2 V VCC ≤ 2.5 ns 50 pF 500 Ω

2.7 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω

3.0 V to 3.6 V 2.7 V ≤ 2.5 ns 50 pF 500 Ω

Product data sheet Rev. 06 — 4 June 2007 10 of 16

NXP Semiconductors 74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

12. Package outline

Fig 10. Package outline SOT108-1 (SO14)

UNIT A

max. A1A2A3bpcD

(1) E(1) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

inches

1.75 0.25

0.10 1.45

1.25 0.25 0.49

0.36 0.25

0.19 8.75

8.55 4.0

3.8 1.27 6.2

5.8 0.7

0.6 0.7

0.3 8

0.25 0.1

DIMENSIONS (inch dimensions are derived from the original mm dimensions)

Note

1. Plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included.

1.0

0.4

SOT108-1

detail X

vMA

(A )

076E06 MS-012

pin 1 index

0.069 0.010

0.004 0.057

0.049 0.01 0.019

0.014 0.0100

0.0075 0.35

0.34 0.16

0.15 0.05

1.05

0.041

0.244

0.228 0.028

0.024 0.028

0.012

0.01

0.25

0.01 0.004

0.039

0.016

99-12-27

03-02-19

0 2.5 5 mm

scale

SO14: plastic small outline package; 14 leads; body width 3.9 mm SOT108-1

Product data sheet Rev. 06 — 4 June 2007 11 of 16

NXP Semiconductors 74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

Fig 11. Package outline SOT337-1 (SSOP14)

UNIT A1A2A3bpcD

(1) E(1) eH

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.21

0.05 1.80

1.65 0.25 0.38

0.25 0.20

0.09 6.4

6.0 5.4

5.2 0.65 1.25 0.2

7.9

7.6 1.03

0.63 0.9

0.7 1.4

0.9 8

0.13 0.1

DIMENSIONS (mm are the original dimensions)

Note

1. Plastic or metal protrusions of 0.25 mm maximum per side are not included.

SOT337-1 99-12-27

03-02-19

(1)

vMA

14 8

detail X

(A )

MO-150

pin 1 index

0 2.5 5 mm

scale

SSOP14: plastic shrink small outline package; 14 leads; body width 5.3 mm SOT337-1

max.

Product data sheet Rev. 06 — 4 June 2007 12 of 16

NXP Semiconductors 74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

Fig 12. Package outline SOT402-1 (TSSOP14)

UNIT A1A2A3bpcD

(1) E(2) (1)

ELL

pQZywv θ

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 0.15

0.05 0.95

0.80 0.30

0.19 0.2

0.1 5.1

4.9 4.5

4.3 0.65 6.6

6.2 0.4

0.3 0.72

0.38 8

0.13 0.10.21

DIMENSIONS (mm are the original dimensions)

Notes

1. Plastic or metal protrusions of 0.15 mm maximum per side are not included.

2. Plastic interlead protrusions of 0.25 mm maximum per side are not included.

0.75

0.50

SOT402-1 MO-153 99-12-27

03-02-18

0.25

14 8

detail X

(A )

vMA

0 2.5 5 mm

scale

TSSOP14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm SOT402-1

max.

1.1

pin 1 index

Product data sheet Rev. 06 — 4 June 2007 13 of 16

NXP Semiconductors 74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

Fig 13. Package outline SOT762-1 (DHVQFN14)

terminal 1

index area

0.51

A1Eh

UNIT ye

0.2

REFERENCES

OUTLINE

VERSION EUROPEAN

PROJECTION ISSUE DATE

IEC JEDEC JEITA

mm 3.1

2.9

1.65

1.35

2.6

2.4 1.15

0.85

0.30

0.18

0.05

0.00 0.05 0.1

DIMENSIONS (mm are the original dimensions)

SOT762-1 MO-241 - - -- - -

0.5

0.3

0.1

0.05

0 2.5 5 mm

scale

SOT762-1

DHVQFN14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads;

14 terminals; body 2.5 x 3 x 0.85 mm

A(1)

max.

AA1c

detail X

y1C

13 9

02-10-17

03-01-27

terminal 1

index area

E(1)

Note

1. Plastic or metal protrusions of 0.075 mm maximum per side are not included.

D(1)

Product data sheet Rev. 06 — 4 June 2007 14 of 16

NXP Semiconductors 74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

13. Abbreviations

14. Revision history

Table 10. Abbreviations

Acronym Description

CDM Charged Device Model

DUT Device Under Test

ESD ElectroStatic Discharge

HBM Human Body Model

TTL Transistor-Transistor Logic

Table 11. Revision history

Document ID Release date Data sheet status Change notice Supersedes

74LVC74A_6 20070604 Product data sheet - 74LVC74A_5

Modiﬁcations: •Change of hold time in Table 8 “Dynamic characteristics”. Minimum values changed to 1.0 ns.

74LVC74A_5 20070525 Product data sheet - 74LVC74A_4

74LVC74A_4 20030526 Product speciﬁcation - 74LVC74A_3

74LVC74A_3 20020618 Product speciﬁcation - 74LVC74A_2

74LVC74A_2 19980617 Product speciﬁcation - 74LVC74A_1

74LVC74A_1 19980617 Product speciﬁcation - -

Product data sheet Rev. 06 — 4 June 2007 15 of 16

NXP Semiconductors 74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

15. Legal information

15.1 Data sheet status

[1] Please consult the most recently issued document before initiating or completing a design.

[2] The term ‘short data sheet’ is explained in section “Deﬁnitions”.

[3] The product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple devices. The latest product status

information is available on the Internet at URL http://www.nxp.com.

15.2 Deﬁnitions

Draft — The document is a draft version only. The content is still under

internal review and subject to formal approval, which may result in

modiﬁcations or additions. NXP Semiconductors does not give any

representations or warranties as to the accuracy or completeness of

information included herein and shall have no liability for the consequences of

use of such information.

Short data sheet — A short data sheet is an extract from a full data sheet

with the same product type number(s) and title. A short data sheet is intended

for quick reference only and should not be relied upon to contain detailed and

full information. For detailed and full information see the relevant full data

sheet, which is available on request via the local NXP Semiconductors sales

ofﬁce. In case of any inconsistency or conﬂict with the short data sheet, the

full data sheet shall prevail.

15.3 Disclaimers

General — Information in this document is believed to be accurate and

reliable. However, NXP Semiconductors does not give any representations or

warranties, expressed or implied, as to the accuracy or completeness of such

information and shall have no liability for the consequences of use of such

information.

Right to make changes — NXP Semiconductors reserves the right to make

changes to information published in this document, including without

limitation speciﬁcations and product descriptions, at any time and without

notice. This document supersedes and replaces all information supplied prior

to the publication hereof.

Suitability for use — NXP Semiconductors products are not designed,

authorized or warranted to be suitable for use in medical, military, aircraft,

space or life support equipment, nor in applications where failure or

malfunction of a NXP Semiconductors product can reasonably be expected to

result in personal injury, death or severe property or environmental damage.

NXP Semiconductors accepts no liability for inclusion and/or use of NXP

Semiconductors products in such equipment or applications and therefore

such inclusion and/or use is at the customer’s own risk.

Applications — Applications that are described herein for any of these

products are for illustrative purposes only. NXP Semiconductors makes no

representation or warranty that such applications will be suitable for the

speciﬁed use without further testing or modiﬁcation.

Limiting values — Stress above one or more limiting values (as deﬁned in

the Absolute Maximum Ratings System of IEC 60134) may cause permanent

damage to the device. Limiting values are stress ratings only and operation of

the device at these or any other conditions above those given in the

Characteristics sections of this document is not implied. Exposure to limiting

values for extended periods may affect device reliability.

Terms and conditions of sale — NXP Semiconductors products are sold

subject to the general terms and conditions of commercial sale, as published

at http://www.nxp.com/proﬁle/terms, including those pertaining to warranty,

intellectual property rights infringement and limitation of liability, unless

explicitly otherwise agreed to in writing by NXP Semiconductors. In case of

any inconsistency or conﬂict between information in this document and such

terms and conditions, the latter will prevail.

No offer to sell or license — Nothing in this document may be interpreted

or construed as an offer to sell products that is open for acceptance or the

grant, conveyance or implication of any license under any copyrights, patents

or other industrial or intellectual property rights.

15.4 Trademarks

Notice: All referenced brands, product names, service names and trademarks

are the property of their respective owners.

16. Contact information

For additional information, please visit: http://www.nxp.com

For sales ofﬁce addresses, send an email to: salesaddresses@nxp.com

Document status[1][2] Product status[3] Deﬁnition

Objective [short] data sheet Development This document contains data from the objective speciﬁcation for product development.

Preliminary [short] data sheet Qualiﬁcation This document contains data from the preliminary speciﬁcation.

Product [short] data sheet Production This document contains the product speciﬁcation.

NXP Semiconductors 74LVC74A

Dual D-type ﬂip-ﬂop with set and reset; positive-edge trigger

For more information, please visit: http://www.nxp.com

For sales office addresses, please send an email to: salesaddresses@nxp.com

Date of release: 4 June 2007

Document identifier: 74LVC74A_6

Please be aware that important notices concerning this document and the product(s)

described herein, have been included in section ‘Legal information’.

17. Contents

1 General description. . . . . . . . . . . . . . . . . . . . . . 1

2 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1

3 Ordering information. . . . . . . . . . . . . . . . . . . . . 1

4 Functional diagram . . . . . . . . . . . . . . . . . . . . . . 2

5 Pinning information. . . . . . . . . . . . . . . . . . . . . . 3

5.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3

5.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 3

6 Functional description . . . . . . . . . . . . . . . . . . . 4

7 Limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 4

8 Recommended operating conditions. . . . . . . . 5

9 Static characteristics. . . . . . . . . . . . . . . . . . . . . 5

10 Dynamic characteristics . . . . . . . . . . . . . . . . . . 6

11 AC waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 7

12 Package outline . . . . . . . . . . . . . . . . . . . . . . . . 10

13 Abbreviations. . . . . . . . . . . . . . . . . . . . . . . . . . 14

14 Revision history. . . . . . . . . . . . . . . . . . . . . . . . 14

15 Legal information. . . . . . . . . . . . . . . . . . . . . . . 15

15.1 Data sheet status . . . . . . . . . . . . . . . . . . . . . . 15

15.2 Deﬁnitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

15.3 Disclaimers. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

15.4 Trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 15

16 Contact information. . . . . . . . . . . . . . . . . . . . . 15

17 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16