DS001-4 (v2.4) April 30, 2001 www.xilinx.com Module 4 of 4
Preliminary Product Specification 1-800-255-7778 1
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Pin D ef i ni ti o n s
0Spartan-II 2.5V FPGA Family:
Pinout Tables
DS001-4 (v2.4) April 30, 2001 00Preliminary Product Speci fication
R
Pin Name Dedicated
Pin Direction Description
GCK0, GCK1, GCK2,
GCK3 No Input Cloc k input pins th at co nnect to Global Cloc k Buf fe rs . These pi ns become
user inputs when not ne eded for clocks.
M0, M1, M2 Yes Input Mode pins are used to speci fy the configuration mode.
CCLK Yes Input or Output The confi guration Clo ck I/O pin. It is an input for slave-paral lel and
slave-seri al modes, and output in master-serial mode.
PROGRAM Yes Input Initiat es a configuration sequence when asserted Low.
DONE Yes Bidirectional Indicates that configuration loa ding is complete, and that the sta rt-up
sequence is in progress. The output may be open drain.
INIT No Bidirectional
(Open-drain) When Low, indicates that the con fi guration memory is bein g cle ared. This
pin becomes a user I/O aft er conf igurati on.
BUSY/DOUT No Output In Slave P arallel mode, BUSY contr ols the rate at which configu ration data
is loaded. This pin be comes a user I/ O after c onfigura tion un less the Sla ve
Parallel port is retai ned.
In serial modes, DOUT provides configuration data to downstream devices
in a dais y-chain. This pin becomes a user I/O aft er configuration.
D0/DIN, D1, D2, D3, D4,
D5, D6, D7 No Input or Output In Sla ve Paral lel mode , D0- D7 are configuratio n data i nput pins. During
readback, D0-D7 are out put pins. These pins become user I/Os after
configuration unless the Sla ve Paral lel port is retained.
In serial modes, DIN is the single data input. This pin becomes a user I/ O
after confi guration.
WRITE No Input In Slave Parallel mode, the active-low Write Enable signal . Thi s pin
becom es a user I/O after confi guration unles s the Slave Parallel port is
retained.
CS No Input In Sla ve Paral lel mode, the a cti ve-low Chi p Select signa l. This pin
becom es a user I/O after confi guration unles s the Slave Parallel port is
retained.
TDI, TDO, TMS , TCK Yes Mixed Bou ndary Scan Test Access Port pins (IEEE 1149.1).
VCCINT Yes I nput Power supply pi ns for the internal core logi c.
VCCO Yes Input Power s upply pins for output drivers (subject to banking rules)
VREF No Input Input threshold voltage pins. Become user I/Os when an e xternal threshold
voltage is not nee ded (subject to banking rul es).
GND Yes Input Ground.
IRDY, TRDY No See PCI core
documentation These si gnals can only be accessed when using Xilinx PCI cores. If the
cores are not used, these pins are avail able as user I/Os.