i.MX51A Automotive and Infotainment Applications Processors, Rev. 6
174 Freescale Semiconductor
Revision History
Rev. 3 06/2010 • Updated Max column of Table 15, "Fuse Supply Current," on page 19. Deleted eFuse Read Current row
from the same table.
• Updated Symbol, Test Conditions, and Max columns of Table 18, "GPIO/HSGPIO DC Electrical
Characteristics," on page 23.
• Updated Max and Unit columns of Table 19, "DDR2 I/O DC Electrical Parameters," on page 24.
• Updated Test Conditions, Max, and Unit columns of Table 20, "LVIO DC Electrical Characteristics," on
page 24
• Updated Symbol, Test Conditions, Max, and Unit columns of Table 21, "UHVIO DC Electrical
Characteristics," on page 25.
• Updated Max and Unit columns of Table 22, "I2C Standard/Fast/High-Speed Mode Electrical
Parameters for Low/Medium Drive Strength," on page 27.
• Added a new table Table 25, "I/O Leakage Current," on page 29.
Rev. 2 05/2010 • Changed the VREFOUT column in Table 3, "Special Signal Considerations," on page 11.
• Added Section 3, “IOMUX Configuration for Boot Media”.
• Updated Figure 2, "Power-Up Sequence," on page 22.
• Added a note in Section 4.2.1, “Power-Up Sequence”.
• Updated Section 4.2.1, “Power-Up Sequence.”
• Changed the Input current (47 kΩ Pull-up) column in Table 21, "UHVIO DC Electrical Characteristics,"
on page 25 to Input current (75 kO Pull-up).
• Added new table for parameters for DDR2 Pad output buffer Impedance. See Table 27, "DDR2 I/O
Output Buffer Impedance HVE = 0," on page 30.
• Added new section under Section 4.5, “I/O AC Parameters”. See Section 4.5.4, “AC Electrical
Characteristics for DDR2”.
• Updated Table 47, "CAMP Electrical Parameters (CKIH1, CKIH2)," on page 46. In the VIH (for square
wave input) parameter, the minimum frequency was changed to NVCC_PER3 - 0.25V and the maximum
frequency was changed to NVCC_PER3.
• Added a note in Section 4.6.6, “NAND Flash Controller (NFC) Parameters” after Ta bl e 49 .
• Updated Asymmetric Mode Min, Symmetric Mode Min, and Max columns of Ta b l e 5 0 .
• Removed Conditions parameters of the Full scale output voltage row in Ta b l e 8 2 .
• Updated Section 4.7.11, “P-ATA Timing Parameters”. Replaced ATA/ATAPI-6 specification with
ATA/ATAPI-5 specification.
•In Table 102, "SSI Transmitter Timing with Internal Clock," on page 133, under the Synchronous Internal
Clock Operation sections for the ID SS42, minimum frequency was changed from 10.0 to 30.
•In Table 103, "SSI Receiver Timing with Internal Clock," on page 134, under the Internal Clock
Operation section for ID SS20, minimum frequency was changed from 10.0 to 30.
•In Table 104, "SSI Transmitter Timing with External Clock," on page 136, under the External Clock
Operation section for ID SS38, maximum frequency was changed from 15.0 to 30.
• Added a new section Section 4.7.16.1, “UART Electrical”, under Section 4.7.16, “UART”.
•In Table 118, "USB Port Timing Specification in VP_VM Bi-directional Mode," on page 146, for IDs SS28
and SS29, direction was changed from out to in.
•In Table 120, "USB Timing Specification in VP_VM Unidirectional Mode," on page 148, for IDs US40 and
US41, direction was changed from out to in and the reference signal was changed to USB_VM1 and
USB_VP1 respectively.
•I
n Table 122, "USB Timing Specification for ULPI Parallel Mode," on page 149, added an extra row for
ID17.
• Updated Signal and Direction columns in Table 120, "USB Timing Specification in VP_VM Unidirectional
Mode," on page 148.
• Updated Signal names in Table 118, "USB Port Timing Specification in VP_VM Bi-directional Mode," on
page 146.
Rev. 1 10/2009 Initial public release.
Table 131. i.MX51 Data Sheet Document Revision History (continued)
Rev.
Number Date Substantive Change(s)