DSP Architectures Transform Your World DSP24 TM High Performance Scalable DSP Chip DSP Architectures Data Sheet Real 24 PORT A Imag 24 DSP24 Imag 24 24 24 X I NP U TB US Y INPUT BU S OUTPU TB US 24 48 Imag 24 Scheduler/ Controller X Y Memory A 24 Memory B 24 System Controls &Test Control 24 PORT E PROM Interface 48 Scalable DSP Logic 24 Real PORT B Real 24 24 24 Imag 48 48 48 48 48 48 24 PORT C 24 Real 48 24 24 Real 24 24 Imag PORT D FEATURES/BENEFITS: DESCRIPTION: 80/100 MHz operation on an unlimited array size, with support for 2-D and 3-D signal/image processing. Supports DSP, Complex math, Matrix math, FIRs, Block Adds, Subtracts, Complex magnitude, etc. 100 MHz execution speed allows a complex sample rate of 50 MHz for a 1K complex FFT, with a window included Highly scalable architecture allows DSP24 chips or die to be cascaded for higher radices and extended functions Two DSP24's cascaded without external memory perform a Radix 1024 at a 100 MHz complex sample rate 24 bit complex FFT's with no overhead block floating point gives signal/noise greater than floating point Radix 2, Radix 4, Radix 8, Radix 16, and Radix 32 instructions, perform 1K complex FFT in two passes On chip ROM for transform coefficients and window functions, window free on all radices The DSP24 breaks the computational bottlenecks associated with real time DSP, with the additional benefit of radically reduced software overhead. Most demanding DSP tasks such as frequency domain digital filtering are reduced to less than a dozen DSP24 machine instructions. The DSP24 concentrates on performing DSP algorithms using the efficiencies of the FFT. Applications using time domain techniques such as the DFT and FIR increase in operations by a N squared function. These same applications using FFT techniques increase in operations by N x Log2 (N), a radical reduction. Multiple chips can be cascaded for higher radices, two cascaded chips will perform a 1024 radix, this gives a 1 million point transform in two passes at a startling 50 MHz complex continuous sample rate. The DSP24 was designed using DSP Architectures Inc macro cells and super cells. The end customer can use the DSP24 as a silicon core and surround the chip with proprietary circuitry to further enhance the application and reduce his overall application hardware. Five complex bi-directional data ports for highly flexible (any port to any port) data routing Macro functions buried in the chip architecture dramatically reduces software development, on chip program controller 100 MHz, 24-BIT PERFORMANCE: Advanced sub-micron, very low power 3.3 volt operation. High Performance BGA Package 1024 point complex FFT........................ approx. 22 msec Enhanced real only FFT support, FFTNN and FFT2N, plus stacked FFTs to reduce latency Complex 16 x 16 Matrix Multiply .......... 41 msec ASIC silicon cores, Macro cells, Super cells, MCMs, and custom constructs available High Reliability, High Temp, Rad Hard versions available 5/1/01 32K point complex FFT......................... approx. 990 msec Real FIR Filter ...................................... 5 nsec/tap Complex Multiply ................................. 10 nsec Complex FIR Filter ............................... 10 nsec/tap DSP Architectures DSP24 Digital Signal Processor Figure 1. FFT Based Approach Input Output 100 MSPS BUFFER BUFFER Multiply -1 FFT FFT PASS 1 PASS 4 PASS 2 PASS 5 PASS 3 PASS 6 100 MSPS Filter Response Coefficients FFT PASS 1 BFLY4 PASS 2 BFLY4 FFT PASS 3 BFLY4 PASS 4 BWND4 0 16 32 48 4 20 36 52 8 24 40 56 12 28 44 60 1 17 33 49 5 21 27 53 9 25 41 57 13 29 45 61 2 18 34 50 6 22 38 54 10 26 42 58 14 30 46 62 3 19 35 51 7 23 39 55 11 27 43 59 15 31 47 63 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 PASS 5 BFLY4 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 first pass on inverse FFT includes the filter response multiply 24 Control BUFFER BUFFER HIGH PERFORMANCE CONFIGURATION PASS 6 BFLY4 0 16 32 48 4 20 36 52 8 24 40 56 12 28 44 60 1 17 33 49 5 21 27 53 9 25 41 57 13 29 45 61 2 18 34 50 6 22 38 54 10 26 42 58 14 30 46 62 3 19 35 51 7 23 39 55 11 27 43 59 15 31 47 63 first pass on FFT includes the window multiply, if any. Input -1 Output 24 24 24 Dr Di Er Ei 6 MMU-24 FUNCTION CODE SYSTEM CTL 9 Control 24 Ar PASS 1 Br PROM DATA FLOW 24 PASS 2 SRAM SRAM PASS 3 PASS 4 PASS 5 PASS 6 Ai 24 Cr DSP24 24 Bi Ci 24 24 MMU-24 Control MMU-24 SRAM Filter Response Coefficients Page 2 Control Data Sheet DSP Architectures Digital Signal Processor DSP24 Figure 2. DSP24 Block Diagram 5 MMU-24 CONTROL SYSCLK SYSCLKEN CLKAIN CLKBIN CLKCIN CLKDIN CLKEIN SYSTEM AND PORT CLOCKS PORT CONTROL 3 24 24 24 24 BI-DIRECTIONAL DATA PORTS 24 24 24 24 24 24 Data Sheet MMU R/W MMU A0 MMU START MMU CS[4:0] MMU TCA MMU TCB MMU TCC MMU TCD MMU TCE AOE BOE COE DOE EOE POUT[2:0] AR [23:0] AI [23:0] BR [23:0] BI [23:0] CR [23:0] CI [23:0] DR [23:0] DI [23:0] ER [23:0] EI [23:0] SCHSEL ADDR[15:0] ADDREN SCH DB[7:0] ALG[7:0] DF[8:0] FC[5:0] ENA ENB GO[1:0] START/STOP SYNCOUT[1:0] SYNCIN[1:0] 16 8 8 9 6 2 2 JCK JMS JDI JDO JRST YSWAP XSWAP XSFISEL XSFI[3:0] YSFI[3:0] YCR XCR DOCR DOCI YCI XCI YZI XZI DZO PI0 PI1 DATA FLOW & FUNCTION CONTROL 2 RESET BUSY BFPI[5:0] BFPO[5:0] DSFO[3:0] BFPCLR PROM INTERFACE SYSTEM SYNCHRONIZATION TEST/JTAG 6 6 4 BLOCK FLOATING POINT CONTROL 4 4 DATA CONDITIONING SWITCHES Page 3 DSP Architectures DSP24 Digital Signal Processor Table 1. DSP24 Signal-Pin Description I/O PIN SIGNAL DESCRIPTION DATA BUSES AR[23:0] I/O Port A real. Bidirectional real data port AI[23:0] I/O Port A imaginary. Bidirectional imaginary data port BR[23:0] I/O Port A real. Bidirectional real data port BI[23:0] I/O Port A imaginary. Bidirectional imaginary data port CR[23:0] I/O Port A real. Bidirectional real data port CI[23:0] I/O Port A imaginary. Bidirectional imaginary data port DR[23:0] I/O Port A real. Bidirectional real data port DI[23:0] I/O Port A imaginary. Bidirectional imaginary data port ER[23:0] I/O Port A real. Bidirectional real data port EI[23:0] I/O Port A imaginary. Bidirectional imaginary data port CONTROL Page 4 DF[8:0] I Data flow control. The data flow opcode (mnemonic) indicates the direction data (read/write) flows within chip based on the source and destination ports. FC[5:0] I Function control. The function opcode (mnemonic) determines the function the chip is to perform on the data for the current pass. START/ STOP I Start of Pass. Indicates the start and stop of a pass and qualifies the opcode. START/STOP is set high for the start of a pass and taken low at the end of the pass. XCR I Complement or invert the X input real input data. When set high, XCR performs a two's complement or an inversion on the real side data beginning one cycle before execution of the selected function.** XCI I Complement or invert the X input imaginary data. When set high, YCI performs a two's complement or an inversion on the imaginary side data beginning one cycle before execution of the selected function.** YCR I Complement or invert the Y input real input data. When set high, XCR performs a two's complement or an inversion on the real side data beginning one cycle before execution of the selected function.** YCI I Complement or invert the Y input imaginary data. When set high, YCI performs a two's complement or an inversion on the imaginary side data beginning one cycle before execution of the selected function.** DOCR I Complement or invert the real output data. When set high, DCRO performs a two's complement or an inversion on the real side data beginning one cycle before the data reaches the output.** DOCI I Complement or invert the imaginary output data. When set high, DCIO performs a two's complement or an inversion on the imaginary side data beginning one cycle before the data reaches the output.** Data Sheet DSP Architectures Digital Signal Processor MMU-24 Table 1. (cont) DSP24 Signal-Pin Description PIN I/O SIGNAL DESCRIPTION CONTROL (cont.) XZI I Zero input data, both real and imaginary. When set high, XZI forces the input data to zero. YZI I Zero input data, both real and imaginary. When set high, YZI forces the input data to zero. DZO I Zero output data, both real and imaginary. When set high, DZO forces the output data to zero. ENA I Enable A. Enables FC[5:0], DF[8:0] control signals to be registered into the chip on the next SYSCLK. ENB I Enable B. Enables the control signals BFPI[5:0], XSFI[3:0], XSFISEL, YSFI[3:0] to be registered into the chip on the next SYSCLK. RESET I When set high, clears all internal counters sets registers to defaults BFPI[5:0] I Block floating point input. Inputs the accumulated scale factor from the preceding passes of an algorithm to sum the exponent for a complete FFT. BFPO[5:0] O Block floating point output. Outputs the accumulated scale factor from the preceding passes since START was asserted. XSFI[3:0] I Data scaling factor input for X input. Assigns the user supplied scale factor (number of right shifts) to the current input data before execution by up to sixteen (16) shifts. If the user has specified automatic scaling by asserting the DSFISEL control signal low, then the internal radix adjusted shift will be applied, instead of the user supplied scale factor. YSFI[3:0] I Data scaling factor input for Y input. Assigns the user supplied scale factor (number of right shifts) to the current input data before execution by up to sixteen (16) shifts. If the user has specified automatic scaling by asserting the DSFISEL control signal low, then the internal radix adjusted shift will be applied, instead of the user supplied scale factor. DSFO[3:0] O Data scale factor output. Assigns a worst case automatic scale factor (number of right shifts) to the DSP24 output data, which is to be scaled by the system when connected to the XSFI[3:0] on the next pass. XSFISEL I Data scale factor input select. When set low, enables the DSFI automatic block floating point adjustment. When set high, disables the automatic scaling and permits a user defined scale input to be performed. SCHSEL I Internal scheduler/controller selection. When set high the internal scheduler and the internal controllers are used. Note: Certain pins are dependent on this signal for there definition. XSWAP I When active high, exchanges the X imaginary data with the X real data * YSWAP I When active high, exchanges the Y imaginary data with the Y real data * BFPCLR I When active high clears BFPI[5:0] on any cycle (synchronous with SYSCLK) SYNCIN[1:0] I User defined arbitrary input waveform. SYNCOUT[1:0] O Data Sheet Delayed version of SYNCIN[1:0]. Matches the pipeline delay of the data as defined by the function code FC[5:0]. * After conjugation, if conjugation is set Page 5 DSP Architectures DSP24 Digital Signal Processor Table 1. (cont) DSP24 Signal-Pin Description PIN I/O SIGNAL DESCRIPTION CLOCKS, ENABLES, FLAGS, & POWER Page 6 CLKAIN I Clock input for port A. Clocks the input data memory to read from port A on the next SYSCLK rising edge. Ground this clock if not used. CLKBIN I Clock input for port B. Clocks the input data memory to read from port A on the next SYSCLK rising edge. Ground this clock if not used. CLKCIN I Clock input for port C. Clocks the input data memory to read from port A on the next SYSCLK rising edge. Ground this clock if not used. CLKDIN I Clock input for port D. Clocks the input data memory to read from port A on the next SYSCLK rising edge. Ground this clock if not used. CLKEIN I Clock input for port E. Clocks the input data memory to read from port A on the next SYSCLK rising edge. Ground this clock if not used. SYSCLK I Chip system clock. Clocks the chip controls and data ports. SYSCLKEN I Enables internal system clock (SYSCLK). AOE I A port output enable. When high allows the DSP24 to drive the bus. BOE I B port output enable. When high allows the DSP24 to drive the bus. COE I C port output enable. When high allows the DSP24 to drive the bus. DOE I D port output enable. When high allows the DSP24 to drive the bus. EOE I E port output enable. When high allows the DSP24 to drive the bus. POUT[2:0] O Encoded port output signal, indicates which data port is outputting data JCK I Input clock for JTAG serial test bus. JMS I Input mode select pin for JTAG serial test bus. JDI I JTAG serial bus input data JD0 O JTAG serial bus output data JRST I JTAG Reset VDD P Power for the chip VSS P Ground for the chip Data Sheet DSP Architectures Digital Signal Processor DSP24 SIGNAL-PIN DESCRIPTION FUNCTION SET SUMMARY Table 1. lists the DSP24 signals and their respective descriptions. Note: There are several pins that have dual functions depending on the state of the SCHSEL pin. The function set is organized into five areas: DSP, Complex Arithmetic, Logical, Vector Arithmetic, and General Purpose. There are thirty-four (34) opcodes for the DSP24. The DSP24 is a pass based processor where each control function and dataflow instruction is valid for one complete pass as framed by the START signal. Table 2 summarizes the DSP24 function set. Table 1. (cont) DSP24 Signal-Pin Description PIN I/O SIGNAL DESCRIPTION SCHEDULER/CONTROLLER SSYNC[1:0] O Scheduler output, usually connected to SYNCIN[1:0] to synchronize cascaded designs. User can optionally use this pin for system sync.. ADDREN I When active low, enables the DSP24 scheduler to drive the external PROM addresses ADDR[15:0]. BUSY O When active high, indicates the internal scheduler is sequencing system ADDR[15:0] O External PROM address lines ALG[7:0] I Offset bits that are summed with the out going ADDR[15:0] bits. Used for pointing to different routines in the external PROM. SCH_DB[7:0] I Scheduler input bus, used to source control information to the DSP24 and to any Memory Management Units (MMU's) in the system. GO[1:0] I Input signals that tell the internal scheduler to initiate the start of an algorithm. MMU START O Output signal, used by the MMU's to initiate the beginning of a pass. MMU R/W O Output signal, used to strobe the SCH_DB[7:0] signals into the MMU's. MMU A0 O Ouput signal, used by the MMU's in the system to point the SCH_DB[7:0] data to the proper internal address or data register. MMU TCA I Input signal from the MMU terminal count signal associated with the A port MMU TCB I Input signal from the MMU terminal count signal associated with the B port MMU TCC I Input signal from the MMU terminal count signal associated with the C port MMU TCD I Input signal from the MMU terminal count signal associated with the D port MMU TCE I Input signal from the MMU terminal count signal associated with the E port PI[1:0] I User supplied signal. Used in scheduler mode to modulate an arbitrary waveform onto two of the following signals; XCR, XCI, DOCR, DOCI, XZI, YZI, or DZO. * MMU CS[4:0] O Output signals, used to select the MMUs in the system. * Selection is accomplished in the firmware Data Sheet Page 7 DSP Architectures DSP24 Digital Signal Processor Table 2. Function Set Summary OPCODE MNEMONIC DESCRIPTION COMPLEX MATH FUNCTIONS 10 CADD Complex Add Performs a complex binary add operation with the input data and the coefficient data. 11 CSUB Complex Subtract Performs a complex binary add operation with the input data and the coefficient data. 0D CMUL Complex Multiply Performs a fractional two's complement complex multiplication operation with the input data and the coefficient data. 08 CMAC Complex Multiply/Accumulate Performs a fractional two's complement complex multiplication and complex accumulation of the result operation with the input data and the coefficient data 0C CMAG Complex Magnitude Performs a fractional two's complement square of the real input data added to the fractional two's complement square of the imaginary input data. LOGIC FUNCTIONS 18 NAND Performs a logical AND of the input data with the coefficient data. 1A NOR Performs a logical OR of the input data with the coefficient data. 1B XNOR Performs a logical XOR of the input data with the coefficient data. GENERAL PURPOSE FUNCTIONS 1D MOVC No operation, passes the complex data from one port to another 1C MOV 1C MOVD No operation, passes the complex data from one port to another 19 VPAS No operation, passes the complex data from one port to another No operation, passes the complex data from one port to another VECTOR FUNCTIONS Page 8 10 VADD Vector Add Performs a binary addition operation with the input data and the coefficient data. 11 VSUB Vector Subtract Performs a binary subtraction operation with the input data and the coefficient data. 12 VMUL Vector Multiply Performs a fractional two's complement multiplication operation with the input data and the coefficient data. 0A VMAC Vector Multiply/Accumulate Performs a fractional two's complement multiplication and accumulation of the result operation with the input data and the coefficient data. Data Sheet Digital Signal Processor DSP Architectures DSP24 Table 2. Function Set Summary (cont.) OPCODE MNEMONIC DESCRIPTION DSP FUNCTIONS 02 BFLY2 Radix2 Butterfly Performs a radix 2 based butterfly operation on the complex input data. 01 BFLY4 Radix4 Butterfly Performs a radix 4 based butterfly operation on complex input data. 0B BFLY8 Radix8 Butterfly Performs a radix 8 based butterfly operation on complex input data. 00 BFLY16 Radix16 Butterfly Performs a radix 16 based butterfly operation on complex input data 0F BFLY32 Radix32 Butterfly Performs a radix 32 based butterfly operation on complex input data 26 BFLY64* Radix64 Butterfly Performs a radix 64 based butterfly operation on complex input data 27 BFLY128* Radix128 Butterfly Performs a radix 128 based butterfly operation on complex input data 28 BFLY256* Radix256 Butterfly Performs a radix 256 based butterfly operation on complex input data 29 BFLY512* Radix512 Butterfly Performs a radix 512 based butterfly operation on complex input data 2A BFLY1024* Radix1024 Butterfly Performs a radix 1024 based butterfly operation on complex input data 17 VWND2 Radix2 Butterfly with Window Function. Performs a radix 2 based butterfly operation on the complex input data, after multiplying the incoming data by a window function. 1F VWND4 Radix4 Butterfly with Window Function. Performs a radix 4 based butterfly operation on complex input data, after multiplying the incoming data by a window function. 14 VWND8 Radix8 Butterfly with Window Function. Performs a radix 8 based butterfly operation on complex input data, after multiplying the incoming data by a window function. 15 VWND16 Radix16 Butterfly with Window Function. Performs a radix 16 based butterfly operation on complex input data, after multiplying the incoming data by a window function. 16 VWND32 Radix 32 Butterfly with Window Function. Performs a radix 32 based butterfly operation on complex input data, after multiplying the incoming data by a window function. 2B VWND64* Radix 64 Butterfly with Window Function. Performs a radix 64 based butterfly operation on complex input data, after multiplying the incoming data by a window function. 2C VWND128* Radix128 Butterfly with Window Function. Performs a radix 128 based butterfly operation on complex input data, after multiplying the incoming data by a window function. 2D VWND256* Radix256 Butterfly with Window Function. Performs a radix 256 based butterfly operation on complex input data, after multiplying the incoming data by a window function. 2E VWND512* Radix512 Butterfly with Window Function. Performs a radix 512 based butterfly operation on complex input data, after multiplying the incoming data by a window function. 2F VWND1024* Radix1024 Butterfly with Window Function. Performs a radix 1024 based butterfly operation on complex input data, after multiplying the incoming data by a window function. * For dual chip, seamless cascading Data Sheet Page 9 DSP Architectures DSP24 Digital Signal Processor Table 2. Function Set Summary (cont.) OPCODE MNEMONIC DESCRIPTION DSP FUNCTIONS (cont.) 05 BWND2 Radix2 Butterfly with Window Function. Performs a radix 2 based butterfly operation on the complex input data. Also multiplies the incoming data by a complex window function. 04 BWND4 Radix4 Butterfly with Window Function. Performs a radix 4 based butterfly operation on complex input data. Also multiplies the incoming data by a complex window function. 25 BWND8 Radix8 Butterfly with Window Function. Performs a radix 8 based butterfly operation on complex input data. Also multiplies the incoming data by a complex window function. 24 BWND16 Radix16 Butterfly with Window Function. Performs a radix 16 based butterfly operation on complex input data Also multiplies the incoming data by a complex window function. 20 BWND32* Radix 32 Butterfly with Window Function. Performs a radix 32 based butterfly operation on complex input data Also multiplies the incoming data by a complex window function. 21 BWND64* Radix 64 Butterfly with Window Function. Performs a radix 64 based butterfly operation on complex input data Also multiplies the incoming data by a complex window function. 22 BWND128* Radix128 Butterfly with Window Function. Performs a radix 128 based butterfly operation on complex input data Also multiplies the incoming data by a complex window function. 23 BWND256* Radix256 Butterfly with Window Function. Performs a radix 256 based butterfly operation on complex input data Also multiplies the incoming data by a complex window function. 03 BWND512* Radix512 Butterfly with Window Function. Performs a radix 512 based butterfly operation on complex input data Also multiplies the incoming data by a complex window function. 07 BRFT Real Only FFT- Two at a Time. Performs dual FFT's if the input data was real only, i.e. performing a 256 point complex FFT yields two seperate 256 point real results. 06 BFCT Real Only FFT-Double Length. Performs a double length FFT if the input data was real only, i.e. performing a 256 point complex FFT yields a 512 point real result. (N Output) 0E BFCT2 Real Only FFT-Double Length. Performs a double length FFT if the input data was real only, i.e. performing a 256 point complex FFT yields a 512 point real result. (2N Output) 08 BCFIR Complex finite impulse response (FIR) filter 09 BDFIR Double real finite impulse response (FIR) filter 0A BRFIR Real finite impulse response (FIR) filter * For dual chip, seamless cascading Page 10 Data Sheet DSP Architectures Digital Signal Processor DSP24 Table 2. Function Set Summary (cont.) OPCODE MNEMONIC DESCRIPTION DSP FUNCTIONS (cont.) 17 FOLD2 Weighted Overlap Add Function (WOA). Performs a vector multiply against an input window followed by a 2 point add. The result is a N/2 size array. 1F FOLD4 Weighted Overlap Add Function (WOA). Performs a vector multiply against an input window followed by a 4 point add. The result is a N/4 size array. 14 FOLD8 Weighted Overlap Add Function (WOA). Performs a vector multiply against an input window followed by a 8 point add. The result is a N/8 size array. 15 FOLD16 Weighted Overlap Add Function (WOA). Performs a vector multiply against an input window followed by a 16 point add. The result is a N/16 size array. 16 FOLD32 Weighted Overlap Add Function (WOA). Performs a vector multiply against an input window followed by a 32 point add. The result is a N/32 size array. Table 3. Data Flow Instructions HEX PORTS AFFECTED CODE MNEMONIC READ A READ B WRITE C 053 RA RB WC READ A READ B WRITE D 054 RA RB WD READ A READ B WRITE E 055 RA RB WE READ A READ C WRITE B 05A RA RC WB READ A READ C WRITE D 05C RA RC WD READ A READ C WRITE E 05D RA RC WE READ A READ D WRITE B 062 RA RD WB READ A READ D WRITE C 063 RA RD WC READ A READ D WRITE E 065 RA RD WE READ A READ E WRITE B 06A RA RE WB READ A READ E WRITE C 06B RA RE WC READ A READ E WRITE D 06C RA RE WD READ B READ A WRITE C 08B RB RA WC READ B READ A WRITE D 08C RB RA WD READ B READ A WRITE E 08D RB RA WE READ B READ C WRITE A 099 RB RC WA READ B READ C WRITE D 09C RB RC WD READ B READ C WRITE E 09D RB RC WE READ B READ D WRITE A 0A1 RB RD WA READ B READ D WRITE C 0A3 RB RD WC READ B READ D WRITE E 0A5 RB RD WE READ B READ E WRITE A 0A9 RB RE WA READ B READ E WRITE C 0AB RB RE WC READ B READ E WRITE D 0AC RB RE WD READ C READ A WRITE B 0CA RC RA WB READ C READ A WRITE D 0CC RC RA WD READ C READ A WRITE E 0CD RC RA WE READ C READ B WRITE A 0D1 RC RB WA READ C READ B WRITE D 0D4 RC RB WD READ C READ B WRITE E 0D5 RC RB WE HEX PORTS AFFECTED CODE MNEMONIC READ C READ D WRITE A 0E1 RC RD WA READ C READ D WRITE B 0E2 RC RD WB READ C READ D WRITE E 0E5 RC RD WE READ C READ E WRITE A 0E9 RC RE WA READ C READ E WRITE B 0EA RC RE WB READ C READ E WRITE D 0EC RC RE WD READ D READ A WRITE B 10A RD RA WB READ D READ A WRITE C 10B RD RA WC READ D READ A WRITE E 10D RD RA WE READ D READ B WRITE A 111 RD RB WA READ D READ B WRITE C 113 RD RB WC READ D READ B WRITE E 115 RD RB WE READ D READ C WRITE A 119 RD RC WA READ D READ C WRITE B 11A RD RC WB READ D READ C WRITE E 11D RD RC WE READ D READ E WRITE A 129 RD RE WA READ D READ E WRITE B 12A RD RE WB READ D READ E WRITE C 12B RD RE WC READ E READ A WRITE B 14A RE RA WB READ E READ A WRITE C 14B RE RA WC READ E READ A WRITE D 14C RE RA WD READ E READ B WRITE A 151 RE RB WA READ E READ B WRITE C 153 RE RB WC READ E READ B WRITE D 154 RE RB WD READ E READ C WRITE A 159 RE RC WA READ E READ C WRITE B 15A RE RC WB READ E READ C WRITE D 15C RE RC WD READ E READ D WRITE A 161 RE RD WA READ E READ D WRITE B 162 RE RD WB READ E READ D WRITE C 163 RE RD WC On all single operand functions like CMAG, the second read port is ignored Example: RAREWD becomes RAWD Data Sheet Page 11 DSP Architectures DSP24 Digital Signal Processor Figure 3. Data Flow Instructions Port A= 001 Port B= 010 Port C= 011 Port D= 100 Port E= 101 Example: 24 PORT A 24 24 24 48 24 48 Scheduler/ Controller Memory A 24 System Controls 24 Memory B 24 PORT E 48 Control 24 24 PROM Interface X Y data coefficients DSP Core X Input 001 010 011 24 48 Bus Y I np u t Bu s O u tp u t Bu s Write Output Read Y Input (coefficients) Read X Input 24 48 24 PORT B 24 48 48 48 48 24 48 48 48 24 24 24 24 24 PORT C PORT D Table 4. Function latencies MNEMONIC OPCODE LATENCY LATENCY 31 *VWND1K 2F 1301 118 *BWND32 20 275 171 *BWND64 21 307 224 *BWND128 22 371 277 *BWND256 23 499 28 *BWND512 3 755 116 BFCT 6 79 169 BFCT2 E 80 222 BRFT 7 47 275 BCFIR 8 47 48 BDFIR 9 23 135 BRFIR A 26 188 CMAG C 29 241 CMUL D 47 343 VMUL 12 26 407 VADD 10 26 535 VSUB 11 26 791 VNAND 18 12 1303 VNOR 1A 12 341 VXNOR 1B 12 405 MOVC 1D 12 533 MOVD 1C 12 789 VPAS 19 12 Latencies vary depending on weather the DSP24 is used in parallel or recursive configurations, see DSP24 Users Guide. *These instructions require two DSP24 chips in cascade MNEMONIC BFLY2 BFLY4 BFLY8 BFLY16 BFLY32 VWND2 VWND4 VWND8 VWND16 VWND32 BWND2 BWND4 BWND8 BWND16 *BFLY64 *BFLY128 *BFLY256 *BFLY512 *BFLY1K *VWND64 *VWND128 *VWND256 *VWND512 Page 12 OPCODE 2 1 B 0 F 17 1F 14 15 16 5 4 25 24 26 27 28 29 2A 2B 2C 2D 2E Data Sheet Digital Signal Processor DSP Architectures DSP24 DATA FLOW SUMMARY Each function requires a data flow opcode DF[8:0] that specifies what ports are to be used to input the operands and what port (Or internal memory) the result of the function code is to be written to. Using Table 3, the user selects the input port as the X input and the input port for the Y input, if any. The example next to Table 3 shows the mnemonic of RARCWB. This means to read port A as the X input data, read port C as the Y input data, and write port C with the result of the function performed. The user supplied binary code for the RARCWB data flow pattern is 001 for port A, 011 for port C, and 010 for port B. The hex code for 001 011 010 is 05A. As another example, Figure 3 illustrates the data flow pattern of RARBWC and a function code for a complex multiply (CMUL). The required operands enter the chip through the A and B ports, appear at the X and Y inputs to the internal core logic, respectively. The core logic performs a 24-bit complex multiply resulting a complex result of the form X+jY appearing after a latency at the C port. Table 4 lists the resulting latency for each type of function that the DSP24 can perform. When the MMU-24 is used in a design, it automatically compensates for the latency for each function code, including any latency generated by using pipelined memories in the system. Data Sheet Page 13 DSP Architectures DSP24 FUNCTIONAL DESCRIPTION The DSP24 is the latest generation of real time DSP designed to facilitate the handling of fast real time digital signals with a minimum of software overhead. The DSP24 is organized into five major groups: " " " " " Input and Output Data Ring Buses Core Logic Internal Memories Scheduler/Controller Control Inputs These major groups work in tandem to acquire complex or real data, apply functions on the acquired arrays of data, and store results both internally and externally for further processing, or output. INPUT AND OUTPUT RING BUSSES Data enters the DSP24 through any of its five complex data ports and exits the DSP24 through any of its complex five ports. The internal ring busses give the user complete control on which port to input operands from and which ports to output the results through. This elaborate internal structure frees the end user from virtually any need to multiplex data external to the DSP24. Additionally the five ports can be used to seamlessly cascade multiple chips as illustrated in the System Configurations section. CORE LOGIC The internal data path is designed to execute Fast Fourier Transforms (FFTs) with efficiency and precision. The core is will execute thirty four high level functions on the incoming data. Functions as sophicated as radix-1024 are performed at the full data rate. Each input complex pair of data id operated upon by the core using a super pipelined approach. This approach allows many operations to be performed on each clock cycle. The acquired array of complex or real data may be passes through the core logic multiple times for execution of complete algorithms such as fast adaptive Page 14 Digital Signal Processor digital filtering without the data having ever left the chip until the final output pass. The core logic reconfigures itself transparent to the user to facilitate unique parallel processing configurations that can command the needed performance to execute a 1024 point by 1024 point complex 2-D FFT at a 100 MHz sample rate sustained, when four chips are used. INTERNAL MEMORIES The DSP24 contains two banks of internal memory organized as 1024 words by 48 bits each. This memory is used to cascade multiple chips and to provide user storage of sampled data when arrays sizes are less than 1024 complex words (24 bits real plus 24 bits imaginary. As an example, the user may acquire 1024 complex words from a buffered analog-to-digital converter, as shown back in Figure 1. During the acquisition pass from Port A, a radix-32 FFT may be performed while the data is passing through the Logic Core into the internal A memory array. The next defined pass, if fast convolution (digital filtering) were being performed would be an inverse FFT with the complex data coming from the same memory A. Cascading of DSP24 chips for more functionally and higher sampled data rates uses the internal memories to store computed FFT columns before passing the complex data to the next chip connected to the output pins. See the System Configurations section. Through proper use of the internal memories, complete real time systems may be scaled up or down in performance by adding multiple ASIC silicon DSP24 cores on one die, by cascading multiple multiple die in one multi-chip module (MCM), by parallelizing multiple packaged chips on a board, or by parallelizing multiple boards in a unit. SCHEDULER/CONTROLLER To enable complete real time systems with minimum effort, the DSP24 contains all the circuitry to implement a robust application controller. The SCHEDULER/CONTROLLER maintains the users application by sourcing a series of instructions for the DSP24 itself and for any Memory Management Units (MMUs) in the system. The overall system control is accomplished through a combination of register programming and scheduling of control signals to synchronize the system resources in Data Sheet Digital Signal Processor DSP Architectures DSP24 SCHEDULER/CONTROLLER (cont.) The SCHEDULER/CONTROLLER plays a dual role in the overall system operation. Its primary role involves synchronously scheduling the events needed to perform demanding real time signal processing. This scheduling essentially takes the user provided program as it exists in the external PROM and parses it to both the internal MMU and the internal DSP controllers. The SCHEDULER/CONTROLLER's secondary role is to program both the DSP24 and any MMU-24's that reside in the system. These controllers provide a robust structure for efficient operation of all the resources in a typical real time system, including systems that contain multiple DSP24's for increased performance. Figure 4. illustrates the SCHEDULER, both internal CONTROLLERS, and the required external program PROM. CONTROL INPUTS For increased system flexibility, the user may select between using the internal SCHEDULER/CONTROLLER and supplying the necessary control signals himself. This option is exercised through either grounding the SCHSEL input pin, or connecting the SCHSEL pin to VCC. If SCHSEL is grounded, the user will be required to manage the signals shown in Figure 5. Note: Most of the signal pins shown in Figure 5 are dual function pins whose function depend on the state of the SCHSEL pin. Data Sheet Page 15 DSP Architectures DSP24 Digital Signal Processor Figure 4. SCHEDULER/CONTROLLER SCHSEL BUSY SSYNC [1:0] GO[1:0] MMUTCA MMUTCB MMUTCC MMUTCD MMUTCE SCHEDULER MMU RESET RESET MMU R/W START/STOP FC[5:0] MMU A0 MMU A1 DF[8:0] ENA MMU CONTROLLER ENB Internal Signals when SCHSEL is active MMU START MMUCSA XSFISEL MMUCSB XSFI[3:0] MMUCSC MMUCSD YSFI[3:0] XCI DSP CONTROLLER MMUCSE XCR DOCR DOCI YCI YCR XZI YZI DZO XSWAP ALG[7:0] + ADDREN ADDR[15:0] SCH DB[7:0] To Memory Management Units (MMU-24s) CS Page 16 EXTERNAL PROM Data Sheet DSP Architectures Digital Signal Processor DSP24 Figure 5. DSP24 Control/ Sync SYNCIN[1:0] SYNCOUT[1:0] Variable Length Shift Register SYSCLK SYSCLKEN FC[5:0] REG A Internal Chip Decodes REG B Internal Chip Decodes ERROR DF[8:0] ENA ENB XSFISEL XSFI[3:0] YSFI[3:0] BFPO[5:0] XCR XCI SFO[3:0] DOCR DOCI BFPI[5:0] YCR YCI XSWAP YSWAP DZO Internal Chip Decodes RESET START/STOP XZI YZI PI[1:0] Data Sheet Page 17 DSP24 DATA FORMATS INPUT/OUTPUT DATA FORMATS DSP Architectures Digital Signal Processor 25th bit (1/2 of the LSB) and adding: Fractional XXXXXXX Rounding + 0000008 XXXXXXX The DSP24 supports (2) two input data streams: one for real and one for imaginary data. For CMAG and FIR operations, the 48-bit output from each ALU accumulation is rounded to 48 bits and output from the DSP24, Most-Significant-Word first, in two clock cycles, one on the real side and one on the imaginary side. All other outputs are rounded up to 24 bits. BLOCK FLOATING-POINT For the radix butterfly transform operations, block floating-point data dependent scaling is provided. This preserves the signal-to-noise ratio by extending the dynamic range of the fixed-point operations. For each pass of an FFT, or on a separation pass, a scale factor is provided on the DSFO [2:0] pins at the completion of that pass. The scale factor is a binary shift number calculated from the size of the largest complex value output in that pass. Also, it is a worst case prediction of how large the magnitude of the largest complex value could be on the next pass. The magnitude is measured for each complex value output in the pass. The maximum magnitude is compared to many threshold values. If the magnitude is gr eater, the corresponding shift value (from an internal lookup table) is output on DSFO [3:0]. It is used at the beginning of the next pass on the XSFI [3:0] pins and causes a right shift of the real and imaginary 24-bit inputs to prevent overflow on the pass. The BFPO [5:0] is the accumulated scale factor for the entire transform and is valid upon the transform's completion. The BFPO and BFPI pins should be connected together for single and parallel chip applications, or connected serially for cascaded operations. When bit 25 is set, the output is rounded up, other-wise the data is not rounded. THEORY OF OPERATION FUNCTION SET OVERVIEW The DSP24 is a high-performance array processor designed to perform operations on large arrays of data. Accordingly, the DSP24 has a powerful function set in the sense that each function opcode accomplishes a substantial task. The following are some key points about the DSP24 function set. " " " " ROUNDING/SHIFTING OPERATION All data input to the DSP24 passes through a shifter and rounder at both the input and output stages. The amount of shifting and rounding is determined by the current instruction. To correctly scale the incoming data, the shifter is capable of shifting up to (16) sixteen DSFI bit positions to the right. The rounder trims the data to the necessary 24 bits needed by monitoring the Page 18 " Since the DSP24 is a pass-based processor,each function is valid for one complete pass. Each opcode defines a basic flow for the desired operation. This basic data flow is then repeated for multiple pairs of data to complete one pass. Each function is qualified by the START/STOP signal to indicate the beginning of a pass and end of a pass respectively. The Transform functions can also be qualified by DZI and DZO signals which, when asserted, cause the DSP24 to input a string of zeros and force output data to zeros respectively. This feature allows a user to zero fill and zero pad the data on any given pass. The DSP24 function set consist of five functional groupings. A 6-bit opcode is assigned to each function, with a total of thirty-four functions supported. The function code on the pins FC[ 5:0] must be setup at least three machine cycles ahead of data setup. This allows the automatic scaling factor to be decoded for the next pass. For a typical array processing application, such as FFTs, first a function code is set up (e.g., BFLY32),and then the whole data array is clocked into the DSP24. The applied function will then be applied to the whole array. There is a latency, given in machine cycles when implementing the DSP24 functions (see Table 4.) This latency is automatically compensated for when the MMU-24 is used in a system. Data Sheet DSP Architectures Digital Signal Processor THEORY OF OPERATION (cont.) FUNCTION SET OVERVIEW (cont.) There are provisions, useful for implementing inverse FFTs, to conjugate the inputs to, and the outputs from, the complex arithmetic functions (pins DCI and DCO). Similarly, the input and output data values can be complemented for the vector arithmetic and logical functions. The DSP24 also includes a PASS general purpose function, this function moves data and coefficients between ports and through the execution unit without altering their value. INPUT/OUTPUT DATA FLOW Data input to and output from the DSP24 depends upon the data flow function given (reference Table 3). TWO REAL TRANSFORMS (BRFT) The BRFT function may be used to process two frames of real-data simultaneously and obtain almost twice the performance while still using a complex data FFT. Given two real sequences, h(n) and g(n), they can be concatenated and represented as a complex sequence, such as: x(n) = h(n) + jg(n). To compute the BRFT do the following: 1. Functions h(k) and g(k) are real k = 0, 1, ..., N - 1 2. Form the complex function y(k) = h(k) + jg(k) k = 0, 1, ..., N - 1 3. Compute the FFT N-1 Y(n)= y(k)e-j2 nk/N DSP24 n = 0, 1, ..., N - 1 where H(n) and G(n) are the discrete transforms of h(k) and g(k), respectively. DOUBLE LENGTH RECOMBINATION OF FFT OUTPUT (BFCT) This pass performs both a fast cosine transform recombination and a double length separation. Double Length Separation separates a 2N length real FFT from a N length complex FFT as follows: 1. Function x(k) is real k = 0, 1, ..., 2N - 1 2. Divide x(k) into two functions h(k) = x(2k) g(k) = x(2k + 1) k = 0, 1, ..., N - 1 3. Form the complex function y(k) = h(k) + jg(k) k = 0, 1, ..., N - 1 4. Compute the FFT N-1 k=0 = R(n) + jI(n) n = 0, 1, ..., N - 1 where R(n) and l(n) are the real and imaginary parts of Y(n), respectively. 5. Compute the separation Xr(n) = = R(n) + jI(n) n = 0, 1, ..., N - 1 where R(n) and l(n) are the real and imaginary parts of Y(n), respectively. 4. Compute the separation H(n)= R(n) + R(N-n) +j 2 2 I(n) 2 G(n)= I(n) 2 R(n) 2 + I(N-n) 2 n=0, 1,....., N-1 Data Sheet -j - I(N-n) 2 R(N-n) 2 R(n) + R(N-n) 2 2 - sin Xi(n) = k=0 y(k)e-j2 nk/N Y(n)= n N I(n) 2 - cos n N - + cos R(n) 2 R(N-n) 2 I(N-n) 2 - sin R(n) 2 R(N-n) 2 n N I(n) 2 + I(N-n) 2 n= 0, 1,....,N-1 n N I(n) 2 + I(N-n) 2 n= 0, 1,....,N-1 where xr(n) and xi(n) are respectively the real and imaginary parts of the 2N point discrete transform of x(k). NOTES: 1. Only N points of the real output are unique, and the imaginary output will be zero since the input function is an even, real only function. 2. The DSP24 does not perform the division by two in the BRFT, BFCT, and BFCT2 functions. This was done to allow the user to perform the division by two, if so decided. Page 19 DSP24 DSP Architectures Digital Signal Processor SYSTEM OVERVIEW The DSP24 incorporates a unique architecture optimized for extremely high data throughput and minimal hardware/software system development. For the digital filter example of Figure 7, do a 4096 point forward FFT, a multiplication, and an inverse FFT, using the following program. BWND4 +Window Column 1 BFLY32 Column 2 BFLY32 Column 3 Conjugate Input BWND4 + Complex multiply Column 4 BFLY32 Column 5 Conjugate Output BFLY32 Column 6 Figure 7 DSP24 BWND4 INPUT DATA COLUMN 1 Window DSP24 INPUT DATA BFLY32 COLUMN 2 For a 4K transform, there are three columns using the radix-4 and radix-32 operations. Each column represents one "pass". A "pass" is transferring data from one memory bank (AB,C,D, or E), through the machine to the other memory bank (A, B, C, D, E, or F). During each pass the DSP24 performs a DSP function on the data using coefficients from the coefficient port, if necessary. As shown in Figure 7 the data is first input through DSP24 and a window function is combined with the first column of the FFT. Next the data is passed a second time through the DSP24 performing a radix32 operation, the third pass back through the DSP24 another radix32 operation is performed. This completes the forward FFT including the window function multiply. For the forth through the sixth passes through the DSP24 this three pass operation is repeated with the window function being replaced with the desired filter coefficients, also the data on the fourth pass is conjugated on the input side and the data on the sixth pass is conjugated on the output side. This approach to real time DSP can be proportionally accelerated by adding multiple DSP24's in the data flow, the following section on system configurations illustrate this. Twiddles DSP24 BFLY32 INPUT DATA COLUMN 3 Twiddles DSP24 INPUT DATA BWND4 COLUMN 4 Filter DSP24 BWND32 INPUT DATA COLUMN 5 Twiddles DSP24 INPUT DATA BWND32 COLUMN 6 Twiddles Page 20 Data Sheet DSP Architectures Digital Signal Processor DSP24 Figure 8a INPUT 50 MHz Complex OUTPUT PORT A 50 MHz Complex PORT B 24 24 24 24 24 24 24 24 PORT E PORT C 24 24 PORT D Figure 8b INPUT OUTPUT 100 MHz Complex 100 MHz Complex PORT A PORT B 24 PORT A 24 24 24 24 PORT E PORT C 24 24 24 24 24 PORT B 24 24 24 PORT D 24 24 24 24 24 PORT E PORT C 24 24 PORT D SYSTEM CONFIGURATIONS For several applications, the DSP24 may be used alone without external components as shown in Figure 8a. This configuration will perform a 1024 point complex FFT in just two passes, for a continuous sampling rate of 50 MHz complex. The 50 MHz performance may be scaled up to 100 MHz by simply adding another DSP24 die in the package or two packaged chips back to back, see Figure 8b. For larger arrays, external memories and external Memory Management Units (MMU-24s) may be required, as shown in Figure 9a. The addition of these simple external devices will support arrays up to 1 million complex points. Again two packaged chips, or two die may be cascaded back to back as shown in Figure 9b to increase performance. Figure 10 shows the four data flow phases required for two DSP24 chips performing a four pass operation such Data Sheet as a 2-D 1024 point complex FFT followed by a 2-D 1024 point inverse complex FFT. As shown in Figure 10a data enters port A of the first DSP24 #1 along with the required twiddle factors through port D. This data is processed through the core logic of DSP24 #1 and passes out of port C to the input port E of DSP24 #2. The data then exits DSP24 #2 through port C into the memory connected to port C. This completes the first of four passes. The second, third, and fourth passes of the algorithm are shown in Figure 10b, 10c, and 10d respectfully. The data is ping ponged in this fashion for the total required number of passes. Page 21 DSP Architectures DSP24 Digital Signal Processor Figure 9a INPUT 50 MHz Complex OUTPUT PORT A 50 MHz Complex PORT B 24 24 24 24 MMU PORT E PORT C M SRA SRA M 24 24 24 24 24 PORT D MMU MMU 24 SRAM Figure 9b INPUT OUTPUT 100 MHz/# of passes Complex 100 MHz/# of passes Complex PORT A PORT B 24 24 24 24 MMU PORT E PORT C DIE 1 DIE 2 24 MMU Page 22 24 SRAM PORT D MMU M SR A 24 24 SRA M 24 24 Data Sheet DSP Architectures Digital Signal Processor DSP24 Figure 10 2-D Complex 1K x 1K Fast Convolution PORT A PORT B 24 24 MMU 24 24 24 24 PORT C 24 24 DSP24 2 PORT E PORT C 24 M SRA 24 MMU M SRA 24 MMU 24 DSP24 2 PORT E 24 24 24 PORT D 24 MMU MMU 24 PORT A PORT C 24 M SR A MMU 24 24 24 PORT D 24 MMU MMU PORT B 24 24 24 24 PORT C 24 24 DSP24 2 PORT E 24 PORT C 24 24 MMU 24 PORT D SRAM Fourth radix-32 column (BFLY32) 24 24 24 MMU 24 SRAM SR A 24 24 PORT D MMU M SRA M 24 PORT A 24 DSP24 1 PORT E Figure 10d Phase 4 PORT D Second radix-32 column (BFLY32) PORT B 24 24 SRAM Combined filter multiply and first radix-32 IFFT (VWND32) column 24 PORT C 24 24 SRAM PORT A 24 DSP24 2 PORT E 24 24 24 24 24 24 PORT B 24 24 DSP24 1 PORT E Figure 10c Phase 3 PORT D Third radix-32 column (BFLY32) PORT B 24 24 SRAM Fourth radix-32 column (BFLY32) 24 PORT C 24 24 SRAM PORT A 24 SR A M PORT C 24 24 24 24 24 MMU MMU 24 PORT B 24 DSP24 1 PORT E PORT A 24 24 Figure 10b Phase 2 Second radix-32 column (BFLY32) PORT B 24 PORT D SRAM Window and first radix-32 column (VWND32) PORT A 24 MMU PORT D SRAM SR A M 24 24 24 MMU 24 SR A M 24 24 24 MMU Data Sheet PORT B 24 DSP24 1 PORT E Figure 10a Phase 1 PORT A 24 Third radix-32 column (BFLY32) Page 23 DSP Architectures DSP24 Figure 11a Cascading Four Chips, Phase one SYSTEM CONFIGURATIONS (cont.) MMU-24 Up tp 100 MSPS Continuous Data Input PORT A 24 PORT B 24 24 PORT A 24 24 24 24 24 24 48 24 24 24 PROM Interface 48 PORT B 24 24 24 24 Scheduler/ Controller 48 System Controls Logic Core PROM Interface 48 Scheduler/ Controller Control Memory A 24 Control 24 24 24 24 Memory B 24 24 24 24 48 24 Memory A 24 Memory B 24 PORT E System Controls Logic Core 24 24 48 24 PORT C SRAM 24 PORT E PORT C MMU-24 24 24 24 24 PORT D PORT A 24 PORT B 24 PORT A 24 24 24 24 24 24 24 24 PROM Interface 48 PORT B 24 24 24 Scheduler/ Controller 48 System Controls Logic Core Up to 100 MSPS Continuous Data Output 24 24 24 48 24 PORT D 24 24 24 PROM Interface 48 Scheduler/ Controller Control Memory A 24 Control 24 24 24 24 Memory B 24 24 24 24 48 24 Memory A 24 Memory B 24 PORT E System Controls Logic Core 24 PORT C SRAM Cascading four DSP24's yields an impressive 100 MSPS complex FFT with 1 million complex points of resolution, or a 1024x1024 two-dimension(2-D) transform in 20 milliseconds. Figure 11 shows a Multi-Chip Module (MCM) with four DSP24 die connected back to back. As illustrated in Figure 11a, phase one runs all four die concurrently with the top two chips performing 1024 of the required 1024 point complex FFT's and storing the result in an external 1 million point RAM. While this is taking place the bottom two chips in the MCM are taking the results from a previous pass and also performing 1024 of the required 1024 point complex FFT's for the final output. Figure 11b shows the second phase of this concurrent process with the chip pairs swapping working memories, this allows real time processing in a seamless pipelined fashion. Digital Signal Processor 24 48 24 24 PORT E 24 24 24 24 24 24 24 24 PORT D PORT C PORT D MMU-24 ROM MMU-24 ROM Figure 11b Cascading Four Chips Phase two MMU-24 Up tp 100 MSPS Continuous Data Input 24 24 24 PORT B PORT A 24 24 24 24 24 PROM Interface 48 24 24 Scheduler/ Controller 48 System Controls Logic Core PROM Interface 48 Scheduler/ Controller Control 24 24 24 Memory B 24 24 24 24 48 24 Memory A 24 Memory B 24 System Controls Logic Core Control Memory A 24 24 PORT E PORT B 24 24 24 48 24 24 24 24 24 48 24 PORT C SRAM PORT A 24 PORT E PORT C MMU-24 24 24 24 PORT D PORT A 24 24 PORT B PORT A 24 24 24 24 24 PROM Interface Scheduler/ Controller 24 48 System Controls PROM Interface 48 Scheduler/ Controller PORT E Control 24 24 Memory B 24 24 24 Memory A 24 24 24 PORT C 24 48 24 24 PORT E 24 24 24 24 24 24 24 24 PORT D Page 24 PORT C PORT D MMU-24 ROM 24 Memory B 24 24 48 System Controls Logic Core Control Memory A 24 24 PORT B 24 24 Logic Core Up to 100 MSPS Continuous Data Output 24 24 24 48 24 24 24 48 24 PORT D 24 24 24 SRAM 24 ROM MMU-24 Data Sheet DSP Architectures Digital Signal Processor ABSOLUTE MAXIMUM RATINGS 1,2 Supply Voltage to VSS Potential Signal Pin Voltage to VSS Potential DC Output Current Storage Temperature range Power Dissipation (Package Limit) DC Voltage Applied to Outputs in High-Z State OPERATING RANGE 1 DC ELECTRICAL CHARACTERISTICS SYMBOL 1 DESCRIPTION ILPUI 6 Current ILPDI Pull-Down Input Leakage 7 -0.3 V to 5V -0.3 to VDD +0.3 V (not to exceed 5 V) + - 10 mA -40 deg C to 125 deg C 18 W -0.3 to VDD +0.3 V (not to exceed 5 V) MIN Temperature, Ambient 0 Supply Voltage 3.13 Supply Voltage 0.0 Logic '0' Input Voltage 5 Logic '1' Input High Voltage 0.7 VDD TA VDD VSS VIL VIH DSP24 ILI VLOH VOL IDDI Input Leakage Current Output High Voltage Output Low Voltage Average Supply Current IDD2 Average Standby Current MAX 70 3.43 0.0 0.3 VDD VDD+0.3 UNIT deg C V V V V (Over Operating Range) TEST CONDITIONS VDD=3.13 V, VIN=0 V VIN=VDD VDD=3.13, VIN=VDD VIN=VSS VDD=3.13 V, VIN= 0 to VDD IOH=-6.0 mA IOL=6.0 mA Measured at tcyc (100MHz) All inputs = VIL (0.3 VDD), MIN -70 -10 15 -10 -10 1.58 MAX -15 10 70 10 10 UNIT uA 0.26 1200 V V mA 1 mA 1 mA Excludes output load current. IDD3 All inputs = VIL (0.3 VDD), Quiescent Standby Current Excludes output load current. See notes on Page 26 Data Sheet Page 25 DSP Architectures DSP24 AC TEST CONDITIONS 1 RATING VSS to 3.0 VDD 1.5 ns (Figure 16a) 0.35 VDD 0.35 VDD Figure 16b PARAMETER Input Pulse levels Input Rise & Fall Times (10% to 90%) Input Timing Reference Levels Output Reference Levels Output Load, Timing Tests CAPACITANCE SYMBOL CIN COUT Digital Signal Processor 1,4 RATING TEST CONDITIONS TA=25 deg C, F=1MHz, VDD=3.13 V 10 pF TA=25 deg C, F=1MHz, VDD=3.13 V 10 pF DESCRIPTION Input Capacitance Output Capacitance 1.0 V 3.0 VDDV 100 90% 67 100 VSS 90% 10% 10% 35 pf 1.5ns INCLUDES JIG AND SCOPE CAPACITANCES DSP24 Figure 12a. Output Load Circuit 1.5ns DSP24 Figure 12b. Input Rise and Fall Times NOTES: 1. All voltages are measured with respect to VSS. 2. Stresses greater than those listed under 'Absolute Maximum Ratings' may cause permanent damage to the device. This is a stress rating for transient conditions only. Functional operation of the device at these or any other conditions above those indicated in the ' Operating Range' of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 3. Outputs should not be shorted for more than 30 seconds. No more than one output should be shorted at any time. 5. The DSP24 inputs are able to withstand a 1.0V undershoot for less than 10 ns per cycle. 6. An internal pull-up resistor is attached to all the data bus pins : AR[23:0], AI[23:0], BR[23:0], BI[23:0], CR[23:0], CI[23:0], DR[23:0], DI[23:0], ER[23:0], EI[23:0]. 7. An internal resistor is attached to all the non-bus signals to bias them inactive when not physically connected at the board level. 8. IDD is dependent upon actual output loading and cycle rates. Specific values are with outputs open. 4. Sample tested only Page 26 Data Sheet DSP Architectures Digital Signal Processor DSP24 AC ELECTRICAL CHARACTERISTICS SIGNAL tCYC tCL tCH tSCLKEN tHCLKEN tRESET tSKL tSKT tDSA tDHA tDODA tDOHA tLZOEA tHZOEA tDSB tDHB tDODB tDOHB tLZOEB tHZOEB tDSC tDHC tDODC tDOHC tLZOEC tHZOEC tDSD tDHD tDODD tDOHD tLZOED tHZOED tDSE tDHE tDODE tDOHE tLZOEE tHZOEE tSA tHA tSCTLA tHCTLA tSB tHB tSCTLB tHCTLB tSCTLC tHCTLC tODCTL tSBFPC tHBFPC tSSTART tHSTART tSSYNC tHSYNC tDODSYNC tDODPOUT tDODERR Data Sheet 80 MHz 100 MHz MIN TYP MAX MIN TYP MAX UNIT ns 12.5 10 SYSCLK Cycle Time ns 6.25 5 Clock Low Time (SYSCLK) ns 6.25 5 Clock High Time (SYSCLK) ns 7 6 SYSCLKEN Setup Time (SYSCLK) ns 0 0 SYSCLKEN Hold Time (SYSCLK) ns 20 20 RESET High Time ns 2 1.5 CLKxIN to SYSCLK, Rising Edge to Rising Edge Skew ns 2 1.5 SYSCLK to CLKxIN, Rising Edge to Rising Edge Skew ns 7 6 AR[23:0], AI[23:0] Setup Time (CLKAIN) ns 0 0 AR[23:0], AI[23:0] Hold Time (CLKAIN) ns 8 7 AR[23:0], AI[23:0] Output Delay Time (SYSCLK) ns 3 2 AR[23:0], AI[23:0] Output Hold Time (SYSCLK) ns 8 9 AOE High to AR[23:0], AI[23:0] Low-Z ns 8 9 AOE Low to AR[23:0], AI[23:0] High-Z ns 7 6 BR[23:0], BI[23:0] Setup Time (CLKBIN) ns 0 0 BR[23:0], BI[23:0] Hold Time (CLKBIN) ns 8 7 BR[23:0], BI[23:0] Output Delay Time (SYSCLK) ns 3 2 BR[23:0], BI[23:0] Output Hold Time (SYSCLK) ns 8 9 BOE High to BR[23:0], BI[23:0] Low-Z ns 8 9 BOE Low to BR[23:0], BI[23:0] High-Z ns 7 6 CR[23:0], CI[23:0] Setup Time (CLKCIN) ns 0 0 CR[23:0], CI[23:0] Hold Time (CLKCIN) ns 8 7 CR[23:0], CI[23:0] Output Delay Time (SYSCLK) ns 3 2 CR[23:0], CI[23:0] Output Hold Time (SYSCLK) ns 8 9 COE High to CR[23:0], CI[23:0] Low-Z ns 8 9 COE Low to CR[23:0], CI[23:0] High-Z ns 7 6 DR[23:0], DI[23:0] Setup Time (CLKDIN) ns 0 0 DR[23:0], DI[23:0] Hold Time (CLKDIN) ns 8 7 DR[23:0], DI[23:0] Output Delay Time (SYSCLK) ns 3 2 DR[23:0], DI[23:0] Output Hold Time (SYSCLK) ns 8 9 DOE High to DR[23:0], DI[23:0] Low-Z ns 8 9 DOE Low to DR[23:0], DI[23:0] High-Z ns 7 6 ER[23:0], EI[23:0] Setup Time (CLKEIN) ns 0 0 ER[23:0], EI[23:0] Hold Time (CLKEIN) ns 8 7 ER[23:0], EI[23:0] Output Delay Time (SYSCLK) ns 3 2 ER[23:0], EI[23:0] Output Hold Time (SYSCLK) ns 8 9 EOE High to ER[23:0], EI[23:0] Low-Z ns 8 9 EOE Low to ER[23:0], EI[23:0] High-Z ns 7 6 ENA Setup Time (SYSCLK) ns 0 0 ENA Hold Time (SYSCLK) ns 7 6 FC[5:0], DF[8:0] Setup Time (SYSCLK) ns 0 0 FC[5:0], DF[8:0] Hold Time (SYSCLK) ns 7 6 ENB Setup Time (SYSCLK) ns 0 0 ENB Hold Time (SYSCLK) ns 7 6 XSFISEL, XSFI[3:0], YSFI[3:0], BFPI[5:0], XCR, XCI, DOCR, DOCI Setup ns 0 0 XSFISEL, XSFI[3:0], YSFI[3:0], BFPI[5:0], XCR, XCI, DOCR, DOCI Hold ns 6 XZI, YZI, DZO, YCR, YCI, YSWAP, XSWAP Setup (SYSCLK) 7 ns 0 0 XZI, YZI, DZO, YCR, YCI, YSWAP, XSWAP Hold (SYSCLK) ns 7 8 BFPO[5:0], DSFO[3:0] Output Delay Time (SYSCLK) ns 7 6 BFPCLR Setup Time (SYSCLK) ns 0 0 BFPCLR Hold Time (SYSCLK) ns 7 6 START/STOP Setup Time (SYSCLK) ns 0 0 START/STOP Hold Time (SYSCLK) ns 7 6 SYNCIN[1:0] Setup Time (SYSCLK) ns 0 0 SYNCIN[1:0] Hold Time (SYSCLK) ns 7 8 SYNCOUT[1:0] Output Delay Time (SYSCLK) ns 7 8 POUT[2:0] Output Delay Time (SYSCLK) ns 7 8 7 8 ERROR Output Delay Time (SYSCLK) DESCRIPTION Page 27 DSP Architectures DSP24 AC ELECTRICAL CHARACTERISTICS SIGNAL tSSCH tHSCH tSGO tHGO tSTC tHTC tHZADDR tLZADDR tODADDR tSSDB tHSDB tODMRESET tODRW tODA0 tODSTART tODCS tODBUSY tODSSYNC DESCRIPTION SCHSEL Setup Time (SYSCLK) SCHSEL Hold Time (SYSCLK) GO[1:0] Setup Time (SYSCLK) GO[1:0] Hold Time (SYSCLK) MMU_TC_A, _B, _C, _D, _E Setup Time (SYSCLK) MMU_TC_A, _B, _C, _D, _E Hold Time (SYSCLK) ADDREN High to ADDR[15:0] High-Z ADDREN Low to ADDR[15:0] Low-Z ADDR[15:0] Output Valid Delay Time (SYSCLK) SCHDB[7:0] Setup Time (SYSCLK) SCHDB[7:0] Hold Time (SYSCLK) MMU_RESET Output Delay Time (SYSCLK) MMU_R/W Output Delay Time (SYSCLK) MMU_A0 Output Delay Time (SYSCLK) MMU_START Output Delay Time (SYSCLK) MMU_CS_A, B, C, D, E Output Delay Time (SYSCLK) BUSY Output Delay Time (SYSCLK) SSYNC[1:0] Output Delay Time (SYSCLK) Digital Signal Processor 80 MHz 100 MHz MIN TYP MAX MIN TYP MAX UNIT ns 7 6 ns 0 0 ns 6 6 ns 0 0 ns 7 6 ns 0 0 ns 8 9 ns 8 9 ns 7 8 ns 7 6 ns 0 0 ns 7 8 ns 7 8 ns 7 8 ns 7 8 ns 7 8 ns 7 8 ns 7 8 7 8 Note: All clocks signals (CLKxIN, SYSCLK) must be driven, or grounded if not used Page 28 Data Sheet DSP Architectures Digital Signal Processor AC ELECTRICAL CHARACTERISTICS SIGNAL tCYC tCL tCH tSCLKEN tHCLKEN tRESET tSKL tSKT tDSA tDHA tDODA tDOHA tLZOEA tHZOEA tDSB tDHB tDODB tDOHB tLZOEB tHZOEB tDSC tDHC tDODC tDOHC tLZOEC tHZOEC tDSD tDHD tDODD tDOHD tLZOED tHZOED tDSE tDHE tDODE tDOHE tLZOEE tHZOEE tSA tHA tSCTLA tHCTLA tSB tHB tSCTLB tHCTLB tSCTLC tHCTLC tODCTL tSBFPC tHBFPC tSSTART tHSTART tSSYNC tHSYNC tDODSYNC tDODPOUT tDODERR Data Sheet DESCRIPTION SYSCLK Cycle Time Clock Low Time (SYSCLK) Clock High Time (SYSCLK) SYSCLKEN Setup Time (SYSCLK) SYSCLKEN Hold Time (SYSCLK) RESET High Time CLKxIN to SYSCLK, Rising Edge to Rising Edge Skew SYSCLK to CLKxIN, Rising Edge to Rising Edge Skew AR[23:0], AI[23:0] Setup Time (CLKAIN) AR[23:0], AI[23:0] Hold Time (CLKAIN) AR[23:0], AI[23:0] Output Delay Time (SYSCLK) AR[23:0], AI[23:0] Output Hold Time (SYSCLK) AOE High to AR[23:0], AI[23:0] Low-Z AOE Low to AR[23:0], AI[23:0] High-Z BR[23:0], BI[23:0] Setup Time (CLKBIN) BR[23:0], BI[23:0] Hold Time (CLKBIN) BR[23:0], BI[23:0] Output Delay Time (SYSCLK) BR[23:0], BI[23:0] Output Hold Time (SYSCLK) BOE High to BR[23:0], BI[23:0] Low-Z BOE Low to BR[23:0], BI[23:0] High-Z CR[23:0], CI[23:0] Setup Time (CLKCIN) CR[23:0], CI[23:0] Hold Time (CLKCIN) CR[23:0], CI[23:0] Output Delay Time (SYSCLK) CR[23:0], CI[23:0] Output Hold Time (SYSCLK) COE High to CR[23:0], CI[23:0] Low-Z COE Low to CR[23:0], CI[23:0] High-Z DR[23:0], DI[23:0] Setup Time (CLKDIN) DR[23:0], DI[23:0] Hold Time (CLKDIN) DR[23:0], DI[23:0] Output Delay Time (SYSCLK) DR[23:0], DI[23:0] Output Hold Time (SYSCLK) DOE High to DR[23:0], DI[23:0] Low-Z DOE Low to DR[23:0], DI[23:0] High-Z ER[23:0], EI[23:0] Setup Time (CLKEIN) ER[23:0], EI[23:0] Hold Time (CLKEIN) ER[23:0], EI[23:0] Output Delay Time (SYSCLK) ER[23:0], EI[23:0] Output Hold Time (SYSCLK) EOE High to ER[23:0], EI[23:0] Low-Z EOE Low to ER[23:0], EI[23:0] High-Z ENA Setup Time (SYSCLK) ENA Hold Time (SYSCLK) FC[5:0], DF[8:0] Setup Time (SYSCLK) FC[5:0], DF[8:0] Hold Time (SYSCLK) ENB Setup Time (SYSCLK) ENB Hold Time (SYSCLK) XSFISEL, XSFI[3:0], YSFI[3:0], BFPI[5:0], XCR, XCI, DOCR, DOCI Setup XSFISEL, XSFI[3:0], YSFI[3:0], BFPI[5:0], XCR, XCI, DOCR, DOCI Hold XZI, YZI, DZO, YCR, YCI, YSWAP, XSWAP Setup (SYSCLK) XZI, YZI, DZO, YCR, YCI, YSWAP, XSWAP Hold (SYSCLK) BFPO[5:0], DSFO[3:0] Output Delay Time (SYSCLK) BFPCLR Setup Time (SYSCLK) BFPCLR Hold Time (SYSCLK) START/STOP Setup Time (SYSCLK) START/STOP Hold Time (SYSCLK) SYNCIN[1:0] Setup Time (SYSCLK) SYNCIN[1:0] Hold Time (SYSCLK) SYNCOUT[1:0] Output Delay Time (SYSCLK) POUT[2:0] Output Delay Time (SYSCLK) ERROR Output Delay Time (SYSCLK) DSP24 60 MHz MIN TYP MAX 16.7 8.3 8.3 7 1 20 2 2 7 0 9 3 9 9 7 0 9 3 9 9 7 0 9 3 9 9 7 0 9 3 9 9 7 0 9 3 9 9 7 0 7 0 7 0 7 0 7 0 8 7 0 7 0 7 0 8 8 8 8 Page 29 DSP Architectures DSP24 AC ELECTRICAL CHARACTERISTICS SIGNAL tSSCH tHSCH tSGO tHGO tSTC tHTC tHZADDR tLZADDR tODADDR tSSDB tHSDB tODMRESET tODRW tODA0 tODSTART tODCS tODBUSY tODSSYNC DESCRIPTION SCHSEL Setup Time (SYSCLK) SCHSEL Hold Time (SYSCLK) GO[1:0] Setup Time (SYSCLK) GO[1:0] Hold Time (SYSCLK) MMU_TC_A, _B, _C, _D, _E Setup Time (SYSCLK) MMU_TC_A, _B, _C, _D, _E Hold Time (SYSCLK) ADDREN High to ADDR[15:0] High-Z ADDREN Low to ADDR[15:0] Low-Z ADDR[15:0] Output Valid Delay Time (SYSCLK) SCHDB[7:0] Setup Time (SYSCLK) SCHDB[7:0] Hold Time (SYSCLK) MMU_RESET Output Delay Time (SYSCLK) MMU_R/W Output Delay Time (SYSCLK) MMU_A0 Output Delay Time (SYSCLK) MMU_START Output Delay Time (SYSCLK) MMU_CS_A, B, C, D, E Output Delay Time (SYSCLK) BUSY Output Delay Time (SYSCLK) SSYNC[1:0] Output Delay Time (SYSCLK) Digital Signal Processor 60 MHz MIN TYP MAX 7 0 6 0 7 0 9 9 8 7 0 8 8 8 8 8 8 8 8 Note: All clocks signals (CLKxIN, SYSCLK) must be driven, or grounded if not used Page 30 Data Sheet DSP Architectures Digital Signal Processor DSP24 AC ELECTRICAL CHARACTERISTICS tCYC Figure 13. DSP24 Timing tCH tCL SYSCLK tSCLKEN SYSCLKEN tHCLKEN tRESET RESET tSCTLA FC[5:0] DF[8:0] tSA tHCTLA tHA ENA tSCTLB XSFISEL, XSFI[3:0] YSFI[3:0], BFPI[5:0] XCR, XCI DOCR, DOCI tSB tHCTLB tHB ENB tSCTLC XZI, YZI, DZO YCR, YCI, YSWAP XSWAP tHCTLC SCHSEL tDODCTL BFPO[[5:0] DSFO[3:0] tSBFPC BFPCLR tSSYNC tHBFPC tHSYNC SYNCIN[1:0] tDODSYNC SYNCOUT[1:0] tSSTART tHSTART START/STOP POUT[2:0] CLKAIN, CLKBIN CLKCIN, CLKDIN CLKEIN AOE AR[23:0] AI[23:0] BOE BR[23:0] BI[23:0] COE CR[23:0] CI[23:0] DOE DR[23:0] DI[23:0] EOE ER[23:0] EI[23:0] tDODPOUT tSKL tSKT tDSA tDSB tDSC tDSD tDSE tDHA tDHB tDHC tDHD tDHE tLZOEA tHZOEA tDODA tDOHA tLZOEB tHZOEB tDODB tDOHB tLZOEC tHZOEC tDODC tDOHC tLZOED tHZOED tDODD tDOHD tLZOEE tHZOEE tDODE tDOHE tDODERR ERROR Data Sheet Page 31 DSP Architectures DSP24 Digital Signal Processor AC ELECTRICAL CHARACTERISTICS Figure 13. DSP24 Timing (Continued) SYSCLK SCHSEL tSSCH tHSCH tSGO tHGO GO[1:0] MMU_TC_A MMU_TC_B MMU_TC_C MMU_TC_D MMU_TC_E ADDREN ADDR[15:0] SCHDB[7:0] MMU_RESET tSTC tHTC tLZADDR tHZADDR tODADDR tSSDB tHSDB tODMRESET tODRW MMU_R/W tODA0 MMU_A0 tODSTART MMU_START MMU_CS_A MMU_CS_B MMU_CS_C MMU_CS_D MMU_CS_E BUSY tODCS tODBUSY tODSSYNC SSYNC[1:0] Page 32 Data Sheet DSP Architectures Digital Signal Processor DSP24 AC ELECTRICAL CHARACTERISTICS Figure 14. DSP24 Scheduler Mode Timing Diagram MMU24 to Memory to DSP-24 - Address to Data memory Latency = 1 SYSCLK SCHSEL A0 ADDR[19:0] TCA,TCB,TCC,TCD,TCE A1 A2 A3 1 2 MEMOE/MEMWR MEMORY DATA D0 D1 D2 D3 CLKxIN PIA/PIB INTERNAL TO DSP24 3 START/STOP 4 5 1 Default TC. (SKEW Reg TC Bits 11:9 = 0, MODE Bit 3 = 0) The TCx used for START/STOP generation is defined by MSB Bits 8:6 of the programed DataFlow. 2 Default Showed. Depending on memory type, these signals may need to be skewed. (SKEW Reg Bits 5:3 move MEMW and Bits 2:0 move MEMOE. 7= -1, 0-6 = 0-6) 3 Internal to DSP-24 the generated START/STOP signal needs to line up with incoming data first point, and go low during the incoming data's last point. 4 The Internal START/STOP rising edge equals Input TC falling edge delayed one clock cycle. 5 The Internal START/STOP falling edge equals Input TC rising edge delayed two clock cycles. System Timing in the Scheduler Mode When using the DSP24's built in Scheduler, the control for specifying the DSP24's function, data flow, and various control signals remains the same. However, the source for the contro lsignals has been internally switched to the output of the internal Scheduler. START/STOP is the most important of these control signals. As shown in Figures14 and15, the internal START/STOP is generated from the TC inputs to the Scheduler. Since latency of the user SRAM is unknown, a value of 1is used for generating the internal timing, see Figure 14.If another type of external SRAM is used, that has a different latency, then the MMU24 must be programmed to delay its TC output accordingly, see Figure 15. Data Sheet Page 33 DSP Architectures DSP24 Digital Signal Processor AC ELECTRICAL CHARACTERISTICS Figure 15. DSP24 Scheduler Mode Timing Diagram (Continued) MMU24 to Memory to DSP-24 - Address to Data memory Latency = 2 SYSCLK SCHSEL ADDR[19:0] A0 TCA,TCB,TCC,TCD,TCE 1 A1 A2 A3 2 MEMOE/MEMWR MEMORY DATA D0 D1 D2 D3 CLKxIN PIA/PIB INTERNAL TO DSP24 3 START/STOP 4 5 1 TC delayed by one cycle. (SKEW Reg TC Bits 11:9 = 1, MODE Bit 3 = 0) The TCx used for START/STOP generation is defined by MSB Bits 8:6 of the programed DataFlow. 2 Default Showed. Depending on memory type, these signals may need to be skewed. (SKEW Reg Bits 5:3 move MEMW and Bits 2:0 move MEMOE. 7= -1, 0-6 = 0-6) 3 Internal to DSP-24 the generated START/STOP signal needs to line up with incoming data first point, and go low during the incoming data's last point. 4 The Internal START/STOP rising edge equals Input TC falling edge delayed one clock cycle. 5 The Internal START/STOP falling edge equals Input TC rising edge delayed two clock cycles. System Timing in the Scheduler Mode (Continued) In addition to setting the START/ STOP timing, the MMU24 must also be programmed to skew the MEMOE and MEMWR signals to the SRAM. This frames the active data, according to the SRAM's specification. Page 34 Data Sheet Digital Signal Processor DSP Architectures DSP24 SBGA PHYSICAL DEMINSIONS BGA Package - BGA432 Data Sheet Page 35 DSP Architectures DSP24 Digital Signal Processor PIN LIST: D27 ADDR12 FC3 C17 XSFI3 XSFI2 AR12 M2 BR00 A5 AR13 M1 BR01 C6 B28 ADDR13 FC2 A16 A28 ADDR14 FC1 B16 AI00 B5 AR14 N3 BR02 C27 ADDR15 FC0 C16 AI01 D6 AR15 N2 BR03 D26 PIA D16 AI02 C5 AR16 N1 BR04 B27 BUSY A15 AI03 A4 AR17 P3 BR05 A27 N/C B15 AI04 B4 AR18 P2 BR06 C26 N/C C15 AI05 D5 AR19 R4 BR07 B26 POUT0 B14 AI06 E4 AR20 R3 BR08 A26 POUT1 D15 AI07 D2 AR21 T1 BR09 C25 POUT2 C14 AI08 D1 AR22 T2 BR10 BR11 ENA N/C A13 AI09 E3 AR23 T3 AI10 F4 MMUCSA T4 BR12 A25 JRST RESET B13 C13 AI11 E2 AOE U1 BR13 C24 SYNCIN0 A12 AI12 E1 BI00 U2 BR14 D23 SYNCIN1 B12 AI13 F3 BI01 U3 BR15 B24 GO0 D13 AI14 F2 BI02 V2 BR16 A24 C12 AI15 F1 BI03 U4 BR17 C23 GO1 JDI A11 AI16 G3 BI04 V3 BR18 B23 JCK B11 AI17 H4 BI05 W1 BR19 A23 JMS D12 AI18 G2 BI06 W2 BR20 C22 JDO C11 AI19 G1 BI07 W3 BR21 D21 PIB ENB A10 AI20 H3 BI08 Y1 BR22 B22 ALG7 DOCI B10 AI21 J4 BI09 Y2 BR23 A22 ALG6 DOCR D11 AI22 H2 BI10 W4 MMUCSB C21 ALG5 XCR C10 AI23 H1 BI11 Y3 BOE D20 ALG4 YSFI3 A9 CLKAIN J3 BI12 AA1 CI00 B21 ALG3 YSFI2 B9 AR00 J2 BI13 AA2 CI01 A21 ALG2 YSFI1 C9 AR01 J1 BI14 Y4 CI02 C20 ALG1 YSFI0 A8 AR02 K3 BI15 AA3 CI03 D19 ALG0 XSFISEL B8 AR03 L4 BI16 AB1 CI04 B20 BFPI0 D9 AR04 K2 BI17 AB2 CI05 A20 BFPI1 C8 AR05 K1 BI18 AA4 CI06 C19 BFPI2 A7 AR06 L3 BI19 AB3 CI07 B19 BFPI3 B7 AR07 M4 BI20 AC1 CI08 A19 BFPI4 D8 AR08 L2 BI21 AC2 CI09 C18 BFPI5 C7 AR09 L1 BI22 AC3 CI10 B18 XSFI0 A6 AR10 M3 BI23 AD1 CI11 D17 XSFI1 B6 AR11 N4 CLKBIN AD2 CI12 D24 B25 Page 36 Data Sheet DSP Architectures Digital Signal Processor DSP24 PIN LIST (cont): AC4 CI13 AK10 DSFO2 AK22 DR03 AD3 CI14 AL10 DSFO1 AH21 DR04 AC28 EI16 AD30 EI17 AE1 CI15 AJ11 DSFO0 AJ22 DR05 AD31 EI18 AE2 CI16 AH12 SYNCOUT1 AL23 DR06 AC29 EI19 AD4 CI17 AK11 SYNCOUT0 AK23 DR07 AC30 EI20 AE3 CI18 AL11 BFPO5 AJ23 DR08 AF1 CI19 AJ12 BFPO4 AL24 DR09 AC31 EI21 AB29 EI22 AF2 CI20 AH13 BFPO3 AK24 DR10 AA28 EI23 AF3 CI21 AK12 BFPO2 AH23 DR11 AB30 CLKEIN AG1 CI22 AL12 BFPO1 AJ24 DR12 AB31 ER00 AG2 CI23 AJ13 BFPO0 AL25 DR13 AA29 ER01 AF4 CLKCIN AK13 DI00 AK25 DR14 Y28 AG3 CR00 AL13 DI01 AH24 DR15 AA30 ER03 AH1 CR01 AJ14 DI02 AJ25 DR16 AA31 ER04 AH2 CR02 AK14 DI03 AL26 DR17 Y29 ER05 AG4 CR03 AH15 DI04 AK26 DR18 W28 ER06 AH5 CR04 AJ15 DI05 AJ26 DR19 Y30 ER07 AK4 CR05 AL16 DI06 AL27 DR20 Y31 ER08 AL4 DI07 AK27 DR21 W29 ER09 ER10 ER02 CR06 AK16 AJ5 CR07 AJ16 DI08 AH26 DR22 W30 AH6 CR08 AH16 DI09 AJ27 DR23 W31 ER11 AK5 CR09 AL17 DI10 AL28 MMUCSD V29 ER12 AL5 CR10 AK17 DI11 AK28 DOE V30 ER13 AJ6 CR11 AJ17 DI12 AH27 EI00 U28 ER14 AK6 CR12 AK18 DI13 AG28 EI01 U29 ER15 AL6 CR13 AH17 DI14 AH30 EI02 T31 ER16 AJ7 CR14 AJ18 DI15 AH31 EI03 T30 ER17 AH8 CR15 AL19 DI16 AG29 EI04 T29 ER18 AK7 CR16 AK19 DI17 AF28 EI05 T28 ER19 AL7 CR17 AJ19 DI18 AG30 EI06 R31 ER20 AJ8 CR18 AL20 DI19 AG31 EI07 R30 ER21 AH9 CR19 AK20 DI20 AF29 EI08 R29 ER22 AK8 CR20 AH19 DI21 AF30 EI09 P30 ER23 AL8 CR21 AJ20 DI22 AF31 EI10 R28 MMUCSE AJ9 CR22 AL21 DI23 AE29 EI11 P29 EOE AK9 N31 SYSCLK CR23 AK21 CLKDIN AD28 EI12 AL9 MMUCSC AH20 DR00 AE30 EI13 N30 SYSCLKEN AJ10 COE AJ21 DR01 AE31 EI14 N29 AH11 DSFO3 AL22 DR02 AD29 EI15 M31 START/STOP YCR Data Sheet Page 37 DSP Architectures DSP24 Digital Signal Processor PIN LIST (cont): Page 38 M30 YCI N28 YSWAP M29 SCHSEL L31 MMUTCA XSWAP L30 MMUTCB XCI M28 MMUTCC XZI L29 MMUTCD YZI K31 K30 MMUTCE DZO SCH_DB0 L28 SCH_DB1 K29 SCH_DB2 J31 SCH_DB3 J30 SCH_DB4 J29 SCH_DB5 H31 SCH_DB6 H30 SCH_DB7 J28 H29 MMU_R/W MMU_A0 G31 MMU_START G30 H28 ADDREN ADDR0 DF0 G29 ADDR1 DF1 F31 ADDR2 DF2 F30 ADDR3 DF3 F29 ADDR4 DF4 E31 ADDR5 DF5 E30 ADDR6 DF6 F28 ADDR7 DF7 E29 ADDR8 DF8 D31 ADDR9 BFPCLR D30 ADDR10 FC5 E28 ADDR11 FC4 Data Sheet DSP Architectures Digital Signal Processor DSP24 PIN LIST (cont): VCC: Data Sheet A1 A31 B2 B30 C3 C29 D4 D7 D10 D14 D18 D22 D25 D28 G4 G28 K4 K28 P4 P28 V4 V28 AB4 AE4 AB28 AE28 AH4 AH7 AH10 AH14 AH18 AH22 AH25 AH28 AJ3 AJ29 AK2 AK30 AL1 AL31 GND: A2 A3 A14 A17 A18 A29 A30 B1 B3 B17 B29 B31 C1 C2 C4 C28 C30 C31 D3 D29 P1 P31 R1 R2 U30 U31 V1 V31 AH3 AH29 AJ1 AJ2 AJ4 AJ30 AJ28 AJ31 AK1 AK3 AK15 AK29 AK31 AL2 AL3 AL14 AL15 AL18 AL29 AL30 Page 39 DSP Architectures MMU-24 Digital Signal Processor note: top label is with SCHSEL=1 i.e. A28=ADDR14 when SCHSEL=1 and A28=FC1 when SCHSEL=0 PACKAGE DRAWING: 432-PIN SBGA PIN CONNECTIONS 1 2 3 4 5 6 7 8 9 10 11 12 13 AR17 AR13 AR10 AR06 AR02 CLKAIN AI20 AI16 AI12 AI09 AR18 AR14 AR11 AR07 AR03 AR00 AI21 AI17 AI13 AI10 AR16 AR12 AR09 AR05 AR01 AI23 AI19 AI15 AI11 AR19 AR15 AR08 AR04 AI22 AI18 AI14 15 16 AI03 XSFI3 AI06 AI04 AI00 AI08 AI05 AI01 XSFI2 AI07 AI02 XSFI1 14 17 19 20 21 22 23 24 BFPI4 BFPI1 ALG2 YSFI1 ALG6 DOCR JMS GO1 XSFI0 BFPI3 BFPI0 ALG3 YSFI2 ALG7 DOCI JCK GO0 BFPI5 BFPI2 ALG1 YSFI0 ALG5 XCR JDO JDI 18 25 26 27 28 N/C ADDR14 FC1 POUT0 BUSY ADDR13 FC2 N/C ADDR15 FC0 PIA ENA ADDR12 FC3 RESET POUT1 29 30 31 A A JRST B B SYNCIN0 POUT2 C C AR22 AR21 BI00 AOE AR23 BI03 BI02 BI01 BI07 BI06 BI04 BI11 BI10 BI08 BI05 BI14 BI13 BI12 BI09 BI18 BI17 BI15 BI22 BI21 BI19 BI16 BR01 BR00 BI23 BI20 BR04 BR03 BR02 CLKBIN BR06 BR05 ALG4 ALG0 XSFISEL YSFI3 PIB ENB SYNCIN1 N/C ADDR10 ADDR9 FC5 BFPCLR D D ADDR11 ADDR8 ADDR6 ADDR5 DF5 DF8 DF6 FC4 AR20 E E ADDR7 ADDR4 ADDR3 DF3 DF7 DF4 MMUCSA ADDR2 DF2 F F ADDR1 DF1 ADDREN MMU_START G G ADDR0 DF0 MMU_A0 SCH_DB7 SCH_DB6 H H MMU_R/W SCH_DB5 SCH_DB4 SCH_DB3 J J MMUTCE SCH_DB2 SCH_DB0 DZO K K SCH_DB1 MMUTCD MMUTCB MMUTCA XCI XSWAP YZI L L MMUTCC SCHSEL XZI YCI YCR M M SBGA432 N YSWAP START/ STOP SYSCLKEN SYSCLK N EOE ER23 MMUCSE ER22 ER21 ER20 ER17 ER16 P P BR08 BR07 R R TOP VIEW BR09 BR10 BR11 BR12 BR13 BR14 BR15 BR17 BR16 BR18 BR19 BR20 BR21 MMUCSB BR22 BR23 BOE CI02 CI00 CI01 T ER19 ER18 ER14 ER15 T U U ER12 ER13 ER06 ER09 ER10 ER11 ER02 ER05 ER07 ER08 EI23 ER01 ER03 ER04 EI22 CLKEIN ER00 V V W W =Vcc Y CI03 Y CI06 =Gnd AA AA CI04 CI05 CI07 CI08 CI09 CI10 CI13 EI16 EI19 EI20 EI21 CI11 CI12 CI14 CI17 EI12 EI15 EI17 EI18 CI15 CI16 CI18 EI11 EI13 EI14 CI19 CI20 CI21 CLKCIN EI05 EI08 EI09 EI10 CI22 CI23 CR00 CR03 EI01 EI04 EI06 EI07 CR01 CR02 EI02 EI03 AB AB AC AC AD AD AE AE AF AF AG AG CR04 CR08 CR07 CR11 CR15 CR19 CR18 CR22 DSFO3 SYNCOUT1 BFPO3 DI04 DI09 DI14 DI05 DI08 DI12 DI21 DR00 DR04 DI22 DR01 DR11 DR15 DR22 EI00 DR05 DR08 DR12 DR16 DR19 DR23 CLKDIN DR03 DR07 DR10 DR14 DR18 DR21 DR06 DR09 DR13 DR17 DR20 MMUCSD AH AH CR14 COE DSFO0 BFPO4 BFPO0 DI02 CR23 DSFO2 SYNCOUT0 BFPO2 DI00 DI03 DI15 DI18 AJ AJ CR05 CR09 CR12 CR16 CR20 CR06 CR10 CR13 CR17 CR21 MMUCSC DSFO1 BFPO5 DI07 DI11 DI06 DI10 DI13 DI17 DI20 DI16 DI19 DOE AK AK BFPO1 DI01 DI23 DR02 AL AL 1 2 Page 40 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 Data Sheet DSP Architectures Digital Signal Processor DSP24 TYPICAL RECURSIVE SYSTEM: TYPICAL PARALLEL SYSTEM: USER INTERFACE 24 4 24 24 24 BFPI Dr Di BFPO 8 2 Channel 0 to 49 Er Ei Channel 0 to 49 A ALG GO E RAM DSP24 C RAM D DSP24 SYSTEM CLOCK B Channel 50 to 99 SYSTEM CLOCK Channel 50 to 99 Control A MMU-24 B ADDR[15:0] CONTROL PROM DB[7:0] 15 24 Ar Br 24 Ai Bi DSP24 C RAM D Channel 100 to 149 SRAM SRAM 24 E RAM Channel 100 to 149 A E RAM 24 B DSP24 C RAM D Adaptive Filter Updates Cr Ci MMU -24 Control RAM MMU -24 15 SYSTEM CLOCK Control 24 24 MMU-24 MMU-24 15 SRAM prom SYSTEM CLOCK MMU -24 The user supplied CONTROL PROM supplies the following: " " " " " " " " " Data Sheet INPUT ZERO FILLING OUTPUT ZERO FILLING INPUT ZERO PADDING OUTPUT ZERO PADDING INPUT DATA SHIFTING INPUT DATA COMPLEMENTING " " " " INITIALIZATION PROGRAMMING FOR UP TO FIVE MMU-24's ADDRESS PATTERNS FOR EACH ONE OF UP TO FIVE MMU24's SYSTEM START/STOP MANAGEMENT SYSTEM SYNCHRONIZATION OUTPUT DATA COMPLEMENTING A FUNCTION CODE PER PASS A DATA FLOW CODE PER PASS Page 41 DSP Architectures DSP24 Digital Signal Processor DATA FLOW WORKSHEET U M RA SS M DSP24 AM SSR E U A MM U B C M MM B E C D U M SS RA M RA SS M DSP24 SS RA M U A MM B E C D U M SS RA M RA SS M DSP24 E D Page 42 SSRAM MM MMU MM SS RA M DSP24 U A MM C U M U B M MM B E C D U AM SSR MM SSRA M U A MM SSRAM U SSRA M RA SS M MMU U M U MMU SSRAM MM SSRAM AM SSR MMU MM U D U DSP24 MM C M M U B E AM SSR MM SSRA M U A MM SSRAM SSRA M RA SS M MMU U M U MM SSRAM AM SSR MMU MM U D SS RA M DSP24 SSRA M MM U A MM U SSRA M SS RA M M U RA SS M AM SSR M Data Sheet Digital Signal Processor DSP Architectures DSP24 Notes: Data Sheet Page 43 DSP Architectures Digital Signal Processor DSP24 ORDERING INFORMATION # - Device - # Package # Speed - # Temperature M=Military, I=Industrial, C=Commercial 20, 40, 60, 80, 100 Operating Frequency (MHz) Y = 432-lead BGA DSP24 Example: DSP24-Y-100-C (432-Lead BGA, 100 MHz Operating Frequency, Commercial Temperature) DSP Architectures Inc. reserves the right to make changes in specifications at any time without notice. DSP Architectures Inc. does not assume any responsibility for the use of any circuitry described; no circuit patent licenses are implied. NORTH AMERICA DSP Architectures Transform Your WorldTM Digital Signal Processing Architectures Inc. 7902 NE St. Johns Rd. Bldg 102 Vancouver, WA 98665, USA Phone: 360 573-4084 Fax: 360 573-4272 Web Page: www.dsparchitectures.com Reference DSPA-DSP24DS DSP Architectures Inc. 2001 Printed and bound in the USA.