DATA SH EET
Product specification
Supersedes data of 2000 Dec 19 2002 May 28
INTEGRATED CIRCUITS
UDA1345TS
Economy audio CODEC
2002 May 28 2
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
CONTENTS
1 FEATURES
1.1 General
1.2 Multiple format input interface
1.3 DAC digital sound processing
1.4 Advanced au dio configuration
2 GENERAL DESCRIPTION
3 ORDERING INFORMATION
4 QUICK REFERENCE DATA
5 BLOCK DIAGRAM
6 PINNING
7 FUNCTIONAL DESCRIPTION
7.1 Analog-to-Digital Conv erter (ADC)
7.2 Analog front-end
7.3 Decimation filter (ADC)
7.4 Interpolation filter (DAC)
7.5 Double speed
7.6 Noise shaper (DAC)
7.7 The Filter Stream DAC (FSDAC)
7.8 Power control
7.9 L3MODE or static pin control
7.10 L3 microcontroller mode
7.10.1 Pinning definition
7.10.2 System clock
7.10.3 Multiple format input/output interface
7.10.4 ADC input voltage control
7.10.5 Overload dete ction (ADC)
7.10.6 DC cancellation filter (ADC)
7.11 Static pin mode
7.11.1 Pinning definition
7.11.2 System clock
7.11.3 Mute an d de-emphasis
7.11.4 Multiple format input/output interface
7.11.5 ADC input voltage control
7.12 L3 interface
7.12.1 Address mode
7.12.2 Data transfer mode
8 LIMITING VALUES
9 THERMAL CHARACTERISTICS
10 DC CHARACTERISTICS
11 AC CHARACTERISTICS (ANALOG)
12 AC CHARACTERISTICS (DIGITAL)
13 APPLICATION INFORMATION
14 PACKAGE OUTLINE
15 SOLDERING
15.1 Introduction to soldering surface mount
packages
15.2 Reflow soldering
15.3 Wave soldering
15.4 Manual soldering
15.5 Suitability of surface mount IC packages for
wave and reflow soldering methods
16 DATA SHEET STATUS
17 DISCLAIMERS
2002 May 28 3
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
1 FEATURES
1.1 General
•Low power cons umption
•2.4 to 3.6 V power supply range wit h 3.0 V typical
•5 V tolerant TTL compatible digital inputs
•256, 384 and 512fs system clock
•Supports sampling frequencies from 8 to 100 kHz
•Non-inverting ADC plus integra ted high-pass filter to
cancel DC offset
•The ADC supports 2 V (RMS) input signals
•Overload detector for easy record level control
•Separate power control for ADC and DAC
•Integrated digital in terpolation filter plus non-inverting
DAC
•Functions controllable either by L3 microcontroller
interface or via static pins
•The UDA1345TS is pin and function compatible with the
UDA1344TS
•Small package size (SSOP28).
1.2 Multiple format input interface
•I2S-bus, MSB-justified up to 24 bits and LSB-justified
16, 18 and 20 bits format compatible
•Three combined data formats with MSB data output and
LSB 16, 18 and 20 bits data input
•1fs input and output format data rate.
1.3 DAC digital sound processing
The sound proces sing features of the UDA1345 T S can
only be used in L3 microcontroller mode:
•Digital dB-linear volume control (low microcontroller
load) via L3 microcontroller with 1 dB steps
•Digital de-emphasis for 32, 44.1 and 48 kHz
•Soft mute via cosine roll-off (in 1024 samples).
Note: in contrast to the UDA1344TS, the UDA1345TS
does not have bass-boost and treble.
1.4 Advanced audio configuration
•Stereo single-ended input configuration
•Stereo line output (under microcontroller volume
control), no post filter required
•High linearity, dynamic ra nge and low distortion.
2 GENERAL DESCRIPTION
The UDA1345TS is a single-chip stereo Analog-to-Digital
Converter (ADC) and Digital-to-A nalog Converter (D AC)
with signal processing features employing bitstream
conversion tech niques. The low power consumption and
low voltage requirements mak e the device eminently
suitable for use in low-voltage low-power portable digital
audio equip ment which incorporates recording an d
playback functions.
The UDA1345TS supports the I2S-bus data format with
word lengths of up to 24 bits, the MSB justified data format
with word lengths of up to 20 bits and the LSB justified
serial data format with word lengths of 16, 18 and 20 bits.
The UDA1345TS also suppor ts thr e e comb ined data
formats with MSB justified data output and LSB 16, 18
and 20 bits data input.
The UDA1345TS can be used either with static pin control
or under L3 microcontroller interface. In L3 mode the
UDA1345TS has basic sound features in playback mod e
such as de-emphasis, volume control and soft mute.
3 ORDERING INFORMATION
TYPE NUMBER PACKAGE
NAME DESCRIPTION VERSION
UDA1345TS SSOP28 plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341-1
2002 May 28 4
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
4 QUICK REFERENCE DATA
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VDDA(ADC) ADC analog supply voltage 2.4 3.0 3.6 V
VDDA(DAC) DAC analog supply voltage 2.4 3.0 3.6 V
VDDD digital supply voltage 2.4 3.0 3.6 V
IDDA(ADC) ADC analog su pply current operating mode −10 14 mA
ADC power-down −600 800 μA
ADC power-down all −300 800 μA
IDDA(DAC) DAC analog supply current operating mode −47.0mA
DAC power-dow n −50 150 μA
IDDO(DAC) DAC operational amplifier supply curr en t operating mod e −2.0 3.0 mA
DAC power-dow n −200 400 μA
IDDD digital supply current operating mode −58mA
ADC and DAC po wer- dow n −350 500 μA
Tamb ambient temperature −40 −+85 °C
Analog-to-digit al converter
Dodigital output level at 1 V (RMS) input
voltage notes 1 and 2 −2.5 −1.5 −0.5 dBFS
(THD + N)/S total harmonic distortion-p lus-noise to
signal ratio at 0dB, 1V(RMS)
fs=44.1kHz −−85 −80 dB
fs=96kHz −−80 −75 dB
at −60 dB, 1 mV (RMS);
A-weighted
fs=44.1kHz −−36 −30 dB
fs=96kHz −−34 −30 dB
S/N signal-to-noise ratio Vi= 0 V; A-weighted
fs= 44.1 kHz 90 96 −dB
fs= 96 kHz 90 94 −dB
αcs channel separation −100 −dB
Digital-to-analog converter
Vo(rms) output voltage (RMS value) note 3 850 900 950 mV
(THD + N)/S total harmonic distortion plus
noise-to-signal ratio at 0 dB
fs=44.1kHz −−85 −80 dB
fs=96kHz −−80 −71 dB
at −60 dB; A-weighted
fs=44.1kHz −−37 −30 dB
fs=96kHz −−35 −30 dB
αcs channel separation −100 −dB
S/N signal-to-noise ratio code = 0; A-weighted
fs= 44.1 kHz 90 100 −dB
fs= 96 kHz 90 98 −dB
2002 May 28 5
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
Notes
1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately
1 mA by using a series resistor.
2. The input voltage to the ADC scales proportionally with the powe r supply voltage.
3. The output voltage of the DAC scales pr oportionally with the power supply voltage.
Power performance
PADDA power consumption in record and playback
mode −64 −mW
PDA power consumpt ion in playback only mode −36 −mW
PAD power consumpt ion in record only mode −46 −mW
PPD power consumption in Power-down mode −2.2 −mW
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2002 May 28 6
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
5 BLOCK DIAGRAM
handbook, full pagewidth
MGS875
ADC
0 dB/6 dB
SWITCH 0 dB/6 dB
SWITCH
3 5
10
11
18
16
17
19
25 27 23 22
12
15
14
13
20
21
8
VINL
VDDD
VSSD
DATAO
BCK
WS
DATAI
MP1
VOUTL
28
24
9
26 VOUTR
SYSCLK
MP4
MP3
MP2
MP5
MC2
MC1
VINR
21 76 4
DECIMATION FILTER
DC-CANCELLATION FILTER
DIGITAL INTERFACE L3-BUS
INTERFACE
ADC
DAC
Vref(D)
VDDO VSSO
DAC
INTERPOLATION FILTER
NOISE SHAPER
VDDA(ADC) VSSA(ADC) VADCP VADCN Vref(A)
UDA1345TS
VDDA(DAC) VSSA(DAC)
Fig.1 Block diagram.
2002 May 28 7
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
6 PINNING
SYMBOL PIN TYPE DESCRIPTION
VSSA(ADC) 1 analog ground pad ADC analog groun d
VDDA(ADC) 2 analog supply pad ADC analog supp ly v oltage
VINL 3 analog input pad ADC input left
Vref(A) 4 analog pad ADC reference voltage
VINR 5 analog input pad ADC input right
VADCN 6 analog pad ADC negative referenc e voltage
VADCP 7 analog pad ADC positive refere nce voltage
MC1 8 5 V tolerant digital input pad with internal pull-down pad mode control 1 (pull-dow n)
MP1 9 5 V tolerant slew rate controlled digital output pad multi purpose pin 1
VDDD 10 digital supply pad digital supply voltage
VSSD 11 digital ground pad digital ground
SYSCLK 12 5 V tolerant digital Schmitt triggered input pad system clock 256, 384 or 512fs
MP2 13 3-lev el input pad multi purpose pin 2
MP3 14 5 V tolerant digital Schmitt triggered input pad multi purpose pin 3
MP4 15 3-lev el input pad multi purpose pin 4
BCK 16 5 V tolerant digital Schmitt triggered input pad bit clock input
WS 17 5 V tolerant digital Schmitt triggered in put pad word select input
DATAO 18 5 V tolerant s le w r ate controlled digital output pad data output
DATAI 19 5 V tolerant digital Schmitt triggered input pad data input
MP5 20 5 V tolerant digital Schmitt triggered input pad multi purpose pin 5 (pull down)
MC2 21 5 V tolerant digital input pad with internal pull-down pad mode control 2 (pull-down)
VSSA(DAC) 22 an alog ground pad DAC analog ground
VDDA(DAC) 23 analog supply pad DAC analog supply voltage
VOUTR 24 analog output pad DAC output right
VDDO 25 analog supply pad operational amplifier supply voltage
VOUTL 26 analog output pad DAC output left
VSSO 27 analog ground pad operational amplifier ground
Vref(D) 28 analog pad DAC reference voltage
2002 May 28 8
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
7 FUNCTIONAL DESCRIPTION
The UDA1345TS acc ommodates slave mode only, this
means that in all applicat ions the system devic es must
provide the system clocks (being the syst em clock itself
and the digital audio interfac e s ig na l s).
The system clock must be locked in frequency to the audio
digital interface input signals.
The BCK clock can be up to 128fs, or in other words the
BCK frequency is 128 times the Word Select (WS)
frequency or less: fBCK ≤128 ×fWS.
Important: the WS edge MUST fall on the negative edge
of the BCK at all times for proper operation of the digital I/O
data interface.
Note: the sampling frequenc y range is from 8 to 100 kHz,
however for the 512fs clock mode the sampling range is
from 8to55kHz.
7.1 Analog-to-Digital Converter (ADC)
The stereo ADC of the UDA1345TS consists of two
5th-order Sigma-Delta modulators. They have a modified
Ritchie-coder arc hitec ture in a differential switched
capacitor implementation. The oversampling ratio is 64.
7.2 Analog front-end
The analog front-end is equipped with a selectable 0 dB or
6 d B gain block (the pin to select this mode is given in
Section 7.10). This block can be used in applications in
which both 1 V (RMS) and 2 V (RMS) input signals can be
input to the UDA1345TS.
In applications in which a 2 V (RMS) input signal is used,
a 12 kΩ resistor must be used in series with the input of the
ADC. This forms a voltage divider together with the internal
ADC resistor and ensures that only 1 V (RMS) maximum
is input to the IC. Using this application for a 2 V (RMS)
input signal, the switch must be set to 0 dB. When a
1 V (RMS) input signal is input to the ADC in the same
application, the gain switch must be set to 6 dB.
An overview of the maximum input voltages allowed
against the presence of an external resistor and the setting
of the gain switch is given in Table 1; the power supply
voltage is assumed to be 3 V.
Table 1 Application modes using input gain stage
7.3 Decimation filter (ADC)
The decimation from 64fs to 1fs is performed in two stages.
The first stage realizes a 4th-order characteristic.
This filter decreases the sample rate by 8. The secon d
stage consists of 2 half-band filters and a re cu rsive filter,
each decimating by a fac tor of 2.
handbook, halfpage
VSSA(ADC)
VDDA(ADC)
VINL
Vref(A)
VINR
VADCN
VADCP
MC1
MP1
VDDD
VSSD
SYSCLK
MP2
MP3
Vref(D)
VSSO
VOUTL
VDDO
VDDA(DAC)
VSSA(DAC)
VOUTR
MC2
MP5
DATAI
DATAO
WS
BCK
MP4
1
2
3
4
5
6
7
8
9
10
11
12
13
28
27
26
25
24
23
22
21
20
19
18
17
16
1514
UDA1345TS
MGS876
Fig.2 Pin configuration.
RESISTOR
(12 kΩ)INPUT GAIN
SWITCH
MAXIMUM
INPUT
VOLTAGE
Present 0 dB 2 V (RMS)
Present 6 dB 1 V (RMS)
Absent 0 dB 1 V (RMS)
Absent 6 dB 0.5 V (RMS)
sin x
x
------------
2002 May 28 9
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
Table 2 Digital decimation filter characteristics
Note: the digital output level is inversely proportional to the
ADC analog power supply. This means that with a
constant analog inp ut level and increasing power supply
the digital output level will decrease proportionally.
7.4 Interpolation filter (DAC)
The digital filter interpolates from 1 to 128fs by means of a
cascade of a recursive filter and an FIR filter.
Table 3 Digital interpolation filter characteristics
7.5 Double speed
Since the device supports a sampling range of
8 to 100 kHz, the device can support double speed (e .g.
for 44.1 kHz and 48 kHz sampling frequency) by just
doubling the system speed. In double spee d all features
are available.
7.6 Noise shaper (DAC)
The 3rd-order no ise shaper operates at 128fs. It shifts
in-band quantization noise to frequencies well above the
audio band. This noise sh aping technique enables high
signal-to-noise ratios to be achieved. The noise shaper
output is converted into an analog signal using a filter
stream digital-to-analog converter.
7.7 The Filter Stream DAC (FSDAC)
The FSDAC is a semi-digital reconstruction filter that
converts the 1-bit data stream of the noise shaper to an
analog output voltage. The filter coefficients are
implemented as current sources and are summed at virtual
ground of the output operational amplifier. In this way very
high signal-to-noise performance and low clock jitter
sensitivity is achieved. A post filter is not needed due to the
inherent filter function of the DAC . On -board amplifiers
convert the FSDAC output current to an output v oltag e
signal capable of d riving a line output.
The output voltage of the FSDAC is scale d proportionally
with the power supply voltage.
7.8 Power control
In the event that the DAC is powered-up or powered-down,
a cosine roll-off mute will be performed (when powering
down) or a cosine roll-up de-mute (when powering up) will
be performed. This is in order to prevent clicks when
powering up or down. This power-on/off mute takes
32 ×4=128samples.
7.9 L3MODE or static pin control
The UDA1345TS can be used under L3 microcontroller
interface mode or under static pin control. The mode can
be set via the Mode Control (MC) pins MC1 (pin 8) and
MC2 (pin 21). The function of these pins is given in
Table 4.
Table 4 Mode Control pins MC1 and MC2
Important: in L3MODE the UDA1345TS is completely pin
and function compatible with the UDA1340M and the
UDA1344TS.
Note: the UDA134 5TS does NOT support bass -boost and
treble.
ITEM CONDITIONS VALUE (dB)
Pass-band rip p l e 0 −0.45fs±0.05
St op band >0.55fs−60
Dynamic range 0 −0.45fs114
Overall gain when
a 0 dB signal is
input to ADC to
digital output
DC −1.16
ITEM CONDITIONS VALUE (dB)
Passband ripple 0 −0.45fs±0.03
Stopband >0.55fs−65
Dynamic range 0 −0.45fs116.5
Gain DC −3.5
MODE MC2 MC1
L3MODE LOW LOW
Test modes LOW HIGH
HIGH LOW
Static pin mode HIGH HIGH
2002 May 28 10
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
7.10 L3 microcontroller mode
The UDA1345TS is s et to th e L3 microcontroller mode by
setting both MC1 (pin 8) and MC2 (pin 21) LOW.
The definition of the control registers is given in
Section 7.12.
7.10.1 PINNING DEFINITION
The pinning definition under L3 microcontroller interface is
given in Table 5.
Table 5 Pinning definition under L3 control
7.10.2 SYSTEM CLOCK
Under L3 control the options are 256, 384 and 512f s.
7.10.3 MULTIPLE FORMAT INPUT/OUTPUT INTERFACE
The UDA1345TS supports the following data input/output
formats under L3 control:
•I2S-bus with data word length of up to 24 bits
•MSB-justified serial format with data word length of up to
20 bits
•LSB-justified serial format with data word lengths of
16,18or20bits
•Three combined data formats with MSB data output and
LSB 16, 18 and 20 bits data input.
The formats are illustrated in Fig.3. Left and right data
channel words are time multiplexed.
7.10.4 ADC INPUT VOLTAGE CONTROL
The UDA1345TS supports a 2 V (RMS) input using a
series resistor of 12 kΩ as described in Section 7.2. In
L3 microcontroller mode, the gain can be selected via
pin MP5.
When MP5 is set LOW, 0 dB gain is selected. When MP5
is set HIGH, 6 dB gain is selected.
7.10.5 OVERLOAD DETECTION (ADC)
In practice the output is us ed to indicate whenever the
output data, in either the left or right channel, is greater
than −1 dB (the ac tual figure i s −1.16 dB) of the maximum
possible digit al swing. Wh en this cond ition is dete cted the
OVERFL output is forced HIGH for at least 512fs cycles
(11.6 ms at fs= 44.1 kHz). This time-out is reset for each
infringement.
7.10.6 DC CANCELLATION FILTER (ADC)
An optional IIR high-pass filter is provided to remove
unwanted DC components. The operation is selected by
the microcontroller via the L3-bus. The filter characteristics
are given in Table 6.
Table 6 DC cancellation filter characteristics
7.11 Static pin mode
The UDA1345TS is set to static pin control mode by setting
both MC1 (pin 8) and MC2 (pin 21) HIGH.
7.11.1 PINNING DEFINITION
The pinning defini tion under static pin control is given in
Table 7.
Table 7 Pinning definition for static pin control
SYMBOL PIN DESCRIPTION
MP1 9 OVERFL output
MP2 13 L3MODE input
MP3 14 L3CLOCK input
MP4 15 L3DATA input
MP5 20 ADC 1 V or 2 V (RMS) input control
ITEM CONDITIONS VALUE (dB)
Pass-band ripp le none
Pass-band gain 0
Droop at 0.00045fs0.031
Attenuation at DC at 0.000000 36fs>40
Dynamic range 0 −0.45fs>110
SYMBOL PIN DESCRIPTION
MP1 9 data input/output setting
MP2 13 3-level pin controlling de-emphasis
and mute
MP3 14 256fsor 384fs system clock
MP4 15 3-level pin to control ADC power mode
and 1 V (RMS) or 2 V (RMS) input
MP5 20 data input/output setting
2002 May 28 11
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
7.11.2 SYSTEM CLOCK
Under static pin con tr ol the options are 256fs and 384fs.
With pin MP3 (pin 14) the mode can be set as is given in
Table 8.
Table 8 System clock settings under static pin mode
7.11.3 MUTE AND DE-EMPHASIS
Under static pin control via MP2 de-emphasis and mute
can be selected for the playback path. The definition of the
MP2 pin is given in Table 9.
Table 9 Settings for pin MP2
7.11.4 MULTIPLE FORMAT INPUT/OUTPUT INTERFACE
The data input/output format s s upported under sta tic pin
control are as follow s:
•I2S-bus with data word length of up to 24 bits
•MSB-justified serial format with data word length of up to
24 bits
•Two combined data formats w i th MSB data output and
LSB 16 and 20 bits data input.
The data formats can be selected using pins MP1 (pin 9)
and MP5 (pin 20) as given in Table 10.
Table 10 Data format settings under static pin control
The formats are illustrated in Fig.3. Left and right data
channel words are time multiplexed.
7.11.5 ADC INPUT VOLTAGE CONTROL
The UDA1345TS supports a 2 V (RMS) input using a
series resistor as described in Section 7.2.
In static pin mode the 3-level pin MP4 (pin 15) is used to
select 0 or 6 dB gain mode. When MP4 is set LOW the
ADC is powered-down. When MP4 is set to half the power
supply voltage, the n 6 dB gain is selected, and when MP4
is set HIGH then 0 dB gain is selected.
Table 11 MP4 mode settings (static mode)
MODE MP3
256fs system clock LOW
384fs system clock HIGH
MODE MP2
No de-emphas is an d mute LOW
De-emphasis 44.1 kHz 0.5VDDD
Muted HIGH
INPUT FORMAT MP1 MP5
MSB-justified LOW LOW
I2S-bus LOW HIGH
MSB output LSB 20 input HIGH LOW
MSB output LSB 16 input HI GH HIGH
MODE MP4
ADC Power-down mode LOW
6 dB gain mode MID
0dB gain mode HIGH
2002 May 28 12
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
ha
ndbook, full pagewidth
LSB-JUSTIFIED FORMAT 16 BITS
LSB-JUSTIFIED FORMAT 18 BITS
LSB-JUSTIFIED FORMAT 20 BITS
MSB-JUSTIFIED FORMAT
WS LEFT
LEFT
LEFT
LEFT
RIGHT
RIGHT
RIGHT
RIGHT
32
2
215161718 1
1516 1
1321
MSB B2 MSBLSB LSB MSB B2B2
MSB LSBB2
MSB B2 B3 B4
B15
LSB
B17
215161718 1
MSB B2 B3 B4 LSB
B17
2151617181920 1
MSB B2 B3 B4 B5 B6 LSB
B19
2151617181920 1
MSB B2 B3 B4 B5 B6 LSB
B19
21516 1
MSB LSBB2 B15
>=8 >=8
BCK
D
ATA
WS LEFT RIGHT
321321
MSB B2 MSBLSB LSB MSBB2
>=8 >=8
BCK
D
ATA
WS
BCK
D
ATA
WS
BCK
D
ATA
WS
BCK
D
ATA
INPUT FORMAT I2S-BUS
MGG84
1
Fig.3 Serial interface formats.
2002 May 28 13
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
7.12 L3 interface
The UDA1345TS has a microcontroller input mode. In the
microcontroller mode, all of the digital sound process i ng
features and the system controlling features can be
controlled by the microcontroller. The controllable features
are:
•System clock frequency
•Data input format
•Power control
•DC filtering
•De-emphasis
•Volume
•Mute.
The exchange of data and control information between the
microcontroller and the UDA1345TS is accomplished
through a serial hardware interface comprising the
following pins:
•L3DATA: microcontroller interface data line
•L3MODE: microcontroller interface mode line
•L3CLOCK: microcontroller interface clock line.
Information transfer via the microcontroller bus is LSB first,
and is organized in accordance with the so called ‘L3’
format, in which two different modes of operation can b e
distinguished; address mode and data transfer mode
(see Figs 4 and 5).
The address mode is required to select a device
communicatin g via the L3-bus and to define the
destination register set for the data transfe r mode. Data
transfer for the UDA134 5TS can only be in one direction:
for the UDA134 5TS, data can only be written to the device.
Important: since the UDA1345TS does not have a
Power-up reset circuit, after power up the L3 interface
registers MUST be initialized.
7.12.1 ADDRESS MODE
The address mode is used to selec t a device for
subsequent data transf er and to define the destination
register set (DATA or STATUS) . The ad dr ess mode is
characterized by L3MODE being LOW and a burst of
8 pulses on L3CLOCK, accompanied by 8 data bits.
The fundamental timing is shown in Fig.4. Data
bits 0 a nd 1 indicate the type of subsequen t data transfer
as given in Table 12.
Table 12 Selection of data transfer
Data bits 7 to 2 represent a 6-bit device address, with bit 7
being the MSB and bit 2 the LSB. The addr ess of the
UDA1345TS is 000101 (bit 7 to bit 2). In the event that the
UDA1345TS receiv es a different address, it will d eselect
its microcontroller interface logic.
7.12.2 DATA TRANSFER MODE
The selection prefo rmed in the address mode remains
active during subsequent data transfers, until the
UDA1345TS rece ives a new address command.
The fundamental timing of data transfers is essentially the
same as in the address mode, shown in Fig.4. The
maximum input cloc k and data rate is 128fs. All transfers
are byte wise, i.e. they are based on groups of 8 bits. Data
will be stored in the UDA1345TS after the eighth bit of a
byte has been received. A multibyte transfer is illustrated
in Fig.6.
7.12.2.1 Programming the sound processing and other
features
The feature values are stored in independent registers.
The first selection of the registers is achieved by the choice
of data type that is transferred, being DATA or STATUS.
This is performed in the address mode, bit 1 and bit 0
(see Table 12). The second selection is performed by the
2 MSBs of the data byte (bi t 7 and bit 6). The other b its in
the data byte (bit 5 to bit 0) are the values that are placed
in the selected registers.
When the data transfer of type DATA is select ed, the
features Volume, De-emphasis, Mute and Power con tr ol
can be controlled. When the data transfer of type STATUS
is selected, the featu res system clock frequency, data
input format and DC filter can be controlled.
BIT 1 BIT 0 TRANSFER
0 0 DATA (volume, de-emphasis, mute,
and power contr o l)
0 1 not used
1 0 STATUS (system clock frequenc y , dat a
input format and DC filter)
1 1 not used
2002 May 28 14
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
handbook, full pagewidth
t h(MA) t s(MA)
t h(DAT)
t s(DAT)
Tcy
BIT 0
L3MODE
L3CLOCK
L3DATA BIT 7
MGL883
tLC
tHC
t s(MA) t h(MA)
Fig.4 Timing address mode.
handbook, full pagewidth thalt
t s(MT)
t h(DAT) t s(DAT)
thalt
t h(MT)
MGL884
Tcy
BIT 0
L3MODE
L3CLOCK
L3DATA
write BIT 7
tLC
tHC
Fig.5 Timing for data transfer mode.
2002 May 28 15
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
handbook, full pagewidth
t
halt
address
L3DATA
L3CLOCK
L3MODE
addressdata byte #1 data byte #2
MGD018
Fig.6 Multibyte transfer.
Table 13 Data transfer of type status
Table 14 Data transfer of type data
LAST IN TIME FIRST IN TIME REGISTER SELECTED
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0 0 SC1 SC0 IF2 IF1 IF0 DC System Clock frequency (5 : 4);
data Input Format (3 : 1); DC-filter
LAST IN TIME FIRST IN TIME REGISTER SELECTED
BIT7 BIT6 BIT5 BIT4 BIT3 BIT2 BIT1 BIT0
0 0 VC5 VC4 VC3 VC2 VC1 VC0 Volume Control (5 : 0)
01000000not used
100DE1DE0MT00De-Emphasis (4:3); MuTe
110000PC1PC0Power Control (1:0)
2002 May 28 16
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
7.12.2.2 System clock frequency
A 2-bit value (SC1 and SC0) to select the used external
clock frequency (see Table 15).
Table 15 System clock frequency set tings
7.12.2.3 Data input format
A 3-bit value (IF2 to IF0) to select the used data format
(see Table 16).
Table 16 Data input format settings
7.12.2.4 DC filter
A 1-bit value to enable the digital DC filter (see Table 17).
Table 17 DC filtering
7.12.2.5 Volume c ontrol
A 6-bit value to program the left and right channel volume
attenuation (VC5 to VC0) . The range is 0 dB to −∞ dB in
steps of 1 dB (see Table 18).
Table 18 Volume settings
7.12.2.6 De-emphasis
A 2-bit value to enable the digital de-empha sis filter.
Table 19 De-emphasis se ttings
7.12.2.7 Mute
A 1-bit value to enable the digital DAC mute (playback).
Table 20 DAC mute
SC1 SC0 FUNCTION
0 0 512fs
0 1 384fs
1 0 256fs
1 1 not used
IF2 IF1 IF0 FUNCTION
000I
2S-bus
0 0 1 LSB-justified; 16 bits
0 1 0 LSB-justified; 18 bits
0 1 1 LSB-justified; 20 bits
1 0 0 MSB-justified
1 0 1 MSB-justified output/
LSB-justified 16 bit s input
1 1 0 MSB-justified output/
LSB-justified 18 bit s input
1 1 1 MSB-justified output/
LSB-justified 20 bit s input
DC FUNCTION
0 no DC filtering
1 DC filtering
VC5 VC4 VC3 VC2 VC1 VC0 VOLUME (dB)
000000 0
000001 0
000010 −1
000011 −2
:::::: :
110011 −50
110100 −52
110001 −54
110010 −57
110111 −60
111000 −66
111001 −∞
:::::: :
111111 −∞
DE1 DE0 FUNCTION
0 0 no de-emphasis
0 1 de-emphasis; 32 kHz
1 0 de-emphasis; 44.1 kHz
1 1 de-emphasis; 48 kHz
MT FUNCTION
0no muting
1muting
2002 May 28 17
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
7.12.2.8 Power control
A 2-bit value to disable the ADC and/or DAC to reduce power consumption.
Table 21 Power co ntrol settings
8 LIMITING VALUES
In accordance wi th the Absolute Maximum Rating System (IEC 60134). All voltages refe renced to ground;
VDDD =V
DDA =V
DDO =3V; T
amb =25°C; unless otherwise specified.
Notes
1. All VDD and VSS connectio ns must be made to the same powe r s upply.
2. DAC operation after short- circuiting cannot be guaranteed.
9 THERMAL CHARACTERISTICS
PC1 PC0 FUNCTION
ADC DAC
00offoff
01offon
10onoff
1 1 on on
SYMBOL PARAMETER CONDITIONS MIN. MAX. UNIT
VDDD digital supply voltage note 1 −5.0 V
Txtal(max) maximum crystal temperature −150 °C
Tstg storage temperature −65 +125 °C
Tamb ambient temperature −40 +85 °C
Vesd electrostatic handling according to JEDEC II specification
Ilu(prot) latch-up protection c urrent Tamb =125°C;
VDD =3.6V −200 mA
Isc(DAC) short-circuit current of DAC Tamb =0°C; VDD =3V;
note 2
output short-circuited
to VSSA(DAC)
−450 mA
output short-circuited
to VDDA(DAC)
−325 mA
SYMBOL PARAMETER CONDITIONS VALUE UNIT
Rth(j-a) thermal resistance from junction to
ambient in free air 90 K/W
2002 May 28 18
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
10 DC CHARACTERISTICS
VDDD =V
DDA =V
DDO = 3.0 V; fs=44.1kHz; T
amb =25°C; RL=5kΩ; note 1; all voltages referenced to ground
(pins 1, 11, 22 and 27); unless other wise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Supplies
VDDA(ADC) ADC analog supply voltage 2.4 3.0 3.6 V
VDDA(DAC) DAC analog supply v oltage 2.4 3.0 3.6 V
VDDD digital sup p l y voltage 2.4 3.0 3.6 V
IDDA(ADC) ADC analog supply current operating mode −10 14 mA
ADC power-down −600 800 μA
ADC power-down all −300 800 μA
IDDA(DAC) DAC analog supply current operating mode −47.0 mA
DAC power-down −50 150 μA
IDDO(DAC) DAC operational amplifier su pply
current operating mode −2.0 3.0 mA
DAC power-down −200 400 μA
IDDD digital supply current operating mode −58 mA
ADC and DAC
power-down −350 500 μA
Digital input pins (5 V tolerant TTL compatible)
VIH HIGH-level input voltage 2.0 −5.0 V
VIL LOW-level input voltage −0.5 −+0.8 V
VIH(th) HIGH-level threshold input
voltage 1.3 −1.9 V
VIL(th) LOW-level threshold input voltage 0.9 −1.35 V
Vhys Schmitt trigger hysteresis voltage 0.4 −0.7 V
⎪ILI⎪input leakage current −−10 μA
Ciinput capacitance −−10 pF
3-level input pins (MP2; MP4)
VIH HIGH-level input voltage 0.9VDDD −VDDD +0.5 V
VIM MIDDLE-level input voltage 0.4VDDD −0.6VDDD V
VIL LOW-level input voltage −0.5 −+0.5 V
Digital output pins
VOH HIGH-level output voltage IOH =−2mA 0.85V
DDD −− V
VOL LOW-level output voltage IOL =2mA −−0.4 V
Analog-to-digit al converter
Vref(A) reference voltage with respect to VSSA 0.45VDDA 0.5VDD
A
0.55VDDA V
Ro(ref) Vref(A) reference output resistance −24 −kΩ
Riinput resistance fi=1kHz −12 −kΩ
2002 May 28 19
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
Notes
1. All power su pply pins (VDD and VSS) must be connec ted to the same external power supply unit.
2. When higher capacitive loads must be driven then a 100 Ω resistor must be connected in series with the DAC output
in order to prevent oscillations in the output operational amplifier.
Ciinput capacitance −20 −pF
Digital-to-analog converter
Vref(D) referenc e voltage with respect to VSSA 0.45VDDA 0.5VDD
A
0.55VDDA V
Ro(ref) Vref(D) reference output resistance −12.5 −kΩ
RoDAC output resis tance −0.13 3.0 Ω
Io(max) maximum output current (THD + N)/S < 0.1%;
RL= 800 Ω
−1.7 −mA
RLload resistance 3 −− kΩ
CLload capacitance note 2 −−200 pF
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
2002 May 28 20
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
11 AC CHARACTERISTICS (ANALOG)
VDDD =V
DDA =V
DDO = 3.0 V; fi= 1 kHz; fs=44.1kHz; T
amb =25°C; RL=5kΩ; all voltages referenced to ground
(pins 1, 11, 22 and 27); unless other wise specified.
Notes
1. The input voltage can be up to 2 V (RMS) when the current through the ADC input pin is limited to approximately
1 mA by using a series resistor.
2. The input voltage to the ADC scales proportionally with the powe r supply voltage.
3. The output voltage of the DAC scales pr oportionally with the power supply voltage.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
Analog-to-digit al converter
Dodigital output level at 1 V (RMS)
input voltage notes 1 and 2 −2.5 −1.5 −0.5 dBFS
ΔViunbalance between channels −0.1 −dB
(THD + N)/S total harmonic distortion-plus-noise
to signal ratio at 0 dB, 1 V (RMS)
fs=44.1kHz −−85 −80 dB
fs=96kHz −−80 −75 dB
at −60 dB, 1 mV (RMS);
A-weighted
fs=44.1kHz −−36 −30 dB
fs=96kHz −−34 −30 dB
S/N signal-to-noise ratio Vi= 0 V; A-weighted
fs= 44.1 kHz 90 96 −dB
fs= 96 kHz 90 94 −dB
αcs channel separation −100 −dB
PSRR powe r s upply rejection ratio fripple = 1 kHz;
Vripple(p-p) =1% −30 −dB
Digital-to-analog converter
Vo(rms) output voltage (RMS value) note 3 850 900 950 mV
ΔVounbalance between channels −0.1 −dB
(THD + N)/S total harmonic distortion plus
noise-to-signal ratio at 0 dB
fs=44.1kHz −−85 −80 dB
fs=96kHz −−80 −71 dB
at −60 dB; A-weighted
fs=44.1kHz −−37 −30 dB
fs=96kHz −−35 −30 dB
S/N signal-to-noise r atio co de = 0; A-weigh te d
fs= 44.1 kHz 90 100 −dB
fs= 96 kHz 90 98 −dB
αcs channel separation −100 −dB
PSRR powe r s upply rejection ratio fripple = 1 kHz;
Vripple(p-p) =1% −60 −dB
2002 May 28 21
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
12 AC CH ARACTERISTICS (DIGITAL)
VDDD =V
DDA =V
DDO = 2.7 to 3.6 V; Tamb =−20 to +85 °C; RL=5kΩ; all voltages referenced to ground
(pins 1, 11, 22 and 27); unless other wise specified.
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
System clock timing; see Fig.7
Tsys system clock cycle fsys = 256fs; note 1 39 88 488 ns
fsys = 384fs; note 1 26 59 325 ns
fsys = 512fs; note 2 36 44 244 ns
tCWL fsys LOW-level pulse width fsys < 19.2 MHz 0.30Tsys −0.70Tsys ns
fsys ≥ 19.2 MHz 0.40Tsys −0.60Tsys ns
tCWH fsys HIGH-level pulse width fsys < 19.2 MHz 0.30Tsys −0.70Tsys ns
fsys ≥19.2 MHz 0.40Tsys −0.60Tsys ns
trrise time −−20 ns
tffall time −−20 ns
Serial input/output data timing; see Fig.8
tBCK bit clock period 1⁄128fs−−ns
tBCKH bit clock HIGH time 34 −−ns
tBCKL bit clock LOW time 34 −−ns
trrise time −−20 ns
tffall time −−20 ns
ts(DATAI) data inpu t set-up time 20 −−ns
th(DATAI) data input hold time 0 −−ns
td(DATAO−BCK
)
data output delay time (from BCK
falling edge) −−80 ns
td(DATAO−WS) data output delay time (from WS edge) MSB-justified format −−80 ns
th(DATAO) data output hold time 0 −−ns
ts(WS) word select set-up time 20 −−ns
th(WS) word select hold time 10 −−ns
Address and data transfer mode timing; see Figs 4 and 5
Tcy L3CLOCK cycle time 500 −−ns
tHC L3CLOCK HIGH period 250 −−ns
tLC L3CLOCK LOW period 250 −−ns
ts(MA) L3MODE set-up time address mode 190 −−ns
th(MA) L3MODE hold time address mode 190 −−ns
ts(MT) L3MODE set-up time data transfer mode 190 −−ns
th(MT) L3MODE hold time data transfer mode 190 −−ns
2002 May 28 22
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
Notes
1. Sampling range from 5 to 100 kHz is supported, with fs= 44.1 kHz typic al.
2. Sampling range from 5 to 55 kHz is supp orted, with fs=44.1kHz typical.
ts(DAT) L3DATA set-up time data transfer mode
and address mod e 190 −−ns
th(DAT) L 3DATA hold time data transfer mode
and address mod e 30 −−ns
thalt L3MODE halt time 190 −−ns
SYMBOL PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
handbook, full pagewidth
MGR984
Tsys
tCWH
tCWL
Fig.7 System clock timing.
handbook, full pagewidth
MGL885
WS
BCK
DATAO
DATAI
tf
trth(WS)
ts(WS)
tBCKH
tBCKL
Tcy
th(DATAO)
ts(DATAI) th(DATAI)
td(DATAO-BCK)
td(DATAO-WS)
Fig.8 Serial interface timing.
2002 May 28 23
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
13 APPLICATION INFORMATION
The application information as given in Fig.9 is an optimum application environment. Simplification is possible at the cost
of some performance deg rad ation. The following notes apply:
•The capacitors at the output of the DAC can be reduced. It should be noted that the cut-off fr equency of the DC filter
also changes.
•The capacitors at the input of the ADC can also be re duced. It should be noted that the cut-off frequen c y of the
capacitor with the 12 kW input resistance of the ADC will also change.
h
andbook, full pagewidth
MGS877
47 Ω
R30
C11
100 μF
(16 V)
C12
100 μF
(16 V)
VDDA
VDDD
L1
8LM32A07
8LM32A07
L2
3 V
g
round
1
VSSA(ADC)
UDA1345TS
12
4
SYSCLK
Vref(A)
10
26711
VDDD
VDDA(ADC) VADCN VADCP VSSD
s
ystem
clock
18
DATAO
16
BCK
17
WS
o
verload
flag 9
MP1
C1
47 μF
(16 V)
3
VINL
26 VOUTL R23
100 Ω
R22
10 kΩ
24 VOUTR R26
100 Ω
R27
10 kΩ
C6
47 μF
(16 V)
5
VINR
19
DATAI
13
MP2
14
MP3
15
MP4
100 nF
(63 V)
R21
1 ΩR24
C2
100 μF
(16 V)
C25
100 nF
(63 V)
C21
VDDA
C3
47 μF
(16 V)
C8
47 μF
(16 V)
C5
47 μF
(16 V)
C22
100 nF
(63 V)
28 Vref(D)
C4
47 μF
(16 V)
C23
100 nF
(63 V)
R28
10 Ω
10 Ω
VDDD
VSSO
27 VDDO
25
R25
1 Ω
C7
100 μF
(16 V)
C26
100 nF
(63 V)
VDDO
VDDA(DAC)
VSSA(DAC)
23
22
R29
1 Ω
C10
100 μF
(16 V)
C27
100 nF
(63 V)
VDDA
left
outp
ut
righ
t
outp
ut
left
input
right
input
X5
X4
X2
X3
Fig.9 Application diagra m.
2002 May 28 24
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
14 PACKAGE OUTLINE
UNIT A1A2A3bpcD
(1) E(1) (1)
eH
ELL
pQZywv θ
REFERENCES
OUTLINE
VERSION EUROPEAN
PROJECTION ISSUE DATE
IEC JEDEC JEITA
mm 0.21
0.05 1.80
1.65 0.38
0.25 0.20
0.09 10.4
10.0 5.4
5.2 0.65 1.25
7.9
7.6 0.9
0.7 1.1
0.7 8
0
o
o
0.13 0.10.2
DIMENSIONS (mm are the original dimensions)
Note
1. Plastic or metal protrusions of 0.2 mm maximum per side are not included.
1.03
0.63
SOT341-1 MO-150 99-12-27
03-02-19
X
wM
θ
A
A1
A2
bp
D
HE
Lp
Q
detail X
E
Z
e
c
L
vMA
(A )
3
A
114
28 15
0.25
y
pin 1 index
0 2.5 5 mm
scale
S
SOP28: plastic shrink small outline package; 28 leads; body width 5.3 mm SOT341
-1
A
max.
2
2002 May 28 25
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
15 SOLDERING
15.1 Introduction to soldering surface mount
packages
This text gives a very brief insight to a complex technology.
A more in-depth acco un t of sold er ing ICs can be found in
our “Data Handbook IC26; Integra te d Circuit Packages”
(document order number 9398 652 90011).
There is no soldering method tha t is idea l for all surface
mount IC packages. Wave soldering can still be used for
certain surface mount ICs, but it is not suitable for fine pitch
SMDs. In these situations reflow soldering is
recommended.
15.2 Reflow solderin g
Reflow soldering requires solder paste (a suspension of
fine solder particles, flux and binding agent) to be applied
to the printed-circuit board by screen printing, stencilling or
pressure-s yringe dispensin g before package placement.
Several methods exist for reflowing; for example,
convection or convection/infrared heating in a conveyor
type oven. Through put times (preheating, soldering and
cooling) vary between 100 and 200 seconds depending
on heating method.
Typical reflow peak temperatur es range from
215to250°C. The top-surface temperature of the
packages sh ould preferable be k ept below 220 °C for
thick/large packages, and below 235 °C for small/thin
packages.
15.3 W ave soldering
Conventional single wave soldering is not recommended
for surface mount devices (SMDs) or printed-circuit boards
with a high component density, as solder bridging and
non-wetting can present major problems.
To overcome these problems the double-wave soldering
method was specifically developed.
If wave soldering is used the following conditions must be
observed for optimal results:
•Use a double-wa ve soldering method comprising a
turbulent wave with high up ward pressure followed by a
smooth laminar wave.
•For packages with leads on two sides and a pitch (e):
– larger than or equal to 1.27 mm, the footprint
longitudinal axi s is preferred to be parallel to the
transport direction of the printed-circuit board;
– smaller than 1.27 mm, the foo tp rint longitudinal axis
must be parallel to the transport direction of the
printed-circuit board .
The footprint must incorporate solder thieves at the
downstream end.
•For packages with leads on four sides, the footprint must
be plac ed at a 45° angle to the transp ort direction of the
printed-circuit board. The footprint must incorporate
solder thieves downstream and at the side corners.
During placement and before soldering, the package must
be fixed with a droplet of adh esive. The adhesive can be
applied by screen printing, pin transfer or syringe
dispensing. The package can be soldered after the
adhesive is cured.
Typical dwell time is 4 seconds at 250 °C.
A mildly-activated flux will eliminate the need for removal
of corrosive residues in most applications.
15.4 Manual soldering
Fix the component by first soldering two
diagonally-opposite end leads. Use a low voltage (24 V or
less) soldering iron applied to the flat part of the lead.
Contact time must be limited to 10 seconds at up to
300 °C.
When using a dedicated tool, all other leads ca n be
soldered in one ope ration within 2 to 5 seconds between
270 and 320 °C.
2002 May 28 26
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
15.5 Suitability of surface mount IC packages for wave and reflow soldering methods
Notes
1. All surface mount (SMD) packages are moisture sensitive. Depending upon the moisture content, the maximum
temperature (with res pect to time) and body size of the package, there is a risk th at internal or external pack age
cracks may occur due to vaporization of the moisture in them (the so called popcorn effect). For details, refer to the
Drypack information in the “Data Handbook IC26; Integ rate d Circuit Packages; Section: Packing Methods”.
2. These packages are not suitable for wave soldering as a solder joint between the printed-circuit board and heatsink
(at bottom version) can not be achieved, and as solder may stick to the heatsink (on top vers ion).
3. If wave soldering is con sid ered, then the package must be p lace d at a 45° angle to the solder wave direction.
The package footprin t mus t incorporate solde r thieves downstream and at the side corne rs .
4. Wave soldering is only suitable for LQFP, TQFP and QFP packages with a pitch (e) equal to or larger than 0.8 mm;
it is definitely not suitable for packages with a pitch (e) equal to or smaller than 0.65 mm.
5. Wave soldering is only suitable for SSOP and TSSOP packages with a pitch (e) equal to or larger than 0.65 mm; it is
definitely not suitable for packages with a pitch (e) equal to or smaller than 0.5 mm.
PACKAGE SOLDERING METHOD
WAVE REFLOW(1)
BGA, LFBGA, SQFP, TFBGA not suitable suitable
HBCC, HLQFP, HSQFP, HSOP, HTQFP, HTSSOP, SMS n ot suitable(2) suitable
PLCC(3), SO, SOJ suitable suitable
LQFP, QFP, TQFP not recommended(3)(4) suitable
SSOP, TSSOP, VSO not recommended(5) suitable
2002 May 28 27
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
16 DATA SHEET STATUS
Notes
1. Please consult the most recently issued docu ment before initiating or completing a des ign.
2. The prod uct status of device(s) described in this document may have changed since this document was publishe d
and may differ in case of multiple devices. The latest product status information is available on the Internet at
URL http://www.nxp.com.
DOCUMENT
STATUS(1) PRODUCT
STATUS(2) DEFINITION
Objective data sheet Development T his document contains data from the objective specification for product
development.
Preliminary data sheet Qualification This document contains data from the preliminary specification.
Product data sheet Production This doc ument contains the product specific ation.
17 DISCLAIMERS
Limited warranty and liability ⎯ Information in this
document is believed to be accurate and reliable.
However, NXP Semiconduc tors does not give any
representations or warranties, expressed or implied, as to
the accuracy or completeness of such information and
shall have no liability for the consequences of use of such
information.
In no event shall NXP Semiconductors be liable for any
indirect, incidental, punitive, special or consequential
damages (including - without limitation - lost profits, lost
savings, busin es s interru ption, costs related to the
removal or replacement of any products or rework
charges) whether or not such damages are based on tort
(including negligence), warranty, breach of contract or any
other legal theory.
Notwithstanding any damages that customer might incur
for any reason whatsoever, NXP Semiconductors’
aggregate and cu mulative liability towards customer for
the products described herein shall be limited in
accordance with the Terms and conditio ns of commercial
sale of NXP Semiconductors.
Right to make changes ⎯ NXP Semiconductors
reserves the right to make changes to informa t ion
published in this doc ument, including without limitation
specifications and product descriptions, at any time and
without notice. This document supersedes and replaces all
information supplied prior to the publication hereof.
Suitability for use ⎯ NXP Semiconduct ors pr oduc ts are
not designed, au thorized or warran ted to be suitable for
use in life support, life-critical or safety-critical systems or
equipment, nor in applications where failure or malfunction
of an NXP Semiconductors product can reason ably be
expected to result in pe rs onal injury, death or severe
property or environmental damage. NXP Semiconductors
accepts no liability for inclusion and/or use of NXP
Semiconductor s pr oducts in such equipme nt or
application s and therefore suc h inclusion and/o r us e i s at
the customer’s own risk.
Applications ⎯ Applications that are described herein for
any of these products are for illustrative purposes only.
NXP Semiconductors makes no representation or
warranty that such applications will be suitable for the
specified use without further testing or modification.
Customers are responsible for the design and operation of
their applications and products using NXP
Semiconductors products, and NXP Semiconductors
accepts no liability for any assistance with applications or
customer product design. It is customer’s sole
responsibility to determine whether the NXP
Semiconductors pro du ct is su itable and fit for the
customer’s applications and products planned, as well as
for the planned a pplication and use of custom er’s third
party customer(s). Customers should provide appropriate
design and opera t ing saf eg ua rd s to minimize the risks
associated with their applications and products.
NXP Semiconduc tors does n ot a ccept any liabil ity rela ted
to any default, damage, costs or problem which is based
on any weakne ss or default in t he customer’s applic ations
or products, or the application or use by customer’s third
party customer( s) . C us to m er is responsible for doin g all
necessary testing for the customer’s applications and
products using NXP Semiconductors products in order to
avoid a default of the applic ations and the products or of
the application or use by customer’s third p arty
customer(s). NXP does not accept any liability in this
respect.
2002 May 28 28
NXP Semiconductors Product specification
Economy audio CODEC UDA1345TS
Limiting values ⎯ Stress above one or more limiting
values (as defined in the Absolute Maximum Ratings
System of IEC 60134) will cause permanent damage to
the device. Limiting values are stress ratin gs only and
(proper) operation of the device at these or any other
conditions abo ve those given in th e Recommended
operating conditions section (if present) or the
Characteristics sections of this document is not warranted.
Constant or repeated exposure to limiting values will
permanently and irreversibly affect the quality and
reliability of the device.
Terms and conditions of commercial sale ⎯ NXP
Semiconductors products are sold subject to the general
terms and conditio ns of commercial sale, as published at
http://www.nxp.com/profile/terms, unless other wise
agreed in a valid written ind i vidual agreement. I n cas e an
individual agreeme nt is co nc luded only the terms and
conditions of the resp ective agreement shall apply. NXP
Semiconductors hereby expressly objects to apply i ng the
customer’s general terms and conditions with regard to the
purchase of NXP Semicon ductors produc ts by customer.
No offer to sell or license ⎯ Nothing in this document
may be interpreted or construed as an offer to sell products
that is open for acceptance or the grant, conveyan ce or
implication of any license under any copyrights, patents or
other industrial or intellectual property rights.
Export control ⎯ This document as well as the item(s)
described he re in may be subject to export con t ro l
regulations. Export might require a prior authorization from
national auth or itie s.
Quick refer ence data ⎯ The Quick reference data is an
extract of th e product data given in the Limiting values an d
Characteristics sections of this document, an d as such is
not complete, exhaus tive or legally binding.
Non-automotive qualified products ⎯ Unless this data
sheet expressly states that this specific NXP
Semiconductors product is au tomotive qualified, the
product is not suitable for automotive use. It is neither
qualified nor te sted in accordanc e with automot ive testing
or application requirements. NXP Semiconductors accepts
no liability for inclusion and/or use of non-automotive
qualified prod ucts in automotive equip ment or
applications.
In the event that customer uses the product for design-in
and use in automotive applications to automotive
specifications and standards, customer (a) shall use the
product without NXP Semiconductors’ warranty of the
product for such au t omo tive applications, us e and
specifications, and (b) whenever customer uses the
product for automotive applications beyond NXP
Semiconductors’ specifications such use shall be solely at
customer’s own ris k, and (c) customer fully inde m nif i es
NXP Semiconductors for any liability, damages or failed
product clai ms r esult ing fr om custo mer desi gn an d us e o f
the product for automotive ap plic ations beyond NXP
Semiconductors ’ st andard warranty and NXP
Semiconductors’ product specifications.
NXP Semiconductors
provides High Performance Mixed Signal and Standard Product
solutions that leverage its leading RF, Analog, Power Management,
Interface, Security and Digital Processing expertise
Contact information
For additional information p lease visit: http://www.nxp.com
For sales offices addresses send e-mail to: salesaddresses@nxp.com
© NXP B.V. 2010
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner.
The information pr e sent ed in this document d oes not form part of an y q uot ation or contract, is believe d to be accurate and re li a ble and may be change d
without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license
under patent- or other ind us trial or intellectual property rights.
Customer notification
This data sheet was changed to reflect the new company name NXP Semiconductors, including new legal
definitions and disclaimer s. No changes were made to the technical content, except for package outline
drawings which were updated to the latest version.
Printed in The Netherlands 753503/04/pp29 Date of release: 2002 May 28 Document o r der number: 9397 750 09587
