®
Data Device Corporation
105 Wilbur Place
Bohemia, New York 11716
631-567-5600 Fax: 631-567-7358
www.ddc-web.com
FOR MORE INFORMATION CONTACT:
Technical Support:
1-800-DDC-5757 ext. 7771
FEATURES
•Supports MIL-STD-1553B Notice 2 and
MIL-STD-1760 Stores Management
•Complete Intergrated Remote
Terminal Including:
•Dual Low-Power Transceiver
•Complete RT Protocol Logic
•Small, 70-Pin Ceramic Package
•Choice of 5V or 3.3V Logic Power
•Meets 1553A/McAir Response Time
Requirements
•Selectable 8/16-bit DMA Interface
•Optional Tri-State Address Bus and
Transfer Control Signals
•Direct Interface to Simple Systems
•Selectable Input Clock, 12 or 16 MHz
•MIL-PRF-38535 Processing Available
DESCRIPTION
The BUS-65153 is a complete, dual redundant MIL-STD-1553B
Remote Terminal. Packaged in a 1.9" x 1.0" x 0.2", 70-pin ceramic
package, the BUS-65153 provides the transmitter voltage level
required by MIL-STD-1760. Also in support of MIL-STD-1760, the RT
address inputs are latchable.
The BUS-65153 contains two low power transceivers and a DDC custom
designed chip. This chip includes dual encoder/decoder, RT protocol logic, tri-
state data buffers, and DMA transfer control logic. The BUS-65153 supports all
13 dual redundant mode codes, any combination of which may be illegalized
by an external PROM, PLD, or RAM device.
Parallel data transfers are accomplished via a DMA type interface. Both 8-bit
and 16-bit transfers are supported.
The BUS-65153 can be easily interfaced to most CPU's. In addition,
the BUS-65153 can interface directly to minimum complexity subsys-
tems such as switches, D/A converters, etc.
The address bus and transfer control signals may be configured for either two-
state or three-state operation. Use of the three-state address mode reduces the
number of external components required for a DMA processor interface.
The input clock frequency is user selectable for either 12 or 16 MHz. In the
12 MHz mode, the decoder operates at 24 MHz, providing superior word error
rate and zero crossing distortion tolerance. The Busy, Service Request, and
Subsystem Flag RT Status Word bits are provided as discrete pins, allowing for
easy access by the subsystem.
Various message timing and error flag indicators are provided to facil-
itate the subsystem interface.
© 2000 Data Device Corporation
BUS-65153
MIL-STD-1553B, NOTICE 2 AND
MIL-STD-1760B SMALL TERMINAL
INTERFACE CIRCUIT “STIC”
Make sure the next
Card you purchase
has...
2
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H-07/07-0
FIGURE 1. BU-61703/5 BLOCK DIAGRAM
*
UPPER
DATA BUS
DATA BUS
UPPER DATA
BUFFER D15-D8
DB_SEL
BUS-25679
8
71TX/RX A
55 ohms
A DIR
A XF
55 ohms
55 ohms
BUS A
BUS B
TX_INH
TRANSMITTER
INHIBIT
A XF
A DIR
B DIR
B XF
B XF
B DIR
BUS-25679
5
4
8
7
5
4
1
3
3
TX/RX A
TX/RX B
TX/RX B
1553
BUS
I/O
2
2TRANSCEIVER
A
TRANSCEIVER
B
ENCODER/
DECODER AND
WATCHDOG
TIMER
DMA HANDSHAKE
CONTROL LOGIC
AND TRANSFER
DT_REQ
DT_GRT
DT_ACK
HS_FAIL
CS
WRT
WIDTH SELECT
DMA
HANDSHAKE
DATA
TRANSFER
CONTROL
ADDRESS
14-BIT
ADDRESS
BUS
LOWER
DATA BUS
TRI-STATE
CONTROL
A13-A0
LOWER DATA
BUFFER D7-D0
ADDR_ENA
ADDRESS
BUFFERS
REGISTERS
5
R.T. ADDRESS
PARITY AND
COMPARE LOGIC
55 ohms
CLK
CLK_SEL
RT_AD4-RT_AD0
RT_AD_P
RT_AD_ERR
R.T.
CLOCK INPUT
AND
FREQUENCY
SELECT
RT_AD_LAT
ADDRESS
RESET
SSFLAG
BUSY
ILLEGALIZATION
AND STATUS
INPUTS
ILLCMD
SERVICE_REQUEST
RESET
AND
TRANSMITTER
INHIBIT LOGIC
STATUS,
ILLEGALIZATION, LAST COMMAND, STATUS,
CURRENT COMMAND,
AND BIT WORD
R.T. STATE
AND
MACHINE
LOGIC
NBGRT
INCMD
GBR
ME
RT_FAIL
MESSAGE
TIMING
SIGNALS
*
3
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H -07/07-0
TABLE 1. BUS-65153 SPECIFICATIONS
PARAMETER MIN MAX
- 0.3
- 0.5
+ 0.3
+ 0.3
- 0.5
11
0.500
kΩ
pF
VP-P
VPEAK
6
20
18
-250
100
22
21
150
9
27
27
10
250
300
0.8
20
20
0.4
0.5
3.4
4.5
4.5
-15.75
4.5
4.5
-12.6
5
65
20
55
90
160
5.5
5.5
-14.25
5.5
5.5
-11.4
115
50
112
175
300
V
V
V
V
V
V
mA
mA
mA
mA
mA
ABSOLUTE MAXIMUN RATINGS
Supply Voltage
Logic + 5V
Transceiver + 5 V
- 15 V
- 12 V
Logic
Voltage Input Range
V
V
V
V
V
TYP UNITS
LOGIC
VIH
VIL
IIH (VIN=VCC)
IIL (VIN=GND)
VOH (IOH = 0)
VOH (IOH = max)
VOL (IOL = 0)
VOL (IOL = min)
IOL
IOH
RECEIVER
Differential Input Resistance
(Bus-65153, Bus-65163,
BUS- 65154, Bus-65164)
(Notes 1 - 6)
Differential Input Capacitance
(Bus-65153, Bus-65163,
BUS-65154, Bus-65164)
(Notes 1 - 6)
Threshold Voltage, Transformer
Coupled, Measured on Stub
Common Mode Voltage (Note 7)
VP-P
VP-P
VP-P
mV
P-P,diff
mV
nsec
TABLE 1. BUS-65153 SPECIFICATIONS
PARAMETER MIN TYP
POWER SUPPLY REQUIREMENTS
(CONTINUED)
Current Drain
(BUS-65154, BUS-65164, Note 9)
+ 5 V Logic (CH A, CH B)
- 12 V (CH A, CH B)
•Idle
•25% Duty Cycle
•50% Duty Cycle
•100% Duty Cycle
65
30
87
135
230
115
60
120
185
305
mA
mA
mA
mA
mA
POWER DISSIPATION
BUS-65153, BUS-65163
Total Hybrid
•Idle
•25% Duty Cycle
•50% Duty Cycle
•100% Duty Cycle
Hottest Die
•Idle
•25% Duty Cycle
•50% Duty Cycle
•100% Duty Cycle
BUS-65154, BUS-65164
Total Hybrid
•Idle
•25% Duty Cycle
•50% Duty Cycle
•100% Duty Cycle
Hottest Die
•Idle
•25% Duty Cycle
•50% Duty Cycle
•100% Duty Cycle
0.625
0.850
1.075
1.525
0.335
0.600
0.860
1.385
0.685
0.985
1.285
1.885
0.290
0.590
0.890
1.490
1.325
1.963
2.600
3.875
0.68
1.06
1.45
2.23
1.295
1.727
2.160
3.035
0.59
0.92
1.36
2.16
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
W
16.0
12.0
33
40
0.01
0.1
0.001
0.01
67
60
MHz
MHz
%
%
%
%
%
%
THERMAL
Thermal Resistance, Junction-to-
Case, Hottest Die (θJC)
BUS-65153, BUS-65163
BUS-65154, BUS-65164
Operating Junction Temperature
Storage Temperature
Lead Temperature
(Soldering for 10 seconds)
1553 MESSAGE TIMING
RT Response Time
•16 MHz
•12 MHz
RT-to-RT No Response Timeout
(Note 8)
Transmitter Watchdog Timeout
-55
-65
6.00
6.18
18.25
6.5
6.5
18.9
668
160
150
+300
6.96
6.76
19.5
°C/W
°C/W
°C
°C
°C
μS
μS
μS
μS
CLOCK INPUT
Frequency
Nominal Value (Selectavle)
•CLOCKSEL Input = Logic ‘0’
•CLOCKSEL Input = Logic ‘1’
Long Term Tolerance
•1553A Compliance
•1553B Compliance
Short Term Tolerance, 1 Second
•1553A Compliance
•1553B Compliance
Duty Cycle
•16 MHz
•12 MHz
5.54
5.54
UNITSMAX
POWER SUPPLY REQUIREMENTS
Voltages/Tolerances
(BUS-65153, BUS-65163)
+ 5 V (Logic)
+ 5 V (CH A, CH B)
- 15 V (CH A, CH B)
Voltages/Tolerances
(BUS-65154, BUS-65164)
+ 5 V (Logic)
+ 5 V (CH A, CH B)
- 12 V (CH A, CH B)
Current Drain
(BUS-65153, BUS-65163, Note 9)
+ 5 V Logic (CH A, CH B)
- 15 V (CH A, CH B)
•Idle
•25% Duty Cycle
•50% Duty Cycle
•100% Duty Cycle
TRANSMITTER
Differential Output Voltage
Direct Coupled Accross 35 ohms,
Measured on Bus
Direct Coupled Accross 70 ohms
Measured on Stub
•BUS-65153, BUS-65163 (Note 10)
•BUS-65154, BUS-65164
Output Noise, Differential
(Direct Coupled)
Output Offset Voltage, Transformer
Coupled Accross 70 Ohms
Rise/Fall Time
2.0
-20
-20
Vcc+0.4
3.7
-3.4
10
0.860
10
7.0
7.0
- 18.0
- 18.0
Vcc+0.5
V
V
μΑ
μΑ
V
V
V
V
mA
mA
4
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H-07/07-0
in
(mm)
oz
(gm)
0.6
(17)
UNITSMAXTYPMINPARAMETER
TABLE 1. BUS-65153 SPECIFICATIONS
1.9 x 1.0 x 0.215
48.26 x 25.4 x 5.46
PHYSICAL CHARACTERISTICS
Size
70-pin, DIP, Flat Pack
Weight
70-pin, DIP, Flat Pack
Notes: Notes 1 through 6 are applicable to the Receiver Differential
Resistance and Differential Capacitance specifications:
(1) Specifications include both transmitter and receiver (tied together
internally).
(2) Measurement of impedance is directly between pins TX/RX A(B)
and TX/RX A(B) of the BUS-65153 or BUS-65163 hybrid.
(3) Assuming the connection of all power and ground inputs to the
hybrid.
(4) The specifications are applicable for both unpowered and powered
conditions.
(5) The specifications assume a 2 volt rms balanced, differential, sinu-
soidal input. The applicable frequency range is 75 KHz to 1 MHz.
(6) Minimum resistance and maximum capacitance parameters are
guaranteed,but not tested, over the operating range.
(7) Assumes a common mode voltage within the frequency range of dc
to 2 MHz, applied to pins of the isolation transformer on the stub side
(either direct or transformer coupled), referenced to hybrid ground. Use
a DDC recommended transformer or other transformer that provides an
equivalent minimum CMRR.
(8) RT-to-RT Timeout is measured from the Mid-Parity crossing of the
Transmit Command word to the Mid-Sync crossing of the Transmitting
RT Status word.
(9) Current drain is for total hybrid (e.g., +5V supply current includes
the sum of logic +5V supply current, channel A +5V supply current and
channel B +5V supply current). Transmitting duty cycles assume one
channel transmitting and alternate channel idle.
(10) Compliant with 1760 applications.
INTRODUCTION
GENERAL
The BUS-65153 is a complete MIL-STD-1553 Remote Terminal
(RT) bus interface unit. Contained in the hybrid are a dual trape-
zoidal transceiver and Manchester II encoder/decoder, and
Remote Terminal (RT) protocol logic for MIL-STD-1553B. Also
included are built-in self-test capability and a parallel subsystem
interface. The subsystem interface includes a 14-bit address bus
and a data bus that may be configured for either 8-bit or 16-bit
DMA transfers.
The transceiver front end of the BUS-65153 is implemented by
means of low-power bipolar analog monolithic and thick-film
hybrid technology. The transceiver requires +5 V and -15 V only
(no +15 V is required) and includes voltage source transmitters.
The voltage source transmitters provide superior line driving
capability for long cables and heavy amounts of bus loading. In
addition, the monolithic transceivers provide a minimum stub
voltage level of 20 volts peak-to-peak transformer coupled, mak-
ing the BUS-65153 suitable for MIL-STD-1760 applications.
The receiver sections of the BUS-65153 are fully compliant with
MIL-STD-1553B in terms of front end overvoltage protection,
threshold and bit-error rate.
The BUS-65153 implements all MIL-STD-1553 message for-
mats, including all 13 of the 1553B dual redundant mode codes.
Any subset of the possible 1553 commands (broadcast, T/R bit,
subaddress, word count/mode code) may be optionally illegal-
ized by means of an external PROM, PAL, or RAM device. An
extensive amount of message validation is performed for each
message received. Each word received is validated for correct
sync type and sync encoding, Manchester II encoding, parity,
and bit count. All messages are verified to contain a legal,
defined Command Word and correct word count. If the BUS-
65153 is the receiving RT in an RT-to-RT transfer, it verifies that
the T/R bit of the transmit Command Word is a one and that the
transmitting RT responds in time and contains the correct RT
address in its Status Word.
The 65153 may be operated from either a 12 MHz or 16 MHz
clock input. In the 12 MHz mode, the decoder samples incoming
data with both edges of the clock input. This, in effect, provides
for 24 MHz decoder sampling. Benefits of the higher sampling
rate include a wider tolerance for zero-crossing distortion and
improved bit error rate performance.
The BUS-65153 includes a hardwired R.T. address input. This
includes 5 address lines, an address parity input, and an address
parity error output. The RT address can also be latched internal-
ly by means of the address latching input signal RT_ADD_LAT.
The 65153 supports command illegalization. Commands may be
illegalized by asserting the output signal
ILLCMD low approximately 5 ms after the mid-parity bit zero-
crossing of the received Command Word. Command Words may
be illegalized as a function of broadcast, T/R bit, subaddress,
word count and/or mode code.
An internal Built-in-Test (BIT) Word register is updated at the end
of each message. The contents of the BIT Word Register are
transmitted in response to a Transmit BIT Word Mode Command.
The BUS-65153 provides a number of real-time output signals.
These various signals provide indications of message start, mes-
sage in progress, valid received message, message error, hand-
shake fail, and looptest fail or transmitter timeout.
The BUS-65153 may be used in a wide variety of interface con-
figurations. The 65153 has an 8/16-bit tri-state data bus and an
address/control bus that may be pin programmed for either two-
state or three-state operation. The three-state mode allows the
BUS-65153 to be connected directly to the host processor's
data, address, and control buses in a DMA configuration. The
BUS-65153 includes standard DMA handshake signals
(Request, Grant, and Acknowledge) as well as transfer control
outputs (CS and WRT). The DMA interface may operate in either
a 16-bit or 8-bit mode, supporting both word-wide and byte-wide
transfers.
The DMA interface also allows the 65153 to be interfaced direct-
ly to a simple system that doesn't have a microprocessor. This
provides a low-cost 1553 interface for A/D and D/A converters,
switch closures, and actuators.
The BUS-65153 may also be used in a shared RAM interface
configuration. By means of tri-state buffers and a very small
amount of “glue” logic, the 65153 will store Command Words and
access Data Words to/from dedicated “mailbox” areas in a
shared RAM for each broadcast / T-R bit / subaddress / mode
code.
5
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H -07/07-0
If a more elaborate shared RAM interface is needed, the BUS-
65153 may be interfaced to a BUS-66315 memory management
unit. If a BUS-66315 is used, the address bus of the BUS-65153
is not used for accessing the system RAM (although the address
outputs may still be used for command illegalizing).
The BUS-66315 provides an RT Lookup Table, allowing the map-
ping of the various T-R/subaddresses to user programmable
areas in the BUS-66315's 64K x 16 shared RAM address space.
The BUS-66315 also provides a stack area of RAM. The stack
provides a chronology of all messages processed, storing a
Block Status Word (message channel, completion, and validity
information), an optional Time Tag Word and the received
Command Word for each message processed. The BUS-66315
also provides maskable interrupts to the host processor for end-
of-message and/or message error conditions.
ADDRESS MAPPING
The memory allocation scheme for the BUS-65153 14-bit
address bus is defined as follows:
A13: BROADCAST/OWNADDRESS
A12: TRANSMIT/RECEIVE
A11-A7: SUBADDRESS 4-0
A6: DATA/COMMAND
A5-A1: WORD COUNT/CURRENT WORD COUNT
A0: UPPER/LOWER BYTE (8-bit mode only)
The method of address mapping implemented by the BUS-
65153 provides for a “mailbox” allocation scheme for the storage
of Command and Data Words. The address outputs A13 through
A1 map directly into 8K words (16K bytes) of processor address
space. A0 is used for upper/lower byte selection in the 8-bit DMA
mode. The same address map is applicable for both the DMA
and shared RAM (without the BUS-66315) interface configura-
tions. The BUS-65153's addressing scheme maps messages in
terms of broadcast/own address, transmit/receive, subaddress,
and mode code. A 64-word message block is allocated for each
T/R-subaddress.
The received Command Word for all nonmode code messages is
stored at relative word location zero (0) within the respective
message block. For mode code messages, the address for the
received Command Word is offset from location zero (0) within
the message block for subaddress 0 or 31. The value of the
address offset is equal to the mode code field of the respective
Command Word (0 to 31).
For nonmode code messages, the Data Words to be transmitted
or received are accessed from (to) relative locations 32 through
63 within the message block. For mode code messages with a
single Data Word that is not read from internal register, the
address for the Data Word is offest from location 32 within the
64-word message block for subaddresses 0 and 31. The value of
the address offset is equal to the mode code field of the received
Command Word.
The Data Words transmitted in response to Transmit Last
Command or Transmit BIT Word mode commands are accessed
from a pair of internal registers.
DMA INTERFACE
An 8/16-bit data bus, a 14-bit address bus, and six control sig-
nals are provided to facilitate communication with the parallel
subsystem. The control signals include the standard DMA hand-
shake signals DT_REQ, DT_GRT, DT_ACK as well as the trans-
fer control outputs CS and WRT. HS_FAIL provides an indication
to the subsystem of a handshake failure condition.
Data is transferred between the subsystem and the BUS-65153
via a DMA handshake, initiated by the BUS-65153. A READ
operation is defined to be the transfer of data from the subsys-
tem to the BUS-65153. Conversely, a WRITE operation transfers
data from the BUS-65153 to the subsystem.
If the BUS-65153 is in 16-bit mode, data is transferred as a sin-
gle 16-bit word. In 8-bit mode, data is transferred in a pair of byte
transfers within the same DMA handshake cycle. The upper byte
is transferred first with A0=1, followed by the lower byte with
A0=0.
HANDSHAKE FAIL
If the BUS-65153 (STIC) asserts DT_REQ and the subsystem
does not respond with DT_GRT in time for the BUS-65153 to
complete the word transfer, the HS_FAIL output will be asserted
low to inform the subsystem of the handshake failure and bit D12
in the internal Built-In-Test (BIT) word is set to logic ©1." If the
handshake failure occurs on a data word read transfer (transmit
command) the STIC will abort the current message processing
and NOT transmit erroneous data back to the bus controller. In
the case of a handshake failure on a write transfer (receive com-
mand word transfer, transmit command transfer, or a receive
data word transfer) the STIC will set the handshake failure out-
put and BIT word bit, and continue processing the current mes-
sage.
DMA READ OPERATION
Whenever the BUS-65153 needs to read a word from the sub-
system, it asserts the signal DT_REQ low. If the subsystem
asserts DT_GRT in time, the BUS-65153 will then assert A13
through A1 (and A0 for the 8-bit mode), WRT high, along with
DT_ACK and CS low to enable data from the subsystem.
After the transfer of each Data Word has been completed,
address bus outputs A5 through A1 are incremented. This pro-
vides the option of connecting the BUS-65153 address lines
directly to the host processor's address bus to access the sub-
system RAM, if desired.
DMA WRITE OPERATION
Whenever the BUS-65153 needs to transfer data to the subsys-
tem, it initiates a DMA WRITE cycle. The BUS-65153 asserts
DT_REQ. The subsystem must respond with DT_GRT.
If DT_GRT was received in time, the BUS-65153 will then assert
DT_ACK. The BUS-65153 will then assert A13 through A1 (and
A0 in 8-bit mode) and WRT low, followed by CS low. The sub-
system may then use the rising edge of CS to latch the data.
Similar to the DMA read operation, the address outputs A5
through A1 are incremented after the completion of a DMA
WRITE operation.
6
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H-07/07-0
MESSAGE PROCESSING OPERATION
Following the receipt and transfer of a valid Command Word, the
BUS-65153 will attempt to (1) transfer received 1553 data to the-
subsystem, (2) read data from the subsystem for transmission on
the 1553 bus, (3) transmit status (and possibly built-in-test) infor-
mation to 1553, and/or (4) set status conditions.
The BUS-65153 responds to all nonbroadcast messages with a
1553 Status Word.
RT ADDRESS
RT Address (RT_AD 4-0, (RT_AD4 = MSB)) and RT Address
Parity (RT_AD_P) should be programmed for a unique RT
address and reflect an odd parity sum. The BUS-65153 will not
respond to any MIL-STD-1553 commands or transfer received
data from any nonbroadcast messages if an odd parity sum is
not presented by RT_AD4-0 and RT_AD_P. An address parity
error will be indicated by a low output on the RT_AD_ERR pin.
The input signal RT_AD_LAT operates a transparent latch for
RTAD4-RTAD0 and RTADP. If RT_AD_LAT is low the output of
the latch tracks the value presented to the input pins. If
RT_AD_LAT is high, the output of the internal latch becomes
latched at the values presented when RT_AD_LAT was low.
COMMAND ILLEGALIZATION
The BUS-65153 provides for command illegalization. If a com-
mand is illegalized, the BUS-65153 will set the Message Error bit
and transmit its status word to the Bus Controller. No Data Words
will be transmitted in response to an illegalized Transmit com-
mand. Data Words associated with an illegalized Receive com-
mand will, however, be presented to the subsystem.
ILLCMD is sampled approximately 5 ms following the mid-parity
bit zero crossing of the received Command Word (reference FIG-
URES 4-9). Command illegalization can be implemented using
either a two-state or three-state address bus. An external PROM,
PLD, or RAM device can be used to define the legality of specif-
ic commands. Any subset of the possible 1553 commands can
be illegalized as a function of broadcast, T/R bit, subaddress,
word count, and/or mode code.
Illegalizing commands in the two-state mode, based on broad-
cast, T/R bit, subaddress, and/or mode code, may be done by
means of a programmable device such as a PROM. The address
outputs from the STIC may be connected directly to the address
inputs to a PROM. Illegalizing commands in the two-state mode,
based on broadcast, T/R bit, subaddress, and word count
requires an external latch to store the value of the word count
field. The word count must be latched after the address lines
A5...A1 are updated for the present command and before these
address lines are cleared to 00000 for the command word trans-
fer.
The word count address lines (A5...A1) are multiplexed internal-
ly between the latched word count field of the command word,
and the current word counter. While the signal INCMD is high
(logic 1) these address lines reflect the word count field of the
present command. While INCMD is low (logic 0) these signals
represent the value of the current word counter, which is cleared
to zero at the start of a message, and is incremented after each
data word transfer.
The output of the illegalization PROM may be latched using a
flip-flop and an AND gate (see FIGURE 2). The output signal
INCMD from the STIC is used as the clock enable input to the
flip-flop. The flip-flop is updated on every rising clock edge while
INCMD is high, and is not updated while INCMD is low. This
allows the output of the PROM to be updated on the last clock
edge before INCMD is asserted low. Once INCMD is asserted,
the clock enable input to the flip-flop is removed, thus preserving
the value of the latched illegal bit.
Illegalizing commands in the three-state mode of operation also
requires the use of a latch. The latch must be updated during a
word transfer since the address lines are normally in a high
impedance state. FIGURE 3 illustrates a method of latching the
output from the PROM using a flip-flop and the signal CS.
The signal CS is driven low during every word transfer. The only
word transfer that takes place before the illegal command input
(ILLCMD) input is sampled is the command word transfer. The
word count field of the command word may be obtained directly
from the lower 5 bits of the data bus. The subaddress, T/R, and
broadcast signals are available on address lines A07-A13. Note
that the signal CS will be asserted twice during a transfer in the
8-bit mode of operation. The word count field is located in the
lower byte, which is presented during the second byte transfer.
The second CS will, therefore, latch the appropriate value for
ILLEGAL.
This method of latching the address lines places a constraint on
the access time of the PROM and on the maximum request to
grant time for the command word transfer. The access time of the
PROM must be less than 195 ns. If the data bus grant signal is
held off too long, the ILLCMD input will not be updated in time.
The maximum request to grant time is equal to the following:
transfer type tmax
16-bit @12 MHz 2.455 ms
16-bit @16 MHz 2.720 ms
8-bit @12 MHz 1.940 ms
8-bit @16 MHz 2.205 ms
TRANSMIT COMMAND (RT-TO-BC TRANSFER)
If the BUS-65153 receives a valid Transmit Command Word that
the subsystem determines is legal (input ILLCMD is high) and
the subsystem is not BUSY (input BUSY is high), the BUS-65153
will initiate a transmit data response following transmission of the
Status Word. This entails a handshake/read cycle for each Data
Word, with the total number of Data Words to be transmitted
specified by the Word Count field of the Command Word.
A low on ILLCMD will result in the Message Error bit being set.
No Data Words will be transmitted following transmission of the
Status Word to an illegalized transmit command. A low on the
BUSY input will set the BUSY bit in the Status Word; in this
instance, only the Status Word will be transmitted, with no Data
Words.
RECEIVE COMMAND (BC-TO-RT TRANSFER)
A DMA handshake will be initiated for each word received over
the 1553 data bus. If successful, the respective handshake will
be followed by a corresponding write cycle. A handshake timeout
7
Data Device Corporation
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BU-65153
Rev H -07/07-0
D00
D01 WC 0
WC 1 A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10
4Kx1
PROM
SA 2
WC 2
WC 3
SA 3
SA 4
T/R
WC 4
SA 0
SA 1
A07
A10
A11
A08
A09
A12
D02
D03
D04
BUS-65153
"STIC" A13
ILLEGAL
_______
BRO A11
OE
__ D
CS
__
QD
Q
4Kx1
PROM
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
SA 2
WC 0
WC 1
WC 2
WC 3
SA 3
SA 4
WC 4
SA 0
SA 1
A07
A10
A11
A08
A09
A01
A02
A03
A04
A05
BUS-65153
"STIC"
A12
A13
ILLEGAL
A10
A11
OE
BRO
T/R
D0
CLOCK
1
2
3
INCMD
CLOCK IN OSCILLATOR
Q
Q
D
FIGURE 2. BUS-65153 TWO-STATE ILLEGALIZATION
FIGURE 3. BUS-65153 THREE-STATE ILLEGALIZATION
8
Data Device Corporation
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BU-65153
Rev H-07/07-0
will not terminate transfer attempts for the remaining Data
Words, error flagging or Status Word transmission. After the
reception of a valid nonmode code receive Command Word fol-
lowed by the correct number of valid Data Words and assuming
that all words are successfully transferred to the subsystem, a
negative pulse will be asserted on the output Good Block
Received (GBR).
RT-TO-RT TRANSFER ERRORS
If the T/R bit of the “transmit” command in an RT-to-RT transfer is
a zero, the transmitting RT does not respond in time or an
address mismatch is detected in the transmitting RT's Status
Word, the BUS-65153, as receiving RT, will classify the condition
as a “Command error” and will not respond.
RT STATUS, ERROR HANDLING, AND MESSAGE TIM-
ING SIGNALS
Message transfer errors are indicated by means of the HS_FAIL,
ME, and RT_FAIL error indication outputs. Additional error detec-
tion and indication mechanisms include updating of the internal
Status and BIT Word registers.
The BUS-65153 provides a number of timing signals during the
processing of 1553 messages. NBGRT provides a negative
pulse output following the receipt of a 1553 Command Word.
INCMD is asserted low when a new command is received. At the
end of a message (either valid or invalid), INCMD transitions
from low to high. Following the last data word of a valid nonmode
code receive message, GBR is asserted low. ME is asserted as
a low output following any detected error in a received message.
LOOPBACK TEST
The BUS-65153 performs a loopback self-test at the end of each
nonbroadcast message processed. The loopback test consists of
the following verifications: (1) The received version of every
transmitted word is verified for validity (encoding, bit count, pari-
ty) and correct sync type; (2) The first transmitted word (RT
Status Word) is checked for correct RT Address field; and (3) The
received version of the last transmitted word is verified by means
of a bit-by-bit comparison to the transmitted version of the word.
If there is a transmitter timeout (668 ms) and/or the loopback test
fails for one or more transmitted words, the Terminal Flag Status
Word bit will be set in response to the next nonbroadcast mes-
sage.
STATUS WORD
The Broadcast Command Received bit is formulated internally.
The Message Error Status bit will be set if the current command
is a Transmit Status Word or Transmit Last Command mode com-
mand and if there was an error in the data portion of the previ-
ous receive message. Message Error will also be set if ILLCMD
has been sampled low for the current message. ILLCMD, Service
Request, Busy, and Subsystem Flag will be sampled from their
respective Status input pins approximately 5 ms following the
mid-parity bit zero crossing of the received Command Word.
BIT WORD
The BUS-65153 provides an internally formulated Built-In-Test
word. This word is transmitted to the BC in response to a
Transmit Bit Word Mode Code Command.
Internal Built-In-Test (BIT) Word Definition
D15: Transmitter Timeout
D14: Loop Test Failure - B Bus
D13: Loop Test Failure - A Bus
D12: Handshake Failure
D11: Bus B Transmitter Shutdown
D10: Bus A Transmitter Shutdown
D09: Terminal Flag Inhibited
D08: Ch A / Ch B
D07: High Word Count
D06: Low Word Count
D05: Incorrect Sync Type Received
D04: Invalid Word Received - Manchester or Parity Error
D03: RT-RT Transfer Response Error (no gap, data sync,
address mismatch)
D02: RT-RT Transfer No Response Timeout
D01: RT-RT Transfer - T/R Error on Second Command or
My Valid Address
D00: Command Word Contents Error
Note: Bits 15 through 9 are cleared only following a RESET
input or reception of a Reset Remote Terminal mode command.
Bits 8 through 0 are updated as a result of every message
processed.
BIT WORD Bit Descriptions
TRANSMITTER TIMEOUT: Set if the STIC's failsafe timer
detected a fault condition. The transmitter timeout circuit will
automatically shut down the CH. A or CH. B transmitter if it trans-
mits for longer than 668 μS.
CH. B LOOP TEST FAILURE, CH. A LOOP TEST FAILURE:
A loopback test is performed on the transmitted portion of every
non-broadcast message. A validity check is performed on the
received version of every word transmitted by the STIC. In addi-
tion, a bit-by-bit comparison is performed on the last word trans-
mitted by the RT for each message. If either the received version
of any transmitted word does not match the transmitted version
and/or the received version of the last transmitted word is deter-
mined to be invalid (sync, encoding, bit count, parity), or a fail-
safe timeout occurs on the respective channel, the LOOP TEST
FAILURE bit for the respective bus channel will be set.
HANDSHAKE FAILURE: If this bit is set, it indicates that the sub-
system had failed to respond with the DMA handshake input
DTGRT asserted within the allotted time in response to the STIC
asserting DTREQ. The allotted time for the subsystem's DTREQ-
to-DTGRT response time is approximately 3.0 to 3.7 ms for a
DMA write cycle and approximately 15.1 to 15.3 ms for a DMA
read cycle.
CH. B TRANSMITTER SHUTDOWN, CH. A TRANSMITTER
SHUTDOWN: Indicates that the transmitter on the respective bus
channel has been shut down by a Transmitter shutdown mode
code command received on the alternate channel. If an Override
9
Data Device Corporation
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BU-65153
Rev H -07/07-0
transmitter shutdown mode code command is received on the
alternate channel, this bit will revert back to logic “0”.
TERMINAL FLAG INHIBITED: Set to logic “1" if the STIC's
Terminal Flag RT Status bit has been disabled by an Inhibit
Terminal Flag mode code command. Will revert to logic “0” if an
Override inhibit terminal flag mode code command is received.
CH. A/CH. B: Logic “0” if the previous message was received on
CH.A, logic “1” if the previous message was received on CH. B.
HIGH WORD COUNT: Set to logic “1” if the previous message
had a high word count error.
LOW WORD COUNT: Set to logic “1” if the previous message
had a low word count error.
INCORRECT SYNC TYPE RECEIVED: If set, indicates that the
STIC detected a Command sync in a received Data Word.
INVALID WORD: Indicates that the STIC received one or more
words containing one or more of the following error types: sync
field error, Manchester encoding error, parity error, and/or bit
count error.
RT-to-RT GAP/SYNC/ADDRESS ERROR: This bit is set if the
STIC RT is the receiving RT for an RT-to-RT transfer and one or
more of the following occur: (1) If the transmitting RT responds
with a response time of less than 4 ms, per MIL-STD-1553B
(mid-parity bit to mid-sync); i.e., less than 2 ms dead time; and/or
(2) There is an incorrect sync type or format error (encoding, bit
count, and/or parity error) in the transmitting RT Status Word;
and/or (3) The RT address field of the transmitting RT Status
Word does not match the RT address in the transmit Command
Word.
RT-to-RT RESPONSE TIMEOUT: If set, indicates that, for the
previous message, the STIC was the receiving RT for an RT-to-
RT transfer and that the transmitting RT either did not respond or
responded later than the STIC's RT-to-RT Timeout time. The
STIC's RT-to-RT Response Timeout Time is defined as the time
from the mid-bit crossing of the parity bit of the transmit
Command Word to the mid-sync crossing of the transmitting RT
Status Word. The value of the STIC's RT-to-RT Response
Timeout time is 18.9 μS.
RT-to-RT SECOND COMMAND ERROR: If the STIC is the
receiving RT for an RT-to-RT transfer, this bit set indicates one or
more of the following error conditions in the transmit Command
Word: (1) T/R bit = logic “0”; (2) subaddress = 00000 or 11111;
(3) Same RT Address field as the receive Command Word.
COMMAND WORD CONTENTS ERROR: Indicates a received
command word is not defined in accordance with MIL-STD-
1553B. This includes the following undefined Command Words:
(1) The Command Word is a non-mode code, broadcast, trans-
mit command; (2) A message with a T/R bit of “0”, a subad-
dress/mode field of 00000 or 11111 and a mode code field
between 00000 and 01111; (3) A mode code command that is
not permitted to be broadcast (e.g., Transmit Status) is sent to
the broadcast address 11111.
MODE CODES
All 13 of the dual redundant MIL-STD-1553B mode codes are
implemented by the BUS-65153. Two mode codes, Transmit
Vector Word and Synchronize (with data) involve data transfer
with the subsystem. For the Transmit BIT Word mode code, the
internally formulated BIT Word is transmitted. TABLE 2 provides
a summary of the 1553B mode codes supported by the BUS-
65153.
TABLE 2. MIL-STD-1553B MODE CODES
T/R
BIT
MODE
CODE
FUNCTION DATA WORD BROADCAST
ALLOWED
100000 Dynamic Bus
Control
No No
100001 Synchronize No Ye s
100010 Transmit Status
Word
No No
100011 Initiate Self Test No Ye s
100100 Transmitter
Shutdown
No Ye s
100101 Override
Transmitter
Shutdown
No Ye s
100110 Inhibit Terminal
Flag
No Ye s
100111 Override Inhibit
Terminal Flag
No Ye s
101000 Reset Remote
Terminal
No Ye s
101001-
11111
RESERVED No TBD
110000 Transmit Vector
Word
From
Subsystem
No
010001 Synchronize with
Data
To Subsystem Ye s
110010 Transmit Last
Command
From Internal
Register
No
010100 Selected
Transmitter
Shutdown (See
Note)
To Subsystem Ye s
010101 Override Selected
Transmitter
Shutdown (See
Note)
To Subsystem Ye s
110011 Terrminal BIT
Word
From Internal
Register
No
010110-
11111
RESERVED Ye s TBD
110110-
11111
RESERVED Ye s TBD
Note: Terminal responds with Clear Status but no action is taken,
assuming a valid Command Word and any valid Data Word is received.
10
Data Device Corporation
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Rev H-07/07-0
BROADCAST MODE CODE (SUBADDRESS 11111),
T/R = 1 (Note: Use TABLE 3E, but increase address by 2000)
3F80-3FFF
BROADCAST, TRANSMIT, SUBADDRESS 30 (UNDEFINED)3F00-3F7F
••
••
••
BROADCAST, TRANSMIT, SUBADDRESS 2 (UNDEFINED)3100-317F
BROADCAST, TRANSMIT, SUBADDRESS 1 (UNDEFINED)3080-30FF
BROADCAST MODE CODE (SUBADDRESS 00000),
T/R = 0 (Note: Use TABLE 3D, but increase address by 2000)
3000-307F
BROADCAST MODE CODE (SUBADDRESS 11111),
T/R = 0 (Note: Use TABLE 3C, but increase address by 2000)
2F80-2FFF
BROADCAST, RECEIVE, SUBADDRESS 30 (See TABLE 3A)2F00-2F7F
••
••
••
BROADCAST, RECEIVE, SUBADDRESS 2 (See TABLE 3A)2100-217F
BROADCAST, RECEIVE, SUBADDRESS 1 (See TABLE 3A)2080-20FF
BROADCAST MODE CODE (SUBADDRESS 00000),
T/R = 0 (Note: Use TABLE 3B, but increase address by 2000)
2000-207F
MODE CODE (SUBADDRESS 11111),
T/R = 1 (SeeTABLE 3E)
1F80-1FFF
TRANSMIT SUBADDRESS 30 (See TABLE 3A)1F00-1F7F
••
••
••
RECEIVE, SUBADDRESS 2 (See TABLE 3A)
TRANSMIT, SUBADDRESS 2 (See TABLE 3A)1100-117F
TRANSMIT, SUBADDRESS 1 (See TABLE 3A)1080-10FF
MODE CODE (SUBADDRESS 00000),
T/R = 1 (SeeTABLE 3D)
1000-107F
MODE CODE (SUBADDRESS 11111),
T/R = 1 (SeeTABLE 3C)
0F80-0FFF
RECEIVE, SUBADDRESS 30 (See TABLE 3A)0F00-0F7F
••
••
••
RECEIVE, SUBADDRESS 1 (See TABLE 3A)0080-00FF
MODE CODE (SUBADDRESS 0000,
T/R = 0), See (TABLE 3B)
0000-007F
FUNCTION
ADDRESS
(HEX)
0100-017F
TABLE 3. OVERALL MEMORY MAP
Note: TABLES 3 and 3A-3D are byte-oriented addressing.
TABLE 3A. TYPICAL MEMORY MAP OF EACH NON-
MODE CODE SUBADDRESS, 64 WORD BLOCK
0040, 0041
OFFSET
(HEX) FUNCTION
0000, 0001 COMMAND WORD
0002, 003F NOT USED
0042, 0043 DATA WORD 1
DATA WORD 0
• •
• •
• •
007E, 007F DATA WORD 31
TABLE 3B. MODE CODE MEMORY MAP FOR SUBADDRESS
00000,T/R = 0
001E, 001F
ADDRESS
(HEX) FUNCTION
0000, 0001 COMMAND WORD, T/R = 0, MODE CODE 00000 (INVALID)
COMMAND WORD, T/R = 0, MODE CODE 01111 (INVALID)
0022, 0023 COMMAND WORD, T/R = 0, MODE CODE 10001 (SYNC
WITH DATA)
020E, 0021 COMMAND WORD, T/R = 0, MODE CODE 10000
(RESERVED)
003E, 003F COMMAND WORD, T/R = 0, MODE CODE 11111
(RESERVED)
0060, 0063 DATA WORD FOR MODE CODE 10000, T/R = 0 (RESERVED)
0040, 005F NOT USED (MODE CODES WITHOUT DATA)
• •
• •
• •
0062, 0063 DATA WORD FOR MODE CODE 10001, T/R = 0 (SYNC WITH
DATA)
• •
• •
• •
007E, 007F DATA WORD FOR MODE CODE 11111, T/R = 0 (RESERVED)
• •
• •
• •
••
••
••
DATA WORD FOR MODE CODE 11111, T/R = 0 (RESERVED)
0FFE, 0FFF
••
••
••
DATA WORD FOR MODE CODE 10001, T/R = 0 (SYNC WITH
DATA)
0FE2, 0FE3
••
••
••
NOT USED (MODE CODES WITHOUT DATA)0FC0, 0FDF
DATA WORD FOR MODE CODE 10000, T/R = 0 (RESERVED)0FE0, 0FE1
COMMAND WORD, T/R = 0, MODE CODE 11111
(RESERVED)
0FBE, 0FBF
COMMAND WORD, T/R = 0, MODE CODE 10000
(RESERVED)
0FA0, 0FA1
COMMAND WORD, T/R = 0, MODE CODE 10001 (SYNC
WITH DATA)
0FA2, 0FA3
COMMAND WORD, T/R = 0, MODE CODE 01111
(UNDEFINED)
COMMAND WORD, T/R = 0, MODE CODE 00000
(UNDEFINED)
0F80, 0F81
FUNCTIONADDRESS
(HEX)
009E, 009F
TABLE 3C. MODE CODE MEMORY MAP
FOR SUBADDRESS 11111
T/R = 0
11
Data Device Corporation
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BU-65153
Rev H -07/07-0
••
••
••
DATA WORD FOR MODE CODE 11111, T/R = 1 (RESERVED)
107E, 107F
••
••
••
DATA WORD FOR MODE CODE 10001, T/R = 1 (RESERVED)1062, 1063
••
••
••
NOT USED (MODE CODES WITHOUT DATA)1040, 105F
DATA WORD FOR MODE CODE 10000, T/R = 1
(TRANSMIT VECTOR WORD)
1060, 1061
COMMAND WORD, T/R = 1, MODE CODE 11111 (RESERVED)103E, 103F
COMMAND WORD, T/R = 1, MODE CODE 10000
(TRANSMIT VECTOR WORD)
1020, 1021
COMMAND WORD, T/R = 1, MODE CODE 10001 RESERVED)1022, 1023
COMMAND WORD,T/R = 1, MODE CODE 01111 (RESERVED)
COMMAND WORD, T/R = 1, MODE CODE 00000
(DYNAMIC BUS CONTROL)
1000, 1001
FUNCTION
ADDRESS
(HEX)
101E, 101F
TABLE 3D. MODE CODE MEMORY MAP FOR SUBADDRESS
00000, T/R = 1
••
••
••
DATA WORD FOR MODE CODE 11111, T/R = 1 (RESERVED)
••
••
••
DATA WORD FOR MODE CODE 10001, T/R = 1 (RESERVED)1FE2, 1FE3
•·
•
•·
•
••
NOT USED (MODE CODES WITHOUT DATA)1FC0, 1FDF
DATA WORD FOR MODE CODE 10000, T/R = 1
(TRANSMIT VECTOR WORD)
1FE0, 1FE1
COMMAND WORD, T/R = 1, MODE CODE 11111
(RESERVED)
1FBE, 1FBF
COMMAND WORD, T/R = 1, MODE CODE 10000
(TRANSMIT VECTOR WORD)
1FA0, 1FA1
COMMAND WORD, T/R = 1, MODE CODE 10001(RESERVED)1FA2, 1FA3
COMMAND WORD, T/R = 1, MODE CODE 01111
(RESERVED)
COMMAND WORD, T/R = 1, MODE CODE 00000
(DYNAMIC BUS CONTROL)
1F80, 0F81
FUNCTION
ADDRESS
(HEX)
1F9E, 1F9F
TABLE 3E. MODE CODE MEMORY MAP FOR SUBADDRESS
11111, T/R = 1
12
Data Device Corporation
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BU-65153
Rev H-07/07-0
MIN MAX
0.97 1.56
0.87
SYMBOL
t12(@16MHz)
DESCRIPTION TYP UNITS
t1(@12MHz)
RT RESPONSE TIME
COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT ms
t1(@16MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT ms
t2(@12MHz)
ms
NBGRT PULSE WIDTH ns
t2(@16MHz) NBGRT PULSE WIDTH ns
t3 NBGRT RISING EDGE TO A6 FALLING EDGE ns
t4(@12MHz) NBGRT FALLING EDGE TO ADDRESS VALID ns
t4(@16MHz) NBGRT FALLING EDGE TO VALID ADDRESS ns
t5(@12MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE ns
t5(@16MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE ns
t6(@12MHz) NBGRT FALLING EDGE TO START OF COMMAND WORD TRANSFER CYCLE (Note 2) ms
t6(@16MHz) NBGRT FALLING EDGE TO START OF COMMAND WORD TRANSFER CYCLE (Note 2) ms
t7
6.0
NBGRT FALLING EDGE TO VALID STATUS INPUTS ms
t8
6.76
INCMD FALLING EDGE TO CWC VALID ns
t9 DATA TRANSFER CYCLE TIME (Notes 2,3,4) ms
t10 STATUS INPUTS HOLD TIME ns
t11(@12MHz) NBGRT RISING TO A6 RISING (Note 5) 3ms
t11(@16MHz) NBGRT RISING TO A6 RISING (Note 5) 3ms
t12(@12MHz) RT RESPONSE TIME ms
1.38
140 190
100 150
45
300 410
220 330
800 865
590 655
1.19 1.28
0.88 0.97
4.1
560
500
6.18 6.96
FIGURE 4. RT TO BC (TRANSMIT) TIMING
See Note 4
MID-PARITY
t1
t2
t12
TRANSMIT COMMAND
1553 BUS
NBGRT
______
A6 (COMMAND/DATA)
_______
A12(T/R),A11-A7(SA4-SA0)
_
ME, HS_FAIL
___
_______
___
LMC, A13(BRDCST/OWN ADDRS),
_________
PREVIOUS COMMAND PRESENT
t4
t3
t11
C
t5
t6
t8
t9
WC
PREVIOUS COMMAND
A5-A1
(WC/MC4-0, CWC4-0)
INCMD
_____
_____
DTREQ, DTGRT, DTACK,
_____
_____
____
WRT (NOTE 1)
ILLEGAL, SERVREQ,
_______
_______
___
GBR
__
DATA15-0, CS (NOTE 1)
SSFLAG, BUSY
______
____
t7 t10
______
RTFAIL
13
Data Device Corporation
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Rev H -07/07-0
FIGURE 4. RT TO BC (TRANSMIT) TIMING (CONTINUED)
1.3500.910
1.4701.010
1.2600.880
1.3650.965
1.405
60
0.920
100
1.7951.430
2.085
μs
MID-PARTIY CROSSING OF LAST DATA WORD TO INCMD RISINGt18(@16MHz)
μs
MID-PARTIY CROSSING OF LAST DATA WORD TO INCMD RISING18(@12MHz)
μs
MID-SYNC CROSSING OF LAST DATA WORD TO WRT FALLING t17(@16MHz)
μs
MID-SYNC CROSSING OF LAST DATA WORD TO WRT FALLING t17(@12MHz)
ms
ns
MID-SYNC CROSSING OF STATUS RESPONSE TO WRT RISING
END OF DATA TRANSFER CYLE TO VALID NEXT WC (Note 3)
t14(@12MHz)
t16
ns
μs
t13
t15(@16MHz)
μs
t15(@12MHz)
μs
MID-SYNC CROSSING OF STATUS RESPONSE TO WRT RISINGt14(@16MHz)
UNITSTYPDESCRIPTION
1.700
1.3050.840
MAXMIN
MID-SYNC CROSSING OF TRANSMITTED DATA TO START OF DATA TRANSFER CYCLE (Note 2)
MID-SYNC CROSSING OF STATUS RESPONSE TO RTFAIL RISING
MID-SYNC CROSSING OF TRANSMITTED DATA TO START OF DATA TRANSFER CYCLE (Note 2)
SYMBOL
Notes:
1)IF ADDR_ENA IS LOGIC “1”, CS, WRT, AND A13..A0 WILL BE IN A HIGH IMPEDANCE STATE EXCEPT FOR WHEN A WORD TRANSFER IS BEING PERFORMED
(DT_ACK = LOGIC “0”).
2)THE LEADING EDGE OF TIME REFERENCE t9 AND THE TRAILING EDGE OF TIME REFERENCES t6 AND t15 ARE DEFINED AS THE FALLING EDGE OF
DT_REQ.
3)THE TRAILING EDGE OF REFERENCE t9 AND THE LEADING EDGE OF TIME REFERENCE t16 ARE DEFINED AS THE RISING EDGE OF DT_REQ.
4)DATA TRANSFER CYCLE TIMING INFORMATION IS DESCRIBED IN OTHER FIGURES.
5)IF THE COMMAND WORD TRANSFER CYCLE IS NOT COMPLETE (i.e., DT_REQ IS STILL LOGIC LOW) BY THE TIME INDICATED BY THE TRAILING EDGE OF t11,
A6 WILL BE HELD LOW UNTIL THE AFTER TRANSFER CYCLE IS COMPLETE (60 ns MAX AFTER THE RISING EDGE OF DT_REQ).
MID-PARITY
DATA
MID-SYNC
DATA
MID-SYNC
STATUS
MID-SYNC
COMMAND
t18
t9
t17
CWC=2
t16
CWC=1
t9 t15
t16
CWC=0
t14
t15
t13
14
Data Device Corporation
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BU-65153
Rev H-07/07-0
MIN MAX
0.97 1.56
0.87
SYMBOL DESCRIPTION TYP UNITS
t1(@12MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT μs
t1(@16MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT μs
t2(@12MHz) NBGRT PULSE WIDTH ns
t2(@16MHz) NBGRT PULSE WIDTH ns
t3 NBGRT RISING EDGE TO A6 FALLING EDGE ns
t4(@12MHz) NBGRT FALLING EDGE TO ADDRESS VALID, LMC ns
t4(@16MHz) NBGRT FALLING EDGE TO VALID ADDRESS, LMC ns
t5(@12MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE ns
t5(@16MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE ns
t6(@12MHz) NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE μs
t6(@16MHz) NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE (Note 2) μs
t7 NBGRT FALLING EDGE TO VALID STATUS INPUTS μs
t8 INCMD FALLING EDGE TO CWC VALID ns
t9 DATA TRANSFER CYCLE TIME (Notes 2,3,4) μs
t10 STATUS INPUTS HOLD TIME ns
t11(@12MHz) FIRST DATA WORD MID-PARITY CROSSING TO A6 RISING EDGE ns
t11(@16MHz) FIRST DATA WORD MID-PARITY CROSSING TO A6 RISING EDGE ns
1.38
140 190
100 150
45
300 410
220 330
800 865
590 655
1.19 1.28
0.88 0.97
4.1
560
500
820 1205
720 1025
FIGURE 5. BC TO RT (RECEIVE) TIMING
See Note 4
DATA
MID-PARITY
t1 t2
RECEIVE COMMAND
PREVIOUS COMMAND PRESENT COMMAND
t3
t4
t5
t6
t8
t9
WCPREVIOUS COMMAND
t7 t10
1553 BUS
NBGRT
_____
A6 (COMMAND/DATA)
_______
A12(T/R),A11-A7(SA4-SA0)
_
ME, HS_FAIL
__
_______
LMC, A13(BRDCST/OWN ADDRS),
___
_________
A5-A1
(WC/MC4-0, CWC4-0)
INCMD
_____
_____
DTREQ, DTGRT, DTACK,
_____
_____
___
WRT (NOTE 1)
ILLEGAL, SERVREQ,
_______
_______
___
GBR
__
DATA15-0, CS (NOTE 1)
SSFLAG, BUSY
______
____
______
RTFAIL
15
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H -07/07-0
FIGURE 5. BC TO RT (RECEIVE) TIMING
150100
190140
3.293.17
3.373.23
3.463.26
3.573.36
100
6.766.0
1.94
6.96
nsGBR PULSE WIDTHt18(@16MHz
GBR PULSE WIDTHt18(@12MHz)
μs
MID-PARITY CROSSING OF STATUS RESPONSE TO GBR FALLINGt17(@16MHz)
μs
MID-PARITY CROSSING OF STATUS RESPONSE TO GBR FALLINGt16(@12MHz)
μs
MID-PARITY CROSSING OF STATUS RESPONSE TO INCMD RISINGt16(@16MHz)
μs
MID-PARITY CROSSING OF STATUS RESPONSE TO INCMD RISINGt16(@12MHz
μs
MID-SYNC CROSSING OF STATUS RESPONSE TO RTFAIL RISINGt15
μs
RT RESPONSE TIMEt14(@16MHz)
ms
μs
MID-PARITY CROSSING OF RECEIVED DATA WORD TO START OF DATA TRANSFER CYCLE (Note 2)
RT RESPONSE TIME
t13(@12MHz)
t14(@12MHz)
nst12
UNITSTYPDESCRIPTIONSYMBOL
1.52
6.18
60
MAXMIN
END OF DATA TRANSFER CYLE TO VALID NEXT WC (Note 3)
Notes:
1)IF ADDR_ENA IS LOGIC “1”, CS, WRT, AND A13..A0 WILL BE IN A HIGH IMPEDANCE STATE EXCEPT FOR WHEN A WORD TRANSFER IS BEING PERFORMED
(DT_ACK = LOGIC “0”).
2)THE LEADING EDGE OF TIME REFERENCE t9 AND THE TRAILING EDGE OF TIME REFERENCES t6 AND t13 ARE DEFINED AS THE FALLING EDGE OF
DT_REQ.
3)THE TRAILING EDGE OF REFERENCE t9 AND THE LEADING EDGE OF TIME REFERENCE t12 ARE DEFINED AS THE RISING EDGE OF DT_REQ.
4)DATA TRANSFER CYCLE TIMING INFORMATION IS DESCRIBED IN OTHER FIGURES.
MID-PARITY
STATUS
MID-SYNC
DATA
MID-PARITY
t14
MID-PARITY
ND PRESENT COMMAND
t11
t16
t9
CWC=2
t12
t13
CWC=1
t12
t13 t9
CWC=0
t15
t17 t18
16
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H-07/07-0
MIN MAX
0.97 1.56
0.87
SYMBOL
t12(@16MHz)
DESCRIPTION TYP UNITS
t1(@12MHz)
RT RESPONSE TIME
COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT μs
t1(@16MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT μs
t2(@12MHz)
μs
NBGRT PULSE WIDTH ns
t2(@16MHz) NBGRT PULSE WIDTH ns
t3 NBGRT RISING EDGE TO A6 FALLING EDGE ns
t4(@12MHz) NBGRT FALLING EDGE TO ADDRESS VALID ns
t4(@16MHz) NBGRT FALLING EDGE TO VALID ADDRESS ns
t5(@12MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE ns
t5(@16MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE ns
t6(@12MHz) NBGRT FALLING EDGE TO START OF COMMAND WORD TRANSFER CYCLE (Note 2) μs
t6(@16MHz) NBGRT FALLING EDGE TO START OF COMMAND WORD TRANSFER CYCLE (Note 2) μs
t7
6.0
NBGRT FALLING EDGE TO VALID STATUS INPUTS μs
t8
6.76
INCMD FALLING EDGE TO CWC VALID ns
t9 DATA TRANSFER CYCLE TIME (Notes 2,3,4) μs
t10 STATUS INPUTS HOLD TIME ns
t11(@12MHz) NBGRT RISING TO A6 RISING (Note 5) 3μs
t11(@16MHz) NBGRT RISING TO A6 RISING (Note 5) 3μs
t12(@12MHz) RT RESPONSE TIME μs
1.38
140 190
100 150
45
300 410
220 330
800 865
590 655
1.19 1.28
0.88 0.97
4.1
560
500
6.18 6.96
FIGURE 6. RT TO RT (TRANSMIT) TIMING
See Note 4
MID-PARITY
t1
TRANSMIT COMMANDRECEIVE COMMAND
PREVIOUS COMMAND
PREVIOUS COMMAND
t4
t5
t
1553 BUS
NBGRT
_____
A6 (COMMAND/DATA)
_______
LMC, A13(BRDCST/OWN ADDRS),
A12(T/R),A11-A7(SA4-SA0)
___
_________
_
A5-A1
(WC/MC4-0, CWC4-0)
INCMD
_____
__
_______
ME, HS_FAIL
ILLEGAL, SERVREQ,
SSFLAG, BUSY
______
____
_______
_______
___
GBR
DTREQ, DTGRT, DTACK,
_____
_____
_____
DATA15-0, CS (NOTE 1)
___
___
WRT (NOTE 1)
RTFAIL
______
17
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H -07/07-0
FIGURE 6. RT TO RT (TRANSMIT) TIMING (CONTINUED)
1.3500.910
1.4701.010
1.2600.880
1.3650.965
60
1.7951.430
1.405
2.085
μs
MID-PARTIY CROSSING OF LAST DATA WORD TO INCMD RISING18(@16MHz)
μs
MID-PARTIY CROSSING OF LAST DATA WORD TO INCMD RISINGt18(@12MHz)
μs
MID-SYNC CROSSING OF LAST DATA WORD TO WRT FALLING t17(@16MHz)
μs
MID-SYNC CROSSING OF LAST DATA WORD TO WRT FALLING t17(@12MHz
nsEND OF DATA TRANSFER CYLE TO VALID NEXT WC (Note 3)t16
μs
MID-SYNC CROSSING OF TRANSMITTED DATA TO START OF DATA TRANSFER CYCLE (Note 2)t15(@16MHz)
μs
μs
MID-SYNC CROSSING OF STATUS RESPONSE TO WRT RISING
MID-SYNC CROSSING OF TRANSMITTED DATA TO START OF DATA TRANSFER CYCLE (Note 2)
t14(@12MHz)
t15(@12MHz)
ns
μs
MID-SYNC CROSSING OF STATUS RESPONSE TO RTFAIL RISING
MID-SYNC CROSSING OF STATUS RESPONSE TO WRT RISING
t13
t14(@16MHz)
UNITSTYPDESCRIPTIONSYMBOL
0.920
1.700
100
1.3050.840
MAXMIN
Notes:
1)IF ADDR_ENA IS LOGIC “1”, CS, WRT, AND A13..A0 WILL BE IN A HIGH IMPEDANCE STATE EXCEPT FOR WHEN A WORD TRANSFER IS BEING PERFORMED
(DT_ACK = LOGIC “0”).
2)THE LEADING EDGE OF TIME REFERENCE t9 AND THE TRAILING EDGE OF TIME REFERENCES t6 AND t15 ARE DEFINED AS THE FALLING EDGE OF
DT_REQ.
3)THE TRAILING EDGE OF REFERENCE t9 AND THE LEADING EDGE OF TIME REFERENCE t16 ARE DEFINED AS THE RISING EDGE OF DT_REQ.
4)DATA TRANSFER CYCLE TIMING INFORMATION IS DESCRIBED IN OTHER FIGURES.
5)IF THE COMMAND WORD TRANSFER CYCLE IS NOT COMPLETE (i.e., DT_REQ IS STILL LOGIC LOW) BY THE TIME INDICATED BY THE TRAILING EDGE OF t11,
A6 WILL BE HELD LOW UNTIL THE AFTER TRANSFER CYCLE IS COMPLETE (60 ns MAX AFTER THE RISING EDGE OF DT_REQ).
MID-PARITY
DATA DATA
MID-SYNC
STATUS
MID-SYNC
MID-SYNC
t2
t12
PRESENT COMMAND
t5 t8
WC
t3
t11
CWC=0
t16
CWC=1 CWC=2
t16
t9t15
t17
t13
t14
t15 t9
t6
t7
t9
t10
18
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H-07/07-0
FIGURE 7. RT TO RT (RECEIVE) TIMING
1025720
1205820
500
605
4.1
0.970.88
1.281.19
655590
865800
330220
410300
45
150100
190140
1.38
nsA6 PULSE WIDTHt11(@16MHz)
nsA6 PULSE WIDTHt11(@12MHz)
nsSTATUS INPUTS HOLD TIMEt10
μs
DATA TRANSFER CYCLE TIME (Notes 2,3,4)t9
nsINCMD FALLING EDGE TO CWC VALIDt8
μs
NBGRT FALLING EDGE TO VALID STATUS INPUTSt7
μs
NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE (Note 2)t6(@16MHz)
μs
NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE t6(@12MHz)
nsNBGRT FALLING EDGE TO INCMD FALLING EDGE
t5(@16MHz)
nsNBGRT FALLING EDGE TO INCMD FALLING EDGEt5(@12MHz)
nsNBGRT FALLING EDGE TO VALID ADDRESS, LMCt4(@16MHz)
nsNBGRT FALLING EDGE TO ADDRESS VALID, LMCt4(@12MHz)
nsNBGRT RISING EDGE TO A6 FALLING EDGEt3
nst2(@16MHz)
nsNBGRT PULSE WIDTHt2(@12MHz)
μs
COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRTt1(@16MHz)
μs
COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRTt1(@12MHz)
UNITSTYPDESCRIPTIONSYMBOL
0.87
1.560.97
MAXMIN
See Note 4
NBGRT PULSE WIDTH
t2
t3
t11
TRANSMIT COMMAND
RECEIVE COMMAND
MID-PARITY
t1
1553 BUS
ME, HS_FAIL
__
_______
NBGRT
_____
_______
A6 (COMMAND/DATA)
A12(T/R),A11-A7(SA4-SA0)
LMC, A13(BRDCST/OWN ADDRS),
___
_________
_
A5-A1
(WC/MC4-0, CWC4-0)
INCMD
_____
___
WRT (NOTE 1)
PREVIOUS COMMAND
PREVIOUS COMMAND
PRESENT COMMAND
t4
t5 t8
CWC=0WC
t6
t7
t9
t10
ILLEGAL, SERVREQ,
SSFLAG, BUSY
______
____
_______
_______
___
GBR
RTFAIL
______
DTREQ, DTGRT, DTACK,
_____
_____
_____
__
DATA15-0, CS (NOTE 1)
19
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H -07/07-0
Notes:
1)IF ADDR_ENA IS LOGIC “1”, CS, WRT, AND A13..A0 WILL BE IN A HIGH IMPEDANCE STATE EXCEPT FOR WHEN A WORD TRANSFER IS BEING PERFORMED
(DT_ACK = LOGIC “0”).
2)THE LEADING EDGE OF TIME REFERENCE t9 AND THE TRAILING EDGE OF TIME REFERENCES t6 AND t13 ARE DEFINED AS THE FALLING EDGE OF
DT_REQ.
3)THE TRAILING EDGE OF REFERENCE t9 AND THE LEADING EDGE OF TIME REFERENCE t12 ARE DEFINED AS THE RISING EDGE OF DT_REQ.
4)DATA TRANSFER CYCLE TIMING INFORMATION IS DESCRIBED IN OTHER FIGURES.
MIN MAX
1.23
60
1.57
1.52
6.18
SYMBOL DESCRIPTION TYP UNITS
t12
t13(@16MHz)
END OF DATA TRANSFER CYLE TO VALID NEXT WC (Note 3)
MID-PARITY CROSSING OF RECEIVED DATA WORD TO START OF DATA TRANSFER CYCLE (Note 2)
ns
μs
t13(@12MHz)
t14(@12MHz)
MID-PARITY CROSSING OF RECEIVED DATA WORD TO START OF DATA TRANSFER CYCLE (Note 2)
RT RESPONSE TIME
μs
μs
t14(@16MHz) RT RESPONSE TIME μs
t15 MID-SYNC CROSSING OF STATUS RESPONSE TO RTFAIL RISING ns
t16(@12MHz) MID-PARITY CROSSING OF STATUS RESPONSE TO INCMD RISING μs
t16(@16MHz) MID-PARITY CROSSING OF STATUS RESPONSE TO INCMD RISING μs
t17(@12MHz) MID-PARITY CROSSING OF STATUS RESPONSE TO GBR FALLING μs
t17(@16MHz) MID-PARITY CROSSING OF STATUS RESPONSE TO GBR FALLING μs
18(@12MHz) GBR PULSE WIDTH ns
t18(@16MHz) GBR PULSE WIDTH ns
1.94
6.96
6.0 6.76
100
3.36 3.57
3.26 3.45
3.23 3.37
3.17 3.29
140 190
100 150
FIGURE 7. RT TO RT (RECEIVE) TIMING (CONTINUED)
STATUS
MID-SYNC
MID-PARITY
DATA
MID-PARITY
t14
DATA
MID-PARITY
STATUS
CWC=1
t12t12 t16
CWC=2
t17 t18
t15
t13t9 t9t13
20
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H-07/07-0
MIN MAX
0.97 1.56
0.87
SYMBOL DESCRIPTION TYP UNITS
t1(@12MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT μs
t1(@16MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT μs
t2(@12MHz) NBGRT PULSE WIDTH ns
t2(@16MHz) NBGRT PULSE WIDTH ns
t3 NBGRT RISING EDGE TO A6 FALLING EDGE ns
t4(@12MHz) NBGRT FALLING EDGE TO ADDRESS VALID, LMC ns
t4(@16MHz) NBGRT FALLING EDGE TO VALID ADDRESS, LMC ns
t5(@12MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE ns
t5(@16MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE ns
t6(@12MHz) NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE μs
t6(@16MHz) NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE (Note 2) μs
t7 NBGRT FALLING EDGE TO VALID STATUS INPUTS μs
t8 INCMD FALLING EDGE TO CWC VALID ns
t9 DATA TRANSFER CYCLE TIME (Notes 2,3,4)
1.38
140 190
100 150
45
300 410
220 330
800 865
590 655
1.19 1.28
0.88 0.97
4.1
560
FIGURE 8. BC TO RT (RECEIVE) MESSAGE ERROR TIMING
See Note 4
MID-PARITY
t1
RECEIVE COMMAND
1553 BUS
NBGRT
_____
A6 (COMMAND/DATA)
_______
_______
HS_FAIL
ME
__
PREVIOUS COMMAND
PREVIOUS COMMAND
LMC, A13(BRDCST/OWN ADDRS),
___
_________
A12(T/R),A11-A7(SA4-SA0)
_
A5-A1
(WC/MC4-0, CWC4-0)
INCMD
_____
___
WRT (NOTE 1)
DTREQ, DTGRT, DTACK,
_____
_____
__
DATA15-0, CS (NOTE 1)
_____
ILLEGAL, SERVREQ,
SSFLAG, BUSY
______
_______
_______
____
___
GBR
RTFAIL
______
21
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H -07/07-0
MIN
5.95
500
5.87
MAX
6.26
6.245
45
t11(@12MHz)
t10
t11(@16MHz)
DESCRIPTION
MID-PARITY CROSSING OF DATA WORD WITH EVEN PARITY TO FALLING EDGE OF ME
STATUS INPUTS HOLD TIME
MID-PARITY CROSSING OF DATA WORD WITH EVEN PARITY TO FALLING EDGE OF ME
TYP
FIGURE 8. BC TO RT (RECEIVE) MESSAGE ERROR TIMING
UNITS
ms
ns
μs
t12 ME FALLING EDGE TO A6 HIGH ns
300 360t13(@12MHz) ME FALLING EDGE TO INCMD RISING EDGE ns
220 280t13(@16MHz) ME FALLING EDGE TO INCMD RISING EDGE ns
75t14 INCMD RISING EDGE TO WORD COUNT VALID
Notes:
1)IF ADDR_ENA IS LOGIC “1”, CS, WRT, AND A13..A0 WILL BE IN A HIGH IMPEDANCE STATE EXCEPT FOR WHEN A WORD TRANSFER IS BEING PERFORMED
(DT_ACK = LOGIC “0”).
2)THE LEADING EDGE OF TIME REFERENCE t9 AND THE TRAILING EDGE OF TIME REFERENCE t6 IS DEFINED AS THE FALLING EDGE OF DT_REQ.
3)THE TRAILING EDGE OF REFERENCE t9 IS DEFINED AS THE RISING EDGE OF DT_REQ.
4)DATA TRANSFER CYCLE TIMING INFORMATION IS DESCRIBED IN OTHER FIGURES.
ns
SYMBOL
DATA
MID-PARITY
t11
Y
t2
DATA
(PARITY ERROR)
PRESENT COMMAND
t3
t4
t12
t13
t14
WC
t5 t8
CWC=0WC
t6
t7
t9
t10
22
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H-07/07-0
MIN MAX
0.97 1.56
0.87
SYMBOL DESCRIPTION TYP UNITS
t1(@12MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT ms
t1(@16MHz) COMMAND MID-PARITY CROSSING TO FALLING EDGE OF NBGRT ms
t2(@12MHz) NBGRT PULSE WIDTH ns
t2(@16MHz) NBGRT PULSE WIDTH ns
t3 NBGRT RISING EDGE TO A6 FALLING EDGE ns
t4(@12MHz) NBGRT FALLING EDGE TO ADDRESS VALID, LMC ns
t4(@16MHz) NBGRT FALLING EDGE TO VALID ADDRESS, LMC ns
t5(@12MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE ns
t5(@16MHz) NBGRT FALLING EDGE TO INCMD FALLING EDGE ns
t6(@12MHz) NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE ms
t6(@16MHz) NBGRT FALLING EDGE TO START OF DATA TRANSFER CYCLE (Note 2) ms
t7 NBGRT FALLING EDGE TO VALID STATUS INPUTS ms
t8 INCMD FALLING EDGE TO CWC VALID
t9 DATA TRANSFER CYCLE TIME (Notes 2,3,4)
1.38
140 190
100 150
45
300 410
220 330
800 865
590 655
1.19 1.28
0.88 0.97
4.1
560
FIGURE 9. RT TO RT (RECEIVE) TIMEOUT TIMING
See Note 4
t2
TRANSMIT COMMANDRECEIVE COMMAND
MID-PARITY
t1
PREVIOUS COMMAND
PREVIOUS COMMAND
PRESENT COMMAND
t3
t4
t5 t8
t11
CWC=0WC
t6
t7
t9
t10
1553 BUS
_______
NBGRT
_____
ME
__
A6 (COMMAND/DATA)
_______
LMC, A13(BRDCST/OWN ADDRS),
A12(T/R),A11-A7(SA4-SA0)
___
_________
_
A5-A1
(WC/MC4-0, CWC4-0)
INCMD
_____
HS_FAIL
___
DTREQ, DTGRT, DTACK,
_____
_____
_____
__
ILLEGAL, SERVREQ,
SSFLAG, BUSY
______
____
_______
_______
GBR
______
DATA15-0, CS (NOTE 1)
___
WRT (NOTE 1)
RTFAIL
23
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H -07/07-0
FIGURE 9. RT TO RT (RECEIVE) TIMEOUT TIMING (CONTINUED)
ns
ns
A6 PULSE WIDTH
INCMD RISING EDGE TO WORD COUNT VALID
t11(@12MHz)
t14
1205
75
820
ns
ns
STATUS INPUTS HOLD TIME
ME FALLING EDGE TO INCMD RISING EDGE
t10
t13(@16MHz) 280
500
220
nsME FALLING EDGE TO INCMD RISING EDGEt13(@12MHz) 360300
ns
ms
A6 PULSE WIDTH
RT-RT NO RESPONSE TIMEOUT (MESSAGE ERROR)
t11(@16MHz)
t12
UNITSTYPDESCRIPTIONSYMBOL
1025
19.5
720
18.25
MAXMIN
Notes:
1)IF ADDR_ENA IS LOGIC “1”, CS, WRT, AND A13..A0 WILL BE IN A HIGH IMPEDANCE STATE EXCEPT FOR WHEN A WORD TRANSFER IS BEING PERFORMED
(DT_ACK = LOGIC “0”).
2)THE LEADING EDGE OF TIME REFERENCE t9 AND THE TRAILING EDGE OF TIME REFERENCE t6 IS DEFINED AS THE FALLING EDGE OF DT_REQ.
3)THE TRAILING EDGE OF REFERENCE t9 IS DEFINED AS THE RISING EDGE OF DT_REQ.
4)DATA TRANSFER CYCLE TIMING INFORMATION IS DESCRIBED IN OTHER FIGURES.
DATASTATUS
t12
WC
t13
t14
24
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H-07/07-0
MAX
3.0
SYMBOL
t12
TYP
t1(@12MHz)
DT_ACK HIGH DELAY TO ADDRESS, WRT, CS TRI-STATE (Note 1)
DMA REQUEST TO DMA GRANT (COMMAND WORD) μs
t1(@16MHz) DMA REQUEST TO DMA GRANT (COMMAND WORD) μs
t1(@12MHz)
ns
DMA REQUEST TO DMA GRANT (DATA WORD) μs
t1(@16MHz) DMA REQUEST TO DMA GRANT (DATA WORD) μs
t2 DMA GRANT PULSE WIDTH ns
t3 DMA GRANT DELAY TO DMA ACKNOWLEDGE ns
t4 DT_ACK PULSE WIDTH ns
t5 DT_ACK LOW DELAY TO ADDRESS ENABLED (Note 1) ns
t6(@12MHz) DT_ACK LOW DELAY TO RISING EDGE OF CS ns
t6(@16MHz) DT_ACK LOW DELAY TO RISING EDGE OF CS ns
t7(@12MHz) DATA VALID SETUP TIME TO RISING EDGE OF CS ns
t7(@16MHz) DATA VALID SETUP TIME TO RISING EDGE OF CS ns
t8(@12MHz)
45
CS LOW PULSE WIDTH ns
t8(@16MHz) CS LOW PULSE WIDTH ns
t9(@12MHz) DATA HOLD TIME FOLLOWING RISING EDGE OF CS ns
t9(@16MHz) DATA HOLD TIME FOLLOWING RISING EDGE OF CS ns
t10 DATA TRI-STATE SETUP TIME PRIOR TO RISING EDGE OF DT_REQ, DT_ACK ns
t11 DT_REQ HIGH DELAY TO ADDRESS UPDATE (Note 1) ns
3.3
3.5
3.7
130
130
485 515
35
315 365
360 410
195
255
150 185
170 205
70
50
10
60
FIGURE 10. DMA WRITE 16-BIT
Note:
1)Diagram assumes ADDR_ENA is set to logic “0”. If is was set to logic “1”, then A13-A00, CS, and WRT would normally be high impedance until activated by DT_ACK as
shown by “ADDR. WINDOW” timing.
DESCRIPTION MIN UNITS
;;
;;;
;;;
;;;
;
;;
;;;
;;;
;;
;
t1
t12
t2
t4
t6
t8
t5
t7
t10
t9
valid
valid
t3
DT_REQ
DT_GRT
DT_ACK
WR
(SEE NOTE 1)
CS
(SEE NOTE 1)
A05-A01
DB15-DB00
(OUTPUT)
ADDR. WINDOW
(SEE NOTE 1)
t11
;
;
25
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H -07/07-0
MIN MAX
15.1
SYMBOL
112
TYP UNITS
t1(@12MHz)
DT_ACK HIGH DELAY TO ADDRESS, WRT, CS TRI-STATE (Note 1)
DMA REQUEST TO DMA GRANT μs
t1(@16MHz) DMA REQUEST TO DMA GRAN) μs
ns
t5(@12MHz)
t2
DT_ACK LOW DELAY TO CS LOW
DMA GRANT PULSE WIDTH ns
t3 DMA GRANT DELAY TO DMA ACKNOWLEDGE ns
t4
ns
DT_ACK PULSE WIDTH ns
t5(@16MHz)
70
DT_ACK LOW DELAY TO CS LOW ns
115
t6 DT_ACK LOW DELAY TO ADDRESS, WRT, CS, ENABLED (Note 1 ns
t7(@12MHz) DATA VALID SETUP TIME TO RISING EDGE OF CS ns
t7(@16MHz) DATA VALID SETUP TIME TO RISING EDGE OF CS ns
t8(@12MHz)
45
CS LOW PULSE WIDTH ns
t8(@16MHz) CS LOW PULSE WIDTH ns
t9(@12MHz) DATA HOLD TIME FOLLOWING CS HIGH ns
t10 DT_REQ HIGH DELAY TO ADDRESS UPDATE (Note 1) ns
15.3
130
130
485 515
50 95
35
180
240
315 345
360 390
0
60
FIGURE 11. DMA READ 16-BIT
Note:
1)Diagram assumes ADDR_ENA is set to logic “0”" If is was set to logic “1”, then A13-A00, CS, and WRT would normally be high impedance until activated by DT_ACK as
shown by “ADDRESS WINDOW” timing.
DESCRIPTION
;
;;
;;
;;
;;
;
;;
;;
;;
;;
t1
t11
t2
t4
t5
t8
t6
t9
valid
t3
DT_REQ
DT_GRT
DT_ACK
WR
(SEE NOTE 1)
CS
(SEE NOTE 1)
A05-A01
DB15-DB00
ADDRESS
WINDOW
(SEE NOTE 1)
t10
;
;;
;;
;
;;
;;
;
;
;;
;
valid
;
t7
26
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H-07/07-0
MIN MAX
3.0
SYMBOL
t11(@12MHz)
DESCRIPTION TYP UNITS
t1(@12MHz)
DATA HOLD TIME FOLLOWING RISING EDGE OF CS
DMA REQUEST TO DMA GRANT (COMMAND WORD) μs
t1(@16MHz) DMA REQUEST TO DMA GRANT (COMMAND WORD) μs
t1(@12MHz)
ns
DMA REQUEST TO DMA GRANT (DATA WORD) μs
t1(@16MHz)
t14
DMA REQUEST TO DMA GRANT (DATA WORD) μs
t2
DT_ACK HIGH DELAY TO ADDRESS, WRT, CS HIGH IMPEDANCE (Note 1)
DMA GRANT PULSE WIDTH ns
t3 DMA GRANT DELAY TO DMA ACKNOWLEDGE ns
t4
ns
DT_ACK PULSE WIDTH ns
t5 DT_ACK LOW DELAY TO A0 LOW (UPPER BYTE TRANSFER CYCLE TIME ns
t6(@12MHz)
45
START OF BYTE TRANSFER CYCLETO RISING EDGE OF CS ns
t6(@16MHz)
t11(@16MHz)
START OF BYTE TRANSFER CYCLETO RISING EDGE OF CS ns
t7
DATA HOLD TIME FOLLOWING RISING EDGE OF CS
DATA TRI-STATE HOLD TIME FOLLOWING START OF BYTE TRANSFER ???ns
70
t8 DT_ACK LOW DELAY TO ADDRESS, WRT, CS ENABLED (Note 1) ???ns
t9(@12MHz)
ns
DATA SETUP TIME PRIOR TO RISING EDGE OF CS ns
t9(@16MHz)
t12
DATA SETUP TIME PRIOR TO RISING EDGE OF CS ns
t10(@12MHz)
DATA TRI-STATE SETUP TIME PRIOR TO END OF BYTE TRANSFER CYCLE
CS PULSE WIDTH ns
t10(@16MHz) CS PULSE WIDTH ns
3.3
3.5
3.7
130
130
985 1015
485 515
315 365
360 410
50
35
195
255
150
170
ns
FIGURE 12. DMA WRITE 8-BIT
50
10
t13 DT_REQ HIGH DELAY TO ADDRESS UPDATE (Note 1) ns60
Note:
1)Diagram assumes ADDR_ENA is set to logic “0”. If is was set to logic “1”, then A13-A00, CS, and WRT would normally be high impedance until activated by DT_ACK as
shown by “ADDR. WINDOW” timing.
;;
;;
;;
;;
;
;;
;;
;;
;;
t1 t2
t4
t5
t8
t10
t14
t11
valid
t3
DT_REQ
DT_GRT
DT_ACK
WR
(SEE NOTE 1)
CS
(SEE NOTE 1)
A05-A01
DB15-DB00
(OUTPUT)
ADDR. WINDOW
(SEE NOTE 1)
t13
t6
t10
t6
A00
valid valid
t9
t11
t9
t17
t12
UPPER BYTE
(15..8) t12
LOWER BYTE
(7..0)
t17
;
27
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H -07/07-0
MIN MAX
15.1
SYMBOL
112
DESCRIPTION TYP UNITS
t1(@12MHz)
DT_ACK HIGH DELAY TO ADDRESS, WRT, CS TRI-STATE (Note 1)
DMA REQUEST TO DMA GRANT μs
t1(@16MHz) DMA REQUEST TO DMA GRAN) μs
t6(@16MHz)
ns
START OF BYTE TRANSFER CYCLE TO FALLING EDGE OF CS ns50
t5
95
t2
DT_ACK DELAY TO A0 LOW (UPPER BYTE TRANSFER CYCLE TIME)
DMA GRANT PULSE WIDTH ns
t3 DMA GRANT DELAY TO DMA ACKNOWLEDGE ns
t4
ns
ns
485 515
t6(@12MHz) START OF BYTE TRANSFER CYCLE TO FALLING EDGE OF CS ns
t7 DT_ACK LOW DELAY TO ADDRESS, WRT, CS ENABLED (Note 1) ns
t8(@12MHz)
45
CS PULSE WIDTH ns
t8(@16MHz) CS PULSE WIDTH ns
t10 DATA HOLD TIME FOLLOWING CS HIGH ns
t11 DT_REQ HIGH DELAY TO ADDRESS UPDATE (Note 1) ns
15.3
130
130
985 1015
70 115
35
315 345
360 390
0
60
FIGURE 13. DMA READ 8-BIT
DT_ACK PULSE WIDTHACK PULSE WIDTH
Note:
1)Diagram assumes ADDR_ENA is set to logic “0”. If is was set to logic “1”, then A13-A00, CS, and WRT would normally be high impedance until activated by DT_ACK as
shown by “ADDR. WINDOW” timing
;;
;;
;;
;;
;;
;;
;;
;;
t1 t2
t4
t5
t7
valid
t3
DT_REQ
DT_GRT
DT_ACK
WR
(SEE NOTE 1)
CS
(SEE NOTE 1)
A05-A01
DB15-DB00
(OUTPUT)
ADDR. WINDOW
(SEE NOTE 1)
t11
t8
A00
UPPER BYTE
(15..8)
LOWER BYTE
(7..0)
valid
valid
;;
;;
;
;;
;;
;
;;
;
;;
;
;
;
t6
t9 t10
t3
t6
t9
;
t10
28
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H-07/07-0
MAX
3.2 3.3
3.5
SYMBOL DESCRIPTIONTRANSFER TYP
FIGURE 14. DMA HANDSHAKE FAILURE
UNITS
t1(@12MHz) DT_REQ PULSE WIDTHCOMMAND WORD WRITE μs
t1(@16MHz) DT_REQ PULSE WIDTHCOMMAND WORD WRITE μs
t6(@16MHz) DT_REQ RISING EDGE TO WRT LOWDATA WORD READ ns220 310
3.7 3.8
t2 DT_GRT HIGH HOLD TIME FROM DT_REQ RISINGALL ns
t3 HS_FAIL FALLING EDGE FROM DT_REQ RISING EDGEALL ns
t4 WORD COUNT VALID FROM DT_REQ RISING EDGEALL ns
3.9
t1(@12MHz) DT_REQ PULSE WIDTHDATA WORD WRITE
t6(@12MHz)
μs
DT_REQ RISING EDGE TO WRT LOWDATA WORD READ ns
t1(@16MHz) DT_REQ PULSE WIDTHDATA WORD WRITE μs
4.0
15.3t1(@12MHz) DT_REQ PULSE WIDTHDATA WORD WRITE μs
t1(@16MHz) DT_REQ PULSE WIDTHDATA WORD WRITE
3.6
μs
15.5
-60
25
60
300 400
MIN
Notes:
1)Diagram assumes ADDR_ENA is set to logic “0”. If it was set to logic “1” then A13-A00, CS and WRT would normally be in high impedance until activated by DT_ACK as
shown by “ADDR. WINDOW” timing.
2)If the transfer requested was a read operation, and a handshake failure occurred, then the WRT signal would return to the write state and the BUS-65153's transmission
of the 1553 Bus would terminate at the conclusion of the preset word.
t1
______
DT_REQ
DT_GRT
______
t2
t3
t4
A05 - A01
HS_FAIL
_______
(NOTE 1)
___
WRT
(NOTES 1,2)
t5
29
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H -07/07-0
TABLE 4. RECOMMENDED BETA TRANSFORMEER
DEVICE TRANSFORMER
BUS-65153/63 BUS-25679, B-2203, LPB-5002
LPB-5009, or M21038/27-02
BUS-65154/64
BUS-29854, B-2204
LPB-5001, LPB-5008
or M21038/27-03
INTERFACE TO MIL-STD-1553 BUS
Interfacing the BUS-65153 to a MIL-STD-1553 bus requires a
pair of pulse transformers. These transformers, or QPL equiva-
lents, are available from Beta Transformer Technology
Corporation, a subsidiary of DDC. The BUS-65153 hybrid and
Beta Transformers may be wired for either direct coupled or stub
coupled configurations. The recommended transformer for each
of the BUS-65153 transceiver options is listed in TABLE 4.
The interface between a BUS-65153 and a MIL-STD-1553 bus is
illustrated in FIGURE 15.Notes for TABLE 4:
Notes for TABLE 4:
(1)Shown for one of two redundant buses that interface to the BUS-
65153 hybrid.
(2)Transmitted voltage level on 1553 bus is 6 Vp-p min, 7 Vp-p nominal,
9 Vp-p max.
(3)Required tolerance on isolation resistors is 2%. Instantaneous power
dissipation (when transmitting) is approximately 0.5 W (typ), 0.8 W
(max).
(4)Transformer pin numbering is correct for DDC BUS-25679 or BUS-
29854 transformer. For the Beta transformer (e.g., B-2203) or the QPL-
21038-31 transformer (e.g., M21038/27-02), the winding sense and
turns ratio are mechanically the same, but the pin numbering is
reversed. Therefore, it is necessary to reverse pins 8 and 4 or pins 7
and 5 in the diagram for the Beta or QPL transformers.
(5) The B-2204, B-2388, and B-2344 transformers have a slightly differ-
ent turns ratio on the direct coupled taps then the turns ratio of the
BUS-29854 direct coupled taps. They do, however, have the same
transformer coupled ratio. For transformer coupled applications, either
transformer may be used. The transceiver in the BU-65170X2 and the
BU-61580X2 was designed to work with a 1:0.83 ratio for direct cou-
pled applications. For direct coupled applications, the 1.20:1 turns ratio
is recommended, but the 1.25:1 may be used. The 1.25:1 turns ratio
will result in a slightly lower transmitter amplitude. (Approximately 3.6%
lower) and a slight shift in the ACE's receiver threshold.
Zo(70 to 85Ω)
Zo(70 to 85Ω)
55 ohm
55 ohm
1
2
34
8
31 Vpp
1.4:1
DIRECT COUPLED (SHORT STUB)
44 Vpp
BUS-65153
BUS-65163
OR
44 Vpp
TRANSFORMER
1
2
35
7
ISOLATION
2:1 22 Vpp
TRANSFORMER COUPLED (LONG STUB)
1
34
8
1:1.4 31Vpp 0.75Zo
0.75Zo
TRANSFORMER
COUPLING
TRANSFORMER
ISOLATION
DIRECT COUPLED (SHORT STUB)
33 Vpp
BUS-65154
BUS-65164
TRANSFORMER
1
2
34
8
ISOLATION
28 Vpp
1:0.83(or 1:0.80)
55 ohm
55 ohm
0.75Zo
0.75Zo
1
34
8
1:1.4 28 Vpp
1
2
35
7
20 Vpp
TRANSFORMER COUPLED (LONG STUB)
1:0.6
OR
33 Vpp
TRANSFORMER
ISOLATION
TRANSFORMER
COUPLING
1 FT MAX
1 FT MAX
20 FT MAX
20 FT MAX
FIGURE 15. BUS-65153 AND BUS-65154 TO MIL-STD-1553 INTERFACE
30
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H-07/07-0
SIMPLE SYSTEM INTERFACE
FIGURE 16 illustrates the capability of the STIC to operate in a
system with no host processor. A simple linear addressing
scheme is used that can be easily decoded to form read and
write signals for direct access to data buffers or data latches. A
double buffered mechanism may be used on received data in
order to maintain data validity and consistency.
The latched discrete outputs section of the drawing uses two
sets of latches. The first latch is updated when the received data
word is transferred from the STIC. The second latch is not updat-
ed until the message is validated, as indicated by the signal
Good Block Received (GBR). If an error, such as parity or
Manchester, occurs on a received data word, all the data asso-
ciated with that message will be ignored, thus fulfilling the data
validity/consistancy requirement.
DMA INTERFACE
The STIC may be interfaced to a host processor by means of a
simple DMA interface. The address and control lines may be
placed in a three-state mode by setting the ADDR_ENA signal to
logic “1”. While the STIC is not accessing the RAM (i.e., DT_ACK
is logic “1”) the address, data, and control lines (CS, WRT) are
held in a high impedance state. The signals CS and WRT require
pull-up resistors.
The STIC may be programmed to operate in either a 16-bit trans-
fer mode (FIGURE 17) or an 8-bit transfer mode (FIGURE 18).
In 16-bit mode (DB_SEL set to logic “0”) the signal A0 is not used
(always logic “1”) and 16-bit transfers are performed on data
lines D0..D15. In 8-bit mode (DB_SEL set to logic “1”) the signal
A0 is used to indicate whether the upper (MSB) data byte (A0 set
to logic “1”) or the lower (LSB) data byte (A0 set to logic “0”) is
being transferred. The upper and lower data bytes are not multi-
plexed internally, therefore, the signals must be connected exter-
nally. D0 must be connected to D8, D1 must be connected to D9,
... , and D7 must be connected to D15.
Q
LATCH LATCH
DQ D
W0
WRITE
ADDRESS
DECODER
CS
A0..A13
__ WN
Vcc
D
Q
_
QLATCHED
DISCRETE
OUTPUTS
Q
LATCH
LATCH
DQ D
BUS
65153
"STIC"
Vcc
D_
Q
TRI-STATE
BUFFER
Q
NBGRT
GBR
_____
___
ADDRESS
DECODER
READ
R0
DISCRETE
BUFFERED
INPUTS
TRI-STATE
BUFFER
RN
DB GRT
DB0..DB15
______
FIGURE 16. BUS-65153 MINIMUM COMPLEXITY SYSTEM
31
Data Device Corporation
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BU-65153
Rev H -07/07-0
FIGURE 18. BUS-65153 8-BIT DMA INTERFACE
BUS REQUEST
BUS GRANT
___________
_________
DT REQ
DT GNT
______
______
RX/TX A
RX/TX A
RX/TX B
RX/TX B
_______
_______ DB0..DB07
A00..A13
DT ACK
______
DB8..DB15
__
BUS ACKNOWLEDGE
_______________
A0
A00
A00..A13
D0..D7
D0 D0
HOST
PROCESSOR
D1
D2
D3
D4
D5
D6
D7
D1
D2
D3
D4
D5
D6
D7
A01
A02
A03
A04
A05
A06
A07
A08
A09
A1
A2
A3
A4
A5
A6
A7
A8
A9
ME
HS FAIL
_______
_______
INCMD
_____
RT_ADD_ERR
__________
_____
GBR
___
RT FAIL
"STIC"
RT AD 4
RT AD 3
RT AD 2
RT AD 1
RT AD 0
BUS-65153
RT AD LATCH
Vcc
Vcc
RT AD P
TX INH
______
ADDR_ENA
________
NBGRT
Vcc
A10
A11
A12
A13
CS
WE
OE
A10
A11
A12
A13
DATA STROBE
___________
READ/WRITE
_____
16Kx8 RAM
CS
WRT
__
___
CLOCK SEL
DB_SEL
SERVREQ
_______
SSFLAG
______
BUSY
____
12 MHZ CLOCK IN
Vcc
OSC
ILLEGAL
_______
RESET
_____
FIGURE 17. BUS-65153 16-BIT DMA INTERFACE
BUS GRANT
___________
BUS REQUEST
BUS ACKNOWLEDGE
_____________
___________________
DT REQ
DT GNT
______
______
DT ACK
______
RX/TX A
RX/TX A
_______
RX/TX B
RX/TX B
_______
Vcc
BUS-65153
DB0..DB15
ME
_______
RT_ADD_ERR
__________
A01..A13
__
A00 A01
A02
A03
A04
A05
A0
A1
A2
A3
A4
D0
D1
D2
D3
D4
D0
D1
D2
D3
D4
D0..D15
A1..A13
HOST
PROCESSOR
A06
A07
A08
A09
A10
A11
A12
A13
A5
A6
A7
A8
A9
A10
A11
A12
D5
D6
D7
D8
D9
D10
D11
D12
D13
D5
D6
D7
D8
D9
D10
D11
D12
D13
HS FAIL
_______
INCMD
_____
GBR
___
RT FAIL
NBGRT
_____
"STIC"
RT AD 4
RT AD 3
RT AD 2
RT AD 1
RT AD 0
RT AD P
TX INH
______
ADDR_ENA
________
DB_SEL
_______
RT AD LATCH
Vcc
CS
__
___
Vcc
CS
WE
OE
D14
D15
D14
D15
8Kx16 RAM
DATA STROBE
_____
_____________
READ/WRITE
WRT
CLOCK IN
CLOCK SEL
12 MHz
OSC
Vcc
ILLEGAL
_______
RESET
_____
SERVREQ
SSFLAG
______
BUSY
____
Vcc
32
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H-07/07-0
P.C. BOARD LAYOUT GUIDELINES
GROUND PLANES
As is the rule in all high speed digital circuits, it is good practice
to use ground and power supply planes under the STIC hybrid
as well as the associated components.
The reason for not using supply or ground planes under the ana-
log signal traces is that the effect of the distributed capacitance
will be to lower the input impedance of the terminal, as seen from
the 1553 bus. MIL-STD-1553 requires a minimum input imped-
ance of 2000 ohms for direct coupled terminals and 1000 ohms
for transformer (stub) coupled terminals. If there are ground
planes under the analog bus signal traces, it is likely that the ter-
minal will not meet this requirement.
POWER AND GROUND DISTRIBUTION
Another important consideration is power and ground distribu-
tion. Refer to FIGURE 19. For the STIC hybrid/transformer com-
bination, the high current path when the STIC is transmitting will
be from the -15 volt power supply, through the transmitter output
stage, through one leg of the isolation transformer to the trans-
former center tap. It is important to realize that the high current
IT IS VERY IMPORTANT THAT THERE BE NO GROUND
AND/OR POWER SUPPLY PLANES UNDERNEATH
ANY OF THE ANALOG BUS SIGNAL TRACESTHIS
APPLIES TO THE TX/RX SIGNALS RUNNING FROM
THE STIC HYBRID TO THE TRANSFORMERS AS
WELL AS FROM THE TRANSFORMERS TO ANY CON-
NECTORS OR CABLES LEAVING THE BOARD
return path is through the transformer center tap and not
through the STIC's GND pin.
It is an important layout consideration to minimize the power sup-
ply distribution impedance along this path. Any resistance will
result in voltage drops for the power supply input voltage, and
can ultimately lower the transmitter output voltage, possibly
below the minimum level required by MIL-STD-1553.
1553 BUS CONNECTIONS
The isolation transformers should be placed as physically close
as possible to the respective TX/RX pins on the STIC and the
distance from the isolation transformers to any connectors or
cables leaving the board should be as short as possible. In
addition to limiting the voltage drops in the analog signal traces
when transmitting, reducing the hybrid-to-transformer and trans-
former-to-connector spacings serves to minimize crosstalk from
other signals on the board.
The general practice in connecting the stub side of a transformer
(or direct) coupled terminal to an external system connector is to
make use of 78 ohm twisted-pair shielded cable. This minimizes
impedance discontinuities. The decision of whether to isolate or
make connections between the center tap of the isolation trans-
former's secondary, the stub shield, the bus shield, and/or chas-
sis ground must be made on a system basis, as determined by
an analysis of EMI/RFI and lightning considerations.
In most systems, it is specified that the 1553 terminal's input
impedance must be measured at the system connector. This is
LOGIC
RX
TRANSCEIVER
TX
1
2
3
6
8
7
5
4
BUS-41429
HIGH LEVEL
CURRENTS
LOW LEVEL
CURRENTS
LOW LEVEL
CURRENTS
LOGIC
GND
GND A/B
+5 V
LOGIC +5 V A/B
-15 V/-12 V (A/B)
BUS-29854
BUS-25679
FIGURE 19. POWER/GROUND CURRENT DISTRIBUTION
33
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H -07/07-0
despite the fact that the MIL-STD-1553B requirement is for it to
be measured looking directly in from the bus side of the isolation
transformer.
The effect of a relatively long stub cable will be to reduce the
measured impedance. In order to keep the impedance above the
required level of 1000 ohms (for transformer-coupled stubs), the
length of any cable between the 1553 RT and the system con-
nector should be minimized.
“SIMULATED BUS” (LAB BENCH) INTERCONNECTIONS
For purposes of software development and system integration, it is gen-
erally not necessary to integrate the required couplers, terminators, etc.,
that comprise a complete MIL-STD-1553B bus. In most instances, a sim-
plified electrical configuration will suffice. The three connection methods
illustrated in FIGURE 20 allow the STIC to be interfaced over a ©simulat-
ed busª to simulation and test equipment. It is important to note that the
termination resistors indicated are necessary in order to ensure reli-
able communications between the STIC and the simulation/test equip-
ment.
1
2
3
8
7
5
4
STIC
HYBRID
TEST/
SIMULATION
EQUIPMENT
STUB
COUPLING
STUB
COUPLING
ISOLATION
TRANSFORMER
78Ω
1.5W
(A)
1
2
3
8
4
STIC
HYBRID
TEST/
SIMULATION
EQUIPMENT
DIRECT
COUPLING
DIRECT
COUPLING
ISOLATION
TRANSFORMER
39Ω
0.5W
(B)
55Ω
1W
55Ω
1W
55Ω
55Ω
1
2
3
8
4
STIC
HYBRID
TEST/
SIMULATION
EQUIPMENT
STUB
COUPLING
DIRECT
COUPLING
ISOLATION
TRANSFORMER
39Ω
0.5W
(C)
55Ω
1W
55Ω
1W
20Ω
0.5W
20Ω
0.5W
FIGURE 20. “SIMULATED BUS” (LAB BENCH) INTERCONNECTIONS
A) DIRECT COUPLED TO DIRECT COUPLED
(B) TRANSFORMER COUPLED TO TRANSFORMER COUPLED
(C) DIRECT COUPLED TO TRANSFORMER COUPLED
34
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H-07/07-0
POWER AND GROUND
TABLE 5. BUS-65153 PIN DESCRIPTIONS
PIN NO DESCRIPTIONI/ONAME
18 Analog and Digital Ground-GND
36
70
35
CH. A and CH. B Transceiver -15V (-12V) Supply Input
CH.B Transceiver +5V Supply Input
Logic and CH. A Transceiver +5V Supply Input
I
I
I
-15 (-12) VOLTS
+5 VOLTS B
+5 VA
I/O
I/O
I/O
DB00 (LSB)
DB02
DB10
26
24
15
I/O
I/O
I/O
DB01
DB03
DB11
25
23
14
I/O
I/O
DB04
DB12
22
13
8/16-bit data bus. DB15 through DB00 may be configured as either a 16-bit or an 8-bit data bus. In the 8-bit mode,
DB15 thru DB8 should be connected directly to DB7 thru DB0, respectively (DB15 to DB7, DB14 to DB6 , ... , DB8
to DB0). DB15-DB00 is maintained in a high-impedance state except when the BUS-65153 is performing a data
write transfer. In the 8-bit mode, the upper byte is transferred first, followed by the lower byte.
I/O
I/O
DB05
DB13
21
12
DESCRIPTION
I/O
I/O
I/O
I/O
I/O
I/O
I/O
DB06
DB14
20
11
DB07
DB15 (MSB)
19
10
DB08
NAME
17
PIN NO
DB0916
DATA BUS (16)
(TABLE 5 CONTINUES ON THE NEXT PAGE.)
35
Data Device Corporation
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BU-65153
Rev H -07/07-0
Transmitter Inhibit. A low level on this input disables both 1553 transmitters.ITXINH49
DESCRIPTION
CLOCK, RESET, AND TRANSMITTER INHIBIT (4)
12 or 16 MHz clock input.
Clock Frequency Select. If high, selects 12 MHz clock input. If low, selects a 16 MHz clock input.
Master Reset - Active low input signal (2 clock cycles minimum) used to reset the entire circuit.
I/O
I
I
IRESET45
CLOCKSEL43
CLOCK IN51
NAME
Notes:
1. A13 through A0, CS, and WRT will be placed in a high impedance state if ADDR_ENA is high and DTACK is inactive (high).
2. The RT Status Word inputs ILLCMD, SERVREQ, SSFLAG, and BUSY are sampled approximately 5 ms following the mid-parity bit zero crossing of the received
Command Word.
PIN NO.
(TABLE 5 CONTINUES ON THE NEXT PAGE.)
A11 through A07 : Subaddress [4:0] - These outputs are the latched data from the Subaddress field of the
received Command Word. They are updated after NBGRT but before INCMD goes active. They are cleared by
RESET. A11 corresponds to SA4 which is the MSB and A07 corresponds to SA0 which is the LSB. (Note 1)
OA07 (LSB)57
O
O
A00
A08
64
56
O
O
A01 (LSB)
A09
63
55
O
O
A02
A10
62
54
TABLE 5. BUS-65153 PIN DESCRIPTIONS - CONTINUED
ADDRESS BUS (14)
DESCRIPTION
Transmit/Receive - Latched output signal that represents the latched T/R bit (bit 10) of the present Command
Word. It is updated after NBGRT but before INCMD goes active. A logic “1” indicates a transmit command, a logic
“0” indicates a receive command. Cleared by RESET. (Note 1)
O
I/O
O
O
O
O
O
O
A03
A11 (MSB)
61
53
A04
A12
60
52
A05 (MSB)
A13
59
50
A06
NAME
58
A05 through A01 (LSB):Word Count [4:0] / Current Word Count [4:0]. Multiplexed output signals which are defined
as follows: these outputs are the latched data from the Word Count field of the received Command Word. They are
updated after NBGRT but before INCMD goes active. They are cleared by RESET. For the Command Word trans-
fer (A06 = 0) of a nonmode code Command Word, A05-A00 will be 00000. For a mode code Command Word
transfer, A05-A00 will reflect the mode code field of the Command Word. If the present command is not a mode
code and INCMD is active then these lines become the output of a current word counter. That is, when INCMD
goes active, these outputs go to logic “0” and are then incremented after every Data Word transfer or handshake
timeout. For a mode code transfer, the single Data Word is accessed at an address location that is offset by a
value of 32 above that of the location for the corresponding Command Word. When INCMD goes inactive, A05-
A01 become the latched Word Count field again. A5 corresponds to WC4 which is the MSB and A1 corresponds
to WC0 which is the LSB. (Note 1)
Broadcast. Latched output signal that represents the RT Address field of the present Command Word. That is, it
was either a broadcast message (all ones in the RT Address Field) or a command addressed explicitly to this ter-
minal (the address field of the command word matches the terminals's RTADD04 to RTADD0 inputs and RTAD4-0,
RTADP has an odd parity sum.). It is updated after NBGRT but before INCMD goes active. A logic “1” indicates a
broadcast command, a logic “0” indicates a command to the BUS-65153's RT Address. Cleared by RESET.
(Note 1)
Command Word Transfer - Active low level output signal that is asserted when the 1553 Command Word is being
transferred to the subsystem over the parallel data bus. A06 is high during all Data Word transfers. (Note 1)
MSB/LSB - Output signal that is used during 8-bit data transfers to indicate which byte of the present 16-bit word
is being transferred. A logic “1” indicates the upper byte (MSB) and a logic “0” indicates the lower byte (LSB). The
upper byte is transferred first. If a 16-bit data structure is used (DB_SEL = logic “0”), this bit will always be logic “1”
(Note 1)
PIN NO.
36
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H-07/07-0
DESCRIPTIONI/ONAME
I
O
DB_SEL
CS
8
3
TABLE 5. BUS-65153 PIN DESCRIPTIONS - CONTINUED
DMA HANDSHAKE AND TRANSFER CONTROL (8)
O
O
O
I
I
O
ADDR_ENA
DT_ACK
7
2
HS_FAIL
DT_GRT
6
1
WRT
DT_REQ
4
69
INTERFACE TO 1553 PULSE TRANSFORMERS (4)
DESCRIPTIONI/ONAMEPIN NO.
Channel A Inverted 1553 Serial DataI/OTX/TXA44
Channel B Non-Inverted 1553 Serial Data.
Channel B Inverted 1553 Serial Data
Channel A Non-Inverted 1553 Serial Data
I/O
I/O
I/ORX/TXA40
RX/TXB9
RX/TXB5
Remote Terminal Address inputs.
I34
I
I
IRTADD0333
RTADD02
DESCRIPTION
RT ADDRESS (8)
NAME
IRTADD00 (LSB)30
31
O
I
IRT_ADD_P29
RT_ADD_LAT28
RT_ADD_ERR27
RTADD0131
Data Transfer Request. Active low level output signal used to inform the subsystem that the BUS-65153 needs con-
trol of the data bus to perform a transfer. Stays low until DT_GRT is received and the transfer is completed or until
a handshake failure timeout has occurred.
Data Transfer Grant. Active low level input signal from the subsystem that, in response to a Data Transfer Request,
passes control of the parallel data bus to the BUS-65153.
Data Transfer Acknowledge - Active low level output signal used to inform the subsystem that the BUS-65153 has
received DT_GRT in response to DT_REQ. DT_ACK remains active until the transfer is complete.
Chip Select - Active low level output pulse present in the middle of every data transfer cycle. When the BUS-65153
is writing data to the subsystem, this signal occurs when the data is valid and should be used to latch the data (rec-
ommend using rising edge). When the BUS-65153 is reading data from the subsystem, this signal is used to inform
the subsystem when to drive the data bus. (Note 1)
Read/Write - Output signal that controls the direction of the data transfers. The direction is normally outward (write
= logic “0”) and only turns inward (read = logic “1”) when the first Data Word is needed from the subsystem. The
output will return low (write) after the transmission of the last data word on the 1553 bus. (Note 1)
Handshake Failure - Active low level output used to flag the subsystem that DT_GRT was not received in response
to DT_REQ in time to perform a data transfer. Latched low and cleared by the next NBGRT or RESET.
Address Enable. Active low level input signal used to control the operation of WRT, CS, and address bus A13
through A00. If a logic “0” is applied, the above signals are always active. If a logic “1” is applied, these signals are
kept in their high impedance state except for when a data transfer is being performed (DT_ACK = logic “0”)
Data Bus Select - Input signal used to select the data bus structure (8- or 16-bit width)
Logic “0” selects 16-bit data bus
Logic “1” selects 8-bit data bus
Note: For 8-bit data bus operation, D15 to D08 should be connected directly to D07 to D00, respectively.
Notes:
1. A13 through A0, CS, and WRT will be placed in a high impedance state if ADDR_ENA is high and DTACK is inactive (high).
2. The RT Status Word inputs ILLCMD, SERVREQ, SSFLAG, and BUSY are sampled approximately 5 ms following the mid-parity bit zero crossing of the received Command Word.
Remote Terminal Address [4:0] - Input signal of the address parity bit. The combination of RT_AD_[0:4], and
RT_AD_P must comprise an odd parity sum in order to enable recognition of the terminal's address.
Remote Terminal Address Latch. When low, the internal RDAD4-0 and RTADP register tracks whatever is applied
to the respective input pins. When RT_ADD_LAT is high, the information that was on RTAD4-0 and RTADP the last
time that RT_ADD_LAT was low is latched internally. The internal RTAD4-0 and RTADP are cleared to logic 0 when
RESET is low.
I/O
Remote Terminal Address Parity Error Output Signal that reflects the parity combination of the RT_AD_[4:0] inputs
and RT_AD_P input. High level indicates odd parity, low level indicates even parity. Note, if RT_ADD_ERR is low,
then the BUS-65153 will not recognize any valid Command Word directed to its own RT address.
(TABLE 5 CONTINUES ON THE NEXT PAGE.)
PIN NO.
RTADD04 (MSB)
PIN NO.
37
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H -07/07-0
Remote Terminal Failure - Latched low level output that goes low if a loopback failure (or transmitter shutdown
timeout) has occurred during a transmission cycle. A loopback failure occurs under any of the following conditions:
(1) the first transmitted word (Status Word) contains an incorrect RT address field, (2) the received version of any
transmitted word is either invalid or contains the incorrect sync type, (3) the received 16-bit data pattern for the last
transmitted word does not match that of the transmitted version of the word and/or (4) A transmitter timeout (668
ms) has occurred. Reset by the start of the next transmission cycle (Status Word) or a low level on the RESET
input. An RTFAIL condition (low level output on RTFAIL) will cause the Terminal Flag bit in the RT Status Register
to be set. When this occurs, the RT Flag Status Word bit will be set in response to the next valid nonbroadcast
command.
DESCRIPTIONI/ONAMEPIN NO.
IBUSY68
TABLE 5. BUS-65153 PIN DESCRIPTIONS - CONTINUED
RT STATUS WORD INPUTS (4)
O
I
ISSFLAG67
SERVREQ66
ILLCMD65
O
DESCRIPTIONI/ONAMEPIN NO.
OINCMD41
MESSAGE TIMING OUTPUT SIGNALS (5)
O
O
ONBGRT39
RTFAIL38
GBR37
ME42
FACTORY TEST INPUTS (3)
PIN NO. NAME I/O DESCRIPTION
Connect to + 5 volts.
Connect to + 5 volts.
Connect to + 5 volts.
I
I
I48
47
46
Notes:
1. A13 through A0, CS, and WRT will be placed in a high impedance state if ADDR_ENA is high and DTACK is inactive (high).
2. The RT Status Word inputs ILLCMD, SERVREQ, SSFLAG, and BUSY are sampled approximately 5 ms following the mid-parity bit zero crossing of
the received Command Word.
Illegal Command Input. Active low Input used to illegalize any command. If low when sampled, the Message Error
bit (bit 10) in the Status Word will be set. The response to an illegal transmit command will be a Status Word only.
The only effect of illegalizing a receive command will to inhibit GBR. An illegalized mode code will not perform the
actual mode functions. (Note 2)
Service Request - Input signal used to control the Service Request bit (bit 8) in the Status Word. If low when sam-
pled, the Service Request bit will be set. If high, it will be logic”0”. (Note 2)
Subsystem Flag - Input signal used to control the Subsystem Flag bit (bit 2) in the Status Word. If low when sam-
pled, the Subsystem Flag bit will be set. If high, the Subsystem Flag bit will be logic “0”. (Note 2)
Input signal used to control the Busy bit (bit 3) in the Status Word. If low when sampled, the Busy bit will be set. If
high, it will be cleared. Note, if the Busy bit is set and the command was a transmit command, only the Status
Word would be transmitted. Has no effect on data received following a receive command. (Note 2)
New Bus Grant - Low level output pulse (2 clock cycles wide), that is used to indicate the start of a new protocol
sequence in response to the Command Word just received from the 1553 bus.
Good Block Received - Low level output pulse (2 clock cycles wide) that is used to flag the subsystem that a valid,
legal, nonmode receive command with the correct number of data words has been received without a message
error and successfully transferred to the subsystem
In Command - Active low level output signal used to inform the subsystem that the BUS-65153 is presently servic-
ing a command that came in on the 1553 bus.
Message Error - Active low level output signal used to flag the subsystem that there was a message error on the
1553 bus communication (word, gap, or word count error). This output goes low upon detecting the error and is
reset at the start of the next NBGRT pulse or master reset. If this output goes low, all further command servicing is
aborted.
FACTORY TEST
POINT
FACTORY TEST
POINT
FACTORY TEST
POINT
38
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H-07/07-0
PINPIN
TABLE 6. BUS-65153/63 PIN LISTING
NAMENAME
361DT_GRT -15 (-12)VOLTS
372GBRDT_ACK
383RTFAILCS
394NBGRTWRT
405RX/TX ARX/TX B
416INCMDHS_FAIL
427
438CLOCKSELDB_SEL
449RX/TX ARX/TX B
4510
4611 FACTORY TEST POINTDB14
4712 FACTORY TEST POINTDB13
4813 FACTORY TEST POINTDB12
4914 TXINHDB11
5015 AT 3DB10
5116 CLOCK INDB09
5217 AT 2DB08
5318 AT11 (MSB)GND
5419 A10DB07
5520 A09DB06
5621 A08DB05
5722 A07 (LSB)DB04
5823 A06DB03
24 A05 (MSB)DB02
6025 A04DB01
6126
6227 A02RT_ADD_ERR
6328 A01 (LSB)RT_ADD_LAT
6429 A00RT_ADD_P
6530
6631 SERVREQRTADD01
6732 SSFLAGRTADD02
6833 BUSYRTADD03
6934 DT_REQRTADD04 (MSB)
7035 + 5 VOLTS B+ 5 VA
MEADDR_ENA
RESETDB!5 (MSB)
A03DB00 (LSB)
ILLCMDRTADD00 (LSB)
59
70 36
351
0.015 ± 0.002 TYP
(0.381 ± 0.051)
1.900 MAX
(48.26)
34 EQ SP @ 0.050 = 1.700
(43.18) (1.27) TOL NONCUM
0.050 TYP
(1.27)
0.400 MIN TYP
(10.16)
INDEX DENOTES PIN 1 1.000 MAX
(25.4)
0.215 (5.46) MAX
0.010 ± 0.002 TYP
(0.254 ± 0.051)
0.070 ± 0.010
(1.78)
PIN NUMBERS
FOR REF ONLY
TOP VIEW SIDE VIEW
NOTES:
1. DIMENSIONS ARE IN INCHES (MILLIMETERS).
2. PACKAGE MATERIAL: ALUMINA (AL2O3).
3. LEAD MATERIAL: KOVAR, PLATED BY 150μ MINIMUM NICKEL, PLATED BY 50μ MINIMUM GOLD.
1.000 MAX
(25.4)
0.400
(10.16)
1.700 (43.18)
INDEX
DENOTES
PIN 1
0.215 (5.46) MAX
NOTES:
1. DIMENSIONS ARE IN INCHES (MILLIMETERS).
2. PACKAGE MATERIAL: ALUMINA (AL2O3).
3. LEAD MATERIAL: KOVAR, PLATED BY 150μ MINIMUM NICKEL, PLATED BY 50μ MINIMUM GOLD.
1.900 MAX
(48.26)
0.180 ±0.010 TYP
(4.57 ±0.25)
0.100 (2.54)
0.100 (2.54) TYP
0.050 (1.27) TYP
0.600
(15.24)
0.018 ±0.002 DIA TYP
(0.46 ±0.05)
34
35
36
37 69
70
2
TOP VIEW
BOTTOM VIEW
INDEX
DENOTES
PIN 1
1.900 (48.26) MAX
SIDE VIEW
FIGURE 21. BUS-65153/54 DIP MECHANICAL OUTLINE
FIGURE 22. BUS-65163/64 FLAT PACK MECHANICAL OUTLINE
39
Data Device Corporation
www.ddc-web.com
BU-65153
Rev H -07/07-0
ORDERING INFORMATION
BUS-651XX-XX0X
Supplemental Process Requirements:
S = Pre-Cap Source Inspection
L = Pull Test
Q = Pull Test and Pre-Cap Inspection
K = One Lot Date Code
W = One Lot Date Code and PreCap Source
Y = One Lot Date Code and 100% Pull Test
Z = One Lot Date Code, PreCap Source and 100% Pull Test
Blank = None of the Above
Process Requirements:
0 = Standard DDC Processing, no Burn-In (See table below.)
1 = MIL-PRF-38534 Compliant
2 = B*
3 = MIL-PRF-38534 Compliant with PIND Testing
4 = MIL-PRF-38534 Compliant with Solder Dip
5 = MIL-PRF-38534 Compliant with PIND Testing and Solder Dip
6 = B* with PIND Testing
7 = B* with Solder Dip
8 = B* with PIND Testing and Solder Dip
9 = Standard DDC Processing with Solder Dip, no Burn-In (See table below.)
Temperature Grade/Data Requirements:
1 = -55°C to +125°C
2 = -40°C to +85°C
3 = 0°C to +70°C
4 = -55°C to +125°C with Variables Test Data
5 = -40°C to +85°C with Variables Test Data
8 = 0°C to +70°C with Variables Test Data
Power Supply and Packaging
53 = +5 V/-15 V DIP
54 = +5 V/-12 V DIP
63 = +5 V/-15 V Flat Pack
64 = +5 V/-12 V Flat Pack
Notes:
1. *Standard DDC Processing with burn-in and full temperature test — see table below.
2. Also available as DESC P/N 5962-92162-01HXC.
3. This product contains tin-lead solder unless noted otherwise
Data Bus Transformers:
For BUS-65153/63 use BUS-25679, B-2203, LPB-5002, LPB-5009, or M21038/27-02.
For BUS-65154/64 use BUS-29854, B-2204, LPB-5001, LPB-5008, or M21038/27-03.
—1015, Table 1BURN-IN
A2001CONSTANT ACCELERATION
C1010TEMPERATURE CYCLE
A and C1014SEAL
—2009, 2010, 2017, and 2032INSPECTION
CONDITION(S)METHOD(S)
MIL-STD-883
TEST
STANDARD DDC PROCESSING
40
Rev H -07/07-0 PRINTED IN THE U.S.A.
DATA DEVICE CORPORATION
REGISTERED TO ISO 9001:2000
FILE NO. A5976
R
E
G
I
S
T
E
R
E
D
F
I
R
M
®
U
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
105 Wilbur Place, Bohemia, New York 11716-2426
For Technical Support - 1-800-DDC-5757 ext. 7771
Headquarters, N.Y., U.S.A. -Tel: (631) 567-5600, Fax: (631) 567-7358
United Kingdom - Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264
France - Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425
Germany - Tel: +49-(0)89-15 00 12-11, Fax: +49-(0)89-15 00 12-22
Japan - Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689
World Wide Web - http://www.ddc-web.com
The information in this data sheet is believed to be accurate; however, no responsibility is
assumed by Data Device Corporation for its use, and no license or rights are
granted by implication or otherwise in connection therewith.
Specifications are subject to change without notice.
Please visit our Web site at www.ddc-web.com for the latest information.
